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8525f280 LR |
1 | /* |
2 | * Copyright (c) 2010 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "hw.h" | |
da6f1d7f | 18 | #include "ar9003_phy.h" |
8525f280 LR |
19 | |
20 | /** | |
21 | * ar9003_hw_set_channel - set channel on single-chip device | |
22 | * @ah: atheros hardware structure | |
23 | * @chan: | |
24 | * | |
25 | * This is the function to change channel on single-chip devices, that is | |
26 | * all devices after ar9280. | |
27 | * | |
28 | * This function takes the channel value in MHz and sets | |
29 | * hardware channel value. Assumes writes have been enabled to analog bus. | |
30 | * | |
31 | * Actual Expression, | |
32 | * | |
33 | * For 2GHz channel, | |
34 | * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) | |
35 | * (freq_ref = 40MHz) | |
36 | * | |
37 | * For 5GHz channel, | |
38 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) | |
39 | * (freq_ref = 40MHz/(24>>amodeRefSel)) | |
40 | * | |
41 | * For 5GHz channels which are 5MHz spaced, | |
42 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) | |
43 | * (freq_ref = 40MHz) | |
44 | */ | |
45 | static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) | |
46 | { | |
f7abf0c1 FF |
47 | u16 bMode, fracMode = 0, aModeRefSel = 0; |
48 | u32 freq, channelSel = 0, reg32 = 0; | |
49 | struct chan_centers centers; | |
50 | int loadSynthChannel; | |
51 | ||
52 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
53 | freq = centers.synth_center; | |
54 | ||
55 | if (freq < 4800) { /* 2 GHz, fractional mode */ | |
56 | channelSel = CHANSEL_2G(freq); | |
57 | /* Set to 2G mode */ | |
58 | bMode = 1; | |
59 | } else { | |
60 | channelSel = CHANSEL_5G(freq); | |
61 | /* Doubler is ON, so, divide channelSel by 2. */ | |
62 | channelSel >>= 1; | |
63 | /* Set to 5G mode */ | |
64 | bMode = 0; | |
65 | } | |
66 | ||
67 | /* Enable fractional mode for all channels */ | |
68 | fracMode = 1; | |
69 | aModeRefSel = 0; | |
70 | loadSynthChannel = 0; | |
71 | ||
72 | reg32 = (bMode << 29); | |
73 | REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); | |
74 | ||
75 | /* Enable Long shift Select for Synthesizer */ | |
76 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, | |
77 | AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); | |
78 | ||
79 | /* Program Synth. setting */ | |
80 | reg32 = (channelSel << 2) | (fracMode << 30) | | |
81 | (aModeRefSel << 28) | (loadSynthChannel << 31); | |
82 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); | |
83 | ||
84 | /* Toggle Load Synth channel bit */ | |
85 | loadSynthChannel = 1; | |
86 | reg32 = (channelSel << 2) | (fracMode << 30) | | |
87 | (aModeRefSel << 28) | (loadSynthChannel << 31); | |
88 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); | |
89 | ||
90 | ah->curchan = chan; | |
91 | ah->curchan_rad_index = -1; | |
92 | ||
8525f280 LR |
93 | return 0; |
94 | } | |
95 | ||
96 | /** | |
97 | * ar9003_hw_spur_mitigate - convert baseband spur frequency | |
98 | * @ah: atheros hardware structure | |
99 | * @chan: | |
100 | * | |
101 | * For single-chip solutions. Converts to baseband spur frequency given the | |
102 | * input channel frequency and compute register settings below. | |
103 | * | |
104 | * Spur mitigation for MRC CCK | |
105 | */ | |
106 | static void ar9003_hw_spur_mitigate(struct ath_hw *ah, | |
107 | struct ath9k_channel *chan) | |
108 | { | |
ca375554 FF |
109 | u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; |
110 | int cur_bb_spur, negative = 0, cck_spur_freq; | |
111 | int i; | |
112 | ||
113 | /* | |
114 | * Need to verify range +/- 10 MHz in control channel, otherwise spur | |
115 | * is out-of-band and can be ignored. | |
116 | */ | |
117 | ||
118 | for (i = 0; i < 4; i++) { | |
119 | negative = 0; | |
120 | cur_bb_spur = spur_freq[i] - chan->channel; | |
121 | ||
122 | if (cur_bb_spur < 0) { | |
123 | negative = 1; | |
124 | cur_bb_spur = -cur_bb_spur; | |
125 | } | |
126 | if (cur_bb_spur < 10) { | |
127 | cck_spur_freq = (int)((cur_bb_spur << 19) / 11); | |
128 | ||
129 | if (negative == 1) | |
130 | cck_spur_freq = -cck_spur_freq; | |
131 | ||
132 | cck_spur_freq = cck_spur_freq & 0xfffff; | |
133 | ||
134 | REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, | |
135 | AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); | |
136 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
137 | AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); | |
138 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
139 | AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, | |
140 | 0x2); | |
141 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
142 | AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, | |
143 | 0x1); | |
144 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
145 | AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, | |
146 | cck_spur_freq); | |
147 | ||
148 | return; | |
149 | } | |
150 | } | |
151 | ||
152 | REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, | |
153 | AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); | |
154 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
155 | AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); | |
156 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
157 | AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); | |
8525f280 LR |
158 | } |
159 | ||
160 | static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, | |
161 | struct ath9k_channel *chan) | |
162 | { | |
317d3328 FF |
163 | u32 pll; |
164 | ||
165 | pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); | |
166 | ||
167 | if (chan && IS_CHAN_HALF_RATE(chan)) | |
168 | pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); | |
169 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
170 | pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); | |
171 | ||
172 | if (chan && IS_CHAN_5GHZ(chan)) { | |
173 | pll |= SM(0x28, AR_RTC_9300_PLL_DIV); | |
174 | ||
175 | /* | |
176 | * When doing fast clock, set PLL to 0x142c | |
177 | */ | |
178 | if (IS_CHAN_A_5MHZ_SPACED(chan)) | |
179 | pll = 0x142c; | |
180 | } else | |
181 | pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); | |
182 | ||
183 | return pll; | |
8525f280 LR |
184 | } |
185 | ||
186 | static void ar9003_hw_set_channel_regs(struct ath_hw *ah, | |
187 | struct ath9k_channel *chan) | |
188 | { | |
cffb5e49 LR |
189 | u32 phymode; |
190 | u32 enableDacFifo = 0; | |
191 | ||
192 | enableDacFifo = | |
193 | (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); | |
194 | ||
195 | /* Enable 11n HT, 20 MHz */ | |
196 | phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH | | |
197 | AR_PHY_GC_SHORT_GI_40 | enableDacFifo; | |
198 | ||
199 | /* Configure baseband for dynamic 20/40 operation */ | |
200 | if (IS_CHAN_HT40(chan)) { | |
201 | phymode |= AR_PHY_GC_DYN2040_EN; | |
202 | /* Configure control (primary) channel at +-10MHz */ | |
203 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || | |
204 | (chan->chanmode == CHANNEL_G_HT40PLUS)) | |
205 | phymode |= AR_PHY_GC_DYN2040_PRI_CH; | |
206 | ||
207 | } | |
208 | ||
209 | /* make sure we preserve INI settings */ | |
210 | phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); | |
211 | /* turn off Green Field detection for STA for now */ | |
212 | phymode &= ~AR_PHY_GC_GF_DETECT_EN; | |
213 | ||
214 | REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); | |
215 | ||
216 | /* Configure MAC for 20/40 operation */ | |
217 | ath9k_hw_set11nmac2040(ah); | |
218 | ||
219 | /* global transmit timeout (25 TUs default)*/ | |
220 | REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); | |
221 | /* carrier sense timeout */ | |
222 | REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); | |
8525f280 LR |
223 | } |
224 | ||
225 | static void ar9003_hw_init_bb(struct ath_hw *ah, | |
226 | struct ath9k_channel *chan) | |
227 | { | |
228 | /* TODO */ | |
229 | } | |
230 | ||
cffb5e49 LR |
231 | void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) |
232 | { | |
233 | switch (rx) { | |
234 | case 0x5: | |
235 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
236 | AR_PHY_SWAP_ALT_CHAIN); | |
237 | case 0x3: | |
238 | case 0x1: | |
239 | case 0x2: | |
240 | case 0x7: | |
241 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); | |
242 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); | |
243 | break; | |
244 | default: | |
245 | break; | |
246 | } | |
247 | ||
248 | REG_WRITE(ah, AR_SELFGEN_MASK, tx); | |
249 | if (tx == 0x5) { | |
250 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
251 | AR_PHY_SWAP_ALT_CHAIN); | |
252 | } | |
253 | } | |
254 | ||
255 | /* | |
256 | * Override INI values with chip specific configuration. | |
257 | */ | |
258 | static void ar9003_hw_override_ini(struct ath_hw *ah) | |
259 | { | |
260 | u32 val; | |
261 | ||
262 | /* | |
263 | * Set the RX_ABORT and RX_DIS and clear it only after | |
264 | * RXE is set for MAC. This prevents frames with | |
265 | * corrupted descriptor status. | |
266 | */ | |
267 | REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); | |
268 | ||
269 | /* | |
270 | * For AR9280 and above, there is a new feature that allows | |
271 | * Multicast search based on both MAC Address and Key ID. By default, | |
272 | * this feature is enabled. But since the driver is not using this | |
273 | * feature, we switch it off; otherwise multicast search based on | |
274 | * MAC addr only will fail. | |
275 | */ | |
276 | val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); | |
277 | REG_WRITE(ah, AR_PCU_MISC_MODE2, | |
278 | val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE); | |
279 | } | |
280 | ||
281 | static void ar9003_hw_prog_ini(struct ath_hw *ah, | |
282 | struct ar5416IniArray *iniArr, | |
283 | int column) | |
284 | { | |
285 | unsigned int i, regWrites = 0; | |
286 | ||
287 | /* New INI format: Array may be undefined (pre, core, post arrays) */ | |
288 | if (!iniArr->ia_array) | |
289 | return; | |
290 | ||
291 | /* | |
292 | * New INI format: Pre, core, and post arrays for a given subsystem | |
293 | * may be modal (> 2 columns) or non-modal (2 columns). Determine if | |
294 | * the array is non-modal and force the column to 1. | |
295 | */ | |
296 | if (column >= iniArr->ia_columns) | |
297 | column = 1; | |
298 | ||
299 | for (i = 0; i < iniArr->ia_rows; i++) { | |
300 | u32 reg = INI_RA(iniArr, i, 0); | |
301 | u32 val = INI_RA(iniArr, i, column); | |
302 | ||
303 | REG_WRITE(ah, reg, val); | |
304 | ||
305 | /* | |
306 | * Determine if this is a shift register value, and insert the | |
307 | * configured delay if so. | |
308 | */ | |
309 | if (reg >= 0x16000 && reg < 0x17000 | |
310 | && ah->config.analog_shiftreg) | |
311 | udelay(100); | |
312 | ||
313 | DO_DELAY(regWrites); | |
314 | } | |
315 | } | |
316 | ||
8525f280 LR |
317 | static int ar9003_hw_process_ini(struct ath_hw *ah, |
318 | struct ath9k_channel *chan) | |
319 | { | |
cffb5e49 LR |
320 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
321 | unsigned int regWrites = 0, i; | |
322 | struct ieee80211_channel *channel = chan->chan; | |
323 | u32 modesIndex, freqIndex; | |
324 | ||
325 | switch (chan->chanmode) { | |
326 | case CHANNEL_A: | |
327 | case CHANNEL_A_HT20: | |
328 | modesIndex = 1; | |
329 | freqIndex = 1; | |
330 | break; | |
331 | case CHANNEL_A_HT40PLUS: | |
332 | case CHANNEL_A_HT40MINUS: | |
333 | modesIndex = 2; | |
334 | freqIndex = 1; | |
335 | break; | |
336 | case CHANNEL_G: | |
337 | case CHANNEL_G_HT20: | |
338 | case CHANNEL_B: | |
339 | modesIndex = 4; | |
340 | freqIndex = 2; | |
341 | break; | |
342 | case CHANNEL_G_HT40PLUS: | |
343 | case CHANNEL_G_HT40MINUS: | |
344 | modesIndex = 3; | |
345 | freqIndex = 2; | |
346 | break; | |
347 | ||
348 | default: | |
349 | return -EINVAL; | |
350 | } | |
351 | ||
352 | for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { | |
353 | ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); | |
354 | ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); | |
355 | ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); | |
356 | ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); | |
357 | } | |
358 | ||
359 | REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); | |
360 | REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); | |
361 | ||
362 | /* | |
363 | * For 5GHz channels requiring Fast Clock, apply | |
364 | * different modal values. | |
365 | */ | |
366 | if (IS_CHAN_A_5MHZ_SPACED(chan)) | |
367 | REG_WRITE_ARRAY(&ah->iniModesAdditional, | |
368 | modesIndex, regWrites); | |
369 | ||
370 | ar9003_hw_override_ini(ah); | |
371 | ar9003_hw_set_channel_regs(ah, chan); | |
372 | ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); | |
373 | ||
374 | /* Set TX power */ | |
375 | ah->eep_ops->set_txpower(ah, chan, | |
376 | ath9k_regd_get_ctl(regulatory, chan), | |
377 | channel->max_antenna_gain * 2, | |
378 | channel->max_power * 2, | |
379 | min((u32) MAX_RATE_POWER, | |
380 | (u32) regulatory->power_limit)); | |
381 | ||
382 | return 0; | |
8525f280 LR |
383 | } |
384 | ||
385 | static void ar9003_hw_set_rfmode(struct ath_hw *ah, | |
386 | struct ath9k_channel *chan) | |
387 | { | |
388 | /* TODO */ | |
389 | } | |
390 | ||
391 | static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) | |
392 | { | |
393 | /* TODO */ | |
394 | } | |
395 | ||
396 | static void ar9003_hw_set_delta_slope(struct ath_hw *ah, | |
397 | struct ath9k_channel *chan) | |
398 | { | |
399 | /* TODO */ | |
400 | } | |
401 | ||
402 | static bool ar9003_hw_rfbus_req(struct ath_hw *ah) | |
403 | { | |
404 | /* TODO */ | |
405 | return false; | |
406 | } | |
407 | ||
408 | static void ar9003_hw_rfbus_done(struct ath_hw *ah) | |
409 | { | |
410 | /* TODO */ | |
411 | } | |
412 | ||
413 | static void ar9003_hw_enable_rfkill(struct ath_hw *ah) | |
414 | { | |
415 | /* TODO */ | |
416 | } | |
417 | ||
418 | static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value) | |
419 | { | |
420 | /* TODO */ | |
421 | } | |
422 | ||
c16fcb49 FF |
423 | static bool ar9003_hw_ani_control(struct ath_hw *ah, |
424 | enum ath9k_ani_cmd cmd, int param) | |
425 | { | |
426 | /* TODO */ | |
427 | return false; | |
428 | } | |
429 | ||
8525f280 LR |
430 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah) |
431 | { | |
432 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
433 | ||
434 | priv_ops->rf_set_freq = ar9003_hw_set_channel; | |
435 | priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; | |
436 | priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; | |
437 | priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; | |
438 | priv_ops->init_bb = ar9003_hw_init_bb; | |
439 | priv_ops->process_ini = ar9003_hw_process_ini; | |
440 | priv_ops->set_rfmode = ar9003_hw_set_rfmode; | |
441 | priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; | |
442 | priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; | |
443 | priv_ops->rfbus_req = ar9003_hw_rfbus_req; | |
444 | priv_ops->rfbus_done = ar9003_hw_rfbus_done; | |
445 | priv_ops->enable_rfkill = ar9003_hw_enable_rfkill; | |
446 | priv_ops->set_diversity = ar9003_hw_set_diversity; | |
c16fcb49 | 447 | priv_ops->ani_control = ar9003_hw_ani_control; |
8525f280 | 448 | } |