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8525f280 LR |
1 | /* |
2 | * Copyright (c) 2010 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "hw.h" | |
da6f1d7f | 18 | #include "ar9003_phy.h" |
8525f280 | 19 | |
e36b27af LR |
20 | static const int firstep_table[] = |
21 | /* level: 0 1 2 3 4 5 6 7 8 */ | |
22 | { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ | |
23 | ||
24 | static const int cycpwrThr1_table[] = | |
25 | /* level: 0 1 2 3 4 5 6 7 8 */ | |
26 | { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ | |
27 | ||
28 | /* | |
29 | * register values to turn OFDM weak signal detection OFF | |
30 | */ | |
31 | static const int m1ThreshLow_off = 127; | |
32 | static const int m2ThreshLow_off = 127; | |
33 | static const int m1Thresh_off = 127; | |
34 | static const int m2Thresh_off = 127; | |
35 | static const int m2CountThr_off = 31; | |
36 | static const int m2CountThrLow_off = 63; | |
37 | static const int m1ThreshLowExt_off = 127; | |
38 | static const int m2ThreshLowExt_off = 127; | |
39 | static const int m1ThreshExt_off = 127; | |
40 | static const int m2ThreshExt_off = 127; | |
41 | ||
8525f280 LR |
42 | /** |
43 | * ar9003_hw_set_channel - set channel on single-chip device | |
44 | * @ah: atheros hardware structure | |
45 | * @chan: | |
46 | * | |
47 | * This is the function to change channel on single-chip devices, that is | |
48 | * all devices after ar9280. | |
49 | * | |
50 | * This function takes the channel value in MHz and sets | |
51 | * hardware channel value. Assumes writes have been enabled to analog bus. | |
52 | * | |
53 | * Actual Expression, | |
54 | * | |
55 | * For 2GHz channel, | |
56 | * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) | |
57 | * (freq_ref = 40MHz) | |
58 | * | |
59 | * For 5GHz channel, | |
60 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) | |
61 | * (freq_ref = 40MHz/(24>>amodeRefSel)) | |
62 | * | |
63 | * For 5GHz channels which are 5MHz spaced, | |
64 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) | |
65 | * (freq_ref = 40MHz) | |
66 | */ | |
67 | static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) | |
68 | { | |
f7abf0c1 FF |
69 | u16 bMode, fracMode = 0, aModeRefSel = 0; |
70 | u32 freq, channelSel = 0, reg32 = 0; | |
71 | struct chan_centers centers; | |
72 | int loadSynthChannel; | |
73 | ||
74 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
75 | freq = centers.synth_center; | |
76 | ||
77 | if (freq < 4800) { /* 2 GHz, fractional mode */ | |
85dd0921 VT |
78 | if (AR_SREV_9485(ah)) |
79 | channelSel = CHANSEL_2G_9485(freq); | |
80 | else | |
81 | channelSel = CHANSEL_2G(freq); | |
f7abf0c1 FF |
82 | /* Set to 2G mode */ |
83 | bMode = 1; | |
84 | } else { | |
85 | channelSel = CHANSEL_5G(freq); | |
86 | /* Doubler is ON, so, divide channelSel by 2. */ | |
87 | channelSel >>= 1; | |
88 | /* Set to 5G mode */ | |
89 | bMode = 0; | |
90 | } | |
91 | ||
92 | /* Enable fractional mode for all channels */ | |
93 | fracMode = 1; | |
94 | aModeRefSel = 0; | |
95 | loadSynthChannel = 0; | |
96 | ||
97 | reg32 = (bMode << 29); | |
98 | REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); | |
99 | ||
100 | /* Enable Long shift Select for Synthesizer */ | |
101 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, | |
102 | AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); | |
103 | ||
104 | /* Program Synth. setting */ | |
105 | reg32 = (channelSel << 2) | (fracMode << 30) | | |
106 | (aModeRefSel << 28) | (loadSynthChannel << 31); | |
107 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); | |
108 | ||
109 | /* Toggle Load Synth channel bit */ | |
110 | loadSynthChannel = 1; | |
111 | reg32 = (channelSel << 2) | (fracMode << 30) | | |
112 | (aModeRefSel << 28) | (loadSynthChannel << 31); | |
113 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); | |
114 | ||
115 | ah->curchan = chan; | |
116 | ah->curchan_rad_index = -1; | |
117 | ||
8525f280 LR |
118 | return 0; |
119 | } | |
120 | ||
121 | /** | |
e36b27af | 122 | * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency |
8525f280 LR |
123 | * @ah: atheros hardware structure |
124 | * @chan: | |
125 | * | |
126 | * For single-chip solutions. Converts to baseband spur frequency given the | |
127 | * input channel frequency and compute register settings below. | |
128 | * | |
129 | * Spur mitigation for MRC CCK | |
130 | */ | |
1547da37 LR |
131 | static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, |
132 | struct ath9k_channel *chan) | |
8525f280 | 133 | { |
07b2fa5a | 134 | static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; |
ca375554 FF |
135 | int cur_bb_spur, negative = 0, cck_spur_freq; |
136 | int i; | |
d9a2545a VT |
137 | int range, max_spur_cnts, synth_freq; |
138 | u8 *spur_fbin_ptr = NULL; | |
ca375554 FF |
139 | |
140 | /* | |
141 | * Need to verify range +/- 10 MHz in control channel, otherwise spur | |
142 | * is out-of-band and can be ignored. | |
143 | */ | |
144 | ||
d9a2545a VT |
145 | if (AR_SREV_9485(ah)) { |
146 | spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, | |
147 | IS_CHAN_2GHZ(chan)); | |
148 | if (spur_fbin_ptr[0] == 0) /* No spur */ | |
149 | return; | |
150 | max_spur_cnts = 5; | |
151 | if (IS_CHAN_HT40(chan)) { | |
152 | range = 19; | |
153 | if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, | |
154 | AR_PHY_GC_DYN2040_PRI_CH) == 0) | |
155 | synth_freq = chan->channel + 10; | |
156 | else | |
157 | synth_freq = chan->channel - 10; | |
158 | } else { | |
159 | range = 10; | |
160 | synth_freq = chan->channel; | |
161 | } | |
162 | } else { | |
163 | range = 10; | |
164 | max_spur_cnts = 4; | |
165 | synth_freq = chan->channel; | |
166 | } | |
167 | ||
168 | for (i = 0; i < max_spur_cnts; i++) { | |
ca375554 | 169 | negative = 0; |
d9a2545a VT |
170 | if (AR_SREV_9485(ah)) |
171 | cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i], | |
172 | IS_CHAN_2GHZ(chan)) - synth_freq; | |
173 | else | |
174 | cur_bb_spur = spur_freq[i] - synth_freq; | |
ca375554 FF |
175 | |
176 | if (cur_bb_spur < 0) { | |
177 | negative = 1; | |
178 | cur_bb_spur = -cur_bb_spur; | |
179 | } | |
d9a2545a | 180 | if (cur_bb_spur < range) { |
ca375554 FF |
181 | cck_spur_freq = (int)((cur_bb_spur << 19) / 11); |
182 | ||
183 | if (negative == 1) | |
184 | cck_spur_freq = -cck_spur_freq; | |
185 | ||
186 | cck_spur_freq = cck_spur_freq & 0xfffff; | |
187 | ||
188 | REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, | |
189 | AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); | |
190 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
191 | AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); | |
192 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
193 | AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, | |
194 | 0x2); | |
195 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
196 | AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, | |
197 | 0x1); | |
198 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
199 | AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, | |
200 | cck_spur_freq); | |
201 | ||
202 | return; | |
203 | } | |
204 | } | |
205 | ||
206 | REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, | |
207 | AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); | |
208 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
209 | AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); | |
210 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
211 | AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); | |
8525f280 LR |
212 | } |
213 | ||
1547da37 LR |
214 | /* Clean all spur register fields */ |
215 | static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) | |
216 | { | |
217 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | |
218 | AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0); | |
219 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | |
220 | AR_PHY_TIMING11_SPUR_FREQ_SD, 0); | |
221 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | |
222 | AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); | |
223 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | |
224 | AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0); | |
225 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | |
226 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0); | |
227 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | |
228 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0); | |
229 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | |
230 | AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0); | |
231 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | |
232 | AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0); | |
233 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | |
234 | AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0); | |
235 | ||
236 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | |
237 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0); | |
238 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | |
239 | AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0); | |
240 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | |
241 | AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0); | |
242 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, | |
243 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0); | |
244 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, | |
245 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0); | |
246 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, | |
247 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0); | |
248 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, | |
249 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0); | |
250 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, | |
251 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0); | |
252 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, | |
253 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0); | |
254 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | |
255 | AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); | |
256 | } | |
257 | ||
258 | static void ar9003_hw_spur_ofdm(struct ath_hw *ah, | |
259 | int freq_offset, | |
260 | int spur_freq_sd, | |
261 | int spur_delta_phase, | |
262 | int spur_subchannel_sd) | |
263 | { | |
264 | int mask_index = 0; | |
265 | ||
266 | /* OFDM Spur mitigation */ | |
267 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | |
268 | AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1); | |
269 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | |
270 | AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd); | |
271 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | |
272 | AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase); | |
273 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | |
274 | AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd); | |
275 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | |
276 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); | |
277 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, | |
278 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1); | |
279 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | |
280 | AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); | |
281 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | |
282 | AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34); | |
283 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | |
284 | AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1); | |
285 | ||
286 | if (REG_READ_FIELD(ah, AR_PHY_MODE, | |
287 | AR_PHY_MODE_DYNAMIC) == 0x1) | |
288 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | |
289 | AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1); | |
290 | ||
291 | mask_index = (freq_offset << 4) / 5; | |
292 | if (mask_index < 0) | |
293 | mask_index = mask_index - 1; | |
294 | ||
295 | mask_index = mask_index & 0x7f; | |
296 | ||
297 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | |
298 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1); | |
299 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | |
300 | AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1); | |
301 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, | |
302 | AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1); | |
303 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, | |
304 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index); | |
305 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, | |
306 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index); | |
307 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, | |
308 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index); | |
309 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, | |
310 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc); | |
311 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, | |
312 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc); | |
313 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, | |
314 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); | |
315 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, | |
316 | AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); | |
317 | } | |
318 | ||
319 | static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, | |
320 | struct ath9k_channel *chan, | |
321 | int freq_offset) | |
322 | { | |
323 | int spur_freq_sd = 0; | |
324 | int spur_subchannel_sd = 0; | |
325 | int spur_delta_phase = 0; | |
326 | ||
327 | if (IS_CHAN_HT40(chan)) { | |
328 | if (freq_offset < 0) { | |
329 | if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, | |
330 | AR_PHY_GC_DYN2040_PRI_CH) == 0x0) | |
331 | spur_subchannel_sd = 1; | |
332 | else | |
333 | spur_subchannel_sd = 0; | |
334 | ||
335 | spur_freq_sd = ((freq_offset + 10) << 9) / 11; | |
336 | ||
337 | } else { | |
338 | if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, | |
339 | AR_PHY_GC_DYN2040_PRI_CH) == 0x0) | |
340 | spur_subchannel_sd = 0; | |
341 | else | |
342 | spur_subchannel_sd = 1; | |
343 | ||
344 | spur_freq_sd = ((freq_offset - 10) << 9) / 11; | |
345 | ||
346 | } | |
347 | ||
348 | spur_delta_phase = (freq_offset << 17) / 5; | |
349 | ||
350 | } else { | |
351 | spur_subchannel_sd = 0; | |
352 | spur_freq_sd = (freq_offset << 9) /11; | |
353 | spur_delta_phase = (freq_offset << 18) / 5; | |
354 | } | |
355 | ||
356 | spur_freq_sd = spur_freq_sd & 0x3ff; | |
357 | spur_delta_phase = spur_delta_phase & 0xfffff; | |
358 | ||
359 | ar9003_hw_spur_ofdm(ah, | |
360 | freq_offset, | |
361 | spur_freq_sd, | |
362 | spur_delta_phase, | |
363 | spur_subchannel_sd); | |
364 | } | |
365 | ||
366 | /* Spur mitigation for OFDM */ | |
367 | static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, | |
368 | struct ath9k_channel *chan) | |
369 | { | |
370 | int synth_freq; | |
371 | int range = 10; | |
372 | int freq_offset = 0; | |
373 | int mode; | |
374 | u8* spurChansPtr; | |
375 | unsigned int i; | |
376 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; | |
377 | ||
378 | if (IS_CHAN_5GHZ(chan)) { | |
379 | spurChansPtr = &(eep->modalHeader5G.spurChans[0]); | |
380 | mode = 0; | |
381 | } | |
382 | else { | |
383 | spurChansPtr = &(eep->modalHeader2G.spurChans[0]); | |
384 | mode = 1; | |
385 | } | |
386 | ||
387 | if (spurChansPtr[0] == 0) | |
388 | return; /* No spur in the mode */ | |
389 | ||
390 | if (IS_CHAN_HT40(chan)) { | |
391 | range = 19; | |
392 | if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, | |
393 | AR_PHY_GC_DYN2040_PRI_CH) == 0x0) | |
394 | synth_freq = chan->channel - 10; | |
395 | else | |
396 | synth_freq = chan->channel + 10; | |
397 | } else { | |
398 | range = 10; | |
399 | synth_freq = chan->channel; | |
400 | } | |
401 | ||
402 | ar9003_hw_spur_ofdm_clear(ah); | |
403 | ||
404 | for (i = 0; spurChansPtr[i] && i < 5; i++) { | |
405 | freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq; | |
406 | if (abs(freq_offset) < range) { | |
407 | ar9003_hw_spur_ofdm_work(ah, chan, freq_offset); | |
408 | break; | |
409 | } | |
410 | } | |
411 | } | |
412 | ||
413 | static void ar9003_hw_spur_mitigate(struct ath_hw *ah, | |
414 | struct ath9k_channel *chan) | |
415 | { | |
416 | ar9003_hw_spur_mitigate_mrc_cck(ah, chan); | |
417 | ar9003_hw_spur_mitigate_ofdm(ah, chan); | |
418 | } | |
419 | ||
8525f280 LR |
420 | static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, |
421 | struct ath9k_channel *chan) | |
422 | { | |
317d3328 FF |
423 | u32 pll; |
424 | ||
425 | pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); | |
426 | ||
427 | if (chan && IS_CHAN_HALF_RATE(chan)) | |
428 | pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); | |
429 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
430 | pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); | |
431 | ||
14bc1104 | 432 | pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); |
317d3328 FF |
433 | |
434 | return pll; | |
8525f280 LR |
435 | } |
436 | ||
437 | static void ar9003_hw_set_channel_regs(struct ath_hw *ah, | |
438 | struct ath9k_channel *chan) | |
439 | { | |
cffb5e49 LR |
440 | u32 phymode; |
441 | u32 enableDacFifo = 0; | |
442 | ||
443 | enableDacFifo = | |
444 | (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); | |
445 | ||
446 | /* Enable 11n HT, 20 MHz */ | |
447 | phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH | | |
448 | AR_PHY_GC_SHORT_GI_40 | enableDacFifo; | |
449 | ||
450 | /* Configure baseband for dynamic 20/40 operation */ | |
451 | if (IS_CHAN_HT40(chan)) { | |
452 | phymode |= AR_PHY_GC_DYN2040_EN; | |
453 | /* Configure control (primary) channel at +-10MHz */ | |
454 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || | |
455 | (chan->chanmode == CHANNEL_G_HT40PLUS)) | |
456 | phymode |= AR_PHY_GC_DYN2040_PRI_CH; | |
457 | ||
458 | } | |
459 | ||
460 | /* make sure we preserve INI settings */ | |
461 | phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); | |
462 | /* turn off Green Field detection for STA for now */ | |
463 | phymode &= ~AR_PHY_GC_GF_DETECT_EN; | |
464 | ||
465 | REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); | |
466 | ||
467 | /* Configure MAC for 20/40 operation */ | |
468 | ath9k_hw_set11nmac2040(ah); | |
469 | ||
470 | /* global transmit timeout (25 TUs default)*/ | |
471 | REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); | |
472 | /* carrier sense timeout */ | |
473 | REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); | |
8525f280 LR |
474 | } |
475 | ||
476 | static void ar9003_hw_init_bb(struct ath_hw *ah, | |
477 | struct ath9k_channel *chan) | |
478 | { | |
af914a9f LR |
479 | u32 synthDelay; |
480 | ||
481 | /* | |
482 | * Wait for the frequency synth to settle (synth goes on | |
483 | * via AR_PHY_ACTIVE_EN). Read the phy active delay register. | |
484 | * Value is in 100ns increments. | |
485 | */ | |
486 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; | |
487 | if (IS_CHAN_B(chan)) | |
488 | synthDelay = (4 * synthDelay) / 22; | |
489 | else | |
490 | synthDelay /= 10; | |
491 | ||
492 | /* Activate the PHY (includes baseband activate + synthesizer on) */ | |
493 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); | |
494 | ||
495 | /* | |
496 | * There is an issue if the AP starts the calibration before | |
497 | * the base band timeout completes. This could result in the | |
498 | * rx_clear false triggering. As a workaround we add delay an | |
499 | * extra BASE_ACTIVATE_DELAY usecs to ensure this condition | |
500 | * does not happen. | |
501 | */ | |
502 | udelay(synthDelay + BASE_ACTIVATE_DELAY); | |
8525f280 LR |
503 | } |
504 | ||
cffb5e49 LR |
505 | void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) |
506 | { | |
507 | switch (rx) { | |
508 | case 0x5: | |
509 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
510 | AR_PHY_SWAP_ALT_CHAIN); | |
511 | case 0x3: | |
512 | case 0x1: | |
513 | case 0x2: | |
514 | case 0x7: | |
515 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); | |
516 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); | |
517 | break; | |
518 | default: | |
519 | break; | |
520 | } | |
521 | ||
ea066d5a MSS |
522 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) |
523 | REG_WRITE(ah, AR_SELFGEN_MASK, 0x3); | |
524 | else | |
525 | REG_WRITE(ah, AR_SELFGEN_MASK, tx); | |
526 | ||
cffb5e49 LR |
527 | if (tx == 0x5) { |
528 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, | |
529 | AR_PHY_SWAP_ALT_CHAIN); | |
530 | } | |
531 | } | |
532 | ||
533 | /* | |
534 | * Override INI values with chip specific configuration. | |
535 | */ | |
536 | static void ar9003_hw_override_ini(struct ath_hw *ah) | |
537 | { | |
538 | u32 val; | |
539 | ||
540 | /* | |
541 | * Set the RX_ABORT and RX_DIS and clear it only after | |
542 | * RXE is set for MAC. This prevents frames with | |
543 | * corrupted descriptor status. | |
544 | */ | |
545 | REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); | |
546 | ||
547 | /* | |
548 | * For AR9280 and above, there is a new feature that allows | |
549 | * Multicast search based on both MAC Address and Key ID. By default, | |
550 | * this feature is enabled. But since the driver is not using this | |
551 | * feature, we switch it off; otherwise multicast search based on | |
552 | * MAC addr only will fail. | |
553 | */ | |
554 | val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); | |
555 | REG_WRITE(ah, AR_PCU_MISC_MODE2, | |
556 | val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE); | |
557 | } | |
558 | ||
559 | static void ar9003_hw_prog_ini(struct ath_hw *ah, | |
560 | struct ar5416IniArray *iniArr, | |
561 | int column) | |
562 | { | |
563 | unsigned int i, regWrites = 0; | |
564 | ||
565 | /* New INI format: Array may be undefined (pre, core, post arrays) */ | |
566 | if (!iniArr->ia_array) | |
567 | return; | |
568 | ||
569 | /* | |
570 | * New INI format: Pre, core, and post arrays for a given subsystem | |
571 | * may be modal (> 2 columns) or non-modal (2 columns). Determine if | |
572 | * the array is non-modal and force the column to 1. | |
573 | */ | |
574 | if (column >= iniArr->ia_columns) | |
575 | column = 1; | |
576 | ||
577 | for (i = 0; i < iniArr->ia_rows; i++) { | |
578 | u32 reg = INI_RA(iniArr, i, 0); | |
579 | u32 val = INI_RA(iniArr, i, column); | |
580 | ||
b2ccc507 FF |
581 | if (reg >= 0x16000 && reg < 0x17000) |
582 | ath9k_hw_analog_shift_regwrite(ah, reg, val); | |
583 | else | |
584 | REG_WRITE(ah, reg, val); | |
585 | ||
cffb5e49 LR |
586 | DO_DELAY(regWrites); |
587 | } | |
588 | } | |
589 | ||
8525f280 LR |
590 | static int ar9003_hw_process_ini(struct ath_hw *ah, |
591 | struct ath9k_channel *chan) | |
592 | { | |
cffb5e49 LR |
593 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
594 | unsigned int regWrites = 0, i; | |
595 | struct ieee80211_channel *channel = chan->chan; | |
596 | u32 modesIndex, freqIndex; | |
597 | ||
598 | switch (chan->chanmode) { | |
599 | case CHANNEL_A: | |
600 | case CHANNEL_A_HT20: | |
601 | modesIndex = 1; | |
602 | freqIndex = 1; | |
603 | break; | |
604 | case CHANNEL_A_HT40PLUS: | |
605 | case CHANNEL_A_HT40MINUS: | |
606 | modesIndex = 2; | |
607 | freqIndex = 1; | |
608 | break; | |
609 | case CHANNEL_G: | |
610 | case CHANNEL_G_HT20: | |
611 | case CHANNEL_B: | |
612 | modesIndex = 4; | |
613 | freqIndex = 2; | |
614 | break; | |
615 | case CHANNEL_G_HT40PLUS: | |
616 | case CHANNEL_G_HT40MINUS: | |
617 | modesIndex = 3; | |
618 | freqIndex = 2; | |
619 | break; | |
620 | ||
621 | default: | |
622 | return -EINVAL; | |
623 | } | |
624 | ||
625 | for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { | |
626 | ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); | |
627 | ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); | |
628 | ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); | |
629 | ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); | |
630 | } | |
631 | ||
632 | REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); | |
633 | REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); | |
634 | ||
635 | /* | |
636 | * For 5GHz channels requiring Fast Clock, apply | |
637 | * different modal values. | |
638 | */ | |
6b42e8d0 | 639 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
cffb5e49 LR |
640 | REG_WRITE_ARRAY(&ah->iniModesAdditional, |
641 | modesIndex, regWrites); | |
642 | ||
643 | ar9003_hw_override_ini(ah); | |
644 | ar9003_hw_set_channel_regs(ah, chan); | |
645 | ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); | |
646 | ||
647 | /* Set TX power */ | |
648 | ah->eep_ops->set_txpower(ah, chan, | |
649 | ath9k_regd_get_ctl(regulatory, chan), | |
650 | channel->max_antenna_gain * 2, | |
651 | channel->max_power * 2, | |
652 | min((u32) MAX_RATE_POWER, | |
de40f316 | 653 | (u32) regulatory->power_limit), false); |
cffb5e49 LR |
654 | |
655 | return 0; | |
8525f280 LR |
656 | } |
657 | ||
658 | static void ar9003_hw_set_rfmode(struct ath_hw *ah, | |
659 | struct ath9k_channel *chan) | |
660 | { | |
af914a9f LR |
661 | u32 rfMode = 0; |
662 | ||
663 | if (chan == NULL) | |
664 | return; | |
665 | ||
666 | rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan)) | |
667 | ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; | |
668 | ||
6b42e8d0 | 669 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
af914a9f LR |
670 | rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); |
671 | ||
672 | REG_WRITE(ah, AR_PHY_MODE, rfMode); | |
8525f280 LR |
673 | } |
674 | ||
675 | static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) | |
676 | { | |
af914a9f | 677 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); |
8525f280 LR |
678 | } |
679 | ||
680 | static void ar9003_hw_set_delta_slope(struct ath_hw *ah, | |
681 | struct ath9k_channel *chan) | |
682 | { | |
af914a9f LR |
683 | u32 coef_scaled, ds_coef_exp, ds_coef_man; |
684 | u32 clockMhzScaled = 0x64000000; | |
685 | struct chan_centers centers; | |
686 | ||
687 | /* | |
688 | * half and quarter rate can divide the scaled clock by 2 or 4 | |
689 | * scale for selected channel bandwidth | |
690 | */ | |
691 | if (IS_CHAN_HALF_RATE(chan)) | |
692 | clockMhzScaled = clockMhzScaled >> 1; | |
693 | else if (IS_CHAN_QUARTER_RATE(chan)) | |
694 | clockMhzScaled = clockMhzScaled >> 2; | |
695 | ||
696 | /* | |
697 | * ALGO -> coef = 1e8/fcarrier*fclock/40; | |
698 | * scaled coef to provide precision for this floating calculation | |
699 | */ | |
700 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
701 | coef_scaled = clockMhzScaled / centers.synth_center; | |
702 | ||
703 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | |
704 | &ds_coef_exp); | |
705 | ||
706 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | |
707 | AR_PHY_TIMING3_DSC_MAN, ds_coef_man); | |
708 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, | |
709 | AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); | |
710 | ||
711 | /* | |
712 | * For Short GI, | |
713 | * scaled coeff is 9/10 that of normal coeff | |
714 | */ | |
715 | coef_scaled = (9 * coef_scaled) / 10; | |
716 | ||
717 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, | |
718 | &ds_coef_exp); | |
719 | ||
720 | /* for short gi */ | |
721 | REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, | |
722 | AR_PHY_SGI_DSC_MAN, ds_coef_man); | |
723 | REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, | |
724 | AR_PHY_SGI_DSC_EXP, ds_coef_exp); | |
8525f280 LR |
725 | } |
726 | ||
727 | static bool ar9003_hw_rfbus_req(struct ath_hw *ah) | |
728 | { | |
af914a9f LR |
729 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); |
730 | return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, | |
731 | AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); | |
8525f280 LR |
732 | } |
733 | ||
af914a9f LR |
734 | /* |
735 | * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). | |
736 | * Read the phy active delay register. Value is in 100ns increments. | |
737 | */ | |
8525f280 LR |
738 | static void ar9003_hw_rfbus_done(struct ath_hw *ah) |
739 | { | |
af914a9f LR |
740 | u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; |
741 | if (IS_CHAN_B(ah->curchan)) | |
742 | synthDelay = (4 * synthDelay) / 22; | |
743 | else | |
744 | synthDelay /= 10; | |
745 | ||
746 | udelay(synthDelay + BASE_ACTIVATE_DELAY); | |
747 | ||
748 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); | |
8525f280 LR |
749 | } |
750 | ||
af914a9f LR |
751 | /* |
752 | * Set the interrupt and GPIO values so the ISR can disable RF | |
753 | * on a switch signal. Assumes GPIO port and interrupt polarity | |
754 | * are set prior to call. | |
755 | */ | |
8525f280 LR |
756 | static void ar9003_hw_enable_rfkill(struct ath_hw *ah) |
757 | { | |
af914a9f LR |
758 | /* Connect rfsilent_bb_l to baseband */ |
759 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, | |
760 | AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); | |
761 | /* Set input mux for rfsilent_bb_l to GPIO #0 */ | |
762 | REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2, | |
763 | AR_GPIO_INPUT_MUX2_RFSILENT); | |
764 | ||
765 | /* | |
766 | * Configure the desired GPIO port for input and | |
767 | * enable baseband rf silence. | |
768 | */ | |
769 | ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); | |
770 | REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); | |
8525f280 LR |
771 | } |
772 | ||
773 | static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value) | |
774 | { | |
af914a9f LR |
775 | u32 v = REG_READ(ah, AR_PHY_CCK_DETECT); |
776 | if (value) | |
777 | v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; | |
778 | else | |
779 | v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; | |
780 | REG_WRITE(ah, AR_PHY_CCK_DETECT, v); | |
8525f280 LR |
781 | } |
782 | ||
c16fcb49 FF |
783 | static bool ar9003_hw_ani_control(struct ath_hw *ah, |
784 | enum ath9k_ani_cmd cmd, int param) | |
785 | { | |
af914a9f | 786 | struct ath_common *common = ath9k_hw_common(ah); |
e36b27af | 787 | struct ath9k_channel *chan = ah->curchan; |
093115b7 | 788 | struct ar5416AniState *aniState = &chan->ani; |
e36b27af | 789 | s32 value, value2; |
af914a9f LR |
790 | |
791 | switch (cmd & ah->ani_function) { | |
af914a9f | 792 | case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ |
e36b27af LR |
793 | /* |
794 | * on == 1 means ofdm weak signal detection is ON | |
795 | * on == 1 is the default, for less noise immunity | |
796 | * | |
797 | * on == 0 means ofdm weak signal detection is OFF | |
798 | * on == 0 means more noise imm | |
799 | */ | |
af914a9f | 800 | u32 on = param ? 1 : 0; |
e36b27af LR |
801 | /* |
802 | * make register setting for default | |
803 | * (weak sig detect ON) come from INI file | |
804 | */ | |
805 | int m1ThreshLow = on ? | |
806 | aniState->iniDef.m1ThreshLow : m1ThreshLow_off; | |
807 | int m2ThreshLow = on ? | |
808 | aniState->iniDef.m2ThreshLow : m2ThreshLow_off; | |
809 | int m1Thresh = on ? | |
810 | aniState->iniDef.m1Thresh : m1Thresh_off; | |
811 | int m2Thresh = on ? | |
812 | aniState->iniDef.m2Thresh : m2Thresh_off; | |
813 | int m2CountThr = on ? | |
814 | aniState->iniDef.m2CountThr : m2CountThr_off; | |
815 | int m2CountThrLow = on ? | |
816 | aniState->iniDef.m2CountThrLow : m2CountThrLow_off; | |
817 | int m1ThreshLowExt = on ? | |
818 | aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; | |
819 | int m2ThreshLowExt = on ? | |
820 | aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; | |
821 | int m1ThreshExt = on ? | |
822 | aniState->iniDef.m1ThreshExt : m1ThreshExt_off; | |
823 | int m2ThreshExt = on ? | |
824 | aniState->iniDef.m2ThreshExt : m2ThreshExt_off; | |
af914a9f LR |
825 | |
826 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, | |
827 | AR_PHY_SFCORR_LOW_M1_THRESH_LOW, | |
e36b27af | 828 | m1ThreshLow); |
af914a9f LR |
829 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, |
830 | AR_PHY_SFCORR_LOW_M2_THRESH_LOW, | |
e36b27af | 831 | m2ThreshLow); |
af914a9f | 832 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, |
e36b27af | 833 | AR_PHY_SFCORR_M1_THRESH, m1Thresh); |
af914a9f | 834 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, |
e36b27af | 835 | AR_PHY_SFCORR_M2_THRESH, m2Thresh); |
af914a9f | 836 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, |
e36b27af | 837 | AR_PHY_SFCORR_M2COUNT_THR, m2CountThr); |
af914a9f LR |
838 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, |
839 | AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, | |
e36b27af | 840 | m2CountThrLow); |
af914a9f LR |
841 | |
842 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, | |
e36b27af | 843 | AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt); |
af914a9f | 844 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, |
e36b27af | 845 | AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt); |
af914a9f | 846 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, |
e36b27af | 847 | AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt); |
af914a9f | 848 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, |
e36b27af | 849 | AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt); |
af914a9f LR |
850 | |
851 | if (on) | |
852 | REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, | |
853 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | |
854 | else | |
855 | REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, | |
856 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); | |
857 | ||
858 | if (!on != aniState->ofdmWeakSigDetectOff) { | |
226afe68 JP |
859 | ath_dbg(common, ATH_DBG_ANI, |
860 | "** ch %d: ofdm weak signal: %s=>%s\n", | |
861 | chan->channel, | |
862 | !aniState->ofdmWeakSigDetectOff ? | |
863 | "on" : "off", | |
864 | on ? "on" : "off"); | |
af914a9f LR |
865 | if (on) |
866 | ah->stats.ast_ani_ofdmon++; | |
867 | else | |
868 | ah->stats.ast_ani_ofdmoff++; | |
869 | aniState->ofdmWeakSigDetectOff = !on; | |
870 | } | |
871 | break; | |
872 | } | |
af914a9f | 873 | case ATH9K_ANI_FIRSTEP_LEVEL:{ |
af914a9f LR |
874 | u32 level = param; |
875 | ||
e36b27af | 876 | if (level >= ARRAY_SIZE(firstep_table)) { |
226afe68 JP |
877 | ath_dbg(common, ATH_DBG_ANI, |
878 | "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", | |
879 | level, ARRAY_SIZE(firstep_table)); | |
af914a9f LR |
880 | return false; |
881 | } | |
e36b27af LR |
882 | |
883 | /* | |
884 | * make register setting relative to default | |
885 | * from INI file & cap value | |
886 | */ | |
887 | value = firstep_table[level] - | |
888 | firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + | |
889 | aniState->iniDef.firstep; | |
890 | if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) | |
891 | value = ATH9K_SIG_FIRSTEP_SETTING_MIN; | |
892 | if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) | |
893 | value = ATH9K_SIG_FIRSTEP_SETTING_MAX; | |
af914a9f LR |
894 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, |
895 | AR_PHY_FIND_SIG_FIRSTEP, | |
e36b27af LR |
896 | value); |
897 | /* | |
898 | * we need to set first step low register too | |
899 | * make register setting relative to default | |
900 | * from INI file & cap value | |
901 | */ | |
902 | value2 = firstep_table[level] - | |
903 | firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] + | |
904 | aniState->iniDef.firstepLow; | |
905 | if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) | |
906 | value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; | |
907 | if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) | |
908 | value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; | |
909 | ||
910 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, | |
911 | AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); | |
912 | ||
913 | if (level != aniState->firstepLevel) { | |
226afe68 JP |
914 | ath_dbg(common, ATH_DBG_ANI, |
915 | "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", | |
916 | chan->channel, | |
917 | aniState->firstepLevel, | |
918 | level, | |
919 | ATH9K_ANI_FIRSTEP_LVL_NEW, | |
920 | value, | |
921 | aniState->iniDef.firstep); | |
922 | ath_dbg(common, ATH_DBG_ANI, | |
923 | "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", | |
924 | chan->channel, | |
925 | aniState->firstepLevel, | |
926 | level, | |
927 | ATH9K_ANI_FIRSTEP_LVL_NEW, | |
928 | value2, | |
929 | aniState->iniDef.firstepLow); | |
e36b27af LR |
930 | if (level > aniState->firstepLevel) |
931 | ah->stats.ast_ani_stepup++; | |
932 | else if (level < aniState->firstepLevel) | |
933 | ah->stats.ast_ani_stepdown++; | |
934 | aniState->firstepLevel = level; | |
935 | } | |
af914a9f LR |
936 | break; |
937 | } | |
938 | case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ | |
af914a9f LR |
939 | u32 level = param; |
940 | ||
e36b27af | 941 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { |
226afe68 JP |
942 | ath_dbg(common, ATH_DBG_ANI, |
943 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", | |
944 | level, ARRAY_SIZE(cycpwrThr1_table)); | |
af914a9f LR |
945 | return false; |
946 | } | |
e36b27af LR |
947 | /* |
948 | * make register setting relative to default | |
949 | * from INI file & cap value | |
950 | */ | |
951 | value = cycpwrThr1_table[level] - | |
952 | cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + | |
953 | aniState->iniDef.cycpwrThr1; | |
954 | if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) | |
955 | value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; | |
956 | if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) | |
957 | value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; | |
af914a9f LR |
958 | REG_RMW_FIELD(ah, AR_PHY_TIMING5, |
959 | AR_PHY_TIMING5_CYCPWR_THR1, | |
e36b27af LR |
960 | value); |
961 | ||
962 | /* | |
963 | * set AR_PHY_EXT_CCA for extension channel | |
964 | * make register setting relative to default | |
965 | * from INI file & cap value | |
966 | */ | |
967 | value2 = cycpwrThr1_table[level] - | |
968 | cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] + | |
969 | aniState->iniDef.cycpwrThr1Ext; | |
970 | if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) | |
971 | value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; | |
972 | if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) | |
973 | value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; | |
974 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, | |
975 | AR_PHY_EXT_CYCPWR_THR1, value2); | |
976 | ||
977 | if (level != aniState->spurImmunityLevel) { | |
226afe68 JP |
978 | ath_dbg(common, ATH_DBG_ANI, |
979 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", | |
980 | chan->channel, | |
981 | aniState->spurImmunityLevel, | |
982 | level, | |
983 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, | |
984 | value, | |
985 | aniState->iniDef.cycpwrThr1); | |
986 | ath_dbg(common, ATH_DBG_ANI, | |
987 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", | |
988 | chan->channel, | |
989 | aniState->spurImmunityLevel, | |
990 | level, | |
991 | ATH9K_ANI_SPUR_IMMUNE_LVL_NEW, | |
992 | value2, | |
993 | aniState->iniDef.cycpwrThr1Ext); | |
e36b27af LR |
994 | if (level > aniState->spurImmunityLevel) |
995 | ah->stats.ast_ani_spurup++; | |
996 | else if (level < aniState->spurImmunityLevel) | |
997 | ah->stats.ast_ani_spurdown++; | |
998 | aniState->spurImmunityLevel = level; | |
999 | } | |
af914a9f LR |
1000 | break; |
1001 | } | |
e36b27af LR |
1002 | case ATH9K_ANI_MRC_CCK:{ |
1003 | /* | |
1004 | * is_on == 1 means MRC CCK ON (default, less noise imm) | |
1005 | * is_on == 0 means MRC CCK is OFF (more noise imm) | |
1006 | */ | |
1007 | bool is_on = param ? 1 : 0; | |
1008 | REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, | |
1009 | AR_PHY_MRC_CCK_ENABLE, is_on); | |
1010 | REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, | |
1011 | AR_PHY_MRC_CCK_MUX_REG, is_on); | |
1012 | if (!is_on != aniState->mrcCCKOff) { | |
226afe68 JP |
1013 | ath_dbg(common, ATH_DBG_ANI, |
1014 | "** ch %d: MRC CCK: %s=>%s\n", | |
1015 | chan->channel, | |
1016 | !aniState->mrcCCKOff ? "on" : "off", | |
1017 | is_on ? "on" : "off"); | |
e36b27af LR |
1018 | if (is_on) |
1019 | ah->stats.ast_ani_ccklow++; | |
1020 | else | |
1021 | ah->stats.ast_ani_cckhigh++; | |
1022 | aniState->mrcCCKOff = !is_on; | |
1023 | } | |
1024 | break; | |
1025 | } | |
af914a9f LR |
1026 | case ATH9K_ANI_PRESENT: |
1027 | break; | |
1028 | default: | |
226afe68 | 1029 | ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd); |
af914a9f LR |
1030 | return false; |
1031 | } | |
1032 | ||
226afe68 JP |
1033 | ath_dbg(common, ATH_DBG_ANI, |
1034 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", | |
1035 | aniState->spurImmunityLevel, | |
1036 | !aniState->ofdmWeakSigDetectOff ? "on" : "off", | |
1037 | aniState->firstepLevel, | |
1038 | !aniState->mrcCCKOff ? "on" : "off", | |
1039 | aniState->listenTime, | |
1040 | aniState->ofdmPhyErrCount, | |
1041 | aniState->cckPhyErrCount); | |
af914a9f | 1042 | return true; |
c16fcb49 FF |
1043 | } |
1044 | ||
641d9921 FF |
1045 | static void ar9003_hw_do_getnf(struct ath_hw *ah, |
1046 | int16_t nfarray[NUM_NF_READINGS]) | |
1047 | { | |
641d9921 FF |
1048 | int16_t nf; |
1049 | ||
1050 | nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR); | |
7919a57b | 1051 | nfarray[0] = sign_extend32(nf, 8); |
641d9921 FF |
1052 | |
1053 | nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR); | |
7919a57b | 1054 | nfarray[1] = sign_extend32(nf, 8); |
641d9921 FF |
1055 | |
1056 | nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR); | |
7919a57b | 1057 | nfarray[2] = sign_extend32(nf, 8); |
641d9921 | 1058 | |
866b7780 FF |
1059 | if (!IS_CHAN_HT40(ah->curchan)) |
1060 | return; | |
1061 | ||
641d9921 | 1062 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); |
7919a57b | 1063 | nfarray[3] = sign_extend32(nf, 8); |
641d9921 FF |
1064 | |
1065 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR); | |
7919a57b | 1066 | nfarray[4] = sign_extend32(nf, 8); |
641d9921 FF |
1067 | |
1068 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR); | |
7919a57b | 1069 | nfarray[5] = sign_extend32(nf, 8); |
641d9921 FF |
1070 | } |
1071 | ||
f2552e28 | 1072 | static void ar9003_hw_set_nf_limits(struct ath_hw *ah) |
641d9921 | 1073 | { |
f2552e28 FF |
1074 | ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; |
1075 | ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; | |
1076 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; | |
1077 | ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; | |
1078 | ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; | |
1079 | ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; | |
641d9921 FF |
1080 | } |
1081 | ||
e36b27af LR |
1082 | /* |
1083 | * Initialize the ANI register values with default (ini) values. | |
1084 | * This routine is called during a (full) hardware reset after | |
1085 | * all the registers are initialised from the INI. | |
1086 | */ | |
1087 | static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) | |
1088 | { | |
1089 | struct ar5416AniState *aniState; | |
1090 | struct ath_common *common = ath9k_hw_common(ah); | |
1091 | struct ath9k_channel *chan = ah->curchan; | |
1092 | struct ath9k_ani_default *iniDef; | |
e36b27af LR |
1093 | u32 val; |
1094 | ||
093115b7 | 1095 | aniState = &ah->curchan->ani; |
e36b27af LR |
1096 | iniDef = &aniState->iniDef; |
1097 | ||
226afe68 JP |
1098 | ath_dbg(common, ATH_DBG_ANI, |
1099 | "ver %d.%d opmode %u chan %d Mhz/0x%x\n", | |
1100 | ah->hw_version.macVersion, | |
1101 | ah->hw_version.macRev, | |
1102 | ah->opmode, | |
1103 | chan->channel, | |
1104 | chan->channelFlags); | |
e36b27af LR |
1105 | |
1106 | val = REG_READ(ah, AR_PHY_SFCORR); | |
1107 | iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); | |
1108 | iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); | |
1109 | iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); | |
1110 | ||
1111 | val = REG_READ(ah, AR_PHY_SFCORR_LOW); | |
1112 | iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); | |
1113 | iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); | |
1114 | iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); | |
1115 | ||
1116 | val = REG_READ(ah, AR_PHY_SFCORR_EXT); | |
1117 | iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); | |
1118 | iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); | |
1119 | iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); | |
1120 | iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); | |
1121 | iniDef->firstep = REG_READ_FIELD(ah, | |
1122 | AR_PHY_FIND_SIG, | |
1123 | AR_PHY_FIND_SIG_FIRSTEP); | |
1124 | iniDef->firstepLow = REG_READ_FIELD(ah, | |
1125 | AR_PHY_FIND_SIG_LOW, | |
1126 | AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW); | |
1127 | iniDef->cycpwrThr1 = REG_READ_FIELD(ah, | |
1128 | AR_PHY_TIMING5, | |
1129 | AR_PHY_TIMING5_CYCPWR_THR1); | |
1130 | iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, | |
1131 | AR_PHY_EXT_CCA, | |
1132 | AR_PHY_EXT_CYCPWR_THR1); | |
1133 | ||
1134 | /* these levels just got reset to defaults by the INI */ | |
1135 | aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW; | |
1136 | aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW; | |
1137 | aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG; | |
1138 | aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK; | |
e36b27af LR |
1139 | } |
1140 | ||
4e8c14e9 FF |
1141 | static void ar9003_hw_set_radar_params(struct ath_hw *ah, |
1142 | struct ath_hw_radar_conf *conf) | |
1143 | { | |
1144 | u32 radar_0 = 0, radar_1 = 0; | |
1145 | ||
1146 | if (!conf) { | |
1147 | REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); | |
1148 | return; | |
1149 | } | |
1150 | ||
1151 | radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; | |
1152 | radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); | |
1153 | radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); | |
1154 | radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); | |
1155 | radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); | |
1156 | radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); | |
1157 | ||
1158 | radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; | |
1159 | radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; | |
1160 | radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); | |
1161 | radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); | |
1162 | radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); | |
1163 | ||
1164 | REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); | |
1165 | REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); | |
1166 | if (conf->ext_channel) | |
1167 | REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); | |
1168 | else | |
1169 | REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); | |
1170 | } | |
1171 | ||
c5d0855a FF |
1172 | static void ar9003_hw_set_radar_conf(struct ath_hw *ah) |
1173 | { | |
1174 | struct ath_hw_radar_conf *conf = &ah->radar_conf; | |
1175 | ||
1176 | conf->fir_power = -28; | |
1177 | conf->radar_rssi = 0; | |
1178 | conf->pulse_height = 10; | |
1179 | conf->pulse_rssi = 24; | |
1180 | conf->pulse_inband = 8; | |
1181 | conf->pulse_maxlen = 255; | |
1182 | conf->pulse_inband_step = 12; | |
1183 | conf->radar_inband = 8; | |
1184 | } | |
1185 | ||
8525f280 LR |
1186 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah) |
1187 | { | |
1188 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
07b2fa5a | 1189 | static const u32 ar9300_cca_regs[6] = { |
bbacee13 FF |
1190 | AR_PHY_CCA_0, |
1191 | AR_PHY_CCA_1, | |
1192 | AR_PHY_CCA_2, | |
1193 | AR_PHY_EXT_CCA, | |
1194 | AR_PHY_EXT_CCA_1, | |
1195 | AR_PHY_EXT_CCA_2, | |
1196 | }; | |
8525f280 LR |
1197 | |
1198 | priv_ops->rf_set_freq = ar9003_hw_set_channel; | |
1199 | priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; | |
1200 | priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; | |
1201 | priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; | |
1202 | priv_ops->init_bb = ar9003_hw_init_bb; | |
1203 | priv_ops->process_ini = ar9003_hw_process_ini; | |
1204 | priv_ops->set_rfmode = ar9003_hw_set_rfmode; | |
1205 | priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; | |
1206 | priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; | |
1207 | priv_ops->rfbus_req = ar9003_hw_rfbus_req; | |
1208 | priv_ops->rfbus_done = ar9003_hw_rfbus_done; | |
1209 | priv_ops->enable_rfkill = ar9003_hw_enable_rfkill; | |
1210 | priv_ops->set_diversity = ar9003_hw_set_diversity; | |
c16fcb49 | 1211 | priv_ops->ani_control = ar9003_hw_ani_control; |
641d9921 | 1212 | priv_ops->do_getnf = ar9003_hw_do_getnf; |
e36b27af | 1213 | priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; |
4e8c14e9 | 1214 | priv_ops->set_radar_params = ar9003_hw_set_radar_params; |
f2552e28 FF |
1215 | |
1216 | ar9003_hw_set_nf_limits(ah); | |
c5d0855a | 1217 | ar9003_hw_set_radar_conf(ah); |
bbacee13 | 1218 | memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); |
8525f280 | 1219 | } |
aea702b7 LR |
1220 | |
1221 | void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) | |
1222 | { | |
1223 | struct ath_common *common = ath9k_hw_common(ah); | |
1224 | u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; | |
1225 | u32 val, idle_count; | |
1226 | ||
1227 | if (!idle_tmo_ms) { | |
1228 | /* disable IRQ, disable chip-reset for BB panic */ | |
1229 | REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, | |
1230 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & | |
1231 | ~(AR_PHY_WATCHDOG_RST_ENABLE | | |
1232 | AR_PHY_WATCHDOG_IRQ_ENABLE)); | |
1233 | ||
1234 | /* disable watchdog in non-IDLE mode, disable in IDLE mode */ | |
1235 | REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, | |
1236 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & | |
1237 | ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | | |
1238 | AR_PHY_WATCHDOG_IDLE_ENABLE)); | |
1239 | ||
226afe68 | 1240 | ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n"); |
aea702b7 LR |
1241 | return; |
1242 | } | |
1243 | ||
1244 | /* enable IRQ, disable chip-reset for BB watchdog */ | |
1245 | val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; | |
1246 | REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, | |
1247 | (val | AR_PHY_WATCHDOG_IRQ_ENABLE) & | |
1248 | ~AR_PHY_WATCHDOG_RST_ENABLE); | |
1249 | ||
1250 | /* bound limit to 10 secs */ | |
1251 | if (idle_tmo_ms > 10000) | |
1252 | idle_tmo_ms = 10000; | |
1253 | ||
1254 | /* | |
1255 | * The time unit for watchdog event is 2^15 44/88MHz cycles. | |
1256 | * | |
1257 | * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick | |
1258 | * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick | |
1259 | * | |
1260 | * Given we use fast clock now in 5 GHz, these time units should | |
1261 | * be common for both 2 GHz and 5 GHz. | |
1262 | */ | |
1263 | idle_count = (100 * idle_tmo_ms) / 74; | |
1264 | if (ah->curchan && IS_CHAN_HT40(ah->curchan)) | |
1265 | idle_count = (100 * idle_tmo_ms) / 37; | |
1266 | ||
1267 | /* | |
1268 | * enable watchdog in non-IDLE mode, disable in IDLE mode, | |
1269 | * set idle time-out. | |
1270 | */ | |
1271 | REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, | |
1272 | AR_PHY_WATCHDOG_NON_IDLE_ENABLE | | |
1273 | AR_PHY_WATCHDOG_IDLE_MASK | | |
1274 | (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); | |
1275 | ||
226afe68 JP |
1276 | ath_dbg(common, ATH_DBG_RESET, |
1277 | "Enabled BB Watchdog timeout (%u ms)\n", | |
1278 | idle_tmo_ms); | |
aea702b7 LR |
1279 | } |
1280 | ||
1281 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) | |
1282 | { | |
1283 | /* | |
1284 | * we want to avoid printing in ISR context so we save the | |
1285 | * watchdog status to be printed later in bottom half context. | |
1286 | */ | |
1287 | ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); | |
1288 | ||
1289 | /* | |
1290 | * the watchdog timer should reset on status read but to be sure | |
1291 | * sure we write 0 to the watchdog status bit. | |
1292 | */ | |
1293 | REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, | |
1294 | ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); | |
1295 | } | |
1296 | ||
1297 | void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) | |
1298 | { | |
1299 | struct ath_common *common = ath9k_hw_common(ah); | |
9dbebc7f | 1300 | u32 status; |
aea702b7 LR |
1301 | |
1302 | if (likely(!(common->debug_mask & ATH_DBG_RESET))) | |
1303 | return; | |
1304 | ||
1305 | status = ah->bb_watchdog_last_status; | |
226afe68 JP |
1306 | ath_dbg(common, ATH_DBG_RESET, |
1307 | "\n==== BB update: BB status=0x%08x ====\n", status); | |
1308 | ath_dbg(common, ATH_DBG_RESET, | |
1309 | "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", | |
1310 | MS(status, AR_PHY_WATCHDOG_INFO), | |
1311 | MS(status, AR_PHY_WATCHDOG_DET_HANG), | |
1312 | MS(status, AR_PHY_WATCHDOG_RADAR_SM), | |
1313 | MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM), | |
1314 | MS(status, AR_PHY_WATCHDOG_RX_CCK_SM), | |
1315 | MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM), | |
1316 | MS(status, AR_PHY_WATCHDOG_TX_CCK_SM), | |
1317 | MS(status, AR_PHY_WATCHDOG_AGC_SM), | |
1318 | MS(status, AR_PHY_WATCHDOG_SRCH_SM)); | |
1319 | ||
1320 | ath_dbg(common, ATH_DBG_RESET, | |
1321 | "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", | |
1322 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), | |
1323 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); | |
1324 | ath_dbg(common, ATH_DBG_RESET, | |
1325 | "** BB mode: BB_gen_controls=0x%08x **\n", | |
1326 | REG_READ(ah, AR_PHY_GEN_CTRL)); | |
aea702b7 | 1327 | |
b5bfc568 FF |
1328 | #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) |
1329 | if (common->cc_survey.cycles) | |
226afe68 JP |
1330 | ath_dbg(common, ATH_DBG_RESET, |
1331 | "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n", | |
1332 | PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); | |
aea702b7 | 1333 | |
226afe68 JP |
1334 | ath_dbg(common, ATH_DBG_RESET, |
1335 | "==== BB update: done ====\n\n"); | |
aea702b7 LR |
1336 | } |
1337 | EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); |