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1 | /* |
2 | * Copyright (c) 2010 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "hw.h" | |
da6f1d7f | 18 | #include "ar9003_phy.h" |
8525f280 LR |
19 | |
20 | /** | |
21 | * ar9003_hw_set_channel - set channel on single-chip device | |
22 | * @ah: atheros hardware structure | |
23 | * @chan: | |
24 | * | |
25 | * This is the function to change channel on single-chip devices, that is | |
26 | * all devices after ar9280. | |
27 | * | |
28 | * This function takes the channel value in MHz and sets | |
29 | * hardware channel value. Assumes writes have been enabled to analog bus. | |
30 | * | |
31 | * Actual Expression, | |
32 | * | |
33 | * For 2GHz channel, | |
34 | * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) | |
35 | * (freq_ref = 40MHz) | |
36 | * | |
37 | * For 5GHz channel, | |
38 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) | |
39 | * (freq_ref = 40MHz/(24>>amodeRefSel)) | |
40 | * | |
41 | * For 5GHz channels which are 5MHz spaced, | |
42 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) | |
43 | * (freq_ref = 40MHz) | |
44 | */ | |
45 | static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) | |
46 | { | |
f7abf0c1 FF |
47 | u16 bMode, fracMode = 0, aModeRefSel = 0; |
48 | u32 freq, channelSel = 0, reg32 = 0; | |
49 | struct chan_centers centers; | |
50 | int loadSynthChannel; | |
51 | ||
52 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
53 | freq = centers.synth_center; | |
54 | ||
55 | if (freq < 4800) { /* 2 GHz, fractional mode */ | |
56 | channelSel = CHANSEL_2G(freq); | |
57 | /* Set to 2G mode */ | |
58 | bMode = 1; | |
59 | } else { | |
60 | channelSel = CHANSEL_5G(freq); | |
61 | /* Doubler is ON, so, divide channelSel by 2. */ | |
62 | channelSel >>= 1; | |
63 | /* Set to 5G mode */ | |
64 | bMode = 0; | |
65 | } | |
66 | ||
67 | /* Enable fractional mode for all channels */ | |
68 | fracMode = 1; | |
69 | aModeRefSel = 0; | |
70 | loadSynthChannel = 0; | |
71 | ||
72 | reg32 = (bMode << 29); | |
73 | REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); | |
74 | ||
75 | /* Enable Long shift Select for Synthesizer */ | |
76 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, | |
77 | AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); | |
78 | ||
79 | /* Program Synth. setting */ | |
80 | reg32 = (channelSel << 2) | (fracMode << 30) | | |
81 | (aModeRefSel << 28) | (loadSynthChannel << 31); | |
82 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); | |
83 | ||
84 | /* Toggle Load Synth channel bit */ | |
85 | loadSynthChannel = 1; | |
86 | reg32 = (channelSel << 2) | (fracMode << 30) | | |
87 | (aModeRefSel << 28) | (loadSynthChannel << 31); | |
88 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); | |
89 | ||
90 | ah->curchan = chan; | |
91 | ah->curchan_rad_index = -1; | |
92 | ||
8525f280 LR |
93 | return 0; |
94 | } | |
95 | ||
96 | /** | |
97 | * ar9003_hw_spur_mitigate - convert baseband spur frequency | |
98 | * @ah: atheros hardware structure | |
99 | * @chan: | |
100 | * | |
101 | * For single-chip solutions. Converts to baseband spur frequency given the | |
102 | * input channel frequency and compute register settings below. | |
103 | * | |
104 | * Spur mitigation for MRC CCK | |
105 | */ | |
106 | static void ar9003_hw_spur_mitigate(struct ath_hw *ah, | |
107 | struct ath9k_channel *chan) | |
108 | { | |
109 | /* TODO */ | |
110 | } | |
111 | ||
112 | static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, | |
113 | struct ath9k_channel *chan) | |
114 | { | |
115 | /* TODO */ | |
116 | return 0; | |
117 | } | |
118 | ||
119 | static void ar9003_hw_set_channel_regs(struct ath_hw *ah, | |
120 | struct ath9k_channel *chan) | |
121 | { | |
122 | /* TODO */ | |
123 | } | |
124 | ||
125 | static void ar9003_hw_init_bb(struct ath_hw *ah, | |
126 | struct ath9k_channel *chan) | |
127 | { | |
128 | /* TODO */ | |
129 | } | |
130 | ||
131 | static int ar9003_hw_process_ini(struct ath_hw *ah, | |
132 | struct ath9k_channel *chan) | |
133 | { | |
134 | /* TODO */ | |
135 | return -1; | |
136 | } | |
137 | ||
138 | static void ar9003_hw_set_rfmode(struct ath_hw *ah, | |
139 | struct ath9k_channel *chan) | |
140 | { | |
141 | /* TODO */ | |
142 | } | |
143 | ||
144 | static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) | |
145 | { | |
146 | /* TODO */ | |
147 | } | |
148 | ||
149 | static void ar9003_hw_set_delta_slope(struct ath_hw *ah, | |
150 | struct ath9k_channel *chan) | |
151 | { | |
152 | /* TODO */ | |
153 | } | |
154 | ||
155 | static bool ar9003_hw_rfbus_req(struct ath_hw *ah) | |
156 | { | |
157 | /* TODO */ | |
158 | return false; | |
159 | } | |
160 | ||
161 | static void ar9003_hw_rfbus_done(struct ath_hw *ah) | |
162 | { | |
163 | /* TODO */ | |
164 | } | |
165 | ||
166 | static void ar9003_hw_enable_rfkill(struct ath_hw *ah) | |
167 | { | |
168 | /* TODO */ | |
169 | } | |
170 | ||
171 | static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value) | |
172 | { | |
173 | /* TODO */ | |
174 | } | |
175 | ||
176 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah) | |
177 | { | |
178 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
179 | ||
180 | priv_ops->rf_set_freq = ar9003_hw_set_channel; | |
181 | priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; | |
182 | priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; | |
183 | priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; | |
184 | priv_ops->init_bb = ar9003_hw_init_bb; | |
185 | priv_ops->process_ini = ar9003_hw_process_ini; | |
186 | priv_ops->set_rfmode = ar9003_hw_set_rfmode; | |
187 | priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; | |
188 | priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; | |
189 | priv_ops->rfbus_req = ar9003_hw_rfbus_req; | |
190 | priv_ops->rfbus_done = ar9003_hw_rfbus_done; | |
191 | priv_ops->enable_rfkill = ar9003_hw_enable_rfkill; | |
192 | priv_ops->set_diversity = ar9003_hw_set_diversity; | |
193 | } |