[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_rtt.c

/*
 * Copyright (c) 2010-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include "hw.h"
#include "hw-ops.h"
#include "ar9003_phy.h"
#include "ar9003_rtt.h"

#define RTT_RESTORE_TIMEOUT          1000
#define RTT_ACCESS_TIMEOUT           100
#define RTT_BAD_VALUE                0x0bad0bad

/*
 * RTT (Radio Retention Table) hardware implementation information
 *
 * There is an internal table (i.e. the rtt) for each chain (or bank).
 * Each table contains 6 entries and each entry is corresponding to
 * a specific calibration parameter as depicted below.
 *  0~2 - DC offset DAC calibration: loop, low, high (offsetI/Q_...)
 *  3   - Filter cal (filterfc)
 *  4   - RX gain settings
 *  5   - Peak detector offset calibration (agc_caldac)
 */

void ar9003_hw_rtt_enable(struct ath_hw *ah)
{
	REG_WRITE(ah, AR_PHY_RTT_CTRL, 1);
}

void ar9003_hw_rtt_disable(struct ath_hw *ah)
{
	REG_WRITE(ah, AR_PHY_RTT_CTRL, 0);
}

void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask)
{
	REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
		      AR_PHY_RTT_CTRL_RESTORE_MASK, rtt_mask);
}

bool ar9003_hw_rtt_force_restore(struct ath_hw *ah)
{
	if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
			   AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
			   0, RTT_RESTORE_TIMEOUT))
		return false;

	REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
		      AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE, 1);

	if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
			   AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
			   0, RTT_RESTORE_TIMEOUT))
		return false;

	return true;
}

static void ar9003_hw_rtt_load_hist_entry(struct ath_hw *ah, u8 chain,
					  u32 index, u32 data28)
{
	u32 val;

	val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA);
	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val);

	val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
	      SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
	      SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
	udelay(1);

	val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
	udelay(1);

	if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
			   AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
			   RTT_ACCESS_TIMEOUT))
		return;

	val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE);
	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
	udelay(1);

	ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
		      AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
		      RTT_ACCESS_TIMEOUT);
}

void ar9003_hw_rtt_load_hist(struct ath_hw *ah)
{
	int chain, i;

	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
		if (!(ah->rxchainmask & (1 << chain)))
			continue;
		for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++) {
			ar9003_hw_rtt_load_hist_entry(ah, chain, i,
					      ah->caldata->rtt_table[chain][i]);
			ath_dbg(ath9k_hw_common(ah), CALIBRATE,
				"Load RTT value at idx %d, chain %d: 0x%x\n",
				i, chain, ah->caldata->rtt_table[chain][i]);
		}
	}
}

static int ar9003_hw_rtt_fill_hist_entry(struct ath_hw *ah, u8 chain, u32 index)
{
	u32 val;

	val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) |
	      SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) |
	      SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);

	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
	udelay(1);

	val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
	udelay(1);

	if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
			   AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
			   RTT_ACCESS_TIMEOUT))
		return RTT_BAD_VALUE;

	val = MS(REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain)),
		 AR_PHY_RTT_SW_RTT_TABLE_DATA);


	return val;
}

void ar9003_hw_rtt_fill_hist(struct ath_hw *ah)
{
	int chain, i;

	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
		if (!(ah->rxchainmask & (1 << chain)))
			continue;
		for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++) {
			ah->caldata->rtt_table[chain][i] =
				ar9003_hw_rtt_fill_hist_entry(ah, chain, i);
			ath_dbg(ath9k_hw_common(ah), CALIBRATE,
				"RTT value at idx %d, chain %d is: 0x%x\n",
				i, chain, ah->caldata->rtt_table[chain][i]);
		}
	}

	ah->caldata->rtt_done = true;
}

void ar9003_hw_rtt_clear_hist(struct ath_hw *ah)
{
	int chain, i;

	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
		if (!(ah->rxchainmask & (1 << chain)))
			continue;
		for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
			ar9003_hw_rtt_load_hist_entry(ah, chain, i, 0);
	}

	if (ah->caldata)
		ah->caldata->rtt_done = false;
}

bool ar9003_hw_rtt_restore(struct ath_hw *ah, struct ath9k_channel *chan)
{
	bool restore;

	if (!ah->caldata)
		return false;

	if (!ah->caldata->rtt_done)
		return false;

	ar9003_hw_rtt_enable(ah);
	ar9003_hw_rtt_set_mask(ah, 0x10);

	if (!ath9k_hw_rfbus_req(ah)) {
		ath_err(ath9k_hw_common(ah), "Could not stop baseband\n");
		restore = false;
		goto fail;
	}

	ar9003_hw_rtt_load_hist(ah);
	restore = ar9003_hw_rtt_force_restore(ah);

fail:
	ath9k_hw_rfbus_done(ah);
	ar9003_hw_rtt_disable(ah);
	return restore;
}
Commit	Line	Data
324c74ad RM	1	/*
	2	* Copyright (c) 2010-2011 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include "hw.h"
8a90555f	18	#include "hw-ops.h"
324c74ad	19	#include "ar9003_phy.h"
e01ff34e	20	#include "ar9003_rtt.h"
324c74ad RM	21
	22	#define RTT_RESTORE_TIMEOUT 1000
	23	#define RTT_ACCESS_TIMEOUT 100
	24	#define RTT_BAD_VALUE 0x0bad0bad
	25
	26	/*
	27	* RTT (Radio Retention Table) hardware implementation information
	28	*
	29	* There is an internal table (i.e. the rtt) for each chain (or bank).
	30	* Each table contains 6 entries and each entry is corresponding to
	31	* a specific calibration parameter as depicted below.
	32	* 0~2 - DC offset DAC calibration: loop, low, high (offsetI/Q_...)
	33	* 3 - Filter cal (filterfc)
	34	* 4 - RX gain settings
	35	* 5 - Peak detector offset calibration (agc_caldac)
	36	*/
	37
	38	void ar9003_hw_rtt_enable(struct ath_hw *ah)
	39	{
	40	REG_WRITE(ah, AR_PHY_RTT_CTRL, 1);
	41	}
	42
	43	void ar9003_hw_rtt_disable(struct ath_hw *ah)
	44	{
	45	REG_WRITE(ah, AR_PHY_RTT_CTRL, 0);
	46	}
	47
	48	void ar9003_hw_rtt_set_mask(struct ath_hw *ah, u32 rtt_mask)
	49	{
	50	REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
	51	AR_PHY_RTT_CTRL_RESTORE_MASK, rtt_mask);
	52	}
	53
	54	bool ar9003_hw_rtt_force_restore(struct ath_hw *ah)
	55	{
	56	if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
	57	AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
	58	0, RTT_RESTORE_TIMEOUT))
	59	return false;
	60
	61	REG_RMW_FIELD(ah, AR_PHY_RTT_CTRL,
	62	AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE, 1);
	63
	64	if (!ath9k_hw_wait(ah, AR_PHY_RTT_CTRL,
	65	AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE,
	66	0, RTT_RESTORE_TIMEOUT))
	67	return false;
	68
	69	return true;
	70	}
	71
	72	static void ar9003_hw_rtt_load_hist_entry(struct ath_hw *ah, u8 chain,
8a90555f	73	u32 index, u32 data28)
324c74ad RM	74	{
	75	u32 val;
	76
	77	val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA);
	78	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val);
	79
	80	val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) \|
	81	SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) \|
	82	SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
	83	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
	84	udelay(1);
	85
	86	val \|= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
	87	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
	88	udelay(1);
	89
	90	if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
	91	AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
	92	RTT_ACCESS_TIMEOUT))
	93	return;
	94
	95	val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE);
	96	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
	97	udelay(1);
	98
	99	ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
	100	AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
	101	RTT_ACCESS_TIMEOUT);
	102	}
	103
8a90555f	104	void ar9003_hw_rtt_load_hist(struct ath_hw *ah)
324c74ad	105	{
8a90555f	106	int chain, i;
324c74ad	107
8a90555f SM	108	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
	109	if (!(ah->rxchainmask & (1 << chain)))
	110	continue;
	111	for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++) {
	112	ar9003_hw_rtt_load_hist_entry(ah, chain, i,
	113	ah->caldata->rtt_table[chain][i]);
	114	ath_dbg(ath9k_hw_common(ah), CALIBRATE,
	115	"Load RTT value at idx %d, chain %d: 0x%x\n",
	116	i, chain, ah->caldata->rtt_table[chain][i]);
	117	}
	118	}
324c74ad RM	119	}
	120
	121	static int ar9003_hw_rtt_fill_hist_entry(struct ath_hw *ah, u8 chain, u32 index)
	122	{
	123	u32 val;
	124
	125	val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) \|
	126	SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) \|
	127	SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR);
	128
	129	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
	130	udelay(1);
	131
	132	val \|= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS);
	133	REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
	134	udelay(1);
	135
	136	if (!ath9k_hw_wait(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain),
	137	AR_PHY_RTT_SW_RTT_TABLE_ACCESS, 0,
	138	RTT_ACCESS_TIMEOUT))
	139	return RTT_BAD_VALUE;
	140
8a90555f SM	141	val = MS(REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain)),
	142	AR_PHY_RTT_SW_RTT_TABLE_DATA);
	143
324c74ad RM	144
	145	return val;
	146	}
	147
8a90555f	148	void ar9003_hw_rtt_fill_hist(struct ath_hw *ah)
324c74ad	149	{
8a90555f SM	150	int chain, i;
	151
	152	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
	153	if (!(ah->rxchainmask & (1 << chain)))
	154	continue;
	155	for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++) {
	156	ah->caldata->rtt_table[chain][i] =
	157	ar9003_hw_rtt_fill_hist_entry(ah, chain, i);
	158	ath_dbg(ath9k_hw_common(ah), CALIBRATE,
	159	"RTT value at idx %d, chain %d is: 0x%x\n",
	160	i, chain, ah->caldata->rtt_table[chain][i]);
	161	}
	162	}
324c74ad	163
8a90555f	164	ah->caldata->rtt_done = true;
324c74ad RM	165	}
	166
	167	void ar9003_hw_rtt_clear_hist(struct ath_hw *ah)
	168	{
8a90555f	169	int chain, i;
324c74ad	170
8a90555f SM	171	for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
8a90555f SM	172	if (!(ah->rxchainmask & (1 << chain)))
324c74ad	173	continue;
8a90555f SM	174	for (i = 0; i < MAX_RTT_TABLE_ENTRY; i++)
8a90555f SM	175	ar9003_hw_rtt_load_hist_entry(ah, chain, i, 0);
324c74ad	176	}
8a90555f SM	177
	178	if (ah->caldata)
	179	ah->caldata->rtt_done = false;
	180	}
	181
	182	bool ar9003_hw_rtt_restore(struct ath_hw ah, struct ath9k_channel chan)
	183	{
	184	bool restore;
	185
	186	if (!ah->caldata)
	187	return false;
	188
	189	if (!ah->caldata->rtt_done)
	190	return false;
	191
	192	ar9003_hw_rtt_enable(ah);
	193	ar9003_hw_rtt_set_mask(ah, 0x10);
	194
	195	if (!ath9k_hw_rfbus_req(ah)) {
	196	ath_err(ath9k_hw_common(ah), "Could not stop baseband\n");
	197	restore = false;
	198	goto fail;
	199	}
	200
	201	ar9003_hw_rtt_load_hist(ah);
	202	restore = ar9003_hw_rtt_force_restore(ah);
	203
	204	fail:
	205	ath9k_hw_rfbus_done(ah);
	206	ar9003_hw_rtt_disable(ah);
	207	return restore;
324c74ad	208	}