[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / ath9k.h

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef ATH9K_H
#define ATH9K_H

#include <linux/etherdevice.h>
#include <linux/device.h>
#include <linux/leds.h>

#include "rc.h"
#include "debug.h"
#include "common.h"

/*
 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
 * should rely on this file or its contents.
 */

struct ath_node;

/* Macro to expand scalars to 64-bit objects */

#define	ito64(x) (sizeof(x) == 8) ?			\
	(((unsigned long long int)(x)) & (0xff)) :	\
	(sizeof(x) == 16) ?				\
	(((unsigned long long int)(x)) & 0xffff) :	\
	((sizeof(x) == 32) ?				\
	 (((unsigned long long int)(x)) & 0xffffffff) : \
	 (unsigned long long int)(x))

/* increment with wrap-around */
#define INCR(_l, _sz)   do {			\
		(_l)++;				\
		(_l) &= ((_sz) - 1);		\
	} while (0)

/* decrement with wrap-around */
#define DECR(_l,  _sz)  do {			\
		(_l)--;				\
		(_l) &= ((_sz) - 1);		\
	} while (0)

#define A_MAX(a, b) ((a) > (b) ? (a) : (b))

#define TSF_TO_TU(_h,_l) \
	((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))

#define	ATH_TXQ_SETUP(sc, i)        ((sc)->tx.txqsetup & (1<<i))

struct ath_config {
	u32 ath_aggr_prot;
	u16 txpowlimit;
	u8 cabqReadytime;
};

/*************************/
/* Descriptor Management */
/*************************/

#define ATH_TXBUF_RESET(_bf) do {				\
		(_bf)->bf_stale = false;			\
		(_bf)->bf_lastbf = NULL;			\
		(_bf)->bf_next = NULL;				\
		memset(&((_bf)->bf_state), 0,			\
		       sizeof(struct ath_buf_state));		\
	} while (0)

#define ATH_RXBUF_RESET(_bf) do {		\
		(_bf)->bf_stale = false;	\
	} while (0)

/**
 * enum buffer_type - Buffer type flags
 *
 * @BUF_HT: Send this buffer using HT capabilities
 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
 * @BUF_AGGR: Indicates whether the buffer can be aggregated
 *	(used in aggregation scheduling)
 * @BUF_RETRY: Indicates whether the buffer is retried
 * @BUF_XRETRY: To denote excessive retries of the buffer
 */
enum buffer_type {
	BUF_HT			= BIT(1),
	BUF_AMPDU		= BIT(2),
	BUF_AGGR		= BIT(3),
	BUF_RETRY		= BIT(4),
	BUF_XRETRY		= BIT(5),
};

#define bf_nframes      	bf_state.bfs_nframes
#define bf_al           	bf_state.bfs_al
#define bf_frmlen       	bf_state.bfs_frmlen
#define bf_retries      	bf_state.bfs_retries
#define bf_seqno        	bf_state.bfs_seqno
#define bf_tidno        	bf_state.bfs_tidno
#define bf_keyix                bf_state.bfs_keyix
#define bf_keytype      	bf_state.bfs_keytype
#define bf_isht(bf)		(bf->bf_state.bf_type & BUF_HT)
#define bf_isampdu(bf)		(bf->bf_state.bf_type & BUF_AMPDU)
#define bf_isaggr(bf)		(bf->bf_state.bf_type & BUF_AGGR)
#define bf_isretried(bf)	(bf->bf_state.bf_type & BUF_RETRY)
#define bf_isxretried(bf)	(bf->bf_state.bf_type & BUF_XRETRY)

struct ath_descdma {
	struct ath_desc *dd_desc;
	dma_addr_t dd_desc_paddr;
	u32 dd_desc_len;
	struct ath_buf *dd_bufptr;
};

int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
		      struct list_head *head, const char *name,
		      int nbuf, int ndesc);
void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
			 struct list_head *head);

/***********/
/* RX / TX */
/***********/

#define ATH_MAX_ANTENNA         3
#define ATH_RXBUF               512
#define ATH_TXBUF               512
#define ATH_TXMAXTRY            13
#define ATH_MGT_TXMAXTRY        4

#define TID_TO_WME_AC(_tid)				\
	((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE :	\
	 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK :	\
	 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI :	\
	 WME_AC_VO)

#define ADDBA_EXCHANGE_ATTEMPTS    10
#define ATH_AGGR_DELIM_SZ          4
#define ATH_AGGR_MINPLEN           256 /* in bytes, minimum packet length */
/* number of delimiters for encryption padding */
#define ATH_AGGR_ENCRYPTDELIM      10
/* minimum h/w qdepth to be sustained to maximize aggregation */
#define ATH_AGGR_MIN_QDEPTH        2
#define ATH_AMPDU_SUBFRAME_DEFAULT 32

#define IEEE80211_SEQ_SEQ_SHIFT    4
#define IEEE80211_SEQ_MAX          4096
#define IEEE80211_WEP_IVLEN        3
#define IEEE80211_WEP_KIDLEN       1
#define IEEE80211_WEP_CRCLEN       4
#define IEEE80211_MAX_MPDU_LEN     (3840 + FCS_LEN +		\
				    (IEEE80211_WEP_IVLEN +	\
				     IEEE80211_WEP_KIDLEN +	\
				     IEEE80211_WEP_CRCLEN))

/* return whether a bit at index _n in bitmap _bm is set
 * _sz is the size of the bitmap  */
#define ATH_BA_ISSET(_bm, _n)  (((_n) < (WME_BA_BMP_SIZE)) &&		\
				((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))

/* return block-ack bitmap index given sequence and starting sequence */
#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))

/* returns delimiter padding required given the packet length */
#define ATH_AGGR_GET_NDELIM(_len)					\
	(((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
	  (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)

#define BAW_WITHIN(_start, _bawsz, _seqno) \
	((((_seqno) - (_start)) & 4095) < (_bawsz))

#define ATH_DS_BA_SEQ(_ds)         ((_ds)->ds_us.tx.ts_seqnum)
#define ATH_DS_BA_BITMAP(_ds)      (&(_ds)->ds_us.tx.ba_low)
#define ATH_DS_TX_BA(_ds)          ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
#define ATH_AN_2_TID(_an, _tidno)  (&(_an)->tid[(_tidno)])

#define ATH_TX_COMPLETE_POLL_INT	1000

enum ATH_AGGR_STATUS {
	ATH_AGGR_DONE,
	ATH_AGGR_BAW_CLOSED,
	ATH_AGGR_LIMITED,
};

struct ath_txq {
	u32 axq_qnum;
	u32 *axq_link;
	struct list_head axq_q;
	spinlock_t axq_lock;
	u32 axq_depth;
	bool stopped;
	bool axq_tx_inprogress;
	struct list_head axq_acq;
};

#define AGGR_CLEANUP         BIT(1)
#define AGGR_ADDBA_COMPLETE  BIT(2)
#define AGGR_ADDBA_PROGRESS  BIT(3)

struct ath_tx_control {
	struct ath_txq *txq;
	int if_id;
	enum ath9k_internal_frame_type frame_type;
};

#define ATH_TX_ERROR        0x01
#define ATH_TX_XRETRY       0x02
#define ATH_TX_BAR          0x04

struct ath_tx {
	u16 seq_no;
	u32 txqsetup;
	int hwq_map[ATH9K_WME_AC_VO+1];
	spinlock_t txbuflock;
	struct list_head txbuf;
	struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
	struct ath_descdma txdma;
};

struct ath_rx {
	u8 defant;
	u8 rxotherant;
	u32 *rxlink;
	unsigned int rxfilter;
	spinlock_t rxflushlock;
	spinlock_t rxbuflock;
	struct list_head rxbuf;
	struct ath_descdma rxdma;
};

int ath_startrecv(struct ath_softc *sc);
bool ath_stoprecv(struct ath_softc *sc);
void ath_flushrecv(struct ath_softc *sc);
u32 ath_calcrxfilter(struct ath_softc *sc);
int ath_rx_init(struct ath_softc *sc, int nbufs);
void ath_rx_cleanup(struct ath_softc *sc);
int ath_rx_tasklet(struct ath_softc *sc, int flush);
struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
int ath_tx_setup(struct ath_softc *sc, int haltype);
void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
void ath_draintxq(struct ath_softc *sc,
		     struct ath_txq *txq, bool retry_tx);
void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
int ath_tx_init(struct ath_softc *sc, int nbufs);
void ath_tx_cleanup(struct ath_softc *sc);
struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
int ath_txq_update(struct ath_softc *sc, int qnum,
		   struct ath9k_tx_queue_info *q);
int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
		 struct ath_tx_control *txctl);
void ath_tx_tasklet(struct ath_softc *sc);
void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
		       u16 tid, u16 *ssn);
void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);

/********/
/* VIFs */
/********/

struct ath_vif {
	int av_bslot;
	__le64 tsf_adjust; /* TSF adjustment for staggered beacons */
	enum nl80211_iftype av_opmode;
	struct ath_buf *av_bcbuf;
	struct ath_tx_control av_btxctl;
	u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
};

/*******************/
/* Beacon Handling */
/*******************/

/*
 * Regardless of the number of beacons we stagger, (i.e. regardless of the
 * number of BSSIDs) if a given beacon does not go out even after waiting this
 * number of beacon intervals, the game's up.
 */
#define BSTUCK_THRESH           	(9 * ATH_BCBUF)
#define	ATH_BCBUF               	4
#define ATH_DEFAULT_BINTVAL     	100 /* TU */
#define ATH_DEFAULT_BMISS_LIMIT 	10
#define IEEE80211_MS_TO_TU(x)           (((x) * 1000) / 1024)

struct ath_beacon_config {
	u16 beacon_interval;
	u16 listen_interval;
	u16 dtim_period;
	u16 bmiss_timeout;
	u8 dtim_count;
};

struct ath_beacon {
	enum {
		OK,		/* no change needed */
		UPDATE,		/* update pending */
		COMMIT		/* beacon sent, commit change */
	} updateslot;		/* slot time update fsm */

	u32 beaconq;
	u32 bmisscnt;
	u32 ast_be_xmit;
	u64 bc_tstamp;
	struct ieee80211_vif *bslot[ATH_BCBUF];
	struct ath_wiphy *bslot_aphy[ATH_BCBUF];
	int slottime;
	int slotupdate;
	struct ath9k_tx_queue_info beacon_qi;
	struct ath_descdma bdma;
	struct ath_txq *cabq;
	struct list_head bbuf;
};

void ath_beacon_tasklet(unsigned long data);
void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif);
void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);

/*******/
/* ANI */
/*******/

#define ATH_STA_SHORT_CALINTERVAL 1000    /* 1 second */
#define ATH_AP_SHORT_CALINTERVAL  100     /* 100 ms */
#define ATH_ANI_POLLINTERVAL      100     /* 100 ms */
#define ATH_LONG_CALINTERVAL      30000   /* 30 seconds */
#define ATH_RESTART_CALINTERVAL   1200000 /* 20 minutes */

/* Defines the BT AR_BT_COEX_WGHT used */
enum ath_stomp_type {
	ATH_BTCOEX_NO_STOMP,
	ATH_BTCOEX_STOMP_ALL,
	ATH_BTCOEX_STOMP_LOW,
	ATH_BTCOEX_STOMP_NONE
};

struct ath_btcoex {
	bool hw_timer_enabled;
	spinlock_t btcoex_lock;
	struct timer_list period_timer; /* Timer for BT period */
	u32 bt_priority_cnt;
	unsigned long bt_priority_time;
	int bt_stomp_type; /* Types of BT stomping */
	u32 btcoex_no_stomp; /* in usec */
	u32 btcoex_period; /* in usec */
	struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
};

/********************/
/*   LED Control    */
/********************/

#define ATH_LED_PIN_DEF 		1
#define ATH_LED_PIN_9287		8
#define ATH_LED_ON_DURATION_IDLE	350	/* in msecs */
#define ATH_LED_OFF_DURATION_IDLE	250	/* in msecs */

enum ath_led_type {
	ATH_LED_RADIO,
	ATH_LED_ASSOC,
	ATH_LED_TX,
	ATH_LED_RX
};

struct ath_led {
	struct ath_softc *sc;
	struct led_classdev led_cdev;
	enum ath_led_type led_type;
	char name[32];
	bool registered;
};

/********************/
/* Main driver core */
/********************/

/*
 * Default cache line size, in bytes.
 * Used when PCI device not fully initialized by bootrom/BIOS
*/
#define DEFAULT_CACHELINE       32
#define ATH_REGCLASSIDS_MAX     10
#define ATH_CABQ_READY_TIME     80      /* % of beacon interval */
#define ATH_MAX_SW_RETRIES      10
#define ATH_CHAN_MAX            255
#define IEEE80211_WEP_NKID      4       /* number of key ids */

#define ATH_TXPOWER_MAX         100     /* .5 dBm units */
#define ATH_RATE_DUMMY_MARKER   0

#define SC_OP_INVALID           BIT(0)
#define SC_OP_BEACONS           BIT(1)
#define SC_OP_RXAGGR            BIT(2)
#define SC_OP_TXAGGR            BIT(3)
#define SC_OP_FULL_RESET        BIT(4)
#define SC_OP_PREAMBLE_SHORT    BIT(5)
#define SC_OP_PROTECT_ENABLE    BIT(6)
#define SC_OP_RXFLUSH           BIT(7)
#define SC_OP_LED_ASSOCIATED    BIT(8)
#define SC_OP_WAIT_FOR_BEACON   BIT(12)
#define SC_OP_LED_ON            BIT(13)
#define SC_OP_SCANNING          BIT(14)
#define SC_OP_TSF_RESET         BIT(15)
#define SC_OP_WAIT_FOR_CAB      BIT(16)
#define SC_OP_WAIT_FOR_PSPOLL_DATA BIT(17)
#define SC_OP_WAIT_FOR_TX_ACK   BIT(18)
#define SC_OP_BEACON_SYNC       BIT(19)
#define SC_OP_BT_PRIORITY_DETECTED BIT(21)

struct ath_wiphy;

struct ath_softc {
	struct ieee80211_hw *hw;
	struct device *dev;

	spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
	struct ath_wiphy *pri_wiphy;
	struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may
				       * have NULL entries */
	int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
	int chan_idx;
	int chan_is_ht;
	struct ath_wiphy *next_wiphy;
	struct work_struct chan_work;
	int wiphy_select_failures;
	unsigned long wiphy_select_first_fail;
	struct delayed_work wiphy_work;
	unsigned long wiphy_scheduler_int;
	int wiphy_scheduler_index;

	struct tasklet_struct intr_tq;
	struct tasklet_struct bcon_tasklet;
	struct ath_hw *sc_ah;
	void __iomem *mem;
	int irq;
	spinlock_t sc_resetlock;
	spinlock_t sc_serial_rw;
	spinlock_t ani_lock;
	spinlock_t sc_pm_lock;
	struct mutex mutex;

	u32 intrstatus;
	u32 sc_flags; /* SC_OP_* */
	u16 curtxpow;
	u8 nbcnvifs;
	u16 nvifs;
	bool ps_enabled;
	unsigned long ps_usecount;
	enum ath9k_int imask;

	struct ath_config config;
	struct ath_rx rx;
	struct ath_tx tx;
	struct ath_beacon beacon;
	struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
	const struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
	const struct ath_rate_table *cur_rate_table;
	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];

	struct ath_led radio_led;
	struct ath_led assoc_led;
	struct ath_led tx_led;
	struct ath_led rx_led;
	struct delayed_work ath_led_blink_work;
	int led_on_duration;
	int led_off_duration;
	int led_on_cnt;
	int led_off_cnt;

	int beacon_interval;

#ifdef CONFIG_ATH9K_DEBUG
	struct ath9k_debug debug;
#endif
	struct ath_beacon_config cur_beacon_conf;
	struct delayed_work tx_complete_work;
	struct ath_btcoex btcoex;
};

struct ath_wiphy {
	struct ath_softc *sc; /* shared for all virtual wiphys */
	struct ieee80211_hw *hw;
	enum ath_wiphy_state {
		ATH_WIPHY_INACTIVE,
		ATH_WIPHY_ACTIVE,
		ATH_WIPHY_PAUSING,
		ATH_WIPHY_PAUSED,
		ATH_WIPHY_SCAN,
	} state;
	bool idle;
	int chan_idx;
	int chan_is_ht;
};

int ath_reset(struct ath_softc *sc, bool retry_tx);
int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
int ath_cabq_update(struct ath_softc *);

static inline void ath_read_cachesize(struct ath_common *common, int *csz)
{
	common->bus_ops->read_cachesize(common, csz);
}

static inline void ath_bus_cleanup(struct ath_common *common)
{
	common->bus_ops->cleanup(common);
}

extern struct ieee80211_ops ath9k_ops;

irqreturn_t ath_isr(int irq, void *dev);
void ath_cleanup(struct ath_softc *sc);
int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
		    const struct ath_bus_ops *bus_ops);
void ath_detach(struct ath_softc *sc);
const char *ath_mac_bb_name(u32 mac_bb_version);
const char *ath_rf_name(u16 rf_version);
void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
			   struct ath9k_channel *ichan);
void ath_update_chainmask(struct ath_softc *sc, int is_ht);
int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
		    struct ath9k_channel *hchan);

void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw);
void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);

#ifdef CONFIG_PCI
int ath_pci_init(void);
void ath_pci_exit(void);
#else
static inline int ath_pci_init(void) { return 0; };
static inline void ath_pci_exit(void) {};
#endif

#ifdef CONFIG_ATHEROS_AR71XX
int ath_ahb_init(void);
void ath_ahb_exit(void);
#else
static inline int ath_ahb_init(void) { return 0; };
static inline void ath_ahb_exit(void) {};
#endif

void ath9k_ps_wakeup(struct ath_softc *sc);
void ath9k_ps_restore(struct ath_softc *sc);

void ath9k_set_bssid_mask(struct ieee80211_hw *hw);
int ath9k_wiphy_add(struct ath_softc *sc);
int ath9k_wiphy_del(struct ath_wiphy *aphy);
void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
int ath9k_wiphy_pause(struct ath_wiphy *aphy);
int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
int ath9k_wiphy_select(struct ath_wiphy *aphy);
void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
void ath9k_wiphy_chan_work(struct work_struct *work);
bool ath9k_wiphy_started(struct ath_softc *sc);
void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
				  struct ath_wiphy *selected);
bool ath9k_wiphy_scanning(struct ath_softc *sc);
void ath9k_wiphy_work(struct work_struct *work);
bool ath9k_all_wiphys_idle(struct ath_softc *sc);
void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);

void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);

int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
#endif /* ATH9K_H */
Commit	Line	Data
f078f209	1	/*
cee075a2	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209 LR	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef ATH9K_H
	18	#define ATH9K_H
	19
394cf0a1 S	20	#include <linux/etherdevice.h>
394cf0a1 S	21	#include <linux/device.h>
394cf0a1	22	#include <linux/leds.h>
394cf0a1	23
394cf0a1 S	24	#include "rc.h"
394cf0a1 S	25	#include "debug.h"
db86f07e LR	26	#include "common.h"
	27
	28	/*
	29	* Header for the ath9k.ko driver core only -- hw code nor any other driver
	30	* should rely on this file or its contents.
	31	*/
394cf0a1 S	32
	33	struct ath_node;
	34
	35	/* Macro to expand scalars to 64-bit objects */
	36
	37	#define ito64(x) (sizeof(x) == 8) ? \
	38	(((unsigned long long int)(x)) & (0xff)) : \
	39	(sizeof(x) == 16) ? \
	40	(((unsigned long long int)(x)) & 0xffff) : \
	41	((sizeof(x) == 32) ? \
	42	(((unsigned long long int)(x)) & 0xffffffff) : \
	43	(unsigned long long int)(x))
	44
	45	/* increment with wrap-around */
	46	#define INCR(_l, _sz) do { \
	47	(_l)++; \
	48	(_l) &= ((_sz) - 1); \
	49	} while (0)
	50
	51	/* decrement with wrap-around */
	52	#define DECR(_l, _sz) do { \
	53	(_l)--; \
	54	(_l) &= ((_sz) - 1); \
	55	} while (0)
	56
	57	#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
	58
394cf0a1 S	59	#define TSF_TO_TU(_h,_l) \
	60	((((u32)(_h)) << 22) \| (((u32)(_l)) >> 10))
	61
	62	#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
	63
394cf0a1 S	64	struct ath_config {
	65	u32 ath_aggr_prot;
	66	u16 txpowlimit;
	67	u8 cabqReadytime;
394cf0a1 S	68	};
	69
	70	/*************************/
	71	/* Descriptor Management */
	72	/*************************/
	73
	74	#define ATH_TXBUF_RESET(_bf) do { \
a119cc49	75	(_bf)->bf_stale = false; \
394cf0a1 S	76	(_bf)->bf_lastbf = NULL; \
	77	(_bf)->bf_next = NULL; \
	78	memset(&((_bf)->bf_state), 0, \
	79	sizeof(struct ath_buf_state)); \
	80	} while (0)
	81
a119cc49 S	82	#define ATH_RXBUF_RESET(_bf) do { \
	83	(_bf)->bf_stale = false; \
	84	} while (0)
	85
394cf0a1 S	86	/**
	87	* enum buffer_type - Buffer type flags
	88	*
	89	* @BUF_HT: Send this buffer using HT capabilities
	90	* @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
	91	* @BUF_AGGR: Indicates whether the buffer can be aggregated
	92	* (used in aggregation scheduling)
	93	* @BUF_RETRY: Indicates whether the buffer is retried
	94	* @BUF_XRETRY: To denote excessive retries of the buffer
	95	*/
	96	enum buffer_type {
	97	BUF_HT = BIT(1),
	98	BUF_AMPDU = BIT(2),
	99	BUF_AGGR = BIT(3),
	100	BUF_RETRY = BIT(4),
	101	BUF_XRETRY = BIT(5),
	102	};
	103
394cf0a1 S	104	#define bf_nframes bf_state.bfs_nframes
	105	#define bf_al bf_state.bfs_al
	106	#define bf_frmlen bf_state.bfs_frmlen
	107	#define bf_retries bf_state.bfs_retries
	108	#define bf_seqno bf_state.bfs_seqno
	109	#define bf_tidno bf_state.bfs_tidno
	110	#define bf_keyix bf_state.bfs_keyix
	111	#define bf_keytype bf_state.bfs_keytype
	112	#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
	113	#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
	114	#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
	115	#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
	116	#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
f078f209	117
394cf0a1	118	struct ath_descdma {
17d7904d S	119	struct ath_desc *dd_desc;
	120	dma_addr_t dd_desc_paddr;
	121	u32 dd_desc_len;
	122	struct ath_buf *dd_bufptr;
394cf0a1 S	123	};
	124
	125	int ath_descdma_setup(struct ath_softc sc, struct ath_descdma dd,
	126	struct list_head head, const char name,
	127	int nbuf, int ndesc);
	128	void ath_descdma_cleanup(struct ath_softc sc, struct ath_descdma dd,
	129	struct list_head *head);
	130
	131	/***********/
	132	/* RX / TX */
	133	/***********/
	134
	135	#define ATH_MAX_ANTENNA 3
	136	#define ATH_RXBUF 512
394cf0a1 S	137	#define ATH_TXBUF 512
394cf0a1 S	138	#define ATH_TXMAXTRY 13
394cf0a1	139	#define ATH_MGT_TXMAXTRY 4
394cf0a1 S	140
	141	#define TID_TO_WME_AC(_tid) \
	142	((((_tid) == 0) \|\| ((_tid) == 3)) ? WME_AC_BE : \
	143	(((_tid) == 1) \|\| ((_tid) == 2)) ? WME_AC_BK : \
	144	(((_tid) == 4) \|\| ((_tid) == 5)) ? WME_AC_VI : \
	145	WME_AC_VO)
	146
394cf0a1 S	147	#define ADDBA_EXCHANGE_ATTEMPTS 10
	148	#define ATH_AGGR_DELIM_SZ 4
	149	#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
	150	/* number of delimiters for encryption padding */
	151	#define ATH_AGGR_ENCRYPTDELIM 10
	152	/* minimum h/w qdepth to be sustained to maximize aggregation */
	153	#define ATH_AGGR_MIN_QDEPTH 2
	154	#define ATH_AMPDU_SUBFRAME_DEFAULT 32
394cf0a1 S	155
	156	#define IEEE80211_SEQ_SEQ_SHIFT 4
	157	#define IEEE80211_SEQ_MAX 4096
394cf0a1 S	158	#define IEEE80211_WEP_IVLEN 3
	159	#define IEEE80211_WEP_KIDLEN 1
	160	#define IEEE80211_WEP_CRCLEN 4
	161	#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
	162	(IEEE80211_WEP_IVLEN + \
	163	IEEE80211_WEP_KIDLEN + \
	164	IEEE80211_WEP_CRCLEN))
	165
	166	/* return whether a bit at index _n in bitmap _bm is set
	167	* _sz is the size of the bitmap */
	168	#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
	169	((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
	170
	171	/* return block-ack bitmap index given sequence and starting sequence */
	172	#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
	173
	174	/* returns delimiter padding required given the packet length */
	175	#define ATH_AGGR_GET_NDELIM(_len) \
	176	(((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
	177	(ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
	178
	179	#define BAW_WITHIN(_start, _bawsz, _seqno) \
	180	((((_seqno) - (_start)) & 4095) < (_bawsz))
	181
	182	#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
	183	#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
	184	#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
	185	#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
	186
164ace38 SB	187	#define ATH_TX_COMPLETE_POLL_INT 1000
164ace38 SB	188
394cf0a1 S	189	enum ATH_AGGR_STATUS {
	190	ATH_AGGR_DONE,
	191	ATH_AGGR_BAW_CLOSED,
	192	ATH_AGGR_LIMITED,
	193	};
	194
	195	struct ath_txq {
17d7904d S	196	u32 axq_qnum;
	197	u32 *axq_link;
	198	struct list_head axq_q;
394cf0a1	199	spinlock_t axq_lock;
17d7904d	200	u32 axq_depth;
17d7904d	201	bool stopped;
164ace38	202	bool axq_tx_inprogress;
394cf0a1 S	203	struct list_head axq_acq;
	204	};
	205
	206	#define AGGR_CLEANUP BIT(1)
	207	#define AGGR_ADDBA_COMPLETE BIT(2)
	208	#define AGGR_ADDBA_PROGRESS BIT(3)
	209
394cf0a1 S	210	struct ath_tx_control {
	211	struct ath_txq *txq;
	212	int if_id;
f0ed85c6	213	enum ath9k_internal_frame_type frame_type;
394cf0a1 S	214	};
394cf0a1 S	215
394cf0a1 S	216	#define ATH_TX_ERROR 0x01
	217	#define ATH_TX_XRETRY 0x02
	218	#define ATH_TX_BAR 0x04
394cf0a1	219
394cf0a1 S	220	struct ath_tx {
	221	u16 seq_no;
	222	u32 txqsetup;
	223	int hwq_map[ATH9K_WME_AC_VO+1];
	224	spinlock_t txbuflock;
	225	struct list_head txbuf;
	226	struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
	227	struct ath_descdma txdma;
	228	};
	229
	230	struct ath_rx {
	231	u8 defant;
	232	u8 rxotherant;
	233	u32 *rxlink;
394cf0a1 S	234	unsigned int rxfilter;
	235	spinlock_t rxflushlock;
	236	spinlock_t rxbuflock;
	237	struct list_head rxbuf;
	238	struct ath_descdma rxdma;
	239	};
	240
	241	int ath_startrecv(struct ath_softc *sc);
	242	bool ath_stoprecv(struct ath_softc *sc);
	243	void ath_flushrecv(struct ath_softc *sc);
	244	u32 ath_calcrxfilter(struct ath_softc *sc);
	245	int ath_rx_init(struct ath_softc *sc, int nbufs);
	246	void ath_rx_cleanup(struct ath_softc *sc);
	247	int ath_rx_tasklet(struct ath_softc *sc, int flush);
	248	struct ath_txq ath_txq_setup(struct ath_softc sc, int qtype, int subtype);
	249	void ath_tx_cleanupq(struct ath_softc sc, struct ath_txq txq);
	250	int ath_tx_setup(struct ath_softc *sc, int haltype);
	251	void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
	252	void ath_draintxq(struct ath_softc *sc,
	253	struct ath_txq *txq, bool retry_tx);
	254	void ath_tx_node_init(struct ath_softc sc, struct ath_node an);
	255	void ath_tx_node_cleanup(struct ath_softc sc, struct ath_node an);
	256	void ath_txq_schedule(struct ath_softc sc, struct ath_txq txq);
	257	int ath_tx_init(struct ath_softc *sc, int nbufs);
797fe5cb	258	void ath_tx_cleanup(struct ath_softc *sc);
394cf0a1 S	259	struct ath_txq ath_test_get_txq(struct ath_softc sc, struct sk_buff *skb);
	260	int ath_txq_update(struct ath_softc *sc, int qnum,
	261	struct ath9k_tx_queue_info *q);
c52f33d0	262	int ath_tx_start(struct ieee80211_hw hw, struct sk_buff skb,
394cf0a1 S	263	struct ath_tx_control *txctl);
394cf0a1 S	264	void ath_tx_tasklet(struct ath_softc *sc);
c52f33d0	265	void ath_tx_cabq(struct ieee80211_hw hw, struct sk_buff skb);
394cf0a1	266	bool ath_tx_aggr_check(struct ath_softc sc, struct ath_node an, u8 tidno);
f83da965 S	267	void ath_tx_aggr_start(struct ath_softc sc, struct ieee80211_sta sta,
	268	u16 tid, u16 *ssn);
	269	void ath_tx_aggr_stop(struct ath_softc sc, struct ieee80211_sta sta, u16 tid);
394cf0a1 S	270	void ath_tx_aggr_resume(struct ath_softc sc, struct ieee80211_sta sta, u16 tid);
	271
	272	/********/
17d7904d	273	/* VIFs */
394cf0a1	274	/********/
f078f209	275
17d7904d	276	struct ath_vif {
394cf0a1	277	int av_bslot;
4ed96f04	278	__le64 tsf_adjust; /* TSF adjustment for staggered beacons */
394cf0a1 S	279	enum nl80211_iftype av_opmode;
	280	struct ath_buf *av_bcbuf;
	281	struct ath_tx_control av_btxctl;
f0ed85c6	282	u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */
f078f209 LR	283	};
f078f209 LR	284
394cf0a1 S	285	/*******************/
	286	/* Beacon Handling */
	287	/*******************/
f078f209	288
394cf0a1 S	289	/*
	290	* Regardless of the number of beacons we stagger, (i.e. regardless of the
	291	* number of BSSIDs) if a given beacon does not go out even after waiting this
	292	* number of beacon intervals, the game's up.
	293	*/
	294	#define BSTUCK_THRESH (9 * ATH_BCBUF)
4ed96f04	295	#define ATH_BCBUF 4
394cf0a1 S	296	#define ATH_DEFAULT_BINTVAL 100 /* TU */
	297	#define ATH_DEFAULT_BMISS_LIMIT 10
	298	#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
	299
	300	struct ath_beacon_config {
	301	u16 beacon_interval;
	302	u16 listen_interval;
	303	u16 dtim_period;
	304	u16 bmiss_timeout;
	305	u8 dtim_count;
394cf0a1 S	306	};
	307
	308	struct ath_beacon {
	309	enum {
	310	OK, /* no change needed */
	311	UPDATE, /* update pending */
	312	COMMIT /* beacon sent, commit change */
	313	} updateslot; /* slot time update fsm */
	314
	315	u32 beaconq;
	316	u32 bmisscnt;
	317	u32 ast_be_xmit;
	318	u64 bc_tstamp;
2c3db3d5	319	struct ieee80211_vif *bslot[ATH_BCBUF];
c52f33d0	320	struct ath_wiphy *bslot_aphy[ATH_BCBUF];
394cf0a1 S	321	int slottime;
	322	int slotupdate;
	323	struct ath9k_tx_queue_info beacon_qi;
	324	struct ath_descdma bdma;
	325	struct ath_txq *cabq;
	326	struct list_head bbuf;
	327	};
	328
9fc9ab0a	329	void ath_beacon_tasklet(unsigned long data);
2c3db3d5	330	void ath_beacon_config(struct ath_softc sc, struct ieee80211_vif vif);
c52f33d0	331	int ath_beacon_alloc(struct ath_wiphy aphy, struct ieee80211_vif vif);
17d7904d	332	void ath_beacon_return(struct ath_softc sc, struct ath_vif avp);
394cf0a1 S	333
	334	/*******/
	335	/* ANI */
	336	/*******/
f078f209	337
20977d3e S	338	#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
	339	#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
	340	#define ATH_ANI_POLLINTERVAL 100 /* 100 ms */
	341	#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
	342	#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
f078f209	343
e08a6ace LR	344	/* Defines the BT AR_BT_COEX_WGHT used */
	345	enum ath_stomp_type {
	346	ATH_BTCOEX_NO_STOMP,
	347	ATH_BTCOEX_STOMP_ALL,
	348	ATH_BTCOEX_STOMP_LOW,
	349	ATH_BTCOEX_STOMP_NONE
	350	};
	351
2e20250a LR	352	struct ath_btcoex {
	353	bool hw_timer_enabled;
	354	spinlock_t btcoex_lock;
	355	struct timer_list period_timer; /* Timer for BT period */
	356	u32 bt_priority_cnt;
	357	unsigned long bt_priority_time;
e08a6ace	358	int bt_stomp_type; /* Types of BT stomping */
2e20250a LR	359	u32 btcoex_no_stomp; /* in usec */
2e20250a LR	360	u32 btcoex_period; /* in usec */
75d7839f	361	struct ath_gen_timer no_stomp_timer; / Timer for no BT stomping */
2e20250a LR	362	};
2e20250a LR	363
394cf0a1 S	364	/********************/
	365	/* LED Control */
	366	/********************/
f078f209	367
08fc5c1b VN	368	#define ATH_LED_PIN_DEF 1
08fc5c1b VN	369	#define ATH_LED_PIN_9287 8
394cf0a1 S	370	#define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
394cf0a1 S	371	#define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
f078f209	372
394cf0a1 S	373	enum ath_led_type {
	374	ATH_LED_RADIO,
	375	ATH_LED_ASSOC,
	376	ATH_LED_TX,
	377	ATH_LED_RX
f078f209 LR	378	};
f078f209 LR	379
394cf0a1 S	380	struct ath_led {
	381	struct ath_softc *sc;
	382	struct led_classdev led_cdev;
	383	enum ath_led_type led_type;
	384	char name[32];
	385	bool registered;
f078f209 LR	386	};
f078f209 LR	387
394cf0a1 S	388	/********************/
	389	/* Main driver core */
	390	/********************/
f078f209	391
394cf0a1 S	392	/*
	393	* Default cache line size, in bytes.
	394	* Used when PCI device not fully initialized by bootrom/BIOS
	395	*/
	396	#define DEFAULT_CACHELINE 32
394cf0a1 S	397	#define ATH_REGCLASSIDS_MAX 10
	398	#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
	399	#define ATH_MAX_SW_RETRIES 10
	400	#define ATH_CHAN_MAX 255
	401	#define IEEE80211_WEP_NKID 4 /* number of key ids */
f1dc5600	402
394cf0a1	403	#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
394cf0a1 S	404	#define ATH_RATE_DUMMY_MARKER 0
394cf0a1 S	405
b238e90e S	406	#define SC_OP_INVALID BIT(0)
	407	#define SC_OP_BEACONS BIT(1)
	408	#define SC_OP_RXAGGR BIT(2)
	409	#define SC_OP_TXAGGR BIT(3)
bdbdf46d S	410	#define SC_OP_FULL_RESET BIT(4)
	411	#define SC_OP_PREAMBLE_SHORT BIT(5)
	412	#define SC_OP_PROTECT_ENABLE BIT(6)
	413	#define SC_OP_RXFLUSH BIT(7)
	414	#define SC_OP_LED_ASSOCIATED BIT(8)
bdbdf46d S	415	#define SC_OP_WAIT_FOR_BEACON BIT(12)
	416	#define SC_OP_LED_ON BIT(13)
	417	#define SC_OP_SCANNING BIT(14)
	418	#define SC_OP_TSF_RESET BIT(15)
cc65965c	419	#define SC_OP_WAIT_FOR_CAB BIT(16)
9a23f9ca JM	420	#define SC_OP_WAIT_FOR_PSPOLL_DATA BIT(17)
9a23f9ca JM	421	#define SC_OP_WAIT_FOR_TX_ACK BIT(18)
ccdfeab6	422	#define SC_OP_BEACON_SYNC BIT(19)
1773912b	423	#define SC_OP_BT_PRIORITY_DETECTED BIT(21)
394cf0a1	424
bce048d7 JM	425	struct ath_wiphy;
bce048d7 JM	426
394cf0a1 S	427	struct ath_softc {
	428	struct ieee80211_hw *hw;
	429	struct device *dev;
c52f33d0 JM	430
c52f33d0 JM	431	spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */
bce048d7	432	struct ath_wiphy *pri_wiphy;
c52f33d0 JM	433	struct ath_wiphy *sec_wiphy; / secondary wiphys (virtual radios); may
	434	* have NULL entries */
	435	int num_sec_wiphy; /* number of sec_wiphy pointers in the array */
0e2dedf9 JM	436	int chan_idx;
	437	int chan_is_ht;
	438	struct ath_wiphy *next_wiphy;
	439	struct work_struct chan_work;
7ec3e514 JM	440	int wiphy_select_failures;
7ec3e514 JM	441	unsigned long wiphy_select_first_fail;
f98c3bd2 JM	442	struct delayed_work wiphy_work;
	443	unsigned long wiphy_scheduler_int;
	444	int wiphy_scheduler_index;
0e2dedf9	445
394cf0a1 S	446	struct tasklet_struct intr_tq;
394cf0a1 S	447	struct tasklet_struct bcon_tasklet;
cbe61d8a	448	struct ath_hw *sc_ah;
394cf0a1 S	449	void __iomem *mem;
	450	int irq;
	451	spinlock_t sc_resetlock;
2d6a5e95	452	spinlock_t sc_serial_rw;
e5f0921a	453	spinlock_t ani_lock;
04717ccd	454	spinlock_t sc_pm_lock;
394cf0a1 S	455	struct mutex mutex;
394cf0a1 S	456
17d7904d	457	u32 intrstatus;
394cf0a1	458	u32 sc_flags; /* SC_OP_* */
17d7904d	459	u16 curtxpow;
17d7904d S	460	u8 nbcnvifs;
17d7904d S	461	u16 nvifs;
96148326	462	bool ps_enabled;
709ade9e	463	unsigned long ps_usecount;
17d7904d	464	enum ath9k_int imask;
394cf0a1	465
17d7904d	466	struct ath_config config;
394cf0a1 S	467	struct ath_rx rx;
	468	struct ath_tx tx;
	469	struct ath_beacon beacon;
394cf0a1	470	struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
4f0fc7c3 LR	471	const struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
4f0fc7c3 LR	472	const struct ath_rate_table *cur_rate_table;
394cf0a1 S	473	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
	474
	475	struct ath_led radio_led;
	476	struct ath_led assoc_led;
	477	struct ath_led tx_led;
	478	struct ath_led rx_led;
	479	struct delayed_work ath_led_blink_work;
	480	int led_on_duration;
	481	int led_off_duration;
	482	int led_on_cnt;
	483	int led_off_cnt;
	484
57c4d7b4 JB	485	int beacon_interval;
57c4d7b4 JB	486
394cf0a1	487	#ifdef CONFIG_ATH9K_DEBUG
17d7904d	488	struct ath9k_debug debug;
394cf0a1	489	#endif
6b96f93e	490	struct ath_beacon_config cur_beacon_conf;
164ace38	491	struct delayed_work tx_complete_work;
2e20250a	492	struct ath_btcoex btcoex;
394cf0a1 S	493	};
394cf0a1 S	494
bce048d7 JM	495	struct ath_wiphy {
	496	struct ath_softc sc; / shared for all virtual wiphys */
	497	struct ieee80211_hw *hw;
f0ed85c6	498	enum ath_wiphy_state {
9580a222	499	ATH_WIPHY_INACTIVE,
f0ed85c6 JM	500	ATH_WIPHY_ACTIVE,
	501	ATH_WIPHY_PAUSING,
	502	ATH_WIPHY_PAUSED,
8089cc47	503	ATH_WIPHY_SCAN,
f0ed85c6	504	} state;
194b7c13	505	bool idle;
0e2dedf9 JM	506	int chan_idx;
0e2dedf9 JM	507	int chan_is_ht;
bce048d7 JM	508	};
bce048d7 JM	509
394cf0a1 S	510	int ath_reset(struct ath_softc *sc, bool retry_tx);
	511	int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
	512	int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
	513	int ath_cabq_update(struct ath_softc *);
	514
5bb12791	515	static inline void ath_read_cachesize(struct ath_common common, int csz)
394cf0a1	516	{
5bb12791	517	common->bus_ops->read_cachesize(common, csz);
394cf0a1 S	518	}
394cf0a1 S	519
5bb12791	520	static inline void ath_bus_cleanup(struct ath_common *common)
394cf0a1	521	{
5bb12791	522	common->bus_ops->cleanup(common);
394cf0a1 S	523	}
	524
	525	extern struct ieee80211_ops ath9k_ops;
	526
	527	irqreturn_t ath_isr(int irq, void *dev);
	528	void ath_cleanup(struct ath_softc *sc);
5bb12791 LR	529	int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
5bb12791 LR	530	const struct ath_bus_ops *bus_ops);
394cf0a1 S	531	void ath_detach(struct ath_softc *sc);
	532	const char *ath_mac_bb_name(u32 mac_bb_version);
	533	const char *ath_rf_name(u16 rf_version);
c52f33d0	534	void ath_set_hw_capab(struct ath_softc sc, struct ieee80211_hw hw);
0e2dedf9 JM	535	void ath9k_update_ichannel(struct ath_softc sc, struct ieee80211_hw hw,
	536	struct ath9k_channel *ichan);
	537	void ath_update_chainmask(struct ath_softc *sc, int is_ht);
	538	int ath_set_channel(struct ath_softc sc, struct ieee80211_hw hw,
	539	struct ath9k_channel *hchan);
68a89116 LR	540
	541	void ath_radio_enable(struct ath_softc sc, struct ieee80211_hw hw);
	542	void ath_radio_disable(struct ath_softc sc, struct ieee80211_hw hw);
394cf0a1 S	543
	544	#ifdef CONFIG_PCI
	545	int ath_pci_init(void);
	546	void ath_pci_exit(void);
	547	#else
	548	static inline int ath_pci_init(void) { return 0; };
	549	static inline void ath_pci_exit(void) {};
f1dc5600	550	#endif
f1dc5600	551
394cf0a1 S	552	#ifdef CONFIG_ATHEROS_AR71XX
	553	int ath_ahb_init(void);
	554	void ath_ahb_exit(void);
	555	#else
	556	static inline int ath_ahb_init(void) { return 0; };
	557	static inline void ath_ahb_exit(void) {};
f078f209	558	#endif
394cf0a1	559
0bc0798b GJ	560	void ath9k_ps_wakeup(struct ath_softc *sc);
0bc0798b GJ	561	void ath9k_ps_restore(struct ath_softc *sc);
8ca21f01 JM	562
8ca21f01 JM	563	void ath9k_set_bssid_mask(struct ieee80211_hw *hw);
c52f33d0 JM	564	int ath9k_wiphy_add(struct ath_softc *sc);
c52f33d0 JM	565	int ath9k_wiphy_del(struct ath_wiphy *aphy);
f0ed85c6 JM	566	void ath9k_tx_status(struct ieee80211_hw hw, struct sk_buff skb);
	567	int ath9k_wiphy_pause(struct ath_wiphy *aphy);
	568	int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
0e2dedf9	569	int ath9k_wiphy_select(struct ath_wiphy *aphy);
f98c3bd2	570	void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int);
0e2dedf9	571	void ath9k_wiphy_chan_work(struct work_struct *work);
9580a222	572	bool ath9k_wiphy_started(struct ath_softc *sc);
18eb62f8 JM	573	void ath9k_wiphy_pause_all_forced(struct ath_softc *sc,
18eb62f8 JM	574	struct ath_wiphy *selected);
8089cc47	575	bool ath9k_wiphy_scanning(struct ath_softc *sc);
f98c3bd2	576	void ath9k_wiphy_work(struct work_struct *work);
64839170	577	bool ath9k_all_wiphys_idle(struct ath_softc *sc);
194b7c13	578	void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle);
8ca21f01	579
f52de03b LR	580	void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue);
	581	void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue);
	582
1773912b	583	int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
394cf0a1	584	#endif /* ATH9K_H */