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Commit | Line | Data |
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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
394cf0a1 | 22 | #include <linux/leds.h> |
9f42c2b6 | 23 | #include <linux/completion.h> |
394cf0a1 | 24 | |
394cf0a1 | 25 | #include "debug.h" |
db86f07e LR |
26 | #include "common.h" |
27 | ||
28 | /* | |
29 | * Header for the ath9k.ko driver core *only* -- hw code nor any other driver | |
30 | * should rely on this file or its contents. | |
31 | */ | |
394cf0a1 S |
32 | |
33 | struct ath_node; | |
34 | ||
35 | /* Macro to expand scalars to 64-bit objects */ | |
36 | ||
13bda122 | 37 | #define ito64(x) (sizeof(x) == 1) ? \ |
394cf0a1 | 38 | (((unsigned long long int)(x)) & (0xff)) : \ |
13bda122 | 39 | (sizeof(x) == 2) ? \ |
394cf0a1 | 40 | (((unsigned long long int)(x)) & 0xffff) : \ |
13bda122 | 41 | ((sizeof(x) == 4) ? \ |
394cf0a1 S |
42 | (((unsigned long long int)(x)) & 0xffffffff) : \ |
43 | (unsigned long long int)(x)) | |
44 | ||
45 | /* increment with wrap-around */ | |
46 | #define INCR(_l, _sz) do { \ | |
47 | (_l)++; \ | |
48 | (_l) &= ((_sz) - 1); \ | |
49 | } while (0) | |
50 | ||
51 | /* decrement with wrap-around */ | |
52 | #define DECR(_l, _sz) do { \ | |
53 | (_l)--; \ | |
54 | (_l) &= ((_sz) - 1); \ | |
55 | } while (0) | |
56 | ||
57 | #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) | |
58 | ||
394cf0a1 S |
59 | #define TSF_TO_TU(_h,_l) \ |
60 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
61 | ||
62 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) | |
63 | ||
394cf0a1 S |
64 | struct ath_config { |
65 | u32 ath_aggr_prot; | |
66 | u16 txpowlimit; | |
67 | u8 cabqReadytime; | |
394cf0a1 S |
68 | }; |
69 | ||
70 | /*************************/ | |
71 | /* Descriptor Management */ | |
72 | /*************************/ | |
73 | ||
74 | #define ATH_TXBUF_RESET(_bf) do { \ | |
a119cc49 | 75 | (_bf)->bf_stale = false; \ |
394cf0a1 S |
76 | (_bf)->bf_lastbf = NULL; \ |
77 | (_bf)->bf_next = NULL; \ | |
78 | memset(&((_bf)->bf_state), 0, \ | |
79 | sizeof(struct ath_buf_state)); \ | |
80 | } while (0) | |
81 | ||
a119cc49 S |
82 | #define ATH_RXBUF_RESET(_bf) do { \ |
83 | (_bf)->bf_stale = false; \ | |
84 | } while (0) | |
85 | ||
394cf0a1 S |
86 | /** |
87 | * enum buffer_type - Buffer type flags | |
88 | * | |
89 | * @BUF_HT: Send this buffer using HT capabilities | |
90 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) | |
91 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
92 | * (used in aggregation scheduling) | |
93 | * @BUF_RETRY: Indicates whether the buffer is retried | |
94 | * @BUF_XRETRY: To denote excessive retries of the buffer | |
95 | */ | |
96 | enum buffer_type { | |
97 | BUF_HT = BIT(1), | |
98 | BUF_AMPDU = BIT(2), | |
99 | BUF_AGGR = BIT(3), | |
100 | BUF_RETRY = BIT(4), | |
101 | BUF_XRETRY = BIT(5), | |
102 | }; | |
103 | ||
394cf0a1 S |
104 | #define bf_nframes bf_state.bfs_nframes |
105 | #define bf_al bf_state.bfs_al | |
106 | #define bf_frmlen bf_state.bfs_frmlen | |
107 | #define bf_retries bf_state.bfs_retries | |
108 | #define bf_seqno bf_state.bfs_seqno | |
109 | #define bf_tidno bf_state.bfs_tidno | |
110 | #define bf_keyix bf_state.bfs_keyix | |
111 | #define bf_keytype bf_state.bfs_keytype | |
112 | #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) | |
113 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) | |
114 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
115 | #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) | |
116 | #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) | |
f078f209 | 117 | |
5088c2f1 VT |
118 | #define ATH_TXSTATUS_RING_SIZE 64 |
119 | ||
394cf0a1 | 120 | struct ath_descdma { |
5088c2f1 | 121 | void *dd_desc; |
17d7904d S |
122 | dma_addr_t dd_desc_paddr; |
123 | u32 dd_desc_len; | |
124 | struct ath_buf *dd_bufptr; | |
394cf0a1 S |
125 | }; |
126 | ||
127 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
128 | struct list_head *head, const char *name, | |
4adfcded | 129 | int nbuf, int ndesc, bool is_tx); |
394cf0a1 S |
130 | void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, |
131 | struct list_head *head); | |
132 | ||
133 | /***********/ | |
134 | /* RX / TX */ | |
135 | /***********/ | |
136 | ||
137 | #define ATH_MAX_ANTENNA 3 | |
138 | #define ATH_RXBUF 512 | |
394cf0a1 | 139 | #define ATH_TXBUF 512 |
84642d6b FF |
140 | #define ATH_TXBUF_RESERVE 5 |
141 | #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) | |
394cf0a1 | 142 | #define ATH_TXMAXTRY 13 |
394cf0a1 | 143 | #define ATH_MGT_TXMAXTRY 4 |
394cf0a1 S |
144 | |
145 | #define TID_TO_WME_AC(_tid) \ | |
146 | ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ | |
147 | (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ | |
148 | (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ | |
149 | WME_AC_VO) | |
150 | ||
394cf0a1 S |
151 | #define ADDBA_EXCHANGE_ATTEMPTS 10 |
152 | #define ATH_AGGR_DELIM_SZ 4 | |
153 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
154 | /* number of delimiters for encryption padding */ | |
155 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
156 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
157 | #define ATH_AGGR_MIN_QDEPTH 2 | |
158 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | |
394cf0a1 S |
159 | |
160 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | |
161 | #define IEEE80211_SEQ_MAX 4096 | |
394cf0a1 S |
162 | #define IEEE80211_WEP_IVLEN 3 |
163 | #define IEEE80211_WEP_KIDLEN 1 | |
164 | #define IEEE80211_WEP_CRCLEN 4 | |
165 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
166 | (IEEE80211_WEP_IVLEN + \ | |
167 | IEEE80211_WEP_KIDLEN + \ | |
168 | IEEE80211_WEP_CRCLEN)) | |
169 | ||
170 | /* return whether a bit at index _n in bitmap _bm is set | |
171 | * _sz is the size of the bitmap */ | |
172 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
173 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
174 | ||
175 | /* return block-ack bitmap index given sequence and starting sequence */ | |
176 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
177 | ||
178 | /* returns delimiter padding required given the packet length */ | |
179 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
180 | (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ | |
181 | (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) | |
182 | ||
183 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
184 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
185 | ||
394cf0a1 S |
186 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) |
187 | ||
164ace38 SB |
188 | #define ATH_TX_COMPLETE_POLL_INT 1000 |
189 | ||
394cf0a1 S |
190 | enum ATH_AGGR_STATUS { |
191 | ATH_AGGR_DONE, | |
192 | ATH_AGGR_BAW_CLOSED, | |
193 | ATH_AGGR_LIMITED, | |
194 | }; | |
195 | ||
e5003249 | 196 | #define ATH_TXFIFO_DEPTH 8 |
394cf0a1 | 197 | struct ath_txq { |
293f2ba8 | 198 | int axq_class; |
17d7904d S |
199 | u32 axq_qnum; |
200 | u32 *axq_link; | |
201 | struct list_head axq_q; | |
394cf0a1 | 202 | spinlock_t axq_lock; |
17d7904d | 203 | u32 axq_depth; |
17d7904d | 204 | bool stopped; |
164ace38 | 205 | bool axq_tx_inprogress; |
394cf0a1 | 206 | struct list_head axq_acq; |
e5003249 VT |
207 | struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; |
208 | struct list_head txq_fifo_pending; | |
209 | u8 txq_headidx; | |
210 | u8 txq_tailidx; | |
394cf0a1 S |
211 | }; |
212 | ||
93ef24b2 S |
213 | struct ath_atx_ac { |
214 | int sched; | |
215 | int qnum; | |
216 | struct list_head list; | |
217 | struct list_head tid_q; | |
218 | }; | |
219 | ||
220 | struct ath_buf_state { | |
221 | int bfs_nframes; | |
222 | u16 bfs_al; | |
223 | u16 bfs_frmlen; | |
224 | int bfs_seqno; | |
225 | int bfs_tidno; | |
226 | int bfs_retries; | |
227 | u8 bf_type; | |
9f42c2b6 | 228 | u8 bfs_paprd; |
ca369eb4 | 229 | unsigned long bfs_paprd_timestamp; |
93ef24b2 S |
230 | u32 bfs_keyix; |
231 | enum ath9k_key_type bfs_keytype; | |
232 | }; | |
233 | ||
234 | struct ath_buf { | |
235 | struct list_head list; | |
236 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
237 | an aggregate) */ | |
238 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
239 | struct sk_buff *bf_mpdu; /* enclosing frame structure */ | |
240 | void *bf_desc; /* virtual addr of desc */ | |
241 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
242 | dma_addr_t bf_buf_addr; /* physical addr of data buffer */ | |
243 | bool bf_stale; | |
244 | bool bf_isnullfunc; | |
245 | bool bf_tx_aborted; | |
246 | u16 bf_flags; | |
247 | struct ath_buf_state bf_state; | |
248 | dma_addr_t bf_dmacontext; | |
249 | struct ath_wiphy *aphy; | |
250 | }; | |
251 | ||
252 | struct ath_atx_tid { | |
253 | struct list_head list; | |
254 | struct list_head buf_q; | |
255 | struct ath_node *an; | |
256 | struct ath_atx_ac *ac; | |
257 | struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; | |
258 | u16 seq_start; | |
259 | u16 seq_next; | |
260 | u16 baw_size; | |
261 | int tidno; | |
262 | int baw_head; /* first un-acked tx buffer */ | |
263 | int baw_tail; /* next unused tx buffer slot */ | |
264 | int sched; | |
265 | int paused; | |
266 | u8 state; | |
267 | }; | |
268 | ||
269 | struct ath_node { | |
270 | struct ath_common *common; | |
271 | struct ath_atx_tid tid[WME_NUM_TID]; | |
272 | struct ath_atx_ac ac[WME_NUM_AC]; | |
273 | u16 maxampdu; | |
274 | u8 mpdudensity; | |
275 | int last_rssi; | |
276 | }; | |
277 | ||
394cf0a1 S |
278 | #define AGGR_CLEANUP BIT(1) |
279 | #define AGGR_ADDBA_COMPLETE BIT(2) | |
280 | #define AGGR_ADDBA_PROGRESS BIT(3) | |
281 | ||
394cf0a1 S |
282 | struct ath_tx_control { |
283 | struct ath_txq *txq; | |
284 | int if_id; | |
f0ed85c6 | 285 | enum ath9k_internal_frame_type frame_type; |
9f42c2b6 | 286 | u8 paprd; |
394cf0a1 S |
287 | }; |
288 | ||
394cf0a1 S |
289 | #define ATH_TX_ERROR 0x01 |
290 | #define ATH_TX_XRETRY 0x02 | |
291 | #define ATH_TX_BAR 0x04 | |
394cf0a1 | 292 | |
394cf0a1 S |
293 | struct ath_tx { |
294 | u16 seq_no; | |
295 | u32 txqsetup; | |
1d2231e2 | 296 | int hwq_map[WME_NUM_AC]; |
394cf0a1 S |
297 | spinlock_t txbuflock; |
298 | struct list_head txbuf; | |
299 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
300 | struct ath_descdma txdma; | |
97923b14 | 301 | int pending_frames[WME_NUM_AC]; |
394cf0a1 S |
302 | }; |
303 | ||
b5c80475 FF |
304 | struct ath_rx_edma { |
305 | struct sk_buff_head rx_fifo; | |
306 | struct sk_buff_head rx_buffers; | |
307 | u32 rx_fifo_hwsize; | |
308 | }; | |
309 | ||
394cf0a1 S |
310 | struct ath_rx { |
311 | u8 defant; | |
312 | u8 rxotherant; | |
313 | u32 *rxlink; | |
394cf0a1 S |
314 | unsigned int rxfilter; |
315 | spinlock_t rxflushlock; | |
316 | spinlock_t rxbuflock; | |
317 | struct list_head rxbuf; | |
318 | struct ath_descdma rxdma; | |
b5c80475 FF |
319 | struct ath_buf *rx_bufptr; |
320 | struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; | |
394cf0a1 S |
321 | }; |
322 | ||
323 | int ath_startrecv(struct ath_softc *sc); | |
324 | bool ath_stoprecv(struct ath_softc *sc); | |
325 | void ath_flushrecv(struct ath_softc *sc); | |
326 | u32 ath_calcrxfilter(struct ath_softc *sc); | |
327 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
328 | void ath_rx_cleanup(struct ath_softc *sc); | |
b5c80475 | 329 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); |
394cf0a1 S |
330 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); |
331 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); | |
332 | int ath_tx_setup(struct ath_softc *sc, int haltype); | |
333 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); | |
334 | void ath_draintxq(struct ath_softc *sc, | |
335 | struct ath_txq *txq, bool retry_tx); | |
336 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); | |
337 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
338 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
339 | int ath_tx_init(struct ath_softc *sc, int nbufs); | |
797fe5cb | 340 | void ath_tx_cleanup(struct ath_softc *sc); |
394cf0a1 S |
341 | int ath_txq_update(struct ath_softc *sc, int qnum, |
342 | struct ath9k_tx_queue_info *q); | |
c52f33d0 | 343 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 S |
344 | struct ath_tx_control *txctl); |
345 | void ath_tx_tasklet(struct ath_softc *sc); | |
e5003249 | 346 | void ath_tx_edma_tasklet(struct ath_softc *sc); |
c52f33d0 | 347 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb); |
394cf0a1 | 348 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); |
f83da965 S |
349 | void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
350 | u16 tid, u16 *ssn); | |
351 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); | |
394cf0a1 | 352 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
3f7c5c10 | 353 | void ath9k_enable_ps(struct ath_softc *sc); |
394cf0a1 S |
354 | |
355 | /********/ | |
17d7904d | 356 | /* VIFs */ |
394cf0a1 | 357 | /********/ |
f078f209 | 358 | |
17d7904d | 359 | struct ath_vif { |
394cf0a1 | 360 | int av_bslot; |
4ed96f04 | 361 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 S |
362 | enum nl80211_iftype av_opmode; |
363 | struct ath_buf *av_bcbuf; | |
364 | struct ath_tx_control av_btxctl; | |
f0ed85c6 | 365 | u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */ |
f078f209 LR |
366 | }; |
367 | ||
394cf0a1 S |
368 | /*******************/ |
369 | /* Beacon Handling */ | |
370 | /*******************/ | |
f078f209 | 371 | |
394cf0a1 S |
372 | /* |
373 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
374 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
375 | * number of beacon intervals, the game's up. | |
376 | */ | |
377 | #define BSTUCK_THRESH (9 * ATH_BCBUF) | |
4ed96f04 | 378 | #define ATH_BCBUF 4 |
394cf0a1 S |
379 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
380 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
381 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | |
382 | ||
383 | struct ath_beacon_config { | |
384 | u16 beacon_interval; | |
385 | u16 listen_interval; | |
386 | u16 dtim_period; | |
387 | u16 bmiss_timeout; | |
388 | u8 dtim_count; | |
394cf0a1 S |
389 | }; |
390 | ||
391 | struct ath_beacon { | |
392 | enum { | |
393 | OK, /* no change needed */ | |
394 | UPDATE, /* update pending */ | |
395 | COMMIT /* beacon sent, commit change */ | |
396 | } updateslot; /* slot time update fsm */ | |
397 | ||
398 | u32 beaconq; | |
399 | u32 bmisscnt; | |
400 | u32 ast_be_xmit; | |
401 | u64 bc_tstamp; | |
2c3db3d5 | 402 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
c52f33d0 | 403 | struct ath_wiphy *bslot_aphy[ATH_BCBUF]; |
394cf0a1 S |
404 | int slottime; |
405 | int slotupdate; | |
406 | struct ath9k_tx_queue_info beacon_qi; | |
407 | struct ath_descdma bdma; | |
408 | struct ath_txq *cabq; | |
409 | struct list_head bbuf; | |
410 | }; | |
411 | ||
9fc9ab0a | 412 | void ath_beacon_tasklet(unsigned long data); |
2c3db3d5 | 413 | void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); |
c52f33d0 | 414 | int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); |
17d7904d | 415 | void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); |
94db2936 | 416 | int ath_beaconq_config(struct ath_softc *sc); |
394cf0a1 S |
417 | |
418 | /*******/ | |
419 | /* ANI */ | |
420 | /*******/ | |
f078f209 | 421 | |
20977d3e S |
422 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
423 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
e36b27af LR |
424 | #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ |
425 | #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ | |
20977d3e S |
426 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ |
427 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
f078f209 | 428 | |
ca369eb4 VT |
429 | #define ATH_PAPRD_TIMEOUT 100 /* msecs */ |
430 | ||
347809fc | 431 | void ath_hw_check(struct work_struct *work); |
9f42c2b6 | 432 | void ath_paprd_calibrate(struct work_struct *work); |
55624204 S |
433 | void ath_ani_calibrate(unsigned long data); |
434 | ||
0fca65c1 S |
435 | /**********/ |
436 | /* BTCOEX */ | |
437 | /**********/ | |
438 | ||
e08a6ace LR |
439 | /* Defines the BT AR_BT_COEX_WGHT used */ |
440 | enum ath_stomp_type { | |
441 | ATH_BTCOEX_NO_STOMP, | |
442 | ATH_BTCOEX_STOMP_ALL, | |
443 | ATH_BTCOEX_STOMP_LOW, | |
444 | ATH_BTCOEX_STOMP_NONE | |
445 | }; | |
446 | ||
2e20250a LR |
447 | struct ath_btcoex { |
448 | bool hw_timer_enabled; | |
449 | spinlock_t btcoex_lock; | |
450 | struct timer_list period_timer; /* Timer for BT period */ | |
451 | u32 bt_priority_cnt; | |
452 | unsigned long bt_priority_time; | |
e08a6ace | 453 | int bt_stomp_type; /* Types of BT stomping */ |
2e20250a LR |
454 | u32 btcoex_no_stomp; /* in usec */ |
455 | u32 btcoex_period; /* in usec */ | |
58da1318 | 456 | u32 btscan_no_stomp; /* in usec */ |
75d7839f | 457 | struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ |
2e20250a LR |
458 | }; |
459 | ||
0fca65c1 S |
460 | int ath_init_btcoex_timer(struct ath_softc *sc); |
461 | void ath9k_btcoex_timer_resume(struct ath_softc *sc); | |
462 | void ath9k_btcoex_timer_pause(struct ath_softc *sc); | |
463 | ||
394cf0a1 S |
464 | /********************/ |
465 | /* LED Control */ | |
466 | /********************/ | |
f078f209 | 467 | |
08fc5c1b VN |
468 | #define ATH_LED_PIN_DEF 1 |
469 | #define ATH_LED_PIN_9287 8 | |
394cf0a1 S |
470 | #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ |
471 | #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ | |
f078f209 | 472 | |
394cf0a1 S |
473 | enum ath_led_type { |
474 | ATH_LED_RADIO, | |
475 | ATH_LED_ASSOC, | |
476 | ATH_LED_TX, | |
477 | ATH_LED_RX | |
f078f209 LR |
478 | }; |
479 | ||
394cf0a1 S |
480 | struct ath_led { |
481 | struct ath_softc *sc; | |
482 | struct led_classdev led_cdev; | |
483 | enum ath_led_type led_type; | |
484 | char name[32]; | |
485 | bool registered; | |
f078f209 LR |
486 | }; |
487 | ||
0fca65c1 S |
488 | void ath_init_leds(struct ath_softc *sc); |
489 | void ath_deinit_leds(struct ath_softc *sc); | |
490 | ||
394cf0a1 S |
491 | /********************/ |
492 | /* Main driver core */ | |
493 | /********************/ | |
f078f209 | 494 | |
394cf0a1 S |
495 | /* |
496 | * Default cache line size, in bytes. | |
497 | * Used when PCI device not fully initialized by bootrom/BIOS | |
498 | */ | |
499 | #define DEFAULT_CACHELINE 32 | |
394cf0a1 S |
500 | #define ATH_REGCLASSIDS_MAX 10 |
501 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | |
502 | #define ATH_MAX_SW_RETRIES 10 | |
503 | #define ATH_CHAN_MAX 255 | |
504 | #define IEEE80211_WEP_NKID 4 /* number of key ids */ | |
f1dc5600 | 505 | |
394cf0a1 | 506 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
394cf0a1 S |
507 | #define ATH_RATE_DUMMY_MARKER 0 |
508 | ||
1b04b930 S |
509 | #define SC_OP_INVALID BIT(0) |
510 | #define SC_OP_BEACONS BIT(1) | |
511 | #define SC_OP_RXAGGR BIT(2) | |
512 | #define SC_OP_TXAGGR BIT(3) | |
513 | #define SC_OP_FULL_RESET BIT(4) | |
514 | #define SC_OP_PREAMBLE_SHORT BIT(5) | |
515 | #define SC_OP_PROTECT_ENABLE BIT(6) | |
516 | #define SC_OP_RXFLUSH BIT(7) | |
517 | #define SC_OP_LED_ASSOCIATED BIT(8) | |
518 | #define SC_OP_LED_ON BIT(9) | |
519 | #define SC_OP_SCANNING BIT(10) | |
520 | #define SC_OP_TSF_RESET BIT(11) | |
521 | #define SC_OP_BT_PRIORITY_DETECTED BIT(12) | |
58da1318 | 522 | #define SC_OP_BT_SCAN BIT(13) |
6c3118e2 | 523 | #define SC_OP_ANI_RUN BIT(14) |
1b04b930 S |
524 | |
525 | /* Powersave flags */ | |
526 | #define PS_WAIT_FOR_BEACON BIT(0) | |
527 | #define PS_WAIT_FOR_CAB BIT(1) | |
528 | #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) | |
529 | #define PS_WAIT_FOR_TX_ACK BIT(3) | |
530 | #define PS_BEACON_SYNC BIT(4) | |
531 | #define PS_NULLFUNC_COMPLETED BIT(5) | |
532 | #define PS_ENABLED BIT(6) | |
394cf0a1 | 533 | |
bce048d7 | 534 | struct ath_wiphy; |
545750d3 | 535 | struct ath_rate_table; |
bce048d7 | 536 | |
394cf0a1 S |
537 | struct ath_softc { |
538 | struct ieee80211_hw *hw; | |
539 | struct device *dev; | |
c52f33d0 JM |
540 | |
541 | spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ | |
bce048d7 | 542 | struct ath_wiphy *pri_wiphy; |
c52f33d0 JM |
543 | struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may |
544 | * have NULL entries */ | |
545 | int num_sec_wiphy; /* number of sec_wiphy pointers in the array */ | |
0e2dedf9 JM |
546 | int chan_idx; |
547 | int chan_is_ht; | |
548 | struct ath_wiphy *next_wiphy; | |
549 | struct work_struct chan_work; | |
7ec3e514 JM |
550 | int wiphy_select_failures; |
551 | unsigned long wiphy_select_first_fail; | |
f98c3bd2 JM |
552 | struct delayed_work wiphy_work; |
553 | unsigned long wiphy_scheduler_int; | |
554 | int wiphy_scheduler_index; | |
0e2dedf9 | 555 | |
394cf0a1 S |
556 | struct tasklet_struct intr_tq; |
557 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 558 | struct ath_hw *sc_ah; |
394cf0a1 S |
559 | void __iomem *mem; |
560 | int irq; | |
561 | spinlock_t sc_resetlock; | |
2d6a5e95 | 562 | spinlock_t sc_serial_rw; |
04717ccd | 563 | spinlock_t sc_pm_lock; |
394cf0a1 | 564 | struct mutex mutex; |
9f42c2b6 | 565 | struct work_struct paprd_work; |
347809fc | 566 | struct work_struct hw_check_work; |
9f42c2b6 | 567 | struct completion paprd_complete; |
394cf0a1 | 568 | |
17d7904d | 569 | u32 intrstatus; |
394cf0a1 | 570 | u32 sc_flags; /* SC_OP_* */ |
1b04b930 | 571 | u16 ps_flags; /* PS_* */ |
17d7904d | 572 | u16 curtxpow; |
17d7904d S |
573 | u8 nbcnvifs; |
574 | u16 nvifs; | |
96148326 | 575 | bool ps_enabled; |
1dbfd9d4 | 576 | bool ps_idle; |
709ade9e | 577 | unsigned long ps_usecount; |
394cf0a1 | 578 | |
17d7904d | 579 | struct ath_config config; |
394cf0a1 S |
580 | struct ath_rx rx; |
581 | struct ath_tx tx; | |
582 | struct ath_beacon beacon; | |
4f0fc7c3 | 583 | const struct ath_rate_table *cur_rate_table; |
545750d3 | 584 | enum wireless_mode cur_rate_mode; |
394cf0a1 S |
585 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; |
586 | ||
587 | struct ath_led radio_led; | |
588 | struct ath_led assoc_led; | |
589 | struct ath_led tx_led; | |
590 | struct ath_led rx_led; | |
591 | struct delayed_work ath_led_blink_work; | |
592 | int led_on_duration; | |
593 | int led_off_duration; | |
594 | int led_on_cnt; | |
595 | int led_off_cnt; | |
596 | ||
57c4d7b4 JB |
597 | int beacon_interval; |
598 | ||
a830df07 | 599 | #ifdef CONFIG_ATH9K_DEBUGFS |
17d7904d | 600 | struct ath9k_debug debug; |
394cf0a1 | 601 | #endif |
6b96f93e | 602 | struct ath_beacon_config cur_beacon_conf; |
164ace38 | 603 | struct delayed_work tx_complete_work; |
2e20250a | 604 | struct ath_btcoex btcoex; |
5088c2f1 VT |
605 | |
606 | struct ath_descdma txsdma; | |
394cf0a1 S |
607 | }; |
608 | ||
bce048d7 JM |
609 | struct ath_wiphy { |
610 | struct ath_softc *sc; /* shared for all virtual wiphys */ | |
611 | struct ieee80211_hw *hw; | |
f0ed85c6 | 612 | enum ath_wiphy_state { |
9580a222 | 613 | ATH_WIPHY_INACTIVE, |
f0ed85c6 JM |
614 | ATH_WIPHY_ACTIVE, |
615 | ATH_WIPHY_PAUSING, | |
616 | ATH_WIPHY_PAUSED, | |
8089cc47 | 617 | ATH_WIPHY_SCAN, |
f0ed85c6 | 618 | } state; |
194b7c13 | 619 | bool idle; |
0e2dedf9 JM |
620 | int chan_idx; |
621 | int chan_is_ht; | |
bce048d7 JM |
622 | }; |
623 | ||
55624204 | 624 | void ath9k_tasklet(unsigned long data); |
394cf0a1 | 625 | int ath_reset(struct ath_softc *sc, bool retry_tx); |
394cf0a1 S |
626 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); |
627 | int ath_cabq_update(struct ath_softc *); | |
628 | ||
5bb12791 | 629 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
394cf0a1 | 630 | { |
5bb12791 | 631 | common->bus_ops->read_cachesize(common, csz); |
394cf0a1 S |
632 | } |
633 | ||
394cf0a1 | 634 | extern struct ieee80211_ops ath9k_ops; |
55624204 | 635 | extern int modparam_nohwcrypt; |
9a75c2ff | 636 | extern int led_blink; |
394cf0a1 S |
637 | |
638 | irqreturn_t ath_isr(int irq, void *dev); | |
285f2dda | 639 | int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, |
5bb12791 | 640 | const struct ath_bus_ops *bus_ops); |
285f2dda | 641 | void ath9k_deinit_device(struct ath_softc *sc); |
285f2dda | 642 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); |
0e2dedf9 JM |
643 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
644 | struct ath9k_channel *ichan); | |
645 | void ath_update_chainmask(struct ath_softc *sc, int is_ht); | |
646 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
647 | struct ath9k_channel *hchan); | |
68a89116 LR |
648 | |
649 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
650 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
55624204 | 651 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode); |
394cf0a1 S |
652 | |
653 | #ifdef CONFIG_PCI | |
654 | int ath_pci_init(void); | |
655 | void ath_pci_exit(void); | |
656 | #else | |
657 | static inline int ath_pci_init(void) { return 0; }; | |
658 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 659 | #endif |
f1dc5600 | 660 | |
394cf0a1 S |
661 | #ifdef CONFIG_ATHEROS_AR71XX |
662 | int ath_ahb_init(void); | |
663 | void ath_ahb_exit(void); | |
664 | #else | |
665 | static inline int ath_ahb_init(void) { return 0; }; | |
666 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 667 | #endif |
394cf0a1 | 668 | |
0bc0798b GJ |
669 | void ath9k_ps_wakeup(struct ath_softc *sc); |
670 | void ath9k_ps_restore(struct ath_softc *sc); | |
8ca21f01 JM |
671 | |
672 | void ath9k_set_bssid_mask(struct ieee80211_hw *hw); | |
c52f33d0 JM |
673 | int ath9k_wiphy_add(struct ath_softc *sc); |
674 | int ath9k_wiphy_del(struct ath_wiphy *aphy); | |
f0ed85c6 JM |
675 | void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb); |
676 | int ath9k_wiphy_pause(struct ath_wiphy *aphy); | |
677 | int ath9k_wiphy_unpause(struct ath_wiphy *aphy); | |
0e2dedf9 | 678 | int ath9k_wiphy_select(struct ath_wiphy *aphy); |
f98c3bd2 | 679 | void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int); |
0e2dedf9 | 680 | void ath9k_wiphy_chan_work(struct work_struct *work); |
9580a222 | 681 | bool ath9k_wiphy_started(struct ath_softc *sc); |
18eb62f8 JM |
682 | void ath9k_wiphy_pause_all_forced(struct ath_softc *sc, |
683 | struct ath_wiphy *selected); | |
8089cc47 | 684 | bool ath9k_wiphy_scanning(struct ath_softc *sc); |
f98c3bd2 | 685 | void ath9k_wiphy_work(struct work_struct *work); |
64839170 | 686 | bool ath9k_all_wiphys_idle(struct ath_softc *sc); |
194b7c13 | 687 | void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle); |
8ca21f01 | 688 | |
f52de03b LR |
689 | void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue); |
690 | void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue); | |
691 | ||
0fca65c1 S |
692 | void ath_start_rfkill_poll(struct ath_softc *sc); |
693 | extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); | |
694 | ||
394cf0a1 | 695 | #endif /* ATH9K_H */ |