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Commit | Line | Data |
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f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
a6b7a407 | 22 | #include <linux/interrupt.h> |
394cf0a1 | 23 | #include <linux/leds.h> |
9f42c2b6 | 24 | #include <linux/completion.h> |
394cf0a1 | 25 | |
394cf0a1 | 26 | #include "debug.h" |
db86f07e | 27 | #include "common.h" |
7dc181c2 | 28 | #include "mci.h" |
8e92d3f2 | 29 | #include "dfs.h" |
db86f07e LR |
30 | |
31 | /* | |
32 | * Header for the ath9k.ko driver core *only* -- hw code nor any other driver | |
33 | * should rely on this file or its contents. | |
34 | */ | |
394cf0a1 S |
35 | |
36 | struct ath_node; | |
37 | ||
38 | /* Macro to expand scalars to 64-bit objects */ | |
39 | ||
13bda122 | 40 | #define ito64(x) (sizeof(x) == 1) ? \ |
394cf0a1 | 41 | (((unsigned long long int)(x)) & (0xff)) : \ |
13bda122 | 42 | (sizeof(x) == 2) ? \ |
394cf0a1 | 43 | (((unsigned long long int)(x)) & 0xffff) : \ |
13bda122 | 44 | ((sizeof(x) == 4) ? \ |
394cf0a1 S |
45 | (((unsigned long long int)(x)) & 0xffffffff) : \ |
46 | (unsigned long long int)(x)) | |
47 | ||
48 | /* increment with wrap-around */ | |
49 | #define INCR(_l, _sz) do { \ | |
50 | (_l)++; \ | |
51 | (_l) &= ((_sz) - 1); \ | |
52 | } while (0) | |
53 | ||
54 | /* decrement with wrap-around */ | |
55 | #define DECR(_l, _sz) do { \ | |
56 | (_l)--; \ | |
57 | (_l) &= ((_sz) - 1); \ | |
58 | } while (0) | |
59 | ||
394cf0a1 S |
60 | #define TSF_TO_TU(_h,_l) \ |
61 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
62 | ||
63 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) | |
64 | ||
394cf0a1 | 65 | struct ath_config { |
394cf0a1 S |
66 | u16 txpowlimit; |
67 | u8 cabqReadytime; | |
394cf0a1 S |
68 | }; |
69 | ||
70 | /*************************/ | |
71 | /* Descriptor Management */ | |
72 | /*************************/ | |
73 | ||
74 | #define ATH_TXBUF_RESET(_bf) do { \ | |
a119cc49 | 75 | (_bf)->bf_stale = false; \ |
394cf0a1 S |
76 | (_bf)->bf_lastbf = NULL; \ |
77 | (_bf)->bf_next = NULL; \ | |
78 | memset(&((_bf)->bf_state), 0, \ | |
79 | sizeof(struct ath_buf_state)); \ | |
80 | } while (0) | |
81 | ||
a119cc49 S |
82 | #define ATH_RXBUF_RESET(_bf) do { \ |
83 | (_bf)->bf_stale = false; \ | |
84 | } while (0) | |
85 | ||
394cf0a1 S |
86 | /** |
87 | * enum buffer_type - Buffer type flags | |
88 | * | |
394cf0a1 S |
89 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) |
90 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
91 | * (used in aggregation scheduling) | |
394cf0a1 S |
92 | */ |
93 | enum buffer_type { | |
436d0d98 MSS |
94 | BUF_AMPDU = BIT(0), |
95 | BUF_AGGR = BIT(1), | |
394cf0a1 S |
96 | }; |
97 | ||
394cf0a1 S |
98 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) |
99 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
f078f209 | 100 | |
016c2177 | 101 | #define ATH_TXSTATUS_RING_SIZE 512 |
5088c2f1 | 102 | |
c3d77696 MSS |
103 | #define DS2PHYS(_dd, _ds) \ |
104 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
105 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
106 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
107 | ||
394cf0a1 | 108 | struct ath_descdma { |
5088c2f1 | 109 | void *dd_desc; |
17d7904d S |
110 | dma_addr_t dd_desc_paddr; |
111 | u32 dd_desc_len; | |
112 | struct ath_buf *dd_bufptr; | |
394cf0a1 S |
113 | }; |
114 | ||
115 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
116 | struct list_head *head, const char *name, | |
4adfcded | 117 | int nbuf, int ndesc, bool is_tx); |
394cf0a1 S |
118 | void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, |
119 | struct list_head *head); | |
120 | ||
121 | /***********/ | |
122 | /* RX / TX */ | |
123 | /***********/ | |
124 | ||
394cf0a1 | 125 | #define ATH_RXBUF 512 |
394cf0a1 | 126 | #define ATH_TXBUF 512 |
84642d6b FF |
127 | #define ATH_TXBUF_RESERVE 5 |
128 | #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) | |
394cf0a1 | 129 | #define ATH_TXMAXTRY 13 |
394cf0a1 S |
130 | |
131 | #define TID_TO_WME_AC(_tid) \ | |
132 | ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ | |
133 | (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ | |
134 | (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ | |
135 | WME_AC_VO) | |
136 | ||
394cf0a1 S |
137 | #define ATH_AGGR_DELIM_SZ 4 |
138 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
139 | /* number of delimiters for encryption padding */ | |
140 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
141 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
142 | #define ATH_AGGR_MIN_QDEPTH 2 | |
143 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | |
394cf0a1 S |
144 | |
145 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | |
146 | #define IEEE80211_SEQ_MAX 4096 | |
394cf0a1 S |
147 | #define IEEE80211_WEP_IVLEN 3 |
148 | #define IEEE80211_WEP_KIDLEN 1 | |
149 | #define IEEE80211_WEP_CRCLEN 4 | |
150 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
151 | (IEEE80211_WEP_IVLEN + \ | |
152 | IEEE80211_WEP_KIDLEN + \ | |
153 | IEEE80211_WEP_CRCLEN)) | |
154 | ||
155 | /* return whether a bit at index _n in bitmap _bm is set | |
156 | * _sz is the size of the bitmap */ | |
157 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
158 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
159 | ||
160 | /* return block-ack bitmap index given sequence and starting sequence */ | |
161 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
162 | ||
156369fa FF |
163 | /* return the seqno for _start + _offset */ |
164 | #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) | |
165 | ||
394cf0a1 S |
166 | /* returns delimiter padding required given the packet length */ |
167 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
39ec2997 VT |
168 | (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ |
169 | DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) | |
394cf0a1 S |
170 | |
171 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
172 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
173 | ||
394cf0a1 S |
174 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) |
175 | ||
164ace38 SB |
176 | #define ATH_TX_COMPLETE_POLL_INT 1000 |
177 | ||
394cf0a1 S |
178 | enum ATH_AGGR_STATUS { |
179 | ATH_AGGR_DONE, | |
180 | ATH_AGGR_BAW_CLOSED, | |
181 | ATH_AGGR_LIMITED, | |
182 | }; | |
183 | ||
e5003249 | 184 | #define ATH_TXFIFO_DEPTH 8 |
394cf0a1 | 185 | struct ath_txq { |
60f2d1d5 BG |
186 | int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ |
187 | u32 axq_qnum; /* ath9k hardware queue number */ | |
fce041be | 188 | void *axq_link; |
17d7904d | 189 | struct list_head axq_q; |
394cf0a1 | 190 | spinlock_t axq_lock; |
17d7904d | 191 | u32 axq_depth; |
4b3ba66a | 192 | u32 axq_ampdu_depth; |
17d7904d | 193 | bool stopped; |
164ace38 | 194 | bool axq_tx_inprogress; |
394cf0a1 | 195 | struct list_head axq_acq; |
e5003249 | 196 | struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; |
e5003249 VT |
197 | u8 txq_headidx; |
198 | u8 txq_tailidx; | |
066dae93 | 199 | int pending_frames; |
23de5dc9 | 200 | struct sk_buff_head complete_q; |
394cf0a1 S |
201 | }; |
202 | ||
93ef24b2 | 203 | struct ath_atx_ac { |
066dae93 | 204 | struct ath_txq *txq; |
93ef24b2 | 205 | int sched; |
93ef24b2 S |
206 | struct list_head list; |
207 | struct list_head tid_q; | |
5519541d | 208 | bool clear_ps_filter; |
93ef24b2 S |
209 | }; |
210 | ||
2d42efc4 | 211 | struct ath_frame_info { |
56dc6336 | 212 | struct ath_buf *bf; |
2d42efc4 | 213 | int framelen; |
2d42efc4 | 214 | enum ath9k_key_type keytype; |
a75c0629 | 215 | u8 keyix; |
2d42efc4 | 216 | u8 retries; |
2d42efc4 FF |
217 | }; |
218 | ||
93ef24b2 | 219 | struct ath_buf_state { |
93ef24b2 | 220 | u8 bf_type; |
9f42c2b6 | 221 | u8 bfs_paprd; |
399c6489 | 222 | u8 ndelim; |
6a0ddaef | 223 | u16 seqno; |
9cf04dcc | 224 | unsigned long bfs_paprd_timestamp; |
93ef24b2 S |
225 | }; |
226 | ||
227 | struct ath_buf { | |
228 | struct list_head list; | |
229 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
230 | an aggregate) */ | |
231 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
232 | struct sk_buff *bf_mpdu; /* enclosing frame structure */ | |
233 | void *bf_desc; /* virtual addr of desc */ | |
234 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
c1739eb3 | 235 | dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ |
93ef24b2 | 236 | bool bf_stale; |
93ef24b2 | 237 | struct ath_buf_state bf_state; |
93ef24b2 S |
238 | }; |
239 | ||
240 | struct ath_atx_tid { | |
241 | struct list_head list; | |
56dc6336 | 242 | struct sk_buff_head buf_q; |
93ef24b2 S |
243 | struct ath_node *an; |
244 | struct ath_atx_ac *ac; | |
81ee13ba | 245 | unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; |
f9437543 | 246 | int bar_index; |
93ef24b2 S |
247 | u16 seq_start; |
248 | u16 seq_next; | |
249 | u16 baw_size; | |
250 | int tidno; | |
251 | int baw_head; /* first un-acked tx buffer */ | |
252 | int baw_tail; /* next unused tx buffer slot */ | |
253 | int sched; | |
254 | int paused; | |
255 | u8 state; | |
256 | }; | |
257 | ||
258 | struct ath_node { | |
7f010c93 BG |
259 | #ifdef CONFIG_ATH9K_DEBUGFS |
260 | struct list_head list; /* for sc->nodes */ | |
156369fa | 261 | #endif |
7f010c93 | 262 | struct ieee80211_sta *sta; /* station struct we're part of */ |
7e1e3864 | 263 | struct ieee80211_vif *vif; /* interface with which we're associated */ |
93ef24b2 S |
264 | struct ath_atx_tid tid[WME_NUM_TID]; |
265 | struct ath_atx_ac ac[WME_NUM_AC]; | |
93ae2dd2 FF |
266 | int ps_key; |
267 | ||
93ef24b2 S |
268 | u16 maxampdu; |
269 | u8 mpdudensity; | |
5519541d FF |
270 | |
271 | bool sleeping; | |
93ef24b2 S |
272 | }; |
273 | ||
394cf0a1 S |
274 | #define AGGR_CLEANUP BIT(1) |
275 | #define AGGR_ADDBA_COMPLETE BIT(2) | |
276 | #define AGGR_ADDBA_PROGRESS BIT(3) | |
277 | ||
394cf0a1 S |
278 | struct ath_tx_control { |
279 | struct ath_txq *txq; | |
2d42efc4 | 280 | struct ath_node *an; |
9f42c2b6 | 281 | u8 paprd; |
394cf0a1 S |
282 | }; |
283 | ||
394cf0a1 | 284 | #define ATH_TX_ERROR 0x01 |
394cf0a1 | 285 | |
60f2d1d5 BG |
286 | /** |
287 | * @txq_map: Index is mac80211 queue number. This is | |
288 | * not necessarily the same as the hardware queue number | |
289 | * (axq_qnum). | |
290 | */ | |
394cf0a1 S |
291 | struct ath_tx { |
292 | u16 seq_no; | |
293 | u32 txqsetup; | |
394cf0a1 S |
294 | spinlock_t txbuflock; |
295 | struct list_head txbuf; | |
296 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
297 | struct ath_descdma txdma; | |
066dae93 | 298 | struct ath_txq *txq_map[WME_NUM_AC]; |
394cf0a1 S |
299 | }; |
300 | ||
b5c80475 FF |
301 | struct ath_rx_edma { |
302 | struct sk_buff_head rx_fifo; | |
b5c80475 FF |
303 | u32 rx_fifo_hwsize; |
304 | }; | |
305 | ||
394cf0a1 S |
306 | struct ath_rx { |
307 | u8 defant; | |
308 | u8 rxotherant; | |
309 | u32 *rxlink; | |
6995fb80 | 310 | u32 num_pkts; |
394cf0a1 | 311 | unsigned int rxfilter; |
394cf0a1 S |
312 | spinlock_t rxbuflock; |
313 | struct list_head rxbuf; | |
314 | struct ath_descdma rxdma; | |
b5c80475 FF |
315 | struct ath_buf *rx_bufptr; |
316 | struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; | |
0d95521e FF |
317 | |
318 | struct sk_buff *frag; | |
394cf0a1 S |
319 | }; |
320 | ||
321 | int ath_startrecv(struct ath_softc *sc); | |
322 | bool ath_stoprecv(struct ath_softc *sc); | |
323 | void ath_flushrecv(struct ath_softc *sc); | |
324 | u32 ath_calcrxfilter(struct ath_softc *sc); | |
325 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
326 | void ath_rx_cleanup(struct ath_softc *sc); | |
b5c80475 | 327 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); |
394cf0a1 S |
328 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); |
329 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); | |
080e1a25 | 330 | bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); |
394cf0a1 S |
331 | void ath_draintxq(struct ath_softc *sc, |
332 | struct ath_txq *txq, bool retry_tx); | |
333 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); | |
334 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
335 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
336 | int ath_tx_init(struct ath_softc *sc, int nbufs); | |
797fe5cb | 337 | void ath_tx_cleanup(struct ath_softc *sc); |
394cf0a1 S |
338 | int ath_txq_update(struct ath_softc *sc, int qnum, |
339 | struct ath9k_tx_queue_info *q); | |
c52f33d0 | 340 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 S |
341 | struct ath_tx_control *txctl); |
342 | void ath_tx_tasklet(struct ath_softc *sc); | |
e5003249 | 343 | void ath_tx_edma_tasklet(struct ath_softc *sc); |
231c3a1f FF |
344 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
345 | u16 tid, u16 *ssn); | |
f83da965 | 346 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
394cf0a1 S |
347 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
348 | ||
5519541d | 349 | void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); |
042ec453 JB |
350 | void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, |
351 | struct ath_node *an); | |
5519541d | 352 | |
394cf0a1 | 353 | /********/ |
17d7904d | 354 | /* VIFs */ |
394cf0a1 | 355 | /********/ |
f078f209 | 356 | |
17d7904d | 357 | struct ath_vif { |
394cf0a1 | 358 | int av_bslot; |
4f5ef75b | 359 | bool is_bslot_active, primary_sta_vif; |
4ed96f04 | 360 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 | 361 | struct ath_buf *av_bcbuf; |
f078f209 LR |
362 | }; |
363 | ||
394cf0a1 S |
364 | /*******************/ |
365 | /* Beacon Handling */ | |
366 | /*******************/ | |
f078f209 | 367 | |
394cf0a1 S |
368 | /* |
369 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
370 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
371 | * number of beacon intervals, the game's up. | |
372 | */ | |
c944daf4 | 373 | #define BSTUCK_THRESH 9 |
689e756f | 374 | #define ATH_BCBUF 8 |
394cf0a1 S |
375 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
376 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
377 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | |
378 | ||
379 | struct ath_beacon_config { | |
9814f6b3 | 380 | int beacon_interval; |
394cf0a1 S |
381 | u16 listen_interval; |
382 | u16 dtim_period; | |
383 | u16 bmiss_timeout; | |
384 | u8 dtim_count; | |
394cf0a1 S |
385 | }; |
386 | ||
387 | struct ath_beacon { | |
388 | enum { | |
389 | OK, /* no change needed */ | |
390 | UPDATE, /* update pending */ | |
391 | COMMIT /* beacon sent, commit change */ | |
392 | } updateslot; /* slot time update fsm */ | |
393 | ||
394 | u32 beaconq; | |
395 | u32 bmisscnt; | |
396 | u32 ast_be_xmit; | |
dd347f2f | 397 | u32 bc_tstamp; |
2c3db3d5 | 398 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
394cf0a1 S |
399 | int slottime; |
400 | int slotupdate; | |
401 | struct ath9k_tx_queue_info beacon_qi; | |
402 | struct ath_descdma bdma; | |
403 | struct ath_txq *cabq; | |
404 | struct list_head bbuf; | |
ba4903f9 FF |
405 | |
406 | bool tx_processed; | |
407 | bool tx_last; | |
394cf0a1 S |
408 | }; |
409 | ||
9fc9ab0a | 410 | void ath_beacon_tasklet(unsigned long data); |
2c3db3d5 | 411 | void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); |
9ac58615 | 412 | int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif); |
17d7904d | 413 | void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); |
94db2936 | 414 | int ath_beaconq_config(struct ath_softc *sc); |
99e4d43a | 415 | void ath_set_beacon(struct ath_softc *sc); |
014cf3bb | 416 | void ath9k_set_beaconing_status(struct ath_softc *sc, bool status); |
394cf0a1 S |
417 | |
418 | /*******/ | |
419 | /* ANI */ | |
420 | /*******/ | |
f078f209 | 421 | |
20977d3e S |
422 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
423 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
e36b27af LR |
424 | #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ |
425 | #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ | |
6044474e | 426 | #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ |
20977d3e S |
427 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ |
428 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
f078f209 | 429 | |
ca369eb4 VT |
430 | #define ATH_PAPRD_TIMEOUT 100 /* msecs */ |
431 | ||
236de514 | 432 | void ath_reset_work(struct work_struct *work); |
347809fc | 433 | void ath_hw_check(struct work_struct *work); |
9eab61c2 | 434 | void ath_hw_pll_work(struct work_struct *work); |
01e18918 RM |
435 | void ath_rx_poll(unsigned long data); |
436 | void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon); | |
9f42c2b6 | 437 | void ath_paprd_calibrate(struct work_struct *work); |
55624204 | 438 | void ath_ani_calibrate(unsigned long data); |
05c0be2f | 439 | void ath_start_ani(struct ath_common *common); |
55624204 | 440 | |
0fca65c1 S |
441 | /**********/ |
442 | /* BTCOEX */ | |
443 | /**********/ | |
444 | ||
e6930c4b SM |
445 | enum bt_op_flags { |
446 | BT_OP_PRIORITY_DETECTED, | |
447 | BT_OP_SCAN, | |
448 | }; | |
449 | ||
2e20250a LR |
450 | struct ath_btcoex { |
451 | bool hw_timer_enabled; | |
452 | spinlock_t btcoex_lock; | |
453 | struct timer_list period_timer; /* Timer for BT period */ | |
454 | u32 bt_priority_cnt; | |
455 | unsigned long bt_priority_time; | |
e6930c4b | 456 | unsigned long op_flags; |
e08a6ace | 457 | int bt_stomp_type; /* Types of BT stomping */ |
2e20250a LR |
458 | u32 btcoex_no_stomp; /* in usec */ |
459 | u32 btcoex_period; /* in usec */ | |
58da1318 | 460 | u32 btscan_no_stomp; /* in usec */ |
7dc181c2 | 461 | u32 duty_cycle; |
6995fb80 | 462 | u32 bt_wait_time; |
75d7839f | 463 | struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ |
7dc181c2 | 464 | struct ath_mci_profile mci; |
2e20250a LR |
465 | }; |
466 | ||
4daa7760 | 467 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
5908120f SM |
468 | int ath9k_init_btcoex(struct ath_softc *sc); |
469 | void ath9k_deinit_btcoex(struct ath_softc *sc); | |
df198b17 SM |
470 | void ath9k_start_btcoex(struct ath_softc *sc); |
471 | void ath9k_stop_btcoex(struct ath_softc *sc); | |
0fca65c1 S |
472 | void ath9k_btcoex_timer_resume(struct ath_softc *sc); |
473 | void ath9k_btcoex_timer_pause(struct ath_softc *sc); | |
56ca0dba | 474 | void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); |
c0ac53fa | 475 | u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); |
4daa7760 SM |
476 | #else |
477 | static inline int ath9k_init_btcoex(struct ath_softc *sc) | |
478 | { | |
479 | return 0; | |
480 | } | |
481 | static inline void ath9k_deinit_btcoex(struct ath_softc *sc) | |
482 | { | |
483 | } | |
484 | static inline void ath9k_start_btcoex(struct ath_softc *sc) | |
485 | { | |
486 | } | |
487 | static inline void ath9k_stop_btcoex(struct ath_softc *sc) | |
488 | { | |
489 | } | |
490 | static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, | |
491 | u32 status) | |
492 | { | |
493 | } | |
494 | static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, | |
495 | u32 max_4ms_framelen) | |
496 | { | |
497 | return 0; | |
498 | } | |
499 | #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ | |
0fca65c1 | 500 | |
394cf0a1 S |
501 | /********************/ |
502 | /* LED Control */ | |
503 | /********************/ | |
f078f209 | 504 | |
08fc5c1b VN |
505 | #define ATH_LED_PIN_DEF 1 |
506 | #define ATH_LED_PIN_9287 8 | |
353e5019 | 507 | #define ATH_LED_PIN_9300 10 |
15178535 | 508 | #define ATH_LED_PIN_9485 6 |
1a68abb0 | 509 | #define ATH_LED_PIN_9462 4 |
f078f209 | 510 | |
0cf55c21 | 511 | #ifdef CONFIG_MAC80211_LEDS |
0fca65c1 S |
512 | void ath_init_leds(struct ath_softc *sc); |
513 | void ath_deinit_leds(struct ath_softc *sc); | |
0cf55c21 FF |
514 | #else |
515 | static inline void ath_init_leds(struct ath_softc *sc) | |
516 | { | |
517 | } | |
518 | ||
519 | static inline void ath_deinit_leds(struct ath_softc *sc) | |
520 | { | |
521 | } | |
522 | #endif | |
523 | ||
0fca65c1 | 524 | |
102885a5 VT |
525 | /* Antenna diversity/combining */ |
526 | #define ATH_ANT_RX_CURRENT_SHIFT 4 | |
527 | #define ATH_ANT_RX_MAIN_SHIFT 2 | |
528 | #define ATH_ANT_RX_MASK 0x3 | |
529 | ||
530 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 | |
531 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 | |
532 | #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 | |
533 | #define ATH_ANT_DIV_COMB_INIT_COUNT 95 | |
534 | #define ATH_ANT_DIV_COMB_MAX_COUNT 100 | |
535 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 | |
536 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 | |
537 | ||
102885a5 VT |
538 | #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 |
539 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 | |
540 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 | |
541 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 | |
542 | ||
543 | enum ath9k_ant_div_comb_lna_conf { | |
544 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, | |
545 | ATH_ANT_DIV_COMB_LNA2, | |
546 | ATH_ANT_DIV_COMB_LNA1, | |
547 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, | |
548 | }; | |
549 | ||
550 | struct ath_ant_comb { | |
551 | u16 count; | |
552 | u16 total_pkt_count; | |
553 | bool scan; | |
554 | bool scan_not_start; | |
555 | int main_total_rssi; | |
556 | int alt_total_rssi; | |
557 | int alt_recv_cnt; | |
558 | int main_recv_cnt; | |
559 | int rssi_lna1; | |
560 | int rssi_lna2; | |
561 | int rssi_add; | |
562 | int rssi_sub; | |
563 | int rssi_first; | |
564 | int rssi_second; | |
565 | int rssi_third; | |
566 | bool alt_good; | |
567 | int quick_scan_cnt; | |
568 | int main_conf; | |
569 | enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; | |
570 | enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; | |
571 | int first_bias; | |
572 | int second_bias; | |
573 | bool first_ratio; | |
574 | bool second_ratio; | |
575 | unsigned long scan_start_time; | |
576 | }; | |
577 | ||
394cf0a1 S |
578 | /********************/ |
579 | /* Main driver core */ | |
580 | /********************/ | |
f078f209 | 581 | |
394cf0a1 S |
582 | /* |
583 | * Default cache line size, in bytes. | |
584 | * Used when PCI device not fully initialized by bootrom/BIOS | |
585 | */ | |
586 | #define DEFAULT_CACHELINE 32 | |
394cf0a1 S |
587 | #define ATH_REGCLASSIDS_MAX 10 |
588 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | |
da647626 | 589 | #define ATH_MAX_SW_RETRIES 30 |
394cf0a1 | 590 | #define ATH_CHAN_MAX 255 |
f1dc5600 | 591 | |
394cf0a1 | 592 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
394cf0a1 S |
593 | #define ATH_RATE_DUMMY_MARKER 0 |
594 | ||
1b04b930 S |
595 | #define SC_OP_INVALID BIT(0) |
596 | #define SC_OP_BEACONS BIT(1) | |
4cb54fa3 SM |
597 | #define SC_OP_RXFLUSH BIT(2) |
598 | #define SC_OP_TSF_RESET BIT(3) | |
e6930c4b SM |
599 | #define SC_OP_ANI_RUN BIT(4) |
600 | #define SC_OP_PRIM_STA_VIF BIT(5) | |
1b04b930 S |
601 | |
602 | /* Powersave flags */ | |
603 | #define PS_WAIT_FOR_BEACON BIT(0) | |
604 | #define PS_WAIT_FOR_CAB BIT(1) | |
605 | #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) | |
606 | #define PS_WAIT_FOR_TX_ACK BIT(3) | |
607 | #define PS_BEACON_SYNC BIT(4) | |
394cf0a1 | 608 | |
545750d3 | 609 | struct ath_rate_table; |
bce048d7 | 610 | |
4801416c BG |
611 | struct ath9k_vif_iter_data { |
612 | const u8 *hw_macaddr; /* phy's hardware address, set | |
613 | * before starting iteration for | |
614 | * valid bssid mask. | |
615 | */ | |
616 | u8 mask[ETH_ALEN]; /* bssid mask */ | |
617 | int naps; /* number of AP vifs */ | |
618 | int nmeshes; /* number of mesh vifs */ | |
619 | int nstations; /* number of station vifs */ | |
e707549a | 620 | int nwds; /* number of WDS vifs */ |
4801416c | 621 | int nadhocs; /* number of adhoc vifs */ |
4801416c BG |
622 | }; |
623 | ||
394cf0a1 S |
624 | struct ath_softc { |
625 | struct ieee80211_hw *hw; | |
626 | struct device *dev; | |
c52f33d0 | 627 | |
3430098a FF |
628 | struct survey_info *cur_survey; |
629 | struct survey_info survey[ATH9K_NUM_CHANNELS]; | |
0e2dedf9 | 630 | |
394cf0a1 S |
631 | struct tasklet_struct intr_tq; |
632 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 633 | struct ath_hw *sc_ah; |
394cf0a1 S |
634 | void __iomem *mem; |
635 | int irq; | |
2d6a5e95 | 636 | spinlock_t sc_serial_rw; |
04717ccd | 637 | spinlock_t sc_pm_lock; |
4bdd1e97 | 638 | spinlock_t sc_pcu_lock; |
394cf0a1 | 639 | struct mutex mutex; |
9f42c2b6 | 640 | struct work_struct paprd_work; |
347809fc | 641 | struct work_struct hw_check_work; |
236de514 | 642 | struct work_struct hw_reset_work; |
9f42c2b6 | 643 | struct completion paprd_complete; |
394cf0a1 | 644 | |
cb8d61de FF |
645 | unsigned int hw_busy_count; |
646 | ||
17d7904d | 647 | u32 intrstatus; |
394cf0a1 | 648 | u32 sc_flags; /* SC_OP_* */ |
1b04b930 | 649 | u16 ps_flags; /* PS_* */ |
17d7904d | 650 | u16 curtxpow; |
96148326 | 651 | bool ps_enabled; |
1dbfd9d4 | 652 | bool ps_idle; |
4801416c BG |
653 | short nbcnvifs; |
654 | short nvifs; | |
709ade9e | 655 | unsigned long ps_usecount; |
394cf0a1 | 656 | |
17d7904d | 657 | struct ath_config config; |
394cf0a1 S |
658 | struct ath_rx rx; |
659 | struct ath_tx tx; | |
660 | struct ath_beacon beacon; | |
394cf0a1 S |
661 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; |
662 | ||
0cf55c21 FF |
663 | #ifdef CONFIG_MAC80211_LEDS |
664 | bool led_registered; | |
665 | char led_name[32]; | |
666 | struct led_classdev led_cdev; | |
667 | #endif | |
394cf0a1 | 668 | |
9ac58615 FF |
669 | struct ath9k_hw_cal_data caldata; |
670 | int last_rssi; | |
671 | ||
a830df07 | 672 | #ifdef CONFIG_ATH9K_DEBUGFS |
17d7904d | 673 | struct ath9k_debug debug; |
7f010c93 BG |
674 | spinlock_t nodes_lock; |
675 | struct list_head nodes; /* basically, stations */ | |
60f2d1d5 | 676 | unsigned int tx_complete_poll_work_seen; |
394cf0a1 | 677 | #endif |
6b96f93e | 678 | struct ath_beacon_config cur_beacon_conf; |
164ace38 | 679 | struct delayed_work tx_complete_work; |
181fb18d | 680 | struct delayed_work hw_pll_work; |
01e18918 | 681 | struct timer_list rx_poll_timer; |
4daa7760 SM |
682 | |
683 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT | |
2e20250a | 684 | struct ath_btcoex btcoex; |
9e25365f | 685 | struct ath_mci_coex mci_coex; |
4daa7760 | 686 | #endif |
5088c2f1 VT |
687 | |
688 | struct ath_descdma txsdma; | |
102885a5 VT |
689 | |
690 | struct ath_ant_comb ant_comb; | |
43c35284 | 691 | u8 ant_tx, ant_rx; |
8e92d3f2 | 692 | struct dfs_pattern_detector *dfs_detector; |
394cf0a1 S |
693 | }; |
694 | ||
55624204 | 695 | void ath9k_tasklet(unsigned long data); |
394cf0a1 S |
696 | int ath_cabq_update(struct ath_softc *); |
697 | ||
5bb12791 | 698 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
394cf0a1 | 699 | { |
5bb12791 | 700 | common->bus_ops->read_cachesize(common, csz); |
394cf0a1 S |
701 | } |
702 | ||
394cf0a1 | 703 | extern struct ieee80211_ops ath9k_ops; |
3e6109c5 | 704 | extern int ath9k_modparam_nohwcrypt; |
9a75c2ff | 705 | extern int led_blink; |
d584747b | 706 | extern bool is_ath9k_unloaded; |
394cf0a1 S |
707 | |
708 | irqreturn_t ath_isr(int irq, void *dev); | |
eb93e891 | 709 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
5bb12791 | 710 | const struct ath_bus_ops *bus_ops); |
285f2dda | 711 | void ath9k_deinit_device(struct ath_softc *sc); |
285f2dda | 712 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); |
43c35284 | 713 | void ath9k_reload_chainmask_settings(struct ath_softc *sc); |
68a89116 | 714 | |
4801416c | 715 | bool ath9k_uses_beacons(int type); |
394cf0a1 | 716 | |
8e26a030 | 717 | #ifdef CONFIG_ATH9K_PCI |
394cf0a1 S |
718 | int ath_pci_init(void); |
719 | void ath_pci_exit(void); | |
720 | #else | |
721 | static inline int ath_pci_init(void) { return 0; }; | |
722 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 723 | #endif |
f1dc5600 | 724 | |
8e26a030 | 725 | #ifdef CONFIG_ATH9K_AHB |
394cf0a1 S |
726 | int ath_ahb_init(void); |
727 | void ath_ahb_exit(void); | |
728 | #else | |
729 | static inline int ath_ahb_init(void) { return 0; }; | |
730 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 731 | #endif |
394cf0a1 | 732 | |
0bc0798b GJ |
733 | void ath9k_ps_wakeup(struct ath_softc *sc); |
734 | void ath9k_ps_restore(struct ath_softc *sc); | |
8ca21f01 | 735 | |
ea066d5a MSS |
736 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); |
737 | ||
0fca65c1 S |
738 | void ath_start_rfkill_poll(struct ath_softc *sc); |
739 | extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); | |
4801416c BG |
740 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, |
741 | struct ieee80211_vif *vif, | |
742 | struct ath9k_vif_iter_data *iter_data); | |
743 | ||
0fca65c1 | 744 | |
394cf0a1 | 745 | #endif /* ATH9K_H */ |