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Commit | Line | Data |
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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
22 | #include <net/mac80211.h> | |
23 | #include <linux/leds.h> | |
24 | #include <linux/rfkill.h> | |
25 | ||
26 | #include "hw.h" | |
27 | #include "rc.h" | |
28 | #include "debug.h" | |
29 | ||
30 | struct ath_node; | |
31 | ||
32 | /* Macro to expand scalars to 64-bit objects */ | |
33 | ||
34 | #define ito64(x) (sizeof(x) == 8) ? \ | |
35 | (((unsigned long long int)(x)) & (0xff)) : \ | |
36 | (sizeof(x) == 16) ? \ | |
37 | (((unsigned long long int)(x)) & 0xffff) : \ | |
38 | ((sizeof(x) == 32) ? \ | |
39 | (((unsigned long long int)(x)) & 0xffffffff) : \ | |
40 | (unsigned long long int)(x)) | |
41 | ||
42 | /* increment with wrap-around */ | |
43 | #define INCR(_l, _sz) do { \ | |
44 | (_l)++; \ | |
45 | (_l) &= ((_sz) - 1); \ | |
46 | } while (0) | |
47 | ||
48 | /* decrement with wrap-around */ | |
49 | #define DECR(_l, _sz) do { \ | |
50 | (_l)--; \ | |
51 | (_l) &= ((_sz) - 1); \ | |
52 | } while (0) | |
53 | ||
54 | #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) | |
55 | ||
0ee904c3 | 56 | #define ASSERT(exp) BUG_ON(!(exp)) |
394cf0a1 S |
57 | |
58 | #define TSF_TO_TU(_h,_l) \ | |
59 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
60 | ||
61 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) | |
62 | ||
63 | static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; | |
64 | ||
65 | struct ath_config { | |
66 | u32 ath_aggr_prot; | |
67 | u16 txpowlimit; | |
68 | u8 cabqReadytime; | |
394cf0a1 S |
69 | }; |
70 | ||
71 | /*************************/ | |
72 | /* Descriptor Management */ | |
73 | /*************************/ | |
74 | ||
75 | #define ATH_TXBUF_RESET(_bf) do { \ | |
a119cc49 | 76 | (_bf)->bf_stale = false; \ |
394cf0a1 S |
77 | (_bf)->bf_lastbf = NULL; \ |
78 | (_bf)->bf_next = NULL; \ | |
79 | memset(&((_bf)->bf_state), 0, \ | |
80 | sizeof(struct ath_buf_state)); \ | |
81 | } while (0) | |
82 | ||
a119cc49 S |
83 | #define ATH_RXBUF_RESET(_bf) do { \ |
84 | (_bf)->bf_stale = false; \ | |
85 | } while (0) | |
86 | ||
394cf0a1 S |
87 | /** |
88 | * enum buffer_type - Buffer type flags | |
89 | * | |
90 | * @BUF_HT: Send this buffer using HT capabilities | |
91 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) | |
92 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
93 | * (used in aggregation scheduling) | |
94 | * @BUF_RETRY: Indicates whether the buffer is retried | |
95 | * @BUF_XRETRY: To denote excessive retries of the buffer | |
96 | */ | |
97 | enum buffer_type { | |
98 | BUF_HT = BIT(1), | |
99 | BUF_AMPDU = BIT(2), | |
100 | BUF_AGGR = BIT(3), | |
101 | BUF_RETRY = BIT(4), | |
102 | BUF_XRETRY = BIT(5), | |
103 | }; | |
104 | ||
105 | struct ath_buf_state { | |
17d7904d S |
106 | int bfs_nframes; |
107 | u16 bfs_al; | |
108 | u16 bfs_frmlen; | |
109 | int bfs_seqno; | |
110 | int bfs_tidno; | |
111 | int bfs_retries; | |
a119cc49 | 112 | u8 bf_type; |
394cf0a1 S |
113 | u32 bfs_keyix; |
114 | enum ath9k_key_type bfs_keytype; | |
115 | }; | |
116 | ||
117 | #define bf_nframes bf_state.bfs_nframes | |
118 | #define bf_al bf_state.bfs_al | |
119 | #define bf_frmlen bf_state.bfs_frmlen | |
120 | #define bf_retries bf_state.bfs_retries | |
121 | #define bf_seqno bf_state.bfs_seqno | |
122 | #define bf_tidno bf_state.bfs_tidno | |
123 | #define bf_keyix bf_state.bfs_keyix | |
124 | #define bf_keytype bf_state.bfs_keytype | |
125 | #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) | |
126 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) | |
127 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
128 | #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) | |
129 | #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) | |
f078f209 | 130 | |
394cf0a1 S |
131 | struct ath_buf { |
132 | struct list_head list; | |
133 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
134 | an aggregate) */ | |
135 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
a22be22a | 136 | struct sk_buff *bf_mpdu; /* enclosing frame structure */ |
394cf0a1 S |
137 | struct ath_desc *bf_desc; /* virtual addr of desc */ |
138 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
139 | dma_addr_t bf_buf_addr; /* physical addr of data buffer */ | |
a119cc49 | 140 | bool bf_stale; |
17d7904d S |
141 | u16 bf_flags; |
142 | struct ath_buf_state bf_state; | |
394cf0a1 S |
143 | dma_addr_t bf_dmacontext; |
144 | }; | |
145 | ||
394cf0a1 | 146 | struct ath_descdma { |
17d7904d S |
147 | struct ath_desc *dd_desc; |
148 | dma_addr_t dd_desc_paddr; | |
149 | u32 dd_desc_len; | |
150 | struct ath_buf *dd_bufptr; | |
394cf0a1 S |
151 | }; |
152 | ||
153 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
154 | struct list_head *head, const char *name, | |
155 | int nbuf, int ndesc); | |
156 | void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, | |
157 | struct list_head *head); | |
158 | ||
159 | /***********/ | |
160 | /* RX / TX */ | |
161 | /***********/ | |
162 | ||
163 | #define ATH_MAX_ANTENNA 3 | |
164 | #define ATH_RXBUF 512 | |
165 | #define WME_NUM_TID 16 | |
166 | #define ATH_TXBUF 512 | |
167 | #define ATH_TXMAXTRY 13 | |
168 | #define ATH_11N_TXMAXTRY 10 | |
169 | #define ATH_MGT_TXMAXTRY 4 | |
170 | #define WME_BA_BMP_SIZE 64 | |
171 | #define WME_MAX_BA WME_BA_BMP_SIZE | |
172 | #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA) | |
173 | ||
174 | #define TID_TO_WME_AC(_tid) \ | |
175 | ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ | |
176 | (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ | |
177 | (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ | |
178 | WME_AC_VO) | |
179 | ||
180 | #define WME_AC_BE 0 | |
181 | #define WME_AC_BK 1 | |
182 | #define WME_AC_VI 2 | |
183 | #define WME_AC_VO 3 | |
184 | #define WME_NUM_AC 4 | |
185 | ||
186 | #define ADDBA_EXCHANGE_ATTEMPTS 10 | |
187 | #define ATH_AGGR_DELIM_SZ 4 | |
188 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
189 | /* number of delimiters for encryption padding */ | |
190 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
191 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
192 | #define ATH_AGGR_MIN_QDEPTH 2 | |
193 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | |
194 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) | |
195 | #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX | |
196 | ||
197 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | |
198 | #define IEEE80211_SEQ_MAX 4096 | |
199 | #define IEEE80211_MIN_AMPDU_BUF 0x8 | |
200 | #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13 | |
201 | #define IEEE80211_WEP_IVLEN 3 | |
202 | #define IEEE80211_WEP_KIDLEN 1 | |
203 | #define IEEE80211_WEP_CRCLEN 4 | |
204 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
205 | (IEEE80211_WEP_IVLEN + \ | |
206 | IEEE80211_WEP_KIDLEN + \ | |
207 | IEEE80211_WEP_CRCLEN)) | |
208 | ||
209 | /* return whether a bit at index _n in bitmap _bm is set | |
210 | * _sz is the size of the bitmap */ | |
211 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
212 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
213 | ||
214 | /* return block-ack bitmap index given sequence and starting sequence */ | |
215 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
216 | ||
217 | /* returns delimiter padding required given the packet length */ | |
218 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
219 | (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ | |
220 | (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) | |
221 | ||
222 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
223 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
224 | ||
225 | #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum) | |
226 | #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low) | |
227 | #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) | |
228 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) | |
229 | ||
230 | enum ATH_AGGR_STATUS { | |
231 | ATH_AGGR_DONE, | |
232 | ATH_AGGR_BAW_CLOSED, | |
233 | ATH_AGGR_LIMITED, | |
234 | }; | |
235 | ||
236 | struct ath_txq { | |
17d7904d S |
237 | u32 axq_qnum; |
238 | u32 *axq_link; | |
239 | struct list_head axq_q; | |
394cf0a1 | 240 | spinlock_t axq_lock; |
17d7904d S |
241 | u32 axq_depth; |
242 | u8 axq_aggr_depth; | |
243 | u32 axq_totalqueued; | |
244 | bool stopped; | |
245 | struct ath_buf *axq_linkbuf; | |
394cf0a1 S |
246 | |
247 | /* first desc of the last descriptor that contains CTS */ | |
248 | struct ath_desc *axq_lastdsWithCTS; | |
249 | ||
250 | /* final desc of the gating desc that determines whether | |
251 | lastdsWithCTS has been DMA'ed or not */ | |
252 | struct ath_desc *axq_gatingds; | |
253 | ||
254 | struct list_head axq_acq; | |
255 | }; | |
256 | ||
257 | #define AGGR_CLEANUP BIT(1) | |
258 | #define AGGR_ADDBA_COMPLETE BIT(2) | |
259 | #define AGGR_ADDBA_PROGRESS BIT(3) | |
260 | ||
394cf0a1 | 261 | struct ath_atx_tid { |
17d7904d S |
262 | struct list_head list; |
263 | struct list_head buf_q; | |
394cf0a1 S |
264 | struct ath_node *an; |
265 | struct ath_atx_ac *ac; | |
17d7904d | 266 | struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; |
394cf0a1 S |
267 | u16 seq_start; |
268 | u16 seq_next; | |
269 | u16 baw_size; | |
270 | int tidno; | |
17d7904d S |
271 | int baw_head; /* first un-acked tx buffer */ |
272 | int baw_tail; /* next unused tx buffer slot */ | |
394cf0a1 S |
273 | int sched; |
274 | int paused; | |
275 | u8 state; | |
276 | int addba_exchangeattempts; | |
277 | }; | |
278 | ||
394cf0a1 | 279 | struct ath_atx_ac { |
17d7904d S |
280 | int sched; |
281 | int qnum; | |
282 | struct list_head list; | |
283 | struct list_head tid_q; | |
394cf0a1 S |
284 | }; |
285 | ||
394cf0a1 S |
286 | struct ath_tx_control { |
287 | struct ath_txq *txq; | |
288 | int if_id; | |
f0ed85c6 | 289 | enum ath9k_internal_frame_type frame_type; |
394cf0a1 S |
290 | }; |
291 | ||
394cf0a1 S |
292 | #define ATH_TX_ERROR 0x01 |
293 | #define ATH_TX_XRETRY 0x02 | |
294 | #define ATH_TX_BAR 0x04 | |
394cf0a1 | 295 | |
394cf0a1 S |
296 | struct ath_node { |
297 | struct ath_softc *an_sc; | |
298 | struct ath_atx_tid tid[WME_NUM_TID]; | |
299 | struct ath_atx_ac ac[WME_NUM_AC]; | |
300 | u16 maxampdu; | |
301 | u8 mpdudensity; | |
302 | }; | |
303 | ||
304 | struct ath_tx { | |
305 | u16 seq_no; | |
306 | u32 txqsetup; | |
307 | int hwq_map[ATH9K_WME_AC_VO+1]; | |
308 | spinlock_t txbuflock; | |
309 | struct list_head txbuf; | |
310 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
311 | struct ath_descdma txdma; | |
312 | }; | |
313 | ||
314 | struct ath_rx { | |
315 | u8 defant; | |
316 | u8 rxotherant; | |
317 | u32 *rxlink; | |
318 | int bufsize; | |
319 | unsigned int rxfilter; | |
320 | spinlock_t rxflushlock; | |
321 | spinlock_t rxbuflock; | |
322 | struct list_head rxbuf; | |
323 | struct ath_descdma rxdma; | |
324 | }; | |
325 | ||
326 | int ath_startrecv(struct ath_softc *sc); | |
327 | bool ath_stoprecv(struct ath_softc *sc); | |
328 | void ath_flushrecv(struct ath_softc *sc); | |
329 | u32 ath_calcrxfilter(struct ath_softc *sc); | |
330 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
331 | void ath_rx_cleanup(struct ath_softc *sc); | |
332 | int ath_rx_tasklet(struct ath_softc *sc, int flush); | |
333 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); | |
334 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); | |
335 | int ath_tx_setup(struct ath_softc *sc, int haltype); | |
336 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); | |
337 | void ath_draintxq(struct ath_softc *sc, | |
338 | struct ath_txq *txq, bool retry_tx); | |
339 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); | |
340 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
341 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
342 | int ath_tx_init(struct ath_softc *sc, int nbufs); | |
797fe5cb | 343 | void ath_tx_cleanup(struct ath_softc *sc); |
394cf0a1 S |
344 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb); |
345 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
346 | struct ath9k_tx_queue_info *q); | |
c52f33d0 | 347 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 S |
348 | struct ath_tx_control *txctl); |
349 | void ath_tx_tasklet(struct ath_softc *sc); | |
c52f33d0 | 350 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb); |
394cf0a1 S |
351 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); |
352 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, | |
353 | u16 tid, u16 *ssn); | |
354 | int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); | |
355 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); | |
356 | ||
357 | /********/ | |
17d7904d | 358 | /* VIFs */ |
394cf0a1 | 359 | /********/ |
f078f209 | 360 | |
17d7904d | 361 | struct ath_vif { |
394cf0a1 | 362 | int av_bslot; |
4ed96f04 | 363 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 S |
364 | enum nl80211_iftype av_opmode; |
365 | struct ath_buf *av_bcbuf; | |
366 | struct ath_tx_control av_btxctl; | |
f0ed85c6 | 367 | u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */ |
f078f209 LR |
368 | }; |
369 | ||
394cf0a1 S |
370 | /*******************/ |
371 | /* Beacon Handling */ | |
372 | /*******************/ | |
f078f209 | 373 | |
394cf0a1 S |
374 | /* |
375 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
376 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
377 | * number of beacon intervals, the game's up. | |
378 | */ | |
379 | #define BSTUCK_THRESH (9 * ATH_BCBUF) | |
4ed96f04 | 380 | #define ATH_BCBUF 4 |
394cf0a1 S |
381 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
382 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
383 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | |
384 | ||
385 | struct ath_beacon_config { | |
386 | u16 beacon_interval; | |
387 | u16 listen_interval; | |
388 | u16 dtim_period; | |
389 | u16 bmiss_timeout; | |
390 | u8 dtim_count; | |
394cf0a1 S |
391 | }; |
392 | ||
393 | struct ath_beacon { | |
394 | enum { | |
395 | OK, /* no change needed */ | |
396 | UPDATE, /* update pending */ | |
397 | COMMIT /* beacon sent, commit change */ | |
398 | } updateslot; /* slot time update fsm */ | |
399 | ||
400 | u32 beaconq; | |
401 | u32 bmisscnt; | |
402 | u32 ast_be_xmit; | |
403 | u64 bc_tstamp; | |
2c3db3d5 | 404 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
c52f33d0 | 405 | struct ath_wiphy *bslot_aphy[ATH_BCBUF]; |
394cf0a1 S |
406 | int slottime; |
407 | int slotupdate; | |
408 | struct ath9k_tx_queue_info beacon_qi; | |
409 | struct ath_descdma bdma; | |
410 | struct ath_txq *cabq; | |
411 | struct list_head bbuf; | |
412 | }; | |
413 | ||
9fc9ab0a | 414 | void ath_beacon_tasklet(unsigned long data); |
2c3db3d5 | 415 | void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); |
cbe61d8a | 416 | int ath_beaconq_setup(struct ath_hw *ah); |
c52f33d0 | 417 | int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); |
17d7904d | 418 | void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); |
394cf0a1 S |
419 | |
420 | /*******/ | |
421 | /* ANI */ | |
422 | /*******/ | |
f078f209 | 423 | |
20977d3e S |
424 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
425 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
426 | #define ATH_ANI_POLLINTERVAL 100 /* 100 ms */ | |
427 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ | |
428 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
f078f209 | 429 | |
394cf0a1 | 430 | struct ath_ani { |
17d7904d S |
431 | bool caldone; |
432 | int16_t noise_floor; | |
433 | unsigned int longcal_timer; | |
434 | unsigned int shortcal_timer; | |
435 | unsigned int resetcal_timer; | |
436 | unsigned int checkani_timer; | |
394cf0a1 | 437 | struct timer_list timer; |
f078f209 LR |
438 | }; |
439 | ||
394cf0a1 S |
440 | /********************/ |
441 | /* LED Control */ | |
442 | /********************/ | |
f078f209 | 443 | |
394cf0a1 S |
444 | #define ATH_LED_PIN 1 |
445 | #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ | |
446 | #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ | |
f078f209 | 447 | |
394cf0a1 S |
448 | enum ath_led_type { |
449 | ATH_LED_RADIO, | |
450 | ATH_LED_ASSOC, | |
451 | ATH_LED_TX, | |
452 | ATH_LED_RX | |
f078f209 LR |
453 | }; |
454 | ||
394cf0a1 S |
455 | struct ath_led { |
456 | struct ath_softc *sc; | |
457 | struct led_classdev led_cdev; | |
458 | enum ath_led_type led_type; | |
459 | char name[32]; | |
460 | bool registered; | |
f078f209 LR |
461 | }; |
462 | ||
394cf0a1 S |
463 | /* Rfkill */ |
464 | #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */ | |
f078f209 | 465 | |
394cf0a1 S |
466 | struct ath_rfkill { |
467 | struct rfkill *rfkill; | |
468 | struct delayed_work rfkill_poll; | |
469 | char rfkill_name[32]; | |
f078f209 LR |
470 | }; |
471 | ||
394cf0a1 S |
472 | /********************/ |
473 | /* Main driver core */ | |
474 | /********************/ | |
f078f209 | 475 | |
394cf0a1 S |
476 | /* |
477 | * Default cache line size, in bytes. | |
478 | * Used when PCI device not fully initialized by bootrom/BIOS | |
479 | */ | |
480 | #define DEFAULT_CACHELINE 32 | |
481 | #define ATH_DEFAULT_NOISE_FLOOR -95 | |
482 | #define ATH_REGCLASSIDS_MAX 10 | |
483 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | |
484 | #define ATH_MAX_SW_RETRIES 10 | |
485 | #define ATH_CHAN_MAX 255 | |
486 | #define IEEE80211_WEP_NKID 4 /* number of key ids */ | |
f1dc5600 | 487 | |
394cf0a1 S |
488 | /* |
489 | * The key cache is used for h/w cipher state and also for | |
490 | * tracking station state such as the current tx antenna. | |
491 | * We also setup a mapping table between key cache slot indices | |
492 | * and station state to short-circuit node lookups on rx. | |
493 | * Different parts have different size key caches. We handle | |
494 | * up to ATH_KEYMAX entries (could dynamically allocate state). | |
495 | */ | |
496 | #define ATH_KEYMAX 128 /* max key cache size we handle */ | |
497 | ||
394cf0a1 S |
498 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
499 | #define ATH_RSSI_DUMMY_MARKER 0x127 | |
500 | #define ATH_RATE_DUMMY_MARKER 0 | |
501 | ||
b238e90e S |
502 | #define SC_OP_INVALID BIT(0) |
503 | #define SC_OP_BEACONS BIT(1) | |
504 | #define SC_OP_RXAGGR BIT(2) | |
505 | #define SC_OP_TXAGGR BIT(3) | |
bdbdf46d S |
506 | #define SC_OP_FULL_RESET BIT(4) |
507 | #define SC_OP_PREAMBLE_SHORT BIT(5) | |
508 | #define SC_OP_PROTECT_ENABLE BIT(6) | |
509 | #define SC_OP_RXFLUSH BIT(7) | |
510 | #define SC_OP_LED_ASSOCIATED BIT(8) | |
511 | #define SC_OP_RFKILL_REGISTERED BIT(9) | |
512 | #define SC_OP_RFKILL_SW_BLOCKED BIT(10) | |
513 | #define SC_OP_RFKILL_HW_BLOCKED BIT(11) | |
514 | #define SC_OP_WAIT_FOR_BEACON BIT(12) | |
515 | #define SC_OP_LED_ON BIT(13) | |
516 | #define SC_OP_SCANNING BIT(14) | |
517 | #define SC_OP_TSF_RESET BIT(15) | |
394cf0a1 S |
518 | |
519 | struct ath_bus_ops { | |
520 | void (*read_cachesize)(struct ath_softc *sc, int *csz); | |
521 | void (*cleanup)(struct ath_softc *sc); | |
cbe61d8a | 522 | bool (*eeprom_read)(struct ath_hw *ah, u32 off, u16 *data); |
394cf0a1 S |
523 | }; |
524 | ||
bce048d7 JM |
525 | struct ath_wiphy; |
526 | ||
394cf0a1 S |
527 | struct ath_softc { |
528 | struct ieee80211_hw *hw; | |
529 | struct device *dev; | |
c52f33d0 JM |
530 | |
531 | spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ | |
bce048d7 | 532 | struct ath_wiphy *pri_wiphy; |
c52f33d0 JM |
533 | struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may |
534 | * have NULL entries */ | |
535 | int num_sec_wiphy; /* number of sec_wiphy pointers in the array */ | |
0e2dedf9 JM |
536 | int chan_idx; |
537 | int chan_is_ht; | |
538 | struct ath_wiphy *next_wiphy; | |
539 | struct work_struct chan_work; | |
7ec3e514 JM |
540 | int wiphy_select_failures; |
541 | unsigned long wiphy_select_first_fail; | |
f98c3bd2 JM |
542 | struct delayed_work wiphy_work; |
543 | unsigned long wiphy_scheduler_int; | |
544 | int wiphy_scheduler_index; | |
0e2dedf9 | 545 | |
394cf0a1 S |
546 | struct tasklet_struct intr_tq; |
547 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 548 | struct ath_hw *sc_ah; |
394cf0a1 S |
549 | void __iomem *mem; |
550 | int irq; | |
551 | spinlock_t sc_resetlock; | |
2d6a5e95 | 552 | spinlock_t sc_serial_rw; |
394cf0a1 S |
553 | struct mutex mutex; |
554 | ||
17d7904d | 555 | u8 curbssid[ETH_ALEN]; |
17d7904d S |
556 | u8 bssidmask[ETH_ALEN]; |
557 | u32 intrstatus; | |
394cf0a1 | 558 | u32 sc_flags; /* SC_OP_* */ |
17d7904d S |
559 | u16 curtxpow; |
560 | u16 curaid; | |
561 | u16 cachelsz; | |
562 | u8 nbcnvifs; | |
563 | u16 nvifs; | |
564 | u8 tx_chainmask; | |
565 | u8 rx_chainmask; | |
566 | u32 keymax; | |
567 | DECLARE_BITMAP(keymap, ATH_KEYMAX); | |
568 | u8 splitmic; | |
394cf0a1 | 569 | atomic_t ps_usecount; |
17d7904d S |
570 | enum ath9k_int imask; |
571 | enum ath9k_ht_extprotspacing ht_extprotspacing; | |
394cf0a1 S |
572 | enum ath9k_ht_macmode tx_chan_width; |
573 | ||
17d7904d | 574 | struct ath_config config; |
394cf0a1 S |
575 | struct ath_rx rx; |
576 | struct ath_tx tx; | |
577 | struct ath_beacon beacon; | |
394cf0a1 S |
578 | struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX]; |
579 | struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX]; | |
580 | struct ath_rate_table *cur_rate_table; | |
581 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; | |
582 | ||
583 | struct ath_led radio_led; | |
584 | struct ath_led assoc_led; | |
585 | struct ath_led tx_led; | |
586 | struct ath_led rx_led; | |
587 | struct delayed_work ath_led_blink_work; | |
588 | int led_on_duration; | |
589 | int led_off_duration; | |
590 | int led_on_cnt; | |
591 | int led_off_cnt; | |
592 | ||
57c4d7b4 JB |
593 | int beacon_interval; |
594 | ||
394cf0a1 | 595 | struct ath_rfkill rf_kill; |
17d7904d S |
596 | struct ath_ani ani; |
597 | struct ath9k_node_stats nodestats; | |
394cf0a1 | 598 | #ifdef CONFIG_ATH9K_DEBUG |
17d7904d | 599 | struct ath9k_debug debug; |
394cf0a1 S |
600 | #endif |
601 | struct ath_bus_ops *bus_ops; | |
602 | }; | |
603 | ||
bce048d7 JM |
604 | struct ath_wiphy { |
605 | struct ath_softc *sc; /* shared for all virtual wiphys */ | |
606 | struct ieee80211_hw *hw; | |
f0ed85c6 | 607 | enum ath_wiphy_state { |
9580a222 | 608 | ATH_WIPHY_INACTIVE, |
f0ed85c6 JM |
609 | ATH_WIPHY_ACTIVE, |
610 | ATH_WIPHY_PAUSING, | |
611 | ATH_WIPHY_PAUSED, | |
8089cc47 | 612 | ATH_WIPHY_SCAN, |
f0ed85c6 | 613 | } state; |
0e2dedf9 JM |
614 | int chan_idx; |
615 | int chan_is_ht; | |
bce048d7 JM |
616 | }; |
617 | ||
394cf0a1 S |
618 | int ath_reset(struct ath_softc *sc, bool retry_tx); |
619 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); | |
620 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); | |
621 | int ath_cabq_update(struct ath_softc *); | |
622 | ||
623 | static inline void ath_read_cachesize(struct ath_softc *sc, int *csz) | |
624 | { | |
625 | sc->bus_ops->read_cachesize(sc, csz); | |
626 | } | |
627 | ||
628 | static inline void ath_bus_cleanup(struct ath_softc *sc) | |
629 | { | |
630 | sc->bus_ops->cleanup(sc); | |
631 | } | |
632 | ||
633 | extern struct ieee80211_ops ath9k_ops; | |
634 | ||
635 | irqreturn_t ath_isr(int irq, void *dev); | |
636 | void ath_cleanup(struct ath_softc *sc); | |
637 | int ath_attach(u16 devid, struct ath_softc *sc); | |
638 | void ath_detach(struct ath_softc *sc); | |
639 | const char *ath_mac_bb_name(u32 mac_bb_version); | |
640 | const char *ath_rf_name(u16 rf_version); | |
c52f33d0 | 641 | void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); |
0e2dedf9 JM |
642 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
643 | struct ath9k_channel *ichan); | |
644 | void ath_update_chainmask(struct ath_softc *sc, int is_ht); | |
645 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
646 | struct ath9k_channel *hchan); | |
7ec3e514 JM |
647 | void ath_radio_enable(struct ath_softc *sc); |
648 | void ath_radio_disable(struct ath_softc *sc); | |
394cf0a1 S |
649 | |
650 | #ifdef CONFIG_PCI | |
651 | int ath_pci_init(void); | |
652 | void ath_pci_exit(void); | |
653 | #else | |
654 | static inline int ath_pci_init(void) { return 0; }; | |
655 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 656 | #endif |
f1dc5600 | 657 | |
394cf0a1 S |
658 | #ifdef CONFIG_ATHEROS_AR71XX |
659 | int ath_ahb_init(void); | |
660 | void ath_ahb_exit(void); | |
661 | #else | |
662 | static inline int ath_ahb_init(void) { return 0; }; | |
663 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 664 | #endif |
394cf0a1 S |
665 | |
666 | static inline void ath9k_ps_wakeup(struct ath_softc *sc) | |
667 | { | |
668 | if (atomic_inc_return(&sc->ps_usecount) == 1) | |
2660b81a S |
669 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) { |
670 | sc->sc_ah->restore_mode = sc->sc_ah->power_mode; | |
394cf0a1 S |
671 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
672 | } | |
673 | } | |
674 | ||
675 | static inline void ath9k_ps_restore(struct ath_softc *sc) | |
676 | { | |
677 | if (atomic_dec_and_test(&sc->ps_usecount)) | |
541d8dd5 VN |
678 | if ((sc->hw->conf.flags & IEEE80211_CONF_PS) && |
679 | !(sc->sc_flags & SC_OP_WAIT_FOR_BEACON)) | |
394cf0a1 | 680 | ath9k_hw_setpower(sc->sc_ah, |
2660b81a | 681 | sc->sc_ah->restore_mode); |
394cf0a1 | 682 | } |
0c98de65 | 683 | |
8ca21f01 JM |
684 | |
685 | void ath9k_set_bssid_mask(struct ieee80211_hw *hw); | |
c52f33d0 JM |
686 | int ath9k_wiphy_add(struct ath_softc *sc); |
687 | int ath9k_wiphy_del(struct ath_wiphy *aphy); | |
f0ed85c6 JM |
688 | void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb); |
689 | int ath9k_wiphy_pause(struct ath_wiphy *aphy); | |
690 | int ath9k_wiphy_unpause(struct ath_wiphy *aphy); | |
0e2dedf9 | 691 | int ath9k_wiphy_select(struct ath_wiphy *aphy); |
f98c3bd2 | 692 | void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int); |
0e2dedf9 | 693 | void ath9k_wiphy_chan_work(struct work_struct *work); |
9580a222 | 694 | bool ath9k_wiphy_started(struct ath_softc *sc); |
18eb62f8 JM |
695 | void ath9k_wiphy_pause_all_forced(struct ath_softc *sc, |
696 | struct ath_wiphy *selected); | |
8089cc47 | 697 | bool ath9k_wiphy_scanning(struct ath_softc *sc); |
f98c3bd2 | 698 | void ath9k_wiphy_work(struct work_struct *work); |
8ca21f01 | 699 | |
fb4a3d35 GJ |
700 | void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val); |
701 | unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset); | |
2d6a5e95 | 702 | |
394cf0a1 | 703 | #endif /* ATH9K_H */ |