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Commit | Line | Data |
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f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
a6b7a407 | 22 | #include <linux/interrupt.h> |
394cf0a1 | 23 | #include <linux/leds.h> |
9f42c2b6 | 24 | #include <linux/completion.h> |
394cf0a1 | 25 | |
394cf0a1 | 26 | #include "debug.h" |
db86f07e LR |
27 | #include "common.h" |
28 | ||
29 | /* | |
30 | * Header for the ath9k.ko driver core *only* -- hw code nor any other driver | |
31 | * should rely on this file or its contents. | |
32 | */ | |
394cf0a1 S |
33 | |
34 | struct ath_node; | |
35 | ||
36 | /* Macro to expand scalars to 64-bit objects */ | |
37 | ||
13bda122 | 38 | #define ito64(x) (sizeof(x) == 1) ? \ |
394cf0a1 | 39 | (((unsigned long long int)(x)) & (0xff)) : \ |
13bda122 | 40 | (sizeof(x) == 2) ? \ |
394cf0a1 | 41 | (((unsigned long long int)(x)) & 0xffff) : \ |
13bda122 | 42 | ((sizeof(x) == 4) ? \ |
394cf0a1 S |
43 | (((unsigned long long int)(x)) & 0xffffffff) : \ |
44 | (unsigned long long int)(x)) | |
45 | ||
46 | /* increment with wrap-around */ | |
47 | #define INCR(_l, _sz) do { \ | |
48 | (_l)++; \ | |
49 | (_l) &= ((_sz) - 1); \ | |
50 | } while (0) | |
51 | ||
52 | /* decrement with wrap-around */ | |
53 | #define DECR(_l, _sz) do { \ | |
54 | (_l)--; \ | |
55 | (_l) &= ((_sz) - 1); \ | |
56 | } while (0) | |
57 | ||
58 | #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) | |
59 | ||
394cf0a1 S |
60 | #define TSF_TO_TU(_h,_l) \ |
61 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
62 | ||
63 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) | |
64 | ||
394cf0a1 | 65 | struct ath_config { |
394cf0a1 S |
66 | u16 txpowlimit; |
67 | u8 cabqReadytime; | |
394cf0a1 S |
68 | }; |
69 | ||
70 | /*************************/ | |
71 | /* Descriptor Management */ | |
72 | /*************************/ | |
73 | ||
74 | #define ATH_TXBUF_RESET(_bf) do { \ | |
a119cc49 | 75 | (_bf)->bf_stale = false; \ |
394cf0a1 S |
76 | (_bf)->bf_lastbf = NULL; \ |
77 | (_bf)->bf_next = NULL; \ | |
78 | memset(&((_bf)->bf_state), 0, \ | |
79 | sizeof(struct ath_buf_state)); \ | |
80 | } while (0) | |
81 | ||
a119cc49 S |
82 | #define ATH_RXBUF_RESET(_bf) do { \ |
83 | (_bf)->bf_stale = false; \ | |
84 | } while (0) | |
85 | ||
394cf0a1 S |
86 | /** |
87 | * enum buffer_type - Buffer type flags | |
88 | * | |
394cf0a1 S |
89 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) |
90 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
91 | * (used in aggregation scheduling) | |
394cf0a1 S |
92 | * @BUF_XRETRY: To denote excessive retries of the buffer |
93 | */ | |
94 | enum buffer_type { | |
436d0d98 MSS |
95 | BUF_AMPDU = BIT(0), |
96 | BUF_AGGR = BIT(1), | |
97 | BUF_XRETRY = BIT(2), | |
394cf0a1 S |
98 | }; |
99 | ||
394cf0a1 S |
100 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) |
101 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
394cf0a1 | 102 | #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) |
f078f209 | 103 | |
5088c2f1 VT |
104 | #define ATH_TXSTATUS_RING_SIZE 64 |
105 | ||
394cf0a1 | 106 | struct ath_descdma { |
5088c2f1 | 107 | void *dd_desc; |
17d7904d S |
108 | dma_addr_t dd_desc_paddr; |
109 | u32 dd_desc_len; | |
110 | struct ath_buf *dd_bufptr; | |
394cf0a1 S |
111 | }; |
112 | ||
113 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
114 | struct list_head *head, const char *name, | |
4adfcded | 115 | int nbuf, int ndesc, bool is_tx); |
394cf0a1 S |
116 | void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, |
117 | struct list_head *head); | |
118 | ||
119 | /***********/ | |
120 | /* RX / TX */ | |
121 | /***********/ | |
122 | ||
394cf0a1 | 123 | #define ATH_RXBUF 512 |
394cf0a1 | 124 | #define ATH_TXBUF 512 |
84642d6b FF |
125 | #define ATH_TXBUF_RESERVE 5 |
126 | #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) | |
394cf0a1 | 127 | #define ATH_TXMAXTRY 13 |
394cf0a1 S |
128 | |
129 | #define TID_TO_WME_AC(_tid) \ | |
130 | ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ | |
131 | (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ | |
132 | (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ | |
133 | WME_AC_VO) | |
134 | ||
394cf0a1 S |
135 | #define ATH_AGGR_DELIM_SZ 4 |
136 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
137 | /* number of delimiters for encryption padding */ | |
138 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
139 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
140 | #define ATH_AGGR_MIN_QDEPTH 2 | |
141 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | |
394cf0a1 S |
142 | |
143 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | |
144 | #define IEEE80211_SEQ_MAX 4096 | |
394cf0a1 S |
145 | #define IEEE80211_WEP_IVLEN 3 |
146 | #define IEEE80211_WEP_KIDLEN 1 | |
147 | #define IEEE80211_WEP_CRCLEN 4 | |
148 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
149 | (IEEE80211_WEP_IVLEN + \ | |
150 | IEEE80211_WEP_KIDLEN + \ | |
151 | IEEE80211_WEP_CRCLEN)) | |
152 | ||
153 | /* return whether a bit at index _n in bitmap _bm is set | |
154 | * _sz is the size of the bitmap */ | |
155 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
156 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
157 | ||
158 | /* return block-ack bitmap index given sequence and starting sequence */ | |
159 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
160 | ||
161 | /* returns delimiter padding required given the packet length */ | |
162 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
39ec2997 VT |
163 | (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ |
164 | DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) | |
394cf0a1 S |
165 | |
166 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
167 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
168 | ||
394cf0a1 S |
169 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) |
170 | ||
164ace38 SB |
171 | #define ATH_TX_COMPLETE_POLL_INT 1000 |
172 | ||
394cf0a1 S |
173 | enum ATH_AGGR_STATUS { |
174 | ATH_AGGR_DONE, | |
175 | ATH_AGGR_BAW_CLOSED, | |
176 | ATH_AGGR_LIMITED, | |
177 | }; | |
178 | ||
e5003249 | 179 | #define ATH_TXFIFO_DEPTH 8 |
394cf0a1 | 180 | struct ath_txq { |
60f2d1d5 BG |
181 | int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ |
182 | u32 axq_qnum; /* ath9k hardware queue number */ | |
17d7904d S |
183 | u32 *axq_link; |
184 | struct list_head axq_q; | |
394cf0a1 | 185 | spinlock_t axq_lock; |
17d7904d | 186 | u32 axq_depth; |
4b3ba66a | 187 | u32 axq_ampdu_depth; |
17d7904d | 188 | bool stopped; |
164ace38 | 189 | bool axq_tx_inprogress; |
394cf0a1 | 190 | struct list_head axq_acq; |
e5003249 VT |
191 | struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; |
192 | struct list_head txq_fifo_pending; | |
193 | u8 txq_headidx; | |
194 | u8 txq_tailidx; | |
066dae93 | 195 | int pending_frames; |
394cf0a1 S |
196 | }; |
197 | ||
93ef24b2 | 198 | struct ath_atx_ac { |
066dae93 | 199 | struct ath_txq *txq; |
93ef24b2 | 200 | int sched; |
93ef24b2 S |
201 | struct list_head list; |
202 | struct list_head tid_q; | |
5519541d | 203 | bool clear_ps_filter; |
93ef24b2 S |
204 | }; |
205 | ||
2d42efc4 FF |
206 | struct ath_frame_info { |
207 | int framelen; | |
208 | u32 keyix; | |
209 | enum ath9k_key_type keytype; | |
210 | u8 retries; | |
211 | u16 seqno; | |
212 | }; | |
213 | ||
93ef24b2 | 214 | struct ath_buf_state { |
93ef24b2 | 215 | u8 bf_type; |
9f42c2b6 | 216 | u8 bfs_paprd; |
9cf04dcc | 217 | unsigned long bfs_paprd_timestamp; |
61117f01 | 218 | enum ath9k_internal_frame_type bfs_ftype; |
93ef24b2 S |
219 | }; |
220 | ||
221 | struct ath_buf { | |
222 | struct list_head list; | |
223 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
224 | an aggregate) */ | |
225 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
226 | struct sk_buff *bf_mpdu; /* enclosing frame structure */ | |
227 | void *bf_desc; /* virtual addr of desc */ | |
228 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
c1739eb3 | 229 | dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ |
93ef24b2 | 230 | bool bf_stale; |
93ef24b2 S |
231 | u16 bf_flags; |
232 | struct ath_buf_state bf_state; | |
93ef24b2 S |
233 | }; |
234 | ||
235 | struct ath_atx_tid { | |
236 | struct list_head list; | |
237 | struct list_head buf_q; | |
238 | struct ath_node *an; | |
239 | struct ath_atx_ac *ac; | |
81ee13ba | 240 | unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; |
93ef24b2 S |
241 | u16 seq_start; |
242 | u16 seq_next; | |
243 | u16 baw_size; | |
244 | int tidno; | |
245 | int baw_head; /* first un-acked tx buffer */ | |
246 | int baw_tail; /* next unused tx buffer slot */ | |
247 | int sched; | |
248 | int paused; | |
249 | u8 state; | |
250 | }; | |
251 | ||
252 | struct ath_node { | |
7f010c93 BG |
253 | #ifdef CONFIG_ATH9K_DEBUGFS |
254 | struct list_head list; /* for sc->nodes */ | |
255 | struct ieee80211_sta *sta; /* station struct we're part of */ | |
256 | #endif | |
93ef24b2 S |
257 | struct ath_atx_tid tid[WME_NUM_TID]; |
258 | struct ath_atx_ac ac[WME_NUM_AC]; | |
93ae2dd2 FF |
259 | int ps_key; |
260 | ||
93ef24b2 S |
261 | u16 maxampdu; |
262 | u8 mpdudensity; | |
5519541d FF |
263 | |
264 | bool sleeping; | |
93ef24b2 S |
265 | }; |
266 | ||
394cf0a1 S |
267 | #define AGGR_CLEANUP BIT(1) |
268 | #define AGGR_ADDBA_COMPLETE BIT(2) | |
269 | #define AGGR_ADDBA_PROGRESS BIT(3) | |
270 | ||
394cf0a1 S |
271 | struct ath_tx_control { |
272 | struct ath_txq *txq; | |
2d42efc4 | 273 | struct ath_node *an; |
394cf0a1 | 274 | int if_id; |
f0ed85c6 | 275 | enum ath9k_internal_frame_type frame_type; |
9f42c2b6 | 276 | u8 paprd; |
394cf0a1 S |
277 | }; |
278 | ||
394cf0a1 S |
279 | #define ATH_TX_ERROR 0x01 |
280 | #define ATH_TX_XRETRY 0x02 | |
281 | #define ATH_TX_BAR 0x04 | |
394cf0a1 | 282 | |
60f2d1d5 BG |
283 | /** |
284 | * @txq_map: Index is mac80211 queue number. This is | |
285 | * not necessarily the same as the hardware queue number | |
286 | * (axq_qnum). | |
287 | */ | |
394cf0a1 S |
288 | struct ath_tx { |
289 | u16 seq_no; | |
290 | u32 txqsetup; | |
394cf0a1 S |
291 | spinlock_t txbuflock; |
292 | struct list_head txbuf; | |
293 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
294 | struct ath_descdma txdma; | |
066dae93 | 295 | struct ath_txq *txq_map[WME_NUM_AC]; |
394cf0a1 S |
296 | }; |
297 | ||
b5c80475 FF |
298 | struct ath_rx_edma { |
299 | struct sk_buff_head rx_fifo; | |
300 | struct sk_buff_head rx_buffers; | |
301 | u32 rx_fifo_hwsize; | |
302 | }; | |
303 | ||
394cf0a1 S |
304 | struct ath_rx { |
305 | u8 defant; | |
306 | u8 rxotherant; | |
307 | u32 *rxlink; | |
394cf0a1 | 308 | unsigned int rxfilter; |
394cf0a1 S |
309 | spinlock_t rxbuflock; |
310 | struct list_head rxbuf; | |
311 | struct ath_descdma rxdma; | |
b5c80475 FF |
312 | struct ath_buf *rx_bufptr; |
313 | struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; | |
0d95521e FF |
314 | |
315 | struct sk_buff *frag; | |
394cf0a1 S |
316 | }; |
317 | ||
318 | int ath_startrecv(struct ath_softc *sc); | |
319 | bool ath_stoprecv(struct ath_softc *sc); | |
320 | void ath_flushrecv(struct ath_softc *sc); | |
321 | u32 ath_calcrxfilter(struct ath_softc *sc); | |
322 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
323 | void ath_rx_cleanup(struct ath_softc *sc); | |
b5c80475 | 324 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); |
394cf0a1 S |
325 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); |
326 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); | |
080e1a25 | 327 | bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); |
394cf0a1 S |
328 | void ath_draintxq(struct ath_softc *sc, |
329 | struct ath_txq *txq, bool retry_tx); | |
330 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); | |
331 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
332 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
333 | int ath_tx_init(struct ath_softc *sc, int nbufs); | |
797fe5cb | 334 | void ath_tx_cleanup(struct ath_softc *sc); |
394cf0a1 S |
335 | int ath_txq_update(struct ath_softc *sc, int qnum, |
336 | struct ath9k_tx_queue_info *q); | |
c52f33d0 | 337 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 S |
338 | struct ath_tx_control *txctl); |
339 | void ath_tx_tasklet(struct ath_softc *sc); | |
e5003249 | 340 | void ath_tx_edma_tasklet(struct ath_softc *sc); |
231c3a1f FF |
341 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
342 | u16 tid, u16 *ssn); | |
f83da965 | 343 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
394cf0a1 S |
344 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
345 | ||
5519541d FF |
346 | void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); |
347 | bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an); | |
348 | ||
394cf0a1 | 349 | /********/ |
17d7904d | 350 | /* VIFs */ |
394cf0a1 | 351 | /********/ |
f078f209 | 352 | |
17d7904d | 353 | struct ath_vif { |
394cf0a1 | 354 | int av_bslot; |
4f5ef75b | 355 | bool is_bslot_active, primary_sta_vif; |
4ed96f04 | 356 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 | 357 | struct ath_buf *av_bcbuf; |
f078f209 LR |
358 | }; |
359 | ||
394cf0a1 S |
360 | /*******************/ |
361 | /* Beacon Handling */ | |
362 | /*******************/ | |
f078f209 | 363 | |
394cf0a1 S |
364 | /* |
365 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
366 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
367 | * number of beacon intervals, the game's up. | |
368 | */ | |
c944daf4 | 369 | #define BSTUCK_THRESH 9 |
4ed96f04 | 370 | #define ATH_BCBUF 4 |
394cf0a1 S |
371 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
372 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
373 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | |
374 | ||
375 | struct ath_beacon_config { | |
9814f6b3 | 376 | int beacon_interval; |
394cf0a1 S |
377 | u16 listen_interval; |
378 | u16 dtim_period; | |
379 | u16 bmiss_timeout; | |
380 | u8 dtim_count; | |
394cf0a1 S |
381 | }; |
382 | ||
383 | struct ath_beacon { | |
384 | enum { | |
385 | OK, /* no change needed */ | |
386 | UPDATE, /* update pending */ | |
387 | COMMIT /* beacon sent, commit change */ | |
388 | } updateslot; /* slot time update fsm */ | |
389 | ||
390 | u32 beaconq; | |
391 | u32 bmisscnt; | |
392 | u32 ast_be_xmit; | |
dd347f2f | 393 | u32 bc_tstamp; |
2c3db3d5 | 394 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
394cf0a1 S |
395 | int slottime; |
396 | int slotupdate; | |
397 | struct ath9k_tx_queue_info beacon_qi; | |
398 | struct ath_descdma bdma; | |
399 | struct ath_txq *cabq; | |
400 | struct list_head bbuf; | |
ba4903f9 FF |
401 | |
402 | bool tx_processed; | |
403 | bool tx_last; | |
394cf0a1 S |
404 | }; |
405 | ||
9fc9ab0a | 406 | void ath_beacon_tasklet(unsigned long data); |
2c3db3d5 | 407 | void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); |
9ac58615 | 408 | int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif); |
17d7904d | 409 | void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); |
94db2936 | 410 | int ath_beaconq_config(struct ath_softc *sc); |
99e4d43a | 411 | void ath_set_beacon(struct ath_softc *sc); |
014cf3bb | 412 | void ath9k_set_beaconing_status(struct ath_softc *sc, bool status); |
394cf0a1 S |
413 | |
414 | /*******/ | |
415 | /* ANI */ | |
416 | /*******/ | |
f078f209 | 417 | |
20977d3e S |
418 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
419 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
e36b27af LR |
420 | #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ |
421 | #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ | |
6044474e | 422 | #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ |
20977d3e S |
423 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ |
424 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
f078f209 | 425 | |
ca369eb4 VT |
426 | #define ATH_PAPRD_TIMEOUT 100 /* msecs */ |
427 | ||
347809fc | 428 | void ath_hw_check(struct work_struct *work); |
9eab61c2 | 429 | void ath_hw_pll_work(struct work_struct *work); |
9f42c2b6 | 430 | void ath_paprd_calibrate(struct work_struct *work); |
55624204 S |
431 | void ath_ani_calibrate(unsigned long data); |
432 | ||
0fca65c1 S |
433 | /**********/ |
434 | /* BTCOEX */ | |
435 | /**********/ | |
436 | ||
2e20250a LR |
437 | struct ath_btcoex { |
438 | bool hw_timer_enabled; | |
439 | spinlock_t btcoex_lock; | |
440 | struct timer_list period_timer; /* Timer for BT period */ | |
441 | u32 bt_priority_cnt; | |
442 | unsigned long bt_priority_time; | |
e08a6ace | 443 | int bt_stomp_type; /* Types of BT stomping */ |
2e20250a LR |
444 | u32 btcoex_no_stomp; /* in usec */ |
445 | u32 btcoex_period; /* in usec */ | |
58da1318 | 446 | u32 btscan_no_stomp; /* in usec */ |
75d7839f | 447 | struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ |
2e20250a LR |
448 | }; |
449 | ||
0fca65c1 S |
450 | int ath_init_btcoex_timer(struct ath_softc *sc); |
451 | void ath9k_btcoex_timer_resume(struct ath_softc *sc); | |
452 | void ath9k_btcoex_timer_pause(struct ath_softc *sc); | |
453 | ||
394cf0a1 S |
454 | /********************/ |
455 | /* LED Control */ | |
456 | /********************/ | |
f078f209 | 457 | |
08fc5c1b VN |
458 | #define ATH_LED_PIN_DEF 1 |
459 | #define ATH_LED_PIN_9287 8 | |
353e5019 | 460 | #define ATH_LED_PIN_9300 10 |
15178535 | 461 | #define ATH_LED_PIN_9485 6 |
f078f209 | 462 | |
0cf55c21 | 463 | #ifdef CONFIG_MAC80211_LEDS |
0fca65c1 S |
464 | void ath_init_leds(struct ath_softc *sc); |
465 | void ath_deinit_leds(struct ath_softc *sc); | |
0cf55c21 FF |
466 | #else |
467 | static inline void ath_init_leds(struct ath_softc *sc) | |
468 | { | |
469 | } | |
470 | ||
471 | static inline void ath_deinit_leds(struct ath_softc *sc) | |
472 | { | |
473 | } | |
474 | #endif | |
475 | ||
0fca65c1 | 476 | |
102885a5 VT |
477 | /* Antenna diversity/combining */ |
478 | #define ATH_ANT_RX_CURRENT_SHIFT 4 | |
479 | #define ATH_ANT_RX_MAIN_SHIFT 2 | |
480 | #define ATH_ANT_RX_MASK 0x3 | |
481 | ||
482 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 | |
483 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 | |
484 | #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 | |
485 | #define ATH_ANT_DIV_COMB_INIT_COUNT 95 | |
486 | #define ATH_ANT_DIV_COMB_MAX_COUNT 100 | |
487 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 | |
488 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 | |
489 | ||
102885a5 VT |
490 | #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 |
491 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 | |
492 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 | |
493 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 | |
494 | ||
495 | enum ath9k_ant_div_comb_lna_conf { | |
496 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, | |
497 | ATH_ANT_DIV_COMB_LNA2, | |
498 | ATH_ANT_DIV_COMB_LNA1, | |
499 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, | |
500 | }; | |
501 | ||
502 | struct ath_ant_comb { | |
503 | u16 count; | |
504 | u16 total_pkt_count; | |
505 | bool scan; | |
506 | bool scan_not_start; | |
507 | int main_total_rssi; | |
508 | int alt_total_rssi; | |
509 | int alt_recv_cnt; | |
510 | int main_recv_cnt; | |
511 | int rssi_lna1; | |
512 | int rssi_lna2; | |
513 | int rssi_add; | |
514 | int rssi_sub; | |
515 | int rssi_first; | |
516 | int rssi_second; | |
517 | int rssi_third; | |
518 | bool alt_good; | |
519 | int quick_scan_cnt; | |
520 | int main_conf; | |
521 | enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; | |
522 | enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; | |
523 | int first_bias; | |
524 | int second_bias; | |
525 | bool first_ratio; | |
526 | bool second_ratio; | |
527 | unsigned long scan_start_time; | |
528 | }; | |
529 | ||
394cf0a1 S |
530 | /********************/ |
531 | /* Main driver core */ | |
532 | /********************/ | |
f078f209 | 533 | |
394cf0a1 S |
534 | /* |
535 | * Default cache line size, in bytes. | |
536 | * Used when PCI device not fully initialized by bootrom/BIOS | |
537 | */ | |
538 | #define DEFAULT_CACHELINE 32 | |
394cf0a1 S |
539 | #define ATH_REGCLASSIDS_MAX 10 |
540 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | |
541 | #define ATH_MAX_SW_RETRIES 10 | |
542 | #define ATH_CHAN_MAX 255 | |
f1dc5600 | 543 | |
394cf0a1 | 544 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
394cf0a1 S |
545 | #define ATH_RATE_DUMMY_MARKER 0 |
546 | ||
1b04b930 S |
547 | #define SC_OP_INVALID BIT(0) |
548 | #define SC_OP_BEACONS BIT(1) | |
549 | #define SC_OP_RXAGGR BIT(2) | |
550 | #define SC_OP_TXAGGR BIT(3) | |
5ee08656 | 551 | #define SC_OP_OFFCHANNEL BIT(4) |
1b04b930 S |
552 | #define SC_OP_PREAMBLE_SHORT BIT(5) |
553 | #define SC_OP_PROTECT_ENABLE BIT(6) | |
554 | #define SC_OP_RXFLUSH BIT(7) | |
555 | #define SC_OP_LED_ASSOCIATED BIT(8) | |
556 | #define SC_OP_LED_ON BIT(9) | |
1b04b930 S |
557 | #define SC_OP_TSF_RESET BIT(11) |
558 | #define SC_OP_BT_PRIORITY_DETECTED BIT(12) | |
58da1318 | 559 | #define SC_OP_BT_SCAN BIT(13) |
6c3118e2 | 560 | #define SC_OP_ANI_RUN BIT(14) |
ea066d5a | 561 | #define SC_OP_ENABLE_APM BIT(15) |
4f5ef75b | 562 | #define SC_OP_PRIM_STA_VIF BIT(16) |
1b04b930 S |
563 | |
564 | /* Powersave flags */ | |
565 | #define PS_WAIT_FOR_BEACON BIT(0) | |
566 | #define PS_WAIT_FOR_CAB BIT(1) | |
567 | #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) | |
568 | #define PS_WAIT_FOR_TX_ACK BIT(3) | |
569 | #define PS_BEACON_SYNC BIT(4) | |
deb75188 | 570 | #define PS_TSFOOR_SYNC BIT(5) |
394cf0a1 | 571 | |
545750d3 | 572 | struct ath_rate_table; |
bce048d7 | 573 | |
4801416c BG |
574 | struct ath9k_vif_iter_data { |
575 | const u8 *hw_macaddr; /* phy's hardware address, set | |
576 | * before starting iteration for | |
577 | * valid bssid mask. | |
578 | */ | |
579 | u8 mask[ETH_ALEN]; /* bssid mask */ | |
580 | int naps; /* number of AP vifs */ | |
581 | int nmeshes; /* number of mesh vifs */ | |
582 | int nstations; /* number of station vifs */ | |
583 | int nwds; /* number of nwd vifs */ | |
584 | int nadhocs; /* number of adhoc vifs */ | |
585 | int nothers; /* number of vifs not specified above. */ | |
586 | }; | |
587 | ||
394cf0a1 S |
588 | struct ath_softc { |
589 | struct ieee80211_hw *hw; | |
590 | struct device *dev; | |
c52f33d0 | 591 | |
0e2dedf9 JM |
592 | int chan_idx; |
593 | int chan_is_ht; | |
3430098a FF |
594 | struct survey_info *cur_survey; |
595 | struct survey_info survey[ATH9K_NUM_CHANNELS]; | |
0e2dedf9 | 596 | |
394cf0a1 S |
597 | struct tasklet_struct intr_tq; |
598 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 599 | struct ath_hw *sc_ah; |
394cf0a1 S |
600 | void __iomem *mem; |
601 | int irq; | |
2d6a5e95 | 602 | spinlock_t sc_serial_rw; |
04717ccd | 603 | spinlock_t sc_pm_lock; |
4bdd1e97 | 604 | spinlock_t sc_pcu_lock; |
394cf0a1 | 605 | struct mutex mutex; |
9f42c2b6 | 606 | struct work_struct paprd_work; |
347809fc | 607 | struct work_struct hw_check_work; |
9f42c2b6 | 608 | struct completion paprd_complete; |
394cf0a1 | 609 | |
cb8d61de FF |
610 | unsigned int hw_busy_count; |
611 | ||
17d7904d | 612 | u32 intrstatus; |
394cf0a1 | 613 | u32 sc_flags; /* SC_OP_* */ |
1b04b930 | 614 | u16 ps_flags; /* PS_* */ |
17d7904d | 615 | u16 curtxpow; |
96148326 | 616 | bool ps_enabled; |
1dbfd9d4 | 617 | bool ps_idle; |
4801416c BG |
618 | short nbcnvifs; |
619 | short nvifs; | |
709ade9e | 620 | unsigned long ps_usecount; |
394cf0a1 | 621 | |
17d7904d | 622 | struct ath_config config; |
394cf0a1 S |
623 | struct ath_rx rx; |
624 | struct ath_tx tx; | |
625 | struct ath_beacon beacon; | |
394cf0a1 S |
626 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; |
627 | ||
0cf55c21 FF |
628 | #ifdef CONFIG_MAC80211_LEDS |
629 | bool led_registered; | |
630 | char led_name[32]; | |
631 | struct led_classdev led_cdev; | |
632 | #endif | |
394cf0a1 | 633 | |
9ac58615 FF |
634 | struct ath9k_hw_cal_data caldata; |
635 | int last_rssi; | |
636 | ||
a830df07 | 637 | #ifdef CONFIG_ATH9K_DEBUGFS |
17d7904d | 638 | struct ath9k_debug debug; |
7f010c93 BG |
639 | spinlock_t nodes_lock; |
640 | struct list_head nodes; /* basically, stations */ | |
60f2d1d5 | 641 | unsigned int tx_complete_poll_work_seen; |
394cf0a1 | 642 | #endif |
6b96f93e | 643 | struct ath_beacon_config cur_beacon_conf; |
164ace38 | 644 | struct delayed_work tx_complete_work; |
181fb18d | 645 | struct delayed_work hw_pll_work; |
2e20250a | 646 | struct ath_btcoex btcoex; |
5088c2f1 VT |
647 | |
648 | struct ath_descdma txsdma; | |
102885a5 VT |
649 | |
650 | struct ath_ant_comb ant_comb; | |
394cf0a1 S |
651 | }; |
652 | ||
55624204 | 653 | void ath9k_tasklet(unsigned long data); |
394cf0a1 | 654 | int ath_reset(struct ath_softc *sc, bool retry_tx); |
394cf0a1 S |
655 | int ath_cabq_update(struct ath_softc *); |
656 | ||
5bb12791 | 657 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
394cf0a1 | 658 | { |
5bb12791 | 659 | common->bus_ops->read_cachesize(common, csz); |
394cf0a1 S |
660 | } |
661 | ||
394cf0a1 | 662 | extern struct ieee80211_ops ath9k_ops; |
3e6109c5 | 663 | extern int ath9k_modparam_nohwcrypt; |
9a75c2ff | 664 | extern int led_blink; |
d584747b | 665 | extern bool is_ath9k_unloaded; |
394cf0a1 S |
666 | |
667 | irqreturn_t ath_isr(int irq, void *dev); | |
db7ec38d | 668 | void ath9k_init_crypto(struct ath_softc *sc); |
285f2dda | 669 | int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, |
5bb12791 | 670 | const struct ath_bus_ops *bus_ops); |
285f2dda | 671 | void ath9k_deinit_device(struct ath_softc *sc); |
285f2dda | 672 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); |
0e2dedf9 JM |
673 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
674 | struct ath9k_channel *hchan); | |
68a89116 LR |
675 | |
676 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
677 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
55624204 | 678 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode); |
4801416c | 679 | bool ath9k_uses_beacons(int type); |
394cf0a1 | 680 | |
8e26a030 | 681 | #ifdef CONFIG_ATH9K_PCI |
394cf0a1 S |
682 | int ath_pci_init(void); |
683 | void ath_pci_exit(void); | |
684 | #else | |
685 | static inline int ath_pci_init(void) { return 0; }; | |
686 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 687 | #endif |
f1dc5600 | 688 | |
8e26a030 | 689 | #ifdef CONFIG_ATH9K_AHB |
394cf0a1 S |
690 | int ath_ahb_init(void); |
691 | void ath_ahb_exit(void); | |
692 | #else | |
693 | static inline int ath_ahb_init(void) { return 0; }; | |
694 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 695 | #endif |
394cf0a1 | 696 | |
0bc0798b GJ |
697 | void ath9k_ps_wakeup(struct ath_softc *sc); |
698 | void ath9k_ps_restore(struct ath_softc *sc); | |
8ca21f01 | 699 | |
ea066d5a MSS |
700 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); |
701 | ||
0fca65c1 S |
702 | void ath_start_rfkill_poll(struct ath_softc *sc); |
703 | extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); | |
4801416c BG |
704 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, |
705 | struct ieee80211_vif *vif, | |
706 | struct ath9k_vif_iter_data *iter_data); | |
707 | ||
0fca65c1 | 708 | |
394cf0a1 | 709 | #endif /* ATH9K_H */ |