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Commit | Line | Data |
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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
394cf0a1 | 22 | #include <linux/leds.h> |
394cf0a1 | 23 | |
394cf0a1 | 24 | #include "debug.h" |
db86f07e LR |
25 | #include "common.h" |
26 | ||
27 | /* | |
28 | * Header for the ath9k.ko driver core *only* -- hw code nor any other driver | |
29 | * should rely on this file or its contents. | |
30 | */ | |
394cf0a1 S |
31 | |
32 | struct ath_node; | |
33 | ||
34 | /* Macro to expand scalars to 64-bit objects */ | |
35 | ||
13bda122 | 36 | #define ito64(x) (sizeof(x) == 1) ? \ |
394cf0a1 | 37 | (((unsigned long long int)(x)) & (0xff)) : \ |
13bda122 | 38 | (sizeof(x) == 2) ? \ |
394cf0a1 | 39 | (((unsigned long long int)(x)) & 0xffff) : \ |
13bda122 | 40 | ((sizeof(x) == 4) ? \ |
394cf0a1 S |
41 | (((unsigned long long int)(x)) & 0xffffffff) : \ |
42 | (unsigned long long int)(x)) | |
43 | ||
44 | /* increment with wrap-around */ | |
45 | #define INCR(_l, _sz) do { \ | |
46 | (_l)++; \ | |
47 | (_l) &= ((_sz) - 1); \ | |
48 | } while (0) | |
49 | ||
50 | /* decrement with wrap-around */ | |
51 | #define DECR(_l, _sz) do { \ | |
52 | (_l)--; \ | |
53 | (_l) &= ((_sz) - 1); \ | |
54 | } while (0) | |
55 | ||
56 | #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) | |
57 | ||
394cf0a1 S |
58 | #define TSF_TO_TU(_h,_l) \ |
59 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
60 | ||
61 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) | |
62 | ||
394cf0a1 S |
63 | struct ath_config { |
64 | u32 ath_aggr_prot; | |
65 | u16 txpowlimit; | |
66 | u8 cabqReadytime; | |
394cf0a1 S |
67 | }; |
68 | ||
69 | /*************************/ | |
70 | /* Descriptor Management */ | |
71 | /*************************/ | |
72 | ||
73 | #define ATH_TXBUF_RESET(_bf) do { \ | |
a119cc49 | 74 | (_bf)->bf_stale = false; \ |
394cf0a1 S |
75 | (_bf)->bf_lastbf = NULL; \ |
76 | (_bf)->bf_next = NULL; \ | |
77 | memset(&((_bf)->bf_state), 0, \ | |
78 | sizeof(struct ath_buf_state)); \ | |
79 | } while (0) | |
80 | ||
a119cc49 S |
81 | #define ATH_RXBUF_RESET(_bf) do { \ |
82 | (_bf)->bf_stale = false; \ | |
83 | } while (0) | |
84 | ||
394cf0a1 S |
85 | /** |
86 | * enum buffer_type - Buffer type flags | |
87 | * | |
88 | * @BUF_HT: Send this buffer using HT capabilities | |
89 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) | |
90 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
91 | * (used in aggregation scheduling) | |
92 | * @BUF_RETRY: Indicates whether the buffer is retried | |
93 | * @BUF_XRETRY: To denote excessive retries of the buffer | |
94 | */ | |
95 | enum buffer_type { | |
96 | BUF_HT = BIT(1), | |
97 | BUF_AMPDU = BIT(2), | |
98 | BUF_AGGR = BIT(3), | |
99 | BUF_RETRY = BIT(4), | |
100 | BUF_XRETRY = BIT(5), | |
101 | }; | |
102 | ||
394cf0a1 S |
103 | #define bf_nframes bf_state.bfs_nframes |
104 | #define bf_al bf_state.bfs_al | |
105 | #define bf_frmlen bf_state.bfs_frmlen | |
106 | #define bf_retries bf_state.bfs_retries | |
107 | #define bf_seqno bf_state.bfs_seqno | |
108 | #define bf_tidno bf_state.bfs_tidno | |
109 | #define bf_keyix bf_state.bfs_keyix | |
110 | #define bf_keytype bf_state.bfs_keytype | |
111 | #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) | |
112 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) | |
113 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
114 | #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) | |
115 | #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) | |
f078f209 | 116 | |
394cf0a1 | 117 | struct ath_descdma { |
17d7904d S |
118 | struct ath_desc *dd_desc; |
119 | dma_addr_t dd_desc_paddr; | |
120 | u32 dd_desc_len; | |
121 | struct ath_buf *dd_bufptr; | |
394cf0a1 S |
122 | }; |
123 | ||
124 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
125 | struct list_head *head, const char *name, | |
126 | int nbuf, int ndesc); | |
127 | void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, | |
128 | struct list_head *head); | |
129 | ||
130 | /***********/ | |
131 | /* RX / TX */ | |
132 | /***********/ | |
133 | ||
134 | #define ATH_MAX_ANTENNA 3 | |
135 | #define ATH_RXBUF 512 | |
394cf0a1 S |
136 | #define ATH_TXBUF 512 |
137 | #define ATH_TXMAXTRY 13 | |
394cf0a1 | 138 | #define ATH_MGT_TXMAXTRY 4 |
394cf0a1 S |
139 | |
140 | #define TID_TO_WME_AC(_tid) \ | |
141 | ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ | |
142 | (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ | |
143 | (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ | |
144 | WME_AC_VO) | |
145 | ||
394cf0a1 S |
146 | #define ADDBA_EXCHANGE_ATTEMPTS 10 |
147 | #define ATH_AGGR_DELIM_SZ 4 | |
148 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
149 | /* number of delimiters for encryption padding */ | |
150 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
151 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
152 | #define ATH_AGGR_MIN_QDEPTH 2 | |
153 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | |
394cf0a1 S |
154 | |
155 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | |
156 | #define IEEE80211_SEQ_MAX 4096 | |
394cf0a1 S |
157 | #define IEEE80211_WEP_IVLEN 3 |
158 | #define IEEE80211_WEP_KIDLEN 1 | |
159 | #define IEEE80211_WEP_CRCLEN 4 | |
160 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
161 | (IEEE80211_WEP_IVLEN + \ | |
162 | IEEE80211_WEP_KIDLEN + \ | |
163 | IEEE80211_WEP_CRCLEN)) | |
164 | ||
165 | /* return whether a bit at index _n in bitmap _bm is set | |
166 | * _sz is the size of the bitmap */ | |
167 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
168 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
169 | ||
170 | /* return block-ack bitmap index given sequence and starting sequence */ | |
171 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
172 | ||
173 | /* returns delimiter padding required given the packet length */ | |
174 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
175 | (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ | |
176 | (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) | |
177 | ||
178 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
179 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
180 | ||
181 | #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum) | |
182 | #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low) | |
183 | #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA) | |
184 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) | |
185 | ||
164ace38 SB |
186 | #define ATH_TX_COMPLETE_POLL_INT 1000 |
187 | ||
394cf0a1 S |
188 | enum ATH_AGGR_STATUS { |
189 | ATH_AGGR_DONE, | |
190 | ATH_AGGR_BAW_CLOSED, | |
191 | ATH_AGGR_LIMITED, | |
192 | }; | |
193 | ||
194 | struct ath_txq { | |
17d7904d S |
195 | u32 axq_qnum; |
196 | u32 *axq_link; | |
197 | struct list_head axq_q; | |
394cf0a1 | 198 | spinlock_t axq_lock; |
17d7904d | 199 | u32 axq_depth; |
17d7904d | 200 | bool stopped; |
164ace38 | 201 | bool axq_tx_inprogress; |
394cf0a1 S |
202 | struct list_head axq_acq; |
203 | }; | |
204 | ||
205 | #define AGGR_CLEANUP BIT(1) | |
206 | #define AGGR_ADDBA_COMPLETE BIT(2) | |
207 | #define AGGR_ADDBA_PROGRESS BIT(3) | |
208 | ||
394cf0a1 S |
209 | struct ath_tx_control { |
210 | struct ath_txq *txq; | |
211 | int if_id; | |
f0ed85c6 | 212 | enum ath9k_internal_frame_type frame_type; |
394cf0a1 S |
213 | }; |
214 | ||
394cf0a1 S |
215 | #define ATH_TX_ERROR 0x01 |
216 | #define ATH_TX_XRETRY 0x02 | |
217 | #define ATH_TX_BAR 0x04 | |
394cf0a1 | 218 | |
394cf0a1 S |
219 | struct ath_tx { |
220 | u16 seq_no; | |
221 | u32 txqsetup; | |
222 | int hwq_map[ATH9K_WME_AC_VO+1]; | |
223 | spinlock_t txbuflock; | |
224 | struct list_head txbuf; | |
225 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
226 | struct ath_descdma txdma; | |
227 | }; | |
228 | ||
229 | struct ath_rx { | |
230 | u8 defant; | |
231 | u8 rxotherant; | |
232 | u32 *rxlink; | |
394cf0a1 S |
233 | unsigned int rxfilter; |
234 | spinlock_t rxflushlock; | |
235 | spinlock_t rxbuflock; | |
236 | struct list_head rxbuf; | |
237 | struct ath_descdma rxdma; | |
238 | }; | |
239 | ||
240 | int ath_startrecv(struct ath_softc *sc); | |
241 | bool ath_stoprecv(struct ath_softc *sc); | |
242 | void ath_flushrecv(struct ath_softc *sc); | |
243 | u32 ath_calcrxfilter(struct ath_softc *sc); | |
244 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
245 | void ath_rx_cleanup(struct ath_softc *sc); | |
246 | int ath_rx_tasklet(struct ath_softc *sc, int flush); | |
247 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); | |
248 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); | |
249 | int ath_tx_setup(struct ath_softc *sc, int haltype); | |
250 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); | |
251 | void ath_draintxq(struct ath_softc *sc, | |
252 | struct ath_txq *txq, bool retry_tx); | |
253 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); | |
254 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
255 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
256 | int ath_tx_init(struct ath_softc *sc, int nbufs); | |
797fe5cb | 257 | void ath_tx_cleanup(struct ath_softc *sc); |
394cf0a1 S |
258 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb); |
259 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
260 | struct ath9k_tx_queue_info *q); | |
c52f33d0 | 261 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 S |
262 | struct ath_tx_control *txctl); |
263 | void ath_tx_tasklet(struct ath_softc *sc); | |
c52f33d0 | 264 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb); |
394cf0a1 | 265 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno); |
f83da965 S |
266 | void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
267 | u16 tid, u16 *ssn); | |
268 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); | |
394cf0a1 S |
269 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
270 | ||
271 | /********/ | |
17d7904d | 272 | /* VIFs */ |
394cf0a1 | 273 | /********/ |
f078f209 | 274 | |
17d7904d | 275 | struct ath_vif { |
394cf0a1 | 276 | int av_bslot; |
4ed96f04 | 277 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 S |
278 | enum nl80211_iftype av_opmode; |
279 | struct ath_buf *av_bcbuf; | |
280 | struct ath_tx_control av_btxctl; | |
f0ed85c6 | 281 | u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */ |
f078f209 LR |
282 | }; |
283 | ||
394cf0a1 S |
284 | /*******************/ |
285 | /* Beacon Handling */ | |
286 | /*******************/ | |
f078f209 | 287 | |
394cf0a1 S |
288 | /* |
289 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
290 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
291 | * number of beacon intervals, the game's up. | |
292 | */ | |
293 | #define BSTUCK_THRESH (9 * ATH_BCBUF) | |
4ed96f04 | 294 | #define ATH_BCBUF 4 |
394cf0a1 S |
295 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
296 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
297 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | |
298 | ||
299 | struct ath_beacon_config { | |
300 | u16 beacon_interval; | |
301 | u16 listen_interval; | |
302 | u16 dtim_period; | |
303 | u16 bmiss_timeout; | |
304 | u8 dtim_count; | |
394cf0a1 S |
305 | }; |
306 | ||
307 | struct ath_beacon { | |
308 | enum { | |
309 | OK, /* no change needed */ | |
310 | UPDATE, /* update pending */ | |
311 | COMMIT /* beacon sent, commit change */ | |
312 | } updateslot; /* slot time update fsm */ | |
313 | ||
314 | u32 beaconq; | |
315 | u32 bmisscnt; | |
316 | u32 ast_be_xmit; | |
317 | u64 bc_tstamp; | |
2c3db3d5 | 318 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
c52f33d0 | 319 | struct ath_wiphy *bslot_aphy[ATH_BCBUF]; |
394cf0a1 S |
320 | int slottime; |
321 | int slotupdate; | |
322 | struct ath9k_tx_queue_info beacon_qi; | |
323 | struct ath_descdma bdma; | |
324 | struct ath_txq *cabq; | |
325 | struct list_head bbuf; | |
326 | }; | |
327 | ||
9fc9ab0a | 328 | void ath_beacon_tasklet(unsigned long data); |
2c3db3d5 | 329 | void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); |
c52f33d0 | 330 | int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); |
17d7904d | 331 | void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); |
94db2936 | 332 | int ath_beaconq_config(struct ath_softc *sc); |
394cf0a1 S |
333 | |
334 | /*******/ | |
335 | /* ANI */ | |
336 | /*******/ | |
f078f209 | 337 | |
20977d3e S |
338 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
339 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
340 | #define ATH_ANI_POLLINTERVAL 100 /* 100 ms */ | |
341 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ | |
342 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
f078f209 | 343 | |
e08a6ace LR |
344 | /* Defines the BT AR_BT_COEX_WGHT used */ |
345 | enum ath_stomp_type { | |
346 | ATH_BTCOEX_NO_STOMP, | |
347 | ATH_BTCOEX_STOMP_ALL, | |
348 | ATH_BTCOEX_STOMP_LOW, | |
349 | ATH_BTCOEX_STOMP_NONE | |
350 | }; | |
351 | ||
2e20250a LR |
352 | struct ath_btcoex { |
353 | bool hw_timer_enabled; | |
354 | spinlock_t btcoex_lock; | |
355 | struct timer_list period_timer; /* Timer for BT period */ | |
356 | u32 bt_priority_cnt; | |
357 | unsigned long bt_priority_time; | |
e08a6ace | 358 | int bt_stomp_type; /* Types of BT stomping */ |
2e20250a LR |
359 | u32 btcoex_no_stomp; /* in usec */ |
360 | u32 btcoex_period; /* in usec */ | |
75d7839f | 361 | struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ |
2e20250a LR |
362 | }; |
363 | ||
394cf0a1 S |
364 | /********************/ |
365 | /* LED Control */ | |
366 | /********************/ | |
f078f209 | 367 | |
08fc5c1b VN |
368 | #define ATH_LED_PIN_DEF 1 |
369 | #define ATH_LED_PIN_9287 8 | |
394cf0a1 S |
370 | #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ |
371 | #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ | |
f078f209 | 372 | |
394cf0a1 S |
373 | enum ath_led_type { |
374 | ATH_LED_RADIO, | |
375 | ATH_LED_ASSOC, | |
376 | ATH_LED_TX, | |
377 | ATH_LED_RX | |
f078f209 LR |
378 | }; |
379 | ||
394cf0a1 S |
380 | struct ath_led { |
381 | struct ath_softc *sc; | |
382 | struct led_classdev led_cdev; | |
383 | enum ath_led_type led_type; | |
384 | char name[32]; | |
385 | bool registered; | |
f078f209 LR |
386 | }; |
387 | ||
394cf0a1 S |
388 | /********************/ |
389 | /* Main driver core */ | |
390 | /********************/ | |
f078f209 | 391 | |
394cf0a1 S |
392 | /* |
393 | * Default cache line size, in bytes. | |
394 | * Used when PCI device not fully initialized by bootrom/BIOS | |
395 | */ | |
396 | #define DEFAULT_CACHELINE 32 | |
394cf0a1 S |
397 | #define ATH_REGCLASSIDS_MAX 10 |
398 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | |
399 | #define ATH_MAX_SW_RETRIES 10 | |
400 | #define ATH_CHAN_MAX 255 | |
401 | #define IEEE80211_WEP_NKID 4 /* number of key ids */ | |
f1dc5600 | 402 | |
394cf0a1 | 403 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
394cf0a1 S |
404 | #define ATH_RATE_DUMMY_MARKER 0 |
405 | ||
b238e90e S |
406 | #define SC_OP_INVALID BIT(0) |
407 | #define SC_OP_BEACONS BIT(1) | |
408 | #define SC_OP_RXAGGR BIT(2) | |
409 | #define SC_OP_TXAGGR BIT(3) | |
bdbdf46d S |
410 | #define SC_OP_FULL_RESET BIT(4) |
411 | #define SC_OP_PREAMBLE_SHORT BIT(5) | |
412 | #define SC_OP_PROTECT_ENABLE BIT(6) | |
413 | #define SC_OP_RXFLUSH BIT(7) | |
414 | #define SC_OP_LED_ASSOCIATED BIT(8) | |
bdbdf46d S |
415 | #define SC_OP_WAIT_FOR_BEACON BIT(12) |
416 | #define SC_OP_LED_ON BIT(13) | |
417 | #define SC_OP_SCANNING BIT(14) | |
418 | #define SC_OP_TSF_RESET BIT(15) | |
cc65965c | 419 | #define SC_OP_WAIT_FOR_CAB BIT(16) |
9a23f9ca JM |
420 | #define SC_OP_WAIT_FOR_PSPOLL_DATA BIT(17) |
421 | #define SC_OP_WAIT_FOR_TX_ACK BIT(18) | |
ccdfeab6 | 422 | #define SC_OP_BEACON_SYNC BIT(19) |
1773912b | 423 | #define SC_OP_BT_PRIORITY_DETECTED BIT(21) |
e7824a50 LR |
424 | #define SC_OP_NULLFUNC_COMPLETED BIT(22) |
425 | #define SC_OP_PS_ENABLED BIT(23) | |
394cf0a1 | 426 | |
bce048d7 | 427 | struct ath_wiphy; |
545750d3 | 428 | struct ath_rate_table; |
bce048d7 | 429 | |
394cf0a1 S |
430 | struct ath_softc { |
431 | struct ieee80211_hw *hw; | |
432 | struct device *dev; | |
c52f33d0 JM |
433 | |
434 | spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ | |
bce048d7 | 435 | struct ath_wiphy *pri_wiphy; |
c52f33d0 JM |
436 | struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may |
437 | * have NULL entries */ | |
438 | int num_sec_wiphy; /* number of sec_wiphy pointers in the array */ | |
0e2dedf9 JM |
439 | int chan_idx; |
440 | int chan_is_ht; | |
441 | struct ath_wiphy *next_wiphy; | |
442 | struct work_struct chan_work; | |
7ec3e514 JM |
443 | int wiphy_select_failures; |
444 | unsigned long wiphy_select_first_fail; | |
f98c3bd2 JM |
445 | struct delayed_work wiphy_work; |
446 | unsigned long wiphy_scheduler_int; | |
447 | int wiphy_scheduler_index; | |
0e2dedf9 | 448 | |
394cf0a1 S |
449 | struct tasklet_struct intr_tq; |
450 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 451 | struct ath_hw *sc_ah; |
394cf0a1 S |
452 | void __iomem *mem; |
453 | int irq; | |
454 | spinlock_t sc_resetlock; | |
2d6a5e95 | 455 | spinlock_t sc_serial_rw; |
04717ccd | 456 | spinlock_t sc_pm_lock; |
394cf0a1 S |
457 | struct mutex mutex; |
458 | ||
17d7904d | 459 | u32 intrstatus; |
394cf0a1 | 460 | u32 sc_flags; /* SC_OP_* */ |
17d7904d | 461 | u16 curtxpow; |
17d7904d S |
462 | u8 nbcnvifs; |
463 | u16 nvifs; | |
96148326 | 464 | bool ps_enabled; |
709ade9e | 465 | unsigned long ps_usecount; |
17d7904d | 466 | enum ath9k_int imask; |
394cf0a1 | 467 | |
17d7904d | 468 | struct ath_config config; |
394cf0a1 S |
469 | struct ath_rx rx; |
470 | struct ath_tx tx; | |
471 | struct ath_beacon beacon; | |
4f0fc7c3 | 472 | const struct ath_rate_table *cur_rate_table; |
545750d3 | 473 | enum wireless_mode cur_rate_mode; |
394cf0a1 S |
474 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; |
475 | ||
476 | struct ath_led radio_led; | |
477 | struct ath_led assoc_led; | |
478 | struct ath_led tx_led; | |
479 | struct ath_led rx_led; | |
480 | struct delayed_work ath_led_blink_work; | |
481 | int led_on_duration; | |
482 | int led_off_duration; | |
483 | int led_on_cnt; | |
484 | int led_off_cnt; | |
485 | ||
57c4d7b4 JB |
486 | int beacon_interval; |
487 | ||
a830df07 | 488 | #ifdef CONFIG_ATH9K_DEBUGFS |
17d7904d | 489 | struct ath9k_debug debug; |
394cf0a1 | 490 | #endif |
6b96f93e | 491 | struct ath_beacon_config cur_beacon_conf; |
164ace38 | 492 | struct delayed_work tx_complete_work; |
2e20250a | 493 | struct ath_btcoex btcoex; |
394cf0a1 S |
494 | }; |
495 | ||
bce048d7 JM |
496 | struct ath_wiphy { |
497 | struct ath_softc *sc; /* shared for all virtual wiphys */ | |
498 | struct ieee80211_hw *hw; | |
f0ed85c6 | 499 | enum ath_wiphy_state { |
9580a222 | 500 | ATH_WIPHY_INACTIVE, |
f0ed85c6 JM |
501 | ATH_WIPHY_ACTIVE, |
502 | ATH_WIPHY_PAUSING, | |
503 | ATH_WIPHY_PAUSED, | |
8089cc47 | 504 | ATH_WIPHY_SCAN, |
f0ed85c6 | 505 | } state; |
194b7c13 | 506 | bool idle; |
0e2dedf9 JM |
507 | int chan_idx; |
508 | int chan_is_ht; | |
bce048d7 JM |
509 | }; |
510 | ||
394cf0a1 S |
511 | int ath_reset(struct ath_softc *sc, bool retry_tx); |
512 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); | |
513 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); | |
514 | int ath_cabq_update(struct ath_softc *); | |
515 | ||
5bb12791 | 516 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
394cf0a1 | 517 | { |
5bb12791 | 518 | common->bus_ops->read_cachesize(common, csz); |
394cf0a1 S |
519 | } |
520 | ||
5bb12791 | 521 | static inline void ath_bus_cleanup(struct ath_common *common) |
394cf0a1 | 522 | { |
5bb12791 | 523 | common->bus_ops->cleanup(common); |
394cf0a1 S |
524 | } |
525 | ||
526 | extern struct ieee80211_ops ath9k_ops; | |
527 | ||
528 | irqreturn_t ath_isr(int irq, void *dev); | |
529 | void ath_cleanup(struct ath_softc *sc); | |
5bb12791 LR |
530 | int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, |
531 | const struct ath_bus_ops *bus_ops); | |
394cf0a1 S |
532 | void ath_detach(struct ath_softc *sc); |
533 | const char *ath_mac_bb_name(u32 mac_bb_version); | |
534 | const char *ath_rf_name(u16 rf_version); | |
c52f33d0 | 535 | void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); |
0e2dedf9 JM |
536 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
537 | struct ath9k_channel *ichan); | |
538 | void ath_update_chainmask(struct ath_softc *sc, int is_ht); | |
539 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
540 | struct ath9k_channel *hchan); | |
68a89116 LR |
541 | |
542 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
543 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
394cf0a1 S |
544 | |
545 | #ifdef CONFIG_PCI | |
546 | int ath_pci_init(void); | |
547 | void ath_pci_exit(void); | |
548 | #else | |
549 | static inline int ath_pci_init(void) { return 0; }; | |
550 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 551 | #endif |
f1dc5600 | 552 | |
394cf0a1 S |
553 | #ifdef CONFIG_ATHEROS_AR71XX |
554 | int ath_ahb_init(void); | |
555 | void ath_ahb_exit(void); | |
556 | #else | |
557 | static inline int ath_ahb_init(void) { return 0; }; | |
558 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 559 | #endif |
394cf0a1 | 560 | |
0bc0798b GJ |
561 | void ath9k_ps_wakeup(struct ath_softc *sc); |
562 | void ath9k_ps_restore(struct ath_softc *sc); | |
8ca21f01 JM |
563 | |
564 | void ath9k_set_bssid_mask(struct ieee80211_hw *hw); | |
c52f33d0 JM |
565 | int ath9k_wiphy_add(struct ath_softc *sc); |
566 | int ath9k_wiphy_del(struct ath_wiphy *aphy); | |
f0ed85c6 JM |
567 | void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb); |
568 | int ath9k_wiphy_pause(struct ath_wiphy *aphy); | |
569 | int ath9k_wiphy_unpause(struct ath_wiphy *aphy); | |
0e2dedf9 | 570 | int ath9k_wiphy_select(struct ath_wiphy *aphy); |
f98c3bd2 | 571 | void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int); |
0e2dedf9 | 572 | void ath9k_wiphy_chan_work(struct work_struct *work); |
9580a222 | 573 | bool ath9k_wiphy_started(struct ath_softc *sc); |
18eb62f8 JM |
574 | void ath9k_wiphy_pause_all_forced(struct ath_softc *sc, |
575 | struct ath_wiphy *selected); | |
8089cc47 | 576 | bool ath9k_wiphy_scanning(struct ath_softc *sc); |
f98c3bd2 | 577 | void ath9k_wiphy_work(struct work_struct *work); |
64839170 | 578 | bool ath9k_all_wiphys_idle(struct ath_softc *sc); |
194b7c13 | 579 | void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle); |
8ca21f01 | 580 | |
f52de03b LR |
581 | void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue); |
582 | void ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue); | |
583 | ||
1773912b | 584 | int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype); |
394cf0a1 | 585 | #endif /* ATH9K_H */ |