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Commit | Line | Data |
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f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
a6b7a407 | 22 | #include <linux/interrupt.h> |
394cf0a1 | 23 | #include <linux/leds.h> |
9f42c2b6 | 24 | #include <linux/completion.h> |
8d7e09dd | 25 | #include <linux/time.h> |
ed14dc0a | 26 | #include <linux/hw_random.h> |
394cf0a1 | 27 | |
db86f07e | 28 | #include "common.h" |
9d83cd5c | 29 | #include "debug.h" |
7dc181c2 | 30 | #include "mci.h" |
8e92d3f2 | 31 | #include "dfs.h" |
db86f07e | 32 | |
394cf0a1 | 33 | struct ath_node; |
11e39a4e | 34 | struct ath_vif; |
394cf0a1 | 35 | |
7b6ef998 SM |
36 | extern struct ieee80211_ops ath9k_ops; |
37 | extern int ath9k_modparam_nohwcrypt; | |
0c8a1e43 | 38 | extern int ath9k_led_blink; |
7b6ef998 | 39 | extern bool is_ath9k_unloaded; |
78b21949 | 40 | extern int ath9k_use_chanctx; |
394cf0a1 | 41 | |
394cf0a1 S |
42 | /*************************/ |
43 | /* Descriptor Management */ | |
44 | /*************************/ | |
45 | ||
7b6ef998 SM |
46 | #define ATH_TXSTATUS_RING_SIZE 512 |
47 | ||
48 | /* Macro to expand scalars to 64-bit objects */ | |
49 | #define ito64(x) (sizeof(x) == 1) ? \ | |
50 | (((unsigned long long int)(x)) & (0xff)) : \ | |
51 | (sizeof(x) == 2) ? \ | |
52 | (((unsigned long long int)(x)) & 0xffff) : \ | |
53 | ((sizeof(x) == 4) ? \ | |
54 | (((unsigned long long int)(x)) & 0xffffffff) : \ | |
55 | (unsigned long long int)(x)) | |
56 | ||
394cf0a1 | 57 | #define ATH_TXBUF_RESET(_bf) do { \ |
394cf0a1 S |
58 | (_bf)->bf_lastbf = NULL; \ |
59 | (_bf)->bf_next = NULL; \ | |
60 | memset(&((_bf)->bf_state), 0, \ | |
61 | sizeof(struct ath_buf_state)); \ | |
62 | } while (0) | |
63 | ||
c3d77696 MSS |
64 | #define DS2PHYS(_dd, _ds) \ |
65 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
66 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
67 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
68 | ||
394cf0a1 | 69 | struct ath_descdma { |
5088c2f1 | 70 | void *dd_desc; |
17d7904d S |
71 | dma_addr_t dd_desc_paddr; |
72 | u32 dd_desc_len; | |
394cf0a1 S |
73 | }; |
74 | ||
75 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
76 | struct list_head *head, const char *name, | |
4adfcded | 77 | int nbuf, int ndesc, bool is_tx); |
394cf0a1 S |
78 | |
79 | /***********/ | |
80 | /* RX / TX */ | |
81 | /***********/ | |
82 | ||
7b6ef998 SM |
83 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) |
84 | ||
85 | /* increment with wrap-around */ | |
86 | #define INCR(_l, _sz) do { \ | |
87 | (_l)++; \ | |
88 | (_l) &= ((_sz) - 1); \ | |
89 | } while (0) | |
90 | ||
394cf0a1 | 91 | #define ATH_RXBUF 512 |
394cf0a1 | 92 | #define ATH_TXBUF 512 |
84642d6b | 93 | #define ATH_TXBUF_RESERVE 5 |
394cf0a1 | 94 | #define ATH_TXMAXTRY 13 |
7b6ef998 | 95 | #define ATH_MAX_SW_RETRIES 30 |
394cf0a1 S |
96 | |
97 | #define TID_TO_WME_AC(_tid) \ | |
bea843c7 SM |
98 | ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \ |
99 | (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \ | |
100 | (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \ | |
101 | IEEE80211_AC_VO) | |
394cf0a1 | 102 | |
394cf0a1 S |
103 | #define ATH_AGGR_DELIM_SZ 4 |
104 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
105 | /* number of delimiters for encryption padding */ | |
106 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
107 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
108 | #define ATH_AGGR_MIN_QDEPTH 2 | |
2800e82b FF |
109 | /* minimum h/w qdepth for non-aggregated traffic */ |
110 | #define ATH_NON_AGGR_MIN_QDEPTH 8 | |
d63ffc45 | 111 | #define ATH_HW_CHECK_POLL_INT 1000 |
7b6ef998 SM |
112 | #define ATH_TXFIFO_DEPTH 8 |
113 | #define ATH_TX_ERROR 0x01 | |
394cf0a1 | 114 | |
63fefa05 THJ |
115 | #define ATH_AIRTIME_QUANTUM 300 /* usec */ |
116 | ||
d463af4a FF |
117 | /* Stop tx traffic 1ms before the GO goes away */ |
118 | #define ATH_P2P_PS_STOP_TIME 1000 | |
119 | ||
394cf0a1 S |
120 | #define IEEE80211_SEQ_SEQ_SHIFT 4 |
121 | #define IEEE80211_SEQ_MAX 4096 | |
394cf0a1 S |
122 | #define IEEE80211_WEP_IVLEN 3 |
123 | #define IEEE80211_WEP_KIDLEN 1 | |
124 | #define IEEE80211_WEP_CRCLEN 4 | |
125 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
126 | (IEEE80211_WEP_IVLEN + \ | |
127 | IEEE80211_WEP_KIDLEN + \ | |
128 | IEEE80211_WEP_CRCLEN)) | |
129 | ||
130 | /* return whether a bit at index _n in bitmap _bm is set | |
131 | * _sz is the size of the bitmap */ | |
132 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
133 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
134 | ||
135 | /* return block-ack bitmap index given sequence and starting sequence */ | |
136 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
137 | ||
156369fa FF |
138 | /* return the seqno for _start + _offset */ |
139 | #define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1)) | |
140 | ||
394cf0a1 S |
141 | /* returns delimiter padding required given the packet length */ |
142 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
39ec2997 VT |
143 | (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \ |
144 | DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ)) | |
394cf0a1 S |
145 | |
146 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
147 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
148 | ||
50f08edf | 149 | #define ATH_AN_2_TID(_an, _tidno) ath_node_to_tid(_an, _tidno) |
394cf0a1 | 150 | |
350e2dcb SM |
151 | #define IS_HT_RATE(rate) (rate & 0x80) |
152 | #define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e)) | |
153 | #define IS_OFDM_RATE(rate) ((rate >= 0x8) && (rate <= 0xf)) | |
365d2ebc | 154 | |
9e495a26 SM |
155 | enum { |
156 | WLAN_RC_PHY_OFDM, | |
157 | WLAN_RC_PHY_CCK, | |
158 | }; | |
159 | ||
394cf0a1 | 160 | struct ath_txq { |
60f2d1d5 BG |
161 | int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */ |
162 | u32 axq_qnum; /* ath9k hardware queue number */ | |
fce041be | 163 | void *axq_link; |
17d7904d | 164 | struct list_head axq_q; |
394cf0a1 | 165 | spinlock_t axq_lock; |
17d7904d | 166 | u32 axq_depth; |
4b3ba66a | 167 | u32 axq_ampdu_depth; |
164ace38 | 168 | bool axq_tx_inprogress; |
e5003249 | 169 | struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; |
e5003249 VT |
170 | u8 txq_headidx; |
171 | u8 txq_tailidx; | |
066dae93 | 172 | int pending_frames; |
23de5dc9 | 173 | struct sk_buff_head complete_q; |
394cf0a1 S |
174 | }; |
175 | ||
2d42efc4 | 176 | struct ath_frame_info { |
56dc6336 | 177 | struct ath_buf *bf; |
d954cd77 FF |
178 | u16 framelen; |
179 | s8 txq; | |
a75c0629 | 180 | u8 keyix; |
80b08a8d | 181 | u8 rtscts_rate; |
8fed1408 FF |
182 | u8 retries : 7; |
183 | u8 baw_tracked : 1; | |
8b537686 | 184 | u8 tx_power; |
3a79e1df | 185 | enum ath9k_key_type keytype:2; |
2d42efc4 FF |
186 | }; |
187 | ||
1a04d59d FF |
188 | struct ath_rxbuf { |
189 | struct list_head list; | |
190 | struct sk_buff *bf_mpdu; | |
191 | void *bf_desc; | |
192 | dma_addr_t bf_daddr; | |
193 | dma_addr_t bf_buf_addr; | |
194 | }; | |
195 | ||
7b6ef998 SM |
196 | /** |
197 | * enum buffer_type - Buffer type flags | |
198 | * | |
199 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) | |
200 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
201 | * (used in aggregation scheduling) | |
202 | */ | |
203 | enum buffer_type { | |
204 | BUF_AMPDU = BIT(0), | |
205 | BUF_AGGR = BIT(1), | |
206 | }; | |
207 | ||
208 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) | |
209 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
210 | ||
93ef24b2 | 211 | struct ath_buf_state { |
93ef24b2 | 212 | u8 bf_type; |
9f42c2b6 | 213 | u8 bfs_paprd; |
399c6489 | 214 | u8 ndelim; |
50676b81 | 215 | bool stale; |
6a0ddaef | 216 | u16 seqno; |
9cf04dcc | 217 | unsigned long bfs_paprd_timestamp; |
93ef24b2 S |
218 | }; |
219 | ||
220 | struct ath_buf { | |
221 | struct list_head list; | |
222 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
223 | an aggregate) */ | |
224 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
225 | struct sk_buff *bf_mpdu; /* enclosing frame structure */ | |
226 | void *bf_desc; /* virtual addr of desc */ | |
227 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
c1739eb3 | 228 | dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ |
79acac07 | 229 | struct ieee80211_tx_rate rates[4]; |
93ef24b2 | 230 | struct ath_buf_state bf_state; |
93ef24b2 S |
231 | }; |
232 | ||
233 | struct ath_atx_tid { | |
234 | struct list_head list; | |
bb195ff6 | 235 | struct sk_buff_head retry_q; |
93ef24b2 | 236 | struct ath_node *an; |
592fa228 | 237 | struct ath_txq *txq; |
81ee13ba | 238 | unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; |
93ef24b2 S |
239 | u16 seq_start; |
240 | u16 seq_next; | |
241 | u16 baw_size; | |
50676b81 | 242 | u8 tidno; |
93ef24b2 S |
243 | int baw_head; /* first un-acked tx buffer */ |
244 | int baw_tail; /* next unused tx buffer slot */ | |
50676b81 FF |
245 | |
246 | s8 bar_index; | |
08c96abd | 247 | bool active; |
592fa228 | 248 | bool clear_ps_filter; |
50f08edf | 249 | bool has_queued; |
93ef24b2 S |
250 | }; |
251 | ||
63fefa05 THJ |
252 | void __ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid); |
253 | void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid); | |
254 | ||
93ef24b2 | 255 | struct ath_node { |
a145daf7 | 256 | struct ath_softc *sc; |
7f010c93 | 257 | struct ieee80211_sta *sta; /* station struct we're part of */ |
7e1e3864 | 258 | struct ieee80211_vif *vif; /* interface with which we're associated */ |
93ae2dd2 | 259 | |
93ef24b2 S |
260 | u16 maxampdu; |
261 | u8 mpdudensity; | |
50676b81 | 262 | s8 ps_key; |
5519541d FF |
263 | |
264 | bool sleeping; | |
f89d1bc4 | 265 | bool no_ps_filter; |
63fefa05 THJ |
266 | s64 airtime_deficit[IEEE80211_NUM_ACS]; |
267 | u32 airtime_rx_start; | |
350e2dcb SM |
268 | |
269 | #ifdef CONFIG_ATH9K_STATION_STATISTICS | |
270 | struct ath_rx_rate_stats rx_rate_stats; | |
63fefa05 | 271 | struct ath_airtime_stats airtime_stats; |
350e2dcb | 272 | #endif |
4bbf4414 | 273 | u8 key_idx[4]; |
c774d57f | 274 | |
fc62b3c9 | 275 | int ackto; |
c774d57f | 276 | struct list_head list; |
93ef24b2 S |
277 | }; |
278 | ||
394cf0a1 S |
279 | struct ath_tx_control { |
280 | struct ath_txq *txq; | |
2d42efc4 | 281 | struct ath_node *an; |
36323f81 | 282 | struct ieee80211_sta *sta; |
befcf7e7 | 283 | u8 paprd; |
394cf0a1 S |
284 | }; |
285 | ||
394cf0a1 | 286 | |
60f2d1d5 BG |
287 | /** |
288 | * @txq_map: Index is mac80211 queue number. This is | |
289 | * not necessarily the same as the hardware queue number | |
290 | * (axq_qnum). | |
291 | */ | |
394cf0a1 | 292 | struct ath_tx { |
394cf0a1 | 293 | u32 txqsetup; |
394cf0a1 S |
294 | spinlock_t txbuflock; |
295 | struct list_head txbuf; | |
296 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
297 | struct ath_descdma txdma; | |
bea843c7 | 298 | struct ath_txq *txq_map[IEEE80211_NUM_ACS]; |
f2c7a793 | 299 | struct ath_txq *uapsdq; |
bea843c7 | 300 | u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32]; |
394cf0a1 S |
301 | }; |
302 | ||
b5c80475 FF |
303 | struct ath_rx_edma { |
304 | struct sk_buff_head rx_fifo; | |
b5c80475 FF |
305 | u32 rx_fifo_hwsize; |
306 | }; | |
307 | ||
394cf0a1 S |
308 | struct ath_rx { |
309 | u8 defant; | |
310 | u8 rxotherant; | |
723e7113 | 311 | bool discard_next; |
394cf0a1 | 312 | u32 *rxlink; |
6995fb80 | 313 | u32 num_pkts; |
394cf0a1 S |
314 | struct list_head rxbuf; |
315 | struct ath_descdma rxdma; | |
b5c80475 | 316 | struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; |
0d95521e | 317 | |
1a04d59d | 318 | struct ath_rxbuf *buf_hold; |
0d95521e | 319 | struct sk_buff *frag; |
21fbbca3 CL |
320 | |
321 | u32 ampdu_ref; | |
394cf0a1 S |
322 | }; |
323 | ||
fb02e95c SM |
324 | /*******************/ |
325 | /* Channel Context */ | |
326 | /*******************/ | |
327 | ||
63fefa05 THJ |
328 | struct ath_acq { |
329 | struct list_head acq_new; | |
330 | struct list_head acq_old; | |
331 | spinlock_t lock; | |
332 | }; | |
333 | ||
fbbcd146 FF |
334 | struct ath_chanctx { |
335 | struct cfg80211_chan_def chandef; | |
336 | struct list_head vifs; | |
63fefa05 | 337 | struct ath_acq acq[IEEE80211_NUM_ACS]; |
3ad9c386 | 338 | int hw_queue_base; |
0453531e | 339 | |
9a9c4fbc RM |
340 | /* do not dereference, use for comparison only */ |
341 | struct ieee80211_vif *primary_sta; | |
342 | ||
ca900ac9 | 343 | struct ath_beacon_config beacon; |
b01459e8 | 344 | struct ath9k_hw_cal_data caldata; |
8d7e09dd FF |
345 | struct timespec tsf_ts; |
346 | u64 tsf_val; | |
58b57375 | 347 | u32 last_beacon; |
b01459e8 | 348 | |
2fae0d9f | 349 | int flush_timeout; |
bc7e1be7 | 350 | u16 txpower; |
d385c5c2 | 351 | u16 cur_txpower; |
fbbcd146 | 352 | bool offchannel; |
bff11766 | 353 | bool stopped; |
c083ce99 | 354 | bool active; |
39305635 | 355 | bool assigned; |
748299f2 | 356 | bool switch_after_beacon; |
fce34430 | 357 | |
ca529c93 | 358 | short nvifs; |
2ce73c02 | 359 | short nvifs_assigned; |
fce34430 | 360 | unsigned int rxfilter; |
748299f2 FF |
361 | }; |
362 | ||
363 | enum ath_chanctx_event { | |
364 | ATH_CHANCTX_EVENT_BEACON_PREPARE, | |
365 | ATH_CHANCTX_EVENT_BEACON_SENT, | |
366 | ATH_CHANCTX_EVENT_TSF_TIMER, | |
58b57375 | 367 | ATH_CHANCTX_EVENT_BEACON_RECEIVED, |
b8f9279b | 368 | ATH_CHANCTX_EVENT_AUTHORIZED, |
73fa2f26 | 369 | ATH_CHANCTX_EVENT_SWITCH, |
02da18b7 | 370 | ATH_CHANCTX_EVENT_ASSIGN, |
73fa2f26 | 371 | ATH_CHANCTX_EVENT_UNASSIGN, |
02da18b7 | 372 | ATH_CHANCTX_EVENT_CHANGE, |
73fa2f26 | 373 | ATH_CHANCTX_EVENT_ENABLE_MULTICHANNEL, |
748299f2 FF |
374 | }; |
375 | ||
376 | enum ath_chanctx_state { | |
377 | ATH_CHANCTX_STATE_IDLE, | |
378 | ATH_CHANCTX_STATE_WAIT_FOR_BEACON, | |
379 | ATH_CHANCTX_STATE_WAIT_FOR_TIMER, | |
380 | ATH_CHANCTX_STATE_SWITCH, | |
6036c284 | 381 | ATH_CHANCTX_STATE_FORCE_ACTIVE, |
748299f2 FF |
382 | }; |
383 | ||
384 | struct ath_chanctx_sched { | |
385 | bool beacon_pending; | |
d9092c98 | 386 | bool beacon_adjust; |
73fa2f26 | 387 | bool offchannel_pending; |
367b341e | 388 | bool wait_switch; |
d0975edd | 389 | bool force_noa_update; |
167bf96d | 390 | bool extend_absence; |
c6500ea2 | 391 | bool mgd_prepare_tx; |
748299f2 | 392 | enum ath_chanctx_state state; |
ec70abe1 | 393 | u8 beacon_miss; |
748299f2 FF |
394 | |
395 | u32 next_tbtt; | |
3ae07d39 FF |
396 | u32 switch_start_time; |
397 | unsigned int offchannel_duration; | |
748299f2 | 398 | unsigned int channel_switch_time; |
42eda115 FF |
399 | |
400 | /* backup, in case the hardware timer fails */ | |
401 | struct timer_list timer; | |
fbbcd146 FF |
402 | }; |
403 | ||
78b21949 FF |
404 | enum ath_offchannel_state { |
405 | ATH_OFFCHANNEL_IDLE, | |
406 | ATH_OFFCHANNEL_PROBE_SEND, | |
407 | ATH_OFFCHANNEL_PROBE_WAIT, | |
408 | ATH_OFFCHANNEL_SUSPEND, | |
405393cf FF |
409 | ATH_OFFCHANNEL_ROC_START, |
410 | ATH_OFFCHANNEL_ROC_WAIT, | |
411 | ATH_OFFCHANNEL_ROC_DONE, | |
78b21949 FF |
412 | }; |
413 | ||
d83520b7 JD |
414 | enum ath_roc_complete_reason { |
415 | ATH_ROC_COMPLETE_EXPIRE, | |
416 | ATH_ROC_COMPLETE_ABORT, | |
417 | ATH_ROC_COMPLETE_CANCEL, | |
418 | }; | |
419 | ||
78b21949 FF |
420 | struct ath_offchannel { |
421 | struct ath_chanctx chan; | |
422 | struct timer_list timer; | |
423 | struct cfg80211_scan_request *scan_req; | |
424 | struct ieee80211_vif *scan_vif; | |
425 | int scan_idx; | |
426 | enum ath_offchannel_state state; | |
405393cf FF |
427 | struct ieee80211_channel *roc_chan; |
428 | struct ieee80211_vif *roc_vif; | |
429 | int roc_duration; | |
ea6ff2de | 430 | int duration; |
78b21949 | 431 | }; |
5a8cbec7 | 432 | |
50f08edf THJ |
433 | static inline struct ath_atx_tid * |
434 | ath_node_to_tid(struct ath_node *an, u8 tidno) | |
435 | { | |
436 | struct ieee80211_sta *sta = an->sta; | |
437 | struct ieee80211_vif *vif = an->vif; | |
438 | struct ieee80211_txq *txq; | |
439 | ||
440 | BUG_ON(!vif); | |
441 | if (sta) | |
442 | txq = sta->txq[tidno % ARRAY_SIZE(sta->txq)]; | |
443 | else | |
444 | txq = vif->txq; | |
445 | ||
446 | return (struct ath_atx_tid *) txq->drv_priv; | |
447 | } | |
448 | ||
5a8cbec7 SM |
449 | #define case_rtn_string(val) case val: return #val |
450 | ||
c4dc0d04 RM |
451 | #define ath_for_each_chanctx(_sc, _ctx) \ |
452 | for (ctx = &sc->chanctx[0]; \ | |
453 | ctx <= &sc->chanctx[ARRAY_SIZE(sc->chanctx) - 1]; \ | |
454 | ctx++) | |
78b21949 | 455 | |
6e47fafb SM |
456 | void ath_chanctx_init(struct ath_softc *sc); |
457 | void ath_chanctx_set_channel(struct ath_softc *sc, struct ath_chanctx *ctx, | |
458 | struct cfg80211_chan_def *chandef); | |
459 | ||
460 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT | |
461 | ||
39305635 FF |
462 | static inline struct ath_chanctx * |
463 | ath_chanctx_get(struct ieee80211_chanctx_conf *ctx) | |
464 | { | |
465 | struct ath_chanctx **ptr = (void *) ctx->drv_priv; | |
466 | return *ptr; | |
467 | } | |
6e47fafb | 468 | |
499afacc SM |
469 | bool ath9k_is_chanctx_enabled(void); |
470 | void ath9k_fill_chanctx_ops(void); | |
705d0bf8 | 471 | void ath9k_init_channel_context(struct ath_softc *sc); |
e90e302a | 472 | void ath9k_offchannel_init(struct ath_softc *sc); |
ea22df29 | 473 | void ath9k_deinit_channel_context(struct ath_softc *sc); |
c7dd40c9 SM |
474 | int ath9k_init_p2p(struct ath_softc *sc); |
475 | void ath9k_deinit_p2p(struct ath_softc *sc); | |
476 | void ath9k_p2p_remove_vif(struct ath_softc *sc, | |
477 | struct ieee80211_vif *vif); | |
478 | void ath9k_p2p_beacon_sync(struct ath_softc *sc); | |
479 | void ath9k_p2p_bss_info_changed(struct ath_softc *sc, | |
480 | struct ieee80211_vif *vif); | |
11e39a4e SM |
481 | void ath9k_beacon_add_noa(struct ath_softc *sc, struct ath_vif *avp, |
482 | struct sk_buff *skb); | |
c7dd40c9 | 483 | void ath9k_p2p_ps_timer(void *priv); |
b3903153 | 484 | void ath9k_chanctx_wake_queues(struct ath_softc *sc, struct ath_chanctx *ctx); |
a064eaa1 | 485 | void ath9k_chanctx_stop_queues(struct ath_softc *sc, struct ath_chanctx *ctx); |
a09798f4 | 486 | void ath_chanctx_check_active(struct ath_softc *sc, struct ath_chanctx *ctx); |
e20a854e | 487 | |
a2b28601 | 488 | void ath_chanctx_beacon_recv_ev(struct ath_softc *sc, |
70b06dac SM |
489 | enum ath_chanctx_event ev); |
490 | void ath_chanctx_beacon_sent_ev(struct ath_softc *sc, | |
491 | enum ath_chanctx_event ev); | |
27babf9f SM |
492 | void ath_chanctx_event(struct ath_softc *sc, struct ieee80211_vif *vif, |
493 | enum ath_chanctx_event ev); | |
e20a854e | 494 | void ath_chanctx_set_next(struct ath_softc *sc, bool force); |
73b5ef0b SM |
495 | void ath_offchannel_next(struct ath_softc *sc); |
496 | void ath_scan_complete(struct ath_softc *sc, bool abort); | |
d83520b7 JD |
497 | void ath_roc_complete(struct ath_softc *sc, |
498 | enum ath_roc_complete_reason reason); | |
26103b8d | 499 | struct ath_chanctx* ath_is_go_chanctx_present(struct ath_softc *sc); |
6e47fafb | 500 | |
c7dd40c9 | 501 | #else |
6e47fafb | 502 | |
499afacc SM |
503 | static inline bool ath9k_is_chanctx_enabled(void) |
504 | { | |
505 | return false; | |
506 | } | |
507 | static inline void ath9k_fill_chanctx_ops(void) | |
508 | { | |
509 | } | |
705d0bf8 SM |
510 | static inline void ath9k_init_channel_context(struct ath_softc *sc) |
511 | { | |
512 | } | |
e90e302a SM |
513 | static inline void ath9k_offchannel_init(struct ath_softc *sc) |
514 | { | |
515 | } | |
ea22df29 SM |
516 | static inline void ath9k_deinit_channel_context(struct ath_softc *sc) |
517 | { | |
518 | } | |
a2b28601 | 519 | static inline void ath_chanctx_beacon_recv_ev(struct ath_softc *sc, |
70b06dac SM |
520 | enum ath_chanctx_event ev) |
521 | { | |
522 | } | |
523 | static inline void ath_chanctx_beacon_sent_ev(struct ath_softc *sc, | |
524 | enum ath_chanctx_event ev) | |
525 | { | |
526 | } | |
27babf9f SM |
527 | static inline void ath_chanctx_event(struct ath_softc *sc, |
528 | struct ieee80211_vif *vif, | |
529 | enum ath_chanctx_event ev) | |
530 | { | |
531 | } | |
c7dd40c9 SM |
532 | static inline int ath9k_init_p2p(struct ath_softc *sc) |
533 | { | |
534 | return 0; | |
535 | } | |
536 | static inline void ath9k_deinit_p2p(struct ath_softc *sc) | |
537 | { | |
538 | } | |
539 | static inline void ath9k_p2p_remove_vif(struct ath_softc *sc, | |
540 | struct ieee80211_vif *vif) | |
541 | { | |
542 | } | |
543 | static inline void ath9k_p2p_beacon_sync(struct ath_softc *sc) | |
544 | { | |
545 | } | |
546 | static inline void ath9k_p2p_bss_info_changed(struct ath_softc *sc, | |
547 | struct ieee80211_vif *vif) | |
548 | { | |
549 | } | |
11e39a4e SM |
550 | static inline void ath9k_beacon_add_noa(struct ath_softc *sc, struct ath_vif *avp, |
551 | struct sk_buff *skb) | |
552 | { | |
553 | } | |
c7dd40c9 SM |
554 | static inline void ath9k_p2p_ps_timer(struct ath_softc *sc) |
555 | { | |
556 | } | |
b3903153 SM |
557 | static inline void ath9k_chanctx_wake_queues(struct ath_softc *sc, |
558 | struct ath_chanctx *ctx) | |
0e08b5fb SM |
559 | { |
560 | } | |
a064eaa1 SM |
561 | static inline void ath9k_chanctx_stop_queues(struct ath_softc *sc, |
562 | struct ath_chanctx *ctx) | |
563 | { | |
564 | } | |
a09798f4 SM |
565 | static inline void ath_chanctx_check_active(struct ath_softc *sc, |
566 | struct ath_chanctx *ctx) | |
567 | { | |
568 | } | |
6e47fafb | 569 | |
c7dd40c9 SM |
570 | #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ |
571 | ||
5c4607eb THJ |
572 | static inline void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq) |
573 | { | |
574 | spin_lock_bh(&txq->axq_lock); | |
575 | } | |
576 | static inline void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq) | |
577 | { | |
578 | spin_unlock_bh(&txq->axq_lock); | |
579 | } | |
580 | ||
19ec477f | 581 | void ath_startrecv(struct ath_softc *sc); |
394cf0a1 | 582 | bool ath_stoprecv(struct ath_softc *sc); |
394cf0a1 S |
583 | u32 ath_calcrxfilter(struct ath_softc *sc); |
584 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
585 | void ath_rx_cleanup(struct ath_softc *sc); | |
b5c80475 | 586 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); |
394cf0a1 | 587 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); |
ef1b6cd9 | 588 | void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq); |
394cf0a1 | 589 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); |
1381559b FF |
590 | bool ath_drain_all_txq(struct ath_softc *sc); |
591 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq); | |
394cf0a1 S |
592 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); |
593 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
594 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
0453531e | 595 | void ath_txq_schedule_all(struct ath_softc *sc); |
394cf0a1 | 596 | int ath_tx_init(struct ath_softc *sc, int nbufs); |
394cf0a1 S |
597 | int ath_txq_update(struct ath_softc *sc, int qnum, |
598 | struct ath9k_tx_queue_info *q); | |
63fefa05 THJ |
599 | u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, |
600 | int width, int half_gi, bool shortPreamble); | |
aa5955c3 | 601 | void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop); |
ca14405e | 602 | void ath_assign_seq(struct ath_common *common, struct sk_buff *skb); |
c52f33d0 | 603 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 | 604 | struct ath_tx_control *txctl); |
59505c02 FF |
605 | void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
606 | struct sk_buff *skb); | |
394cf0a1 | 607 | void ath_tx_tasklet(struct ath_softc *sc); |
e5003249 | 608 | void ath_tx_edma_tasklet(struct ath_softc *sc); |
231c3a1f FF |
609 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
610 | u16 tid, u16 *ssn); | |
f83da965 | 611 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
394cf0a1 | 612 | |
5519541d | 613 | void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an); |
042ec453 JB |
614 | void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, |
615 | struct ath_node *an); | |
86a22acf FF |
616 | void ath9k_release_buffered_frames(struct ieee80211_hw *hw, |
617 | struct ieee80211_sta *sta, | |
618 | u16 tids, int nframes, | |
619 | enum ieee80211_frame_release_type reason, | |
620 | bool more_data); | |
50f08edf | 621 | void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue); |
5519541d | 622 | |
394cf0a1 | 623 | /********/ |
17d7904d | 624 | /* VIFs */ |
394cf0a1 | 625 | /********/ |
f078f209 | 626 | |
fdcf1bd4 SM |
627 | #define P2P_DEFAULT_CTWIN 10 |
628 | ||
17d7904d | 629 | struct ath_vif { |
fbbcd146 FF |
630 | struct list_head list; |
631 | ||
ca14405e SM |
632 | u16 seq_no; |
633 | ||
cb35582a | 634 | /* BSS info */ |
62ae1aef | 635 | u8 bssid[ETH_ALEN] __aligned(2); |
cb35582a SM |
636 | u16 aid; |
637 | bool assoc; | |
638 | ||
d463af4a | 639 | struct ieee80211_vif *vif; |
f89d1bc4 | 640 | struct ath_node mcast_node; |
394cf0a1 | 641 | int av_bslot; |
4ed96f04 | 642 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 | 643 | struct ath_buf *av_bcbuf; |
fbbcd146 | 644 | struct ath_chanctx *chanctx; |
d463af4a FF |
645 | |
646 | /* P2P Client */ | |
647 | struct ieee80211_noa_data noa; | |
3ae07d39 FF |
648 | |
649 | /* P2P GO */ | |
650 | u8 noa_index; | |
651 | u32 offchannel_start; | |
652 | u32 offchannel_duration; | |
7414863e | 653 | |
d0975edd SM |
654 | /* These are used for both periodic and one-shot */ |
655 | u32 noa_start; | |
656 | u32 noa_duration; | |
657 | bool periodic_noa; | |
0a019a58 | 658 | bool oneshot_noa; |
f078f209 LR |
659 | }; |
660 | ||
7b6ef998 SM |
661 | struct ath9k_vif_iter_data { |
662 | u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */ | |
663 | u8 mask[ETH_ALEN]; /* bssid mask */ | |
664 | bool has_hw_macaddr; | |
9a9c4fbc RM |
665 | u8 slottime; |
666 | bool beacons; | |
7b6ef998 SM |
667 | |
668 | int naps; /* number of AP vifs */ | |
669 | int nmeshes; /* number of mesh vifs */ | |
670 | int nstations; /* number of station vifs */ | |
671 | int nwds; /* number of WDS vifs */ | |
672 | int nadhocs; /* number of adhoc vifs */ | |
862a336c | 673 | int nocbs; /* number of OCB vifs */ |
cfda2d8e BB |
674 | int nbcnvifs; /* number of beaconing vifs */ |
675 | struct ieee80211_vif *primary_beacon_vif; | |
9a9c4fbc | 676 | struct ieee80211_vif *primary_sta; |
7b6ef998 SM |
677 | }; |
678 | ||
9a9c4fbc RM |
679 | void ath9k_calculate_iter_data(struct ath_softc *sc, |
680 | struct ath_chanctx *ctx, | |
7b6ef998 | 681 | struct ath9k_vif_iter_data *iter_data); |
9a9c4fbc RM |
682 | void ath9k_calculate_summary_state(struct ath_softc *sc, |
683 | struct ath_chanctx *ctx); | |
283dd119 | 684 | void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif); |
7b6ef998 | 685 | |
394cf0a1 S |
686 | /*******************/ |
687 | /* Beacon Handling */ | |
688 | /*******************/ | |
f078f209 | 689 | |
394cf0a1 S |
690 | /* |
691 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
692 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
693 | * number of beacon intervals, the game's up. | |
694 | */ | |
c944daf4 | 695 | #define BSTUCK_THRESH 9 |
689e756f | 696 | #define ATH_BCBUF 8 |
394cf0a1 S |
697 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
698 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
394cf0a1 | 699 | |
7b6ef998 SM |
700 | #define TSF_TO_TU(_h,_l) \ |
701 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
702 | ||
394cf0a1 S |
703 | struct ath_beacon { |
704 | enum { | |
705 | OK, /* no change needed */ | |
706 | UPDATE, /* update pending */ | |
707 | COMMIT /* beacon sent, commit change */ | |
708 | } updateslot; /* slot time update fsm */ | |
709 | ||
710 | u32 beaconq; | |
711 | u32 bmisscnt; | |
2c3db3d5 | 712 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
394cf0a1 S |
713 | int slottime; |
714 | int slotupdate; | |
394cf0a1 S |
715 | struct ath_descdma bdma; |
716 | struct ath_txq *cabq; | |
717 | struct list_head bbuf; | |
ba4903f9 FF |
718 | |
719 | bool tx_processed; | |
720 | bool tx_last; | |
394cf0a1 S |
721 | }; |
722 | ||
fb6e252f | 723 | void ath9k_beacon_tasklet(unsigned long data); |
cfda2d8e BB |
724 | void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *main_vif, |
725 | bool beacons); | |
130ef6e9 SM |
726 | void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif); |
727 | void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif); | |
cfda2d8e | 728 | void ath9k_beacon_ensure_primary_slot(struct ath_softc *sc); |
ef4ad633 | 729 | void ath9k_set_beacon(struct ath_softc *sc); |
4effc6fd MK |
730 | bool ath9k_csa_is_finished(struct ath_softc *sc, struct ieee80211_vif *vif); |
731 | void ath9k_csa_update(struct ath_softc *sc); | |
394cf0a1 | 732 | |
ef1b6cd9 SM |
733 | /*******************/ |
734 | /* Link Monitoring */ | |
735 | /*******************/ | |
f078f209 | 736 | |
20977d3e S |
737 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
738 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
e36b27af LR |
739 | #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ |
740 | #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ | |
6044474e | 741 | #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ |
20977d3e S |
742 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ |
743 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
7b6ef998 SM |
744 | #define ATH_ANI_MAX_SKIP_COUNT 10 |
745 | #define ATH_PAPRD_TIMEOUT 100 /* msecs */ | |
746 | #define ATH_PLL_WORK_INTERVAL 100 | |
ca369eb4 | 747 | |
d63ffc45 | 748 | void ath_hw_check_work(struct work_struct *work); |
236de514 | 749 | void ath_reset_work(struct work_struct *work); |
415ec61b | 750 | bool ath_hw_check(struct ath_softc *sc); |
9eab61c2 | 751 | void ath_hw_pll_work(struct work_struct *work); |
9f42c2b6 | 752 | void ath_paprd_calibrate(struct work_struct *work); |
7ac76764 | 753 | void ath_ani_calibrate(struct timer_list *t); |
da0d45f7 SM |
754 | void ath_start_ani(struct ath_softc *sc); |
755 | void ath_stop_ani(struct ath_softc *sc); | |
756 | void ath_check_ani(struct ath_softc *sc); | |
ef1b6cd9 SM |
757 | int ath_update_survey_stats(struct ath_softc *sc); |
758 | void ath_update_survey_nf(struct ath_softc *sc, int channel); | |
124b979b | 759 | void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type); |
7ac76764 | 760 | void ath_ps_full_sleep(struct timer_list *t); |
e2d389b5 | 761 | void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop, |
25f3bc7d | 762 | bool sw_pending, bool timeout_override); |
55624204 | 763 | |
0fca65c1 S |
764 | /**********/ |
765 | /* BTCOEX */ | |
766 | /**********/ | |
767 | ||
ac46ba43 SM |
768 | #define ATH_DUMP_BTCOEX(_s, _val) \ |
769 | do { \ | |
5e88ba62 ZK |
770 | len += scnprintf(buf + len, size - len, \ |
771 | "%20s : %10d\n", _s, (_val)); \ | |
ac46ba43 SM |
772 | } while (0) |
773 | ||
e6930c4b SM |
774 | enum bt_op_flags { |
775 | BT_OP_PRIORITY_DETECTED, | |
776 | BT_OP_SCAN, | |
777 | }; | |
778 | ||
2e20250a | 779 | struct ath_btcoex { |
2e20250a LR |
780 | spinlock_t btcoex_lock; |
781 | struct timer_list period_timer; /* Timer for BT period */ | |
168c6f89 | 782 | struct timer_list no_stomp_timer; |
2e20250a LR |
783 | u32 bt_priority_cnt; |
784 | unsigned long bt_priority_time; | |
e6930c4b | 785 | unsigned long op_flags; |
e08a6ace | 786 | int bt_stomp_type; /* Types of BT stomping */ |
168c6f89 | 787 | u32 btcoex_no_stomp; /* in msec */ |
94ae77ea | 788 | u32 btcoex_period; /* in msec */ |
168c6f89 | 789 | u32 btscan_no_stomp; /* in msec */ |
7dc181c2 | 790 | u32 duty_cycle; |
6995fb80 | 791 | u32 bt_wait_time; |
e82cb03f | 792 | int rssi_count; |
7dc181c2 | 793 | struct ath_mci_profile mci; |
2884561a | 794 | u8 stomp_audio; |
2e20250a LR |
795 | }; |
796 | ||
4daa7760 | 797 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
5908120f SM |
798 | int ath9k_init_btcoex(struct ath_softc *sc); |
799 | void ath9k_deinit_btcoex(struct ath_softc *sc); | |
df198b17 SM |
800 | void ath9k_start_btcoex(struct ath_softc *sc); |
801 | void ath9k_stop_btcoex(struct ath_softc *sc); | |
0fca65c1 S |
802 | void ath9k_btcoex_timer_resume(struct ath_softc *sc); |
803 | void ath9k_btcoex_timer_pause(struct ath_softc *sc); | |
56ca0dba | 804 | void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status); |
c0ac53fa | 805 | u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen); |
08d4df41 | 806 | void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc); |
ac46ba43 | 807 | int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size); |
4daa7760 SM |
808 | #else |
809 | static inline int ath9k_init_btcoex(struct ath_softc *sc) | |
810 | { | |
811 | return 0; | |
812 | } | |
813 | static inline void ath9k_deinit_btcoex(struct ath_softc *sc) | |
814 | { | |
815 | } | |
816 | static inline void ath9k_start_btcoex(struct ath_softc *sc) | |
817 | { | |
818 | } | |
819 | static inline void ath9k_stop_btcoex(struct ath_softc *sc) | |
820 | { | |
821 | } | |
822 | static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, | |
823 | u32 status) | |
824 | { | |
825 | } | |
826 | static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, | |
827 | u32 max_4ms_framelen) | |
828 | { | |
829 | return 0; | |
830 | } | |
08d4df41 RM |
831 | static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc) |
832 | { | |
833 | } | |
ac46ba43 | 834 | static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size) |
4df50ca8 RM |
835 | { |
836 | return 0; | |
837 | } | |
4daa7760 | 838 | #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ |
0fca65c1 | 839 | |
394cf0a1 S |
840 | /********************/ |
841 | /* LED Control */ | |
842 | /********************/ | |
f078f209 | 843 | |
08fc5c1b VN |
844 | #define ATH_LED_PIN_DEF 1 |
845 | #define ATH_LED_PIN_9287 8 | |
353e5019 | 846 | #define ATH_LED_PIN_9300 10 |
15178535 | 847 | #define ATH_LED_PIN_9485 6 |
1a68abb0 | 848 | #define ATH_LED_PIN_9462 4 |
f078f209 | 849 | |
0cf55c21 | 850 | #ifdef CONFIG_MAC80211_LEDS |
0fca65c1 S |
851 | void ath_init_leds(struct ath_softc *sc); |
852 | void ath_deinit_leds(struct ath_softc *sc); | |
0cf55c21 FF |
853 | #else |
854 | static inline void ath_init_leds(struct ath_softc *sc) | |
855 | { | |
856 | } | |
857 | ||
858 | static inline void ath_deinit_leds(struct ath_softc *sc) | |
8f176a3a RM |
859 | { |
860 | } | |
0cf55c21 FF |
861 | #endif |
862 | ||
e60001e7 SM |
863 | /************************/ |
864 | /* Wake on Wireless LAN */ | |
865 | /************************/ | |
866 | ||
867 | #ifdef CONFIG_ATH9K_WOW | |
babaa80a | 868 | void ath9k_init_wow(struct ieee80211_hw *hw); |
661d2581 | 869 | void ath9k_deinit_wow(struct ieee80211_hw *hw); |
e60001e7 SM |
870 | int ath9k_suspend(struct ieee80211_hw *hw, |
871 | struct cfg80211_wowlan *wowlan); | |
872 | int ath9k_resume(struct ieee80211_hw *hw); | |
873 | void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled); | |
874 | #else | |
babaa80a SM |
875 | static inline void ath9k_init_wow(struct ieee80211_hw *hw) |
876 | { | |
877 | } | |
661d2581 SM |
878 | static inline void ath9k_deinit_wow(struct ieee80211_hw *hw) |
879 | { | |
880 | } | |
e60001e7 SM |
881 | static inline int ath9k_suspend(struct ieee80211_hw *hw, |
882 | struct cfg80211_wowlan *wowlan) | |
883 | { | |
884 | return 0; | |
885 | } | |
886 | static inline int ath9k_resume(struct ieee80211_hw *hw) | |
887 | { | |
888 | return 0; | |
889 | } | |
890 | static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) | |
891 | { | |
892 | } | |
893 | #endif /* CONFIG_ATH9K_WOW */ | |
894 | ||
8da07830 | 895 | /*******************************/ |
102885a5 | 896 | /* Antenna diversity/combining */ |
8da07830 SM |
897 | /*******************************/ |
898 | ||
102885a5 VT |
899 | #define ATH_ANT_RX_CURRENT_SHIFT 4 |
900 | #define ATH_ANT_RX_MAIN_SHIFT 2 | |
901 | #define ATH_ANT_RX_MASK 0x3 | |
902 | ||
903 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 | |
904 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 | |
905 | #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 | |
906 | #define ATH_ANT_DIV_COMB_INIT_COUNT 95 | |
907 | #define ATH_ANT_DIV_COMB_MAX_COUNT 100 | |
908 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 | |
909 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 | |
3afa6b4f SM |
910 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50 |
911 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50 | |
102885a5 | 912 | |
102885a5 VT |
913 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 |
914 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 | |
915 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 | |
916 | ||
102885a5 VT |
917 | struct ath_ant_comb { |
918 | u16 count; | |
919 | u16 total_pkt_count; | |
920 | bool scan; | |
921 | bool scan_not_start; | |
922 | int main_total_rssi; | |
923 | int alt_total_rssi; | |
924 | int alt_recv_cnt; | |
925 | int main_recv_cnt; | |
926 | int rssi_lna1; | |
927 | int rssi_lna2; | |
928 | int rssi_add; | |
929 | int rssi_sub; | |
930 | int rssi_first; | |
931 | int rssi_second; | |
932 | int rssi_third; | |
3afa6b4f SM |
933 | int ant_ratio; |
934 | int ant_ratio2; | |
102885a5 VT |
935 | bool alt_good; |
936 | int quick_scan_cnt; | |
3fbaf4c5 | 937 | enum ath9k_ant_div_comb_lna_conf main_conf; |
102885a5 VT |
938 | enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; |
939 | enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; | |
102885a5 VT |
940 | bool first_ratio; |
941 | bool second_ratio; | |
942 | unsigned long scan_start_time; | |
3afa6b4f SM |
943 | |
944 | /* | |
945 | * Card-specific config values. | |
946 | */ | |
947 | int low_rssi_thresh; | |
948 | int fast_div_bias; | |
102885a5 VT |
949 | }; |
950 | ||
8da07830 | 951 | void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs); |
8da07830 | 952 | |
394cf0a1 S |
953 | /********************/ |
954 | /* Main driver core */ | |
955 | /********************/ | |
f078f209 | 956 | |
2d22c7dd SM |
957 | #define ATH9K_PCI_CUS198 0x0001 |
958 | #define ATH9K_PCI_CUS230 0x0002 | |
959 | #define ATH9K_PCI_CUS217 0x0004 | |
960 | #define ATH9K_PCI_CUS252 0x0008 | |
961 | #define ATH9K_PCI_WOW 0x0010 | |
962 | #define ATH9K_PCI_BT_ANT_DIV 0x0020 | |
963 | #define ATH9K_PCI_D3_L1_WAR 0x0040 | |
964 | #define ATH9K_PCI_AR9565_1ANT 0x0080 | |
965 | #define ATH9K_PCI_AR9565_2ANT 0x0100 | |
966 | #define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200 | |
4dd35640 | 967 | #define ATH9K_PCI_KILLER 0x0400 |
aeeb2065 | 968 | #define ATH9K_PCI_LED_ACT_HI 0x0800 |
9b60b64b | 969 | |
394cf0a1 S |
970 | /* |
971 | * Default cache line size, in bytes. | |
972 | * Used when PCI device not fully initialized by bootrom/BIOS | |
973 | */ | |
974 | #define DEFAULT_CACHELINE 32 | |
394cf0a1 | 975 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ |
394cf0a1 | 976 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
071aa9a8 | 977 | #define MAX_GTT_CNT 5 |
394cf0a1 | 978 | |
1b04b930 S |
979 | /* Powersave flags */ |
980 | #define PS_WAIT_FOR_BEACON BIT(0) | |
981 | #define PS_WAIT_FOR_CAB BIT(1) | |
982 | #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) | |
983 | #define PS_WAIT_FOR_TX_ACK BIT(3) | |
984 | #define PS_BEACON_SYNC BIT(4) | |
424749c7 | 985 | #define PS_WAIT_FOR_ANI BIT(5) |
394cf0a1 | 986 | |
fbbcd146 FF |
987 | #define ATH9K_NUM_CHANCTX 2 /* supports 2 operating channels */ |
988 | ||
63fefa05 THJ |
989 | #define AIRTIME_USE_TX BIT(0) |
990 | #define AIRTIME_USE_RX BIT(1) | |
991 | #define AIRTIME_USE_NEW_QUEUES BIT(2) | |
992 | #define AIRTIME_ACTIVE(flags) (!!(flags & (AIRTIME_USE_TX|AIRTIME_USE_RX))) | |
993 | ||
394cf0a1 S |
994 | struct ath_softc { |
995 | struct ieee80211_hw *hw; | |
996 | struct device *dev; | |
c52f33d0 | 997 | |
3430098a FF |
998 | struct survey_info *cur_survey; |
999 | struct survey_info survey[ATH9K_NUM_CHANNELS]; | |
0e2dedf9 | 1000 | |
3a5e969b | 1001 | spinlock_t intr_lock; |
394cf0a1 S |
1002 | struct tasklet_struct intr_tq; |
1003 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 1004 | struct ath_hw *sc_ah; |
394cf0a1 S |
1005 | void __iomem *mem; |
1006 | int irq; | |
2d6a5e95 | 1007 | spinlock_t sc_serial_rw; |
04717ccd | 1008 | spinlock_t sc_pm_lock; |
4bdd1e97 | 1009 | spinlock_t sc_pcu_lock; |
394cf0a1 | 1010 | struct mutex mutex; |
9f42c2b6 | 1011 | struct work_struct paprd_work; |
236de514 | 1012 | struct work_struct hw_reset_work; |
9f42c2b6 | 1013 | struct completion paprd_complete; |
10e23181 | 1014 | wait_queue_head_t tx_wait; |
394cf0a1 | 1015 | |
c7dd40c9 | 1016 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
fb02e95c | 1017 | struct work_struct chanctx_work; |
d463af4a FF |
1018 | struct ath_gen_timer *p2p_ps_timer; |
1019 | struct ath_vif *p2p_ps_vif; | |
70b06dac | 1020 | struct ath_chanctx_sched sched; |
77843167 | 1021 | struct ath_offchannel offchannel; |
fb02e95c | 1022 | struct ath_chanctx *next_chan; |
c6500ea2 | 1023 | struct completion go_beacon; |
02edab5b | 1024 | struct timespec last_event_time; |
c7dd40c9 | 1025 | #endif |
d463af4a | 1026 | |
9b60b64b | 1027 | unsigned long driver_data; |
cb8d61de | 1028 | |
071aa9a8 | 1029 | u8 gtt_cnt; |
17d7904d | 1030 | u32 intrstatus; |
1b04b930 | 1031 | u16 ps_flags; /* PS_* */ |
96148326 | 1032 | bool ps_enabled; |
1dbfd9d4 | 1033 | bool ps_idle; |
4801416c | 1034 | short nbcnvifs; |
709ade9e | 1035 | unsigned long ps_usecount; |
394cf0a1 | 1036 | |
63fefa05 THJ |
1037 | u16 airtime_flags; /* AIRTIME_* */ |
1038 | ||
394cf0a1 S |
1039 | struct ath_rx rx; |
1040 | struct ath_tx tx; | |
1041 | struct ath_beacon beacon; | |
394cf0a1 | 1042 | |
bff11766 | 1043 | struct cfg80211_chan_def cur_chandef; |
fbbcd146 FF |
1044 | struct ath_chanctx chanctx[ATH9K_NUM_CHANCTX]; |
1045 | struct ath_chanctx *cur_chan; | |
bff11766 | 1046 | spinlock_t chan_lock; |
fbbcd146 | 1047 | |
0cf55c21 FF |
1048 | #ifdef CONFIG_MAC80211_LEDS |
1049 | bool led_registered; | |
1050 | char led_name[32]; | |
1051 | struct led_classdev led_cdev; | |
1052 | #endif | |
394cf0a1 | 1053 | |
a830df07 | 1054 | #ifdef CONFIG_ATH9K_DEBUGFS |
17d7904d | 1055 | struct ath9k_debug debug; |
394cf0a1 | 1056 | #endif |
d63ffc45 | 1057 | struct delayed_work hw_check_work; |
181fb18d | 1058 | struct delayed_work hw_pll_work; |
bf3dac5a | 1059 | struct timer_list sleep_timer; |
4daa7760 SM |
1060 | |
1061 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT | |
2e20250a | 1062 | struct ath_btcoex btcoex; |
9e25365f | 1063 | struct ath_mci_coex mci_coex; |
3c7992e3 | 1064 | struct work_struct mci_work; |
4daa7760 | 1065 | #endif |
5088c2f1 VT |
1066 | |
1067 | struct ath_descdma txsdma; | |
102885a5 VT |
1068 | |
1069 | struct ath_ant_comb ant_comb; | |
43c35284 | 1070 | u8 ant_tx, ant_rx; |
8e92d3f2 | 1071 | struct dfs_pattern_detector *dfs_detector; |
3f3c09f3 | 1072 | u64 dfs_prev_pulse_ts; |
b11e640a | 1073 | u32 wow_enabled; |
21af25d0 | 1074 | |
911ea79f | 1075 | struct ath_spec_scan_priv spec_priv; |
01c78533 | 1076 | |
d976ee0a | 1077 | struct ieee80211_vif *tx99_vif; |
89f927af LR |
1078 | struct sk_buff *tx99_skb; |
1079 | bool tx99_state; | |
1080 | s16 tx99_power; | |
1081 | ||
e60001e7 | 1082 | #ifdef CONFIG_ATH9K_WOW |
01c78533 | 1083 | u32 wow_intr_before_sleep; |
8b861715 | 1084 | bool force_wow; |
01c78533 | 1085 | #endif |
ed14dc0a MP |
1086 | |
1087 | #ifdef CONFIG_ATH9K_HWRNG | |
1088 | u32 rng_last; | |
1089 | struct task_struct *rng_task; | |
1090 | #endif | |
394cf0a1 S |
1091 | }; |
1092 | ||
ef6b19e4 SM |
1093 | /********/ |
1094 | /* TX99 */ | |
1095 | /********/ | |
1096 | ||
1097 | #ifdef CONFIG_ATH9K_TX99 | |
1098 | void ath9k_tx99_init_debug(struct ath_softc *sc); | |
89f927af LR |
1099 | int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, |
1100 | struct ath_tx_control *txctl); | |
ef6b19e4 SM |
1101 | #else |
1102 | static inline void ath9k_tx99_init_debug(struct ath_softc *sc) | |
1103 | { | |
1104 | } | |
1105 | static inline int ath9k_tx99_send(struct ath_softc *sc, | |
1106 | struct sk_buff *skb, | |
1107 | struct ath_tx_control *txctl) | |
1108 | { | |
1109 | return 0; | |
1110 | } | |
1111 | #endif /* CONFIG_ATH9K_TX99 */ | |
89f927af | 1112 | |
ed14dc0a MP |
1113 | /***************************/ |
1114 | /* Random Number Generator */ | |
1115 | /***************************/ | |
1116 | #ifdef CONFIG_ATH9K_HWRNG | |
1117 | void ath9k_rng_start(struct ath_softc *sc); | |
1118 | void ath9k_rng_stop(struct ath_softc *sc); | |
1119 | #else | |
1120 | static inline void ath9k_rng_start(struct ath_softc *sc) | |
1121 | { | |
1122 | } | |
1123 | ||
1124 | static inline void ath9k_rng_stop(struct ath_softc *sc) | |
1125 | { | |
1126 | } | |
1127 | #endif | |
1128 | ||
5bb12791 | 1129 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
394cf0a1 | 1130 | { |
5bb12791 | 1131 | common->bus_ops->read_cachesize(common, csz); |
394cf0a1 S |
1132 | } |
1133 | ||
7b6ef998 SM |
1134 | void ath9k_tasklet(unsigned long data); |
1135 | int ath_cabq_update(struct ath_softc *); | |
313eb87f | 1136 | u8 ath9k_parse_mpdudensity(u8 mpdudensity); |
394cf0a1 | 1137 | irqreturn_t ath_isr(int irq, void *dev); |
5555c955 | 1138 | int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan); |
e60001e7 SM |
1139 | void ath_cancel_work(struct ath_softc *sc); |
1140 | void ath_restart_work(struct ath_softc *sc); | |
eb93e891 | 1141 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
5bb12791 | 1142 | const struct ath_bus_ops *bus_ops); |
285f2dda | 1143 | void ath9k_deinit_device(struct ath_softc *sc); |
43c35284 | 1144 | void ath9k_reload_chainmask_settings(struct ath_softc *sc); |
7b6ef998 SM |
1145 | u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate); |
1146 | void ath_start_rfkill_poll(struct ath_softc *sc); | |
1147 | void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); | |
1148 | void ath9k_ps_wakeup(struct ath_softc *sc); | |
1149 | void ath9k_ps_restore(struct ath_softc *sc); | |
68a89116 | 1150 | |
8e26a030 | 1151 | #ifdef CONFIG_ATH9K_PCI |
394cf0a1 S |
1152 | int ath_pci_init(void); |
1153 | void ath_pci_exit(void); | |
1154 | #else | |
1155 | static inline int ath_pci_init(void) { return 0; }; | |
1156 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 1157 | #endif |
f1dc5600 | 1158 | |
8e26a030 | 1159 | #ifdef CONFIG_ATH9K_AHB |
394cf0a1 S |
1160 | int ath_ahb_init(void); |
1161 | void ath_ahb_exit(void); | |
1162 | #else | |
1163 | static inline int ath_ahb_init(void) { return 0; }; | |
1164 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 1165 | #endif |
394cf0a1 | 1166 | |
394cf0a1 | 1167 | #endif /* ATH9K_H */ |