[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / ath / ath9k / calib.c

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include "hw.h"
#include "hw-ops.h"
#include <linux/export.h>

/* Common calibration code */


static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
{
	int16_t nfval;
	int16_t sort[ATH9K_NF_CAL_HIST_MAX];
	int i, j;

	for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
		sort[i] = nfCalBuffer[i];

	for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
		for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
			if (sort[j] > sort[j - 1]) {
				nfval = sort[j];
				sort[j] = sort[j - 1];
				sort[j - 1] = nfval;
			}
		}
	}
	nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];

	return nfval;
}

static struct ath_nf_limits *ath9k_hw_get_nf_limits(struct ath_hw *ah,
						    struct ath9k_channel *chan)
{
	struct ath_nf_limits *limit;

	if (!chan || IS_CHAN_2GHZ(chan))
		limit = &ah->nf_2g;
	else
		limit = &ah->nf_5g;

	return limit;
}

static s16 ath9k_hw_get_default_nf(struct ath_hw *ah,
				   struct ath9k_channel *chan)
{
	return ath9k_hw_get_nf_limits(ah, chan)->nominal;
}

s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan,
			   s16 nf)
{
	s8 noise = ATH_DEFAULT_NOISE_FLOOR;

	if (nf) {
		s8 delta = nf - ATH9K_NF_CAL_NOISE_THRESH -
			   ath9k_hw_get_default_nf(ah, chan);
		if (delta > 0)
			noise += delta;
	}
	return noise;
}
EXPORT_SYMBOL(ath9k_hw_getchan_noise);

static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
					      struct ath9k_hw_cal_data *cal,
					      int16_t *nfarray)
{
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath_nf_limits *limit;
	struct ath9k_nfcal_hist *h;
	bool high_nf_mid = false;
	u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
	int i;

	h = cal->nfCalHist;
	limit = ath9k_hw_get_nf_limits(ah, ah->curchan);

	for (i = 0; i < NUM_NF_READINGS; i++) {
		if (!(chainmask & (1 << i)) ||
		    ((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(ah->curchan)))
			continue;

		h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];

		if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
			h[i].currIndex = 0;

		if (h[i].invalidNFcount > 0) {
			h[i].invalidNFcount--;
			h[i].privNF = nfarray[i];
		} else {
			h[i].privNF =
				ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
		}

		if (!h[i].privNF)
			continue;

		if (h[i].privNF > limit->max) {
			high_nf_mid = true;

			ath_dbg(common, CALIBRATE,
				"NFmid[%d] (%d) > MAX (%d), %s\n",
				i, h[i].privNF, limit->max,
				(test_bit(NFCAL_INTF, &cal->cal_flags) ?
				 "not corrected (due to interference)" :
				 "correcting to MAX"));

			/*
			 * Normally we limit the average noise floor by the
			 * hardware specific maximum here. However if we have
			 * encountered stuck beacons because of interference,
			 * we bypass this limit here in order to better deal
			 * with our environment.
			 */
			if (!test_bit(NFCAL_INTF, &cal->cal_flags))
				h[i].privNF = limit->max;
		}
	}

	/*
	 * If the noise floor seems normal for all chains, assume that
	 * there is no significant interference in the environment anymore.
	 * Re-enable the enforcement of the NF maximum again.
	 */
	if (!high_nf_mid)
		clear_bit(NFCAL_INTF, &cal->cal_flags);
}

static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
				   enum nl80211_band band,
				   int16_t *nft)
{
	switch (band) {
	case NL80211_BAND_5GHZ:
		*nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
		break;
	case NL80211_BAND_2GHZ:
		*nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
		break;
	default:
		BUG_ON(1);
		return false;
	}

	return true;
}

void ath9k_hw_reset_calibration(struct ath_hw *ah,
				struct ath9k_cal_list *currCal)
{
	int i;

	ath9k_hw_setup_calibration(ah, currCal);

	currCal->calState = CAL_RUNNING;

	for (i = 0; i < AR5416_MAX_CHAINS; i++) {
		ah->meas0.sign[i] = 0;
		ah->meas1.sign[i] = 0;
		ah->meas2.sign[i] = 0;
		ah->meas3.sign[i] = 0;
	}

	ah->cal_samples = 0;
}

/* This is done for the currently configured channel */
bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
{
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath9k_cal_list *currCal = ah->cal_list_curr;

	if (!ah->caldata)
		return true;

	if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
		return true;

	if (currCal == NULL)
		return true;

	if (currCal->calState != CAL_DONE) {
		ath_dbg(common, CALIBRATE, "Calibration state incorrect, %d\n",
			currCal->calState);
		return true;
	}

	if (!(ah->supp_cals & currCal->calData->calType))
		return true;

	ath_dbg(common, CALIBRATE, "Resetting Cal %d state for channel %u\n",
		currCal->calData->calType, ah->curchan->chan->center_freq);

	ah->caldata->CalValid &= ~currCal->calData->calType;
	currCal->calState = CAL_WAITING;

	return false;
}
EXPORT_SYMBOL(ath9k_hw_reset_calvalid);

void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update)
{
	if (ah->caldata)
		set_bit(NFCAL_PENDING, &ah->caldata->cal_flags);

	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
		    AR_PHY_AGC_CONTROL_ENABLE_NF);

	if (update)
		REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
		    AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
	else
		REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
		    AR_PHY_AGC_CONTROL_NO_UPDATE_NF);

	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
}

int ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
{
	struct ath9k_nfcal_hist *h = NULL;
	unsigned i, j;
	u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
	struct ath_common *common = ath9k_hw_common(ah);
	s16 default_nf = ath9k_hw_get_default_nf(ah, chan);
	u32 bb_agc_ctl = REG_READ(ah, AR_PHY_AGC_CONTROL);

	if (ah->caldata)
		h = ah->caldata->nfCalHist;

	ENABLE_REG_RMW_BUFFER(ah);
	for (i = 0; i < NUM_NF_READINGS; i++) {
		if (chainmask & (1 << i)) {
			s16 nfval;

			if ((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(chan))
				continue;

			if (h)
				nfval = h[i].privNF;
			else
				nfval = default_nf;

			REG_RMW(ah, ah->nf_regs[i],
				(((u32) nfval << 1) & 0x1ff), 0x1ff);
		}
	}

	/*
	 * stop NF cal if ongoing to ensure NF load completes immediately
	 * (or after end rx/tx frame if ongoing)
	 */
	if (bb_agc_ctl & AR_PHY_AGC_CONTROL_NF) {
		REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
		REG_RMW_BUFFER_FLUSH(ah);
		ENABLE_REG_RMW_BUFFER(ah);
	}

	/*
	 * Load software filtered NF value into baseband internal minCCApwr
	 * variable.
	 */
	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
		    AR_PHY_AGC_CONTROL_ENABLE_NF);
	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
		    AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
	REG_RMW_BUFFER_FLUSH(ah);

	/*
	 * Wait for load to complete, should be fast, a few 10s of us.
	 * The max delay was changed from an original 250us to 22.2 msec.
	 * This would increase timeout to the longest possible frame
	 * (11n max length 22.1 msec)
	 */
	for (j = 0; j < 22200; j++) {
		if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
			      AR_PHY_AGC_CONTROL_NF) == 0)
			break;
		udelay(10);
	}

	/*
	 * Restart NF so it can continue.
	 */
	if (bb_agc_ctl & AR_PHY_AGC_CONTROL_NF) {
		ENABLE_REG_RMW_BUFFER(ah);
		if (bb_agc_ctl & AR_PHY_AGC_CONTROL_ENABLE_NF)
			REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
				    AR_PHY_AGC_CONTROL_ENABLE_NF);
		if (bb_agc_ctl & AR_PHY_AGC_CONTROL_NO_UPDATE_NF)
			REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
				    AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
		REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
		REG_RMW_BUFFER_FLUSH(ah);
	}

	/*
	 * We timed out waiting for the noisefloor to load, probably due to an
	 * in-progress rx. Simply return here and allow the load plenty of time
	 * to complete before the next calibration interval.  We need to avoid
	 * trying to load -50 (which happens below) while the previous load is
	 * still in progress as this can cause rx deafness. Instead by returning
	 * here, the baseband nf cal will just be capped by our present
	 * noisefloor until the next calibration timer.
	 */
	if (j == 22200) {
		ath_dbg(common, ANY,
			"Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
			REG_READ(ah, AR_PHY_AGC_CONTROL));
		return -ETIMEDOUT;
	}

	/*
	 * Restore maxCCAPower register parameter again so that we're not capped
	 * by the median we just loaded.  This will be initial (and max) value
	 * of next noise floor calibration the baseband does.
	 */
	ENABLE_REG_RMW_BUFFER(ah);
	for (i = 0; i < NUM_NF_READINGS; i++) {
		if (chainmask & (1 << i)) {
			if ((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(chan))
				continue;

			REG_RMW(ah, ah->nf_regs[i],
					(((u32) (-50) << 1) & 0x1ff), 0x1ff);
		}
	}
	REG_RMW_BUFFER_FLUSH(ah);

	return 0;
}


static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
{
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath_nf_limits *limit;
	int i;

	if (IS_CHAN_2GHZ(ah->curchan))
		limit = &ah->nf_2g;
	else
		limit = &ah->nf_5g;

	for (i = 0; i < NUM_NF_READINGS; i++) {
		if (!nf[i])
			continue;

		ath_dbg(common, CALIBRATE,
			"NF calibrated [%s] [chain %d] is %d\n",
			(i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);

		if (nf[i] > limit->max) {
			ath_dbg(common, CALIBRATE,
				"NF[%d] (%d) > MAX (%d), correcting to MAX\n",
				i, nf[i], limit->max);
			nf[i] = limit->max;
		} else if (nf[i] < limit->min) {
			ath_dbg(common, CALIBRATE,
				"NF[%d] (%d) < MIN (%d), correcting to NOM\n",
				i, nf[i], limit->min);
			nf[i] = limit->nominal;
		}
	}
}

bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
{
	struct ath_common *common = ath9k_hw_common(ah);
	int16_t nf, nfThresh;
	int16_t nfarray[NUM_NF_READINGS] = { 0 };
	struct ath9k_nfcal_hist *h;
	struct ieee80211_channel *c = chan->chan;
	struct ath9k_hw_cal_data *caldata = ah->caldata;

	if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
		ath_dbg(common, CALIBRATE,
			"NF did not complete in calibration window\n");
		return false;
	}

	ath9k_hw_do_getnf(ah, nfarray);
	ath9k_hw_nf_sanitize(ah, nfarray);
	nf = nfarray[0];
	if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
	    && nf > nfThresh) {
		ath_dbg(common, CALIBRATE,
			"noise floor failed detected; detected %d, threshold %d\n",
			nf, nfThresh);
	}

	if (!caldata) {
		chan->noisefloor = nf;
		return false;
	}

	h = caldata->nfCalHist;
	clear_bit(NFCAL_PENDING, &caldata->cal_flags);
	ath9k_hw_update_nfcal_hist_buffer(ah, caldata, nfarray);
	chan->noisefloor = h[0].privNF;
	ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
	return true;
}
EXPORT_SYMBOL(ath9k_hw_getnf);

void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
				  struct ath9k_channel *chan)
{
	struct ath9k_nfcal_hist *h;
	s16 default_nf;
	int i, j;

	ah->caldata->channel = chan->channel;
	ah->caldata->channelFlags = chan->channelFlags;
	h = ah->caldata->nfCalHist;
	default_nf = ath9k_hw_get_default_nf(ah, chan);
	for (i = 0; i < NUM_NF_READINGS; i++) {
		h[i].currIndex = 0;
		h[i].privNF = default_nf;
		h[i].invalidNFcount = AR_PHY_CCA_FILTERWINDOW_LENGTH;
		for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
			h[i].nfCalBuffer[j] = default_nf;
		}
	}
}


void ath9k_hw_bstuck_nfcal(struct ath_hw *ah)
{
	struct ath9k_hw_cal_data *caldata = ah->caldata;

	if (unlikely(!caldata))
		return;

	/*
	 * If beacons are stuck, the most likely cause is interference.
	 * Triggering a noise floor calibration at this point helps the
	 * hardware adapt to a noisy environment much faster.
	 * To ensure that we recover from stuck beacons quickly, let
	 * the baseband update the internal NF value itself, similar to
	 * what is being done after a full reset.
	 */
	if (!test_bit(NFCAL_PENDING, &caldata->cal_flags))
		ath9k_hw_start_nfcal(ah, true);
	else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
		ath9k_hw_getnf(ah, ah->curchan);

	set_bit(NFCAL_INTF, &caldata->cal_flags);
}
EXPORT_SYMBOL(ath9k_hw_bstuck_nfcal);
Commit	Line	Data
f1dc5600	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
f1dc5600 S	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
c46917bb	17	#include "hw.h"
641d9921	18	#include "hw-ops.h"
ee40fa06	19	#include <linux/export.h>
f1dc5600	20
795f5e2c LR	21	/* Common calibration code */
795f5e2c LR	22
f1dc5600	23
f1dc5600 S	24	static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
	25	{
	26	int16_t nfval;
	27	int16_t sort[ATH9K_NF_CAL_HIST_MAX];
	28	int i, j;
	29
	30	for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
	31	sort[i] = nfCalBuffer[i];
	32
	33	for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
	34	for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
	35	if (sort[j] > sort[j - 1]) {
	36	nfval = sort[j];
	37	sort[j] = sort[j - 1];
	38	sort[j - 1] = nfval;
	39	}
	40	}
	41	}
	42	nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
	43
	44	return nfval;
	45	}
	46
2292ca6d FF	47	static struct ath_nf_limits ath9k_hw_get_nf_limits(struct ath_hw ah,
	48	struct ath9k_channel *chan)
	49	{
	50	struct ath_nf_limits *limit;
	51
	52	if (!chan \|\| IS_CHAN_2GHZ(chan))
	53	limit = &ah->nf_2g;
	54	else
	55	limit = &ah->nf_5g;
	56
	57	return limit;
	58	}
	59
	60	static s16 ath9k_hw_get_default_nf(struct ath_hw *ah,
	61	struct ath9k_channel *chan)
	62	{
	63	return ath9k_hw_get_nf_limits(ah, chan)->nominal;
	64	}
	65
5bc225ac LB	66	s16 ath9k_hw_getchan_noise(struct ath_hw ah, struct ath9k_channel chan,
5bc225ac LB	67	s16 nf)
f23fba49 FF	68	{
	69	s8 noise = ATH_DEFAULT_NOISE_FLOOR;
	70
5bc225ac LB	71	if (nf) {
5bc225ac LB	72	s8 delta = nf - ATH9K_NF_CAL_NOISE_THRESH -
f23fba49 FF	73	ath9k_hw_get_default_nf(ah, chan);
	74	if (delta > 0)
	75	noise += delta;
	76	}
	77	return noise;
	78	}
	79	EXPORT_SYMBOL(ath9k_hw_getchan_noise);
2292ca6d FF	80
2292ca6d FF	81	static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
70cf1533	82	struct ath9k_hw_cal_data *cal,
f1dc5600 S	83	int16_t *nfarray)
f1dc5600 S	84	{
70cf1533	85	struct ath_common *common = ath9k_hw_common(ah);
2292ca6d	86	struct ath_nf_limits *limit;
70cf1533 FF	87	struct ath9k_nfcal_hist *h;
70cf1533 FF	88	bool high_nf_mid = false;
28ef6450	89	u8 chainmask = (ah->rxchainmask << 3) \| ah->rxchainmask;
f1dc5600 S	90	int i;
f1dc5600 S	91
70cf1533	92	h = cal->nfCalHist;
2292ca6d FF	93	limit = ath9k_hw_get_nf_limits(ah, ah->curchan);
2292ca6d FF	94
f1dc5600	95	for (i = 0; i < NUM_NF_READINGS; i++) {
28ef6450	96	if (!(chainmask & (1 << i)) \|\|
6b3d3486	97	((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(ah->curchan)))
28ef6450 RM	98	continue;
28ef6450 RM	99
f1dc5600 S	100	h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
	101
	102	if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
	103	h[i].currIndex = 0;
	104
	105	if (h[i].invalidNFcount > 0) {
f2552e28 FF	106	h[i].invalidNFcount--;
f2552e28 FF	107	h[i].privNF = nfarray[i];
f1dc5600 S	108	} else {
	109	h[i].privNF =
	110	ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
	111	}
2292ca6d	112
70cf1533 FF	113	if (!h[i].privNF)
	114	continue;
	115
	116	if (h[i].privNF > limit->max) {
	117	high_nf_mid = true;
	118
d2182b69	119	ath_dbg(common, CALIBRATE,
226afe68 JP	120	"NFmid[%d] (%d) > MAX (%d), %s\n",
226afe68 JP	121	i, h[i].privNF, limit->max,
4b9b42bf	122	(test_bit(NFCAL_INTF, &cal->cal_flags) ?
226afe68 JP	123	"not corrected (due to interference)" :
226afe68 JP	124	"correcting to MAX"));
70cf1533 FF	125
	126	/*
	127	* Normally we limit the average noise floor by the
	128	* hardware specific maximum here. However if we have
	129	* encountered stuck beacons because of interference,
	130	* we bypass this limit here in order to better deal
	131	* with our environment.
	132	*/
4b9b42bf	133	if (!test_bit(NFCAL_INTF, &cal->cal_flags))
70cf1533 FF	134	h[i].privNF = limit->max;
70cf1533 FF	135	}
f1dc5600	136	}
70cf1533 FF	137
	138	/*
	139	* If the noise floor seems normal for all chains, assume that
	140	* there is no significant interference in the environment anymore.
	141	* Re-enable the enforcement of the NF maximum again.
	142	*/
	143	if (!high_nf_mid)
4b9b42bf	144	clear_bit(NFCAL_INTF, &cal->cal_flags);
f1dc5600 S	145	}
f1dc5600 S	146
b43d59fb	147	static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
57fbcce3	148	enum nl80211_band band,
b43d59fb	149	int16_t *nft)
f1dc5600	150	{
76061abb	151	switch (band) {
57fbcce3	152	case NL80211_BAND_5GHZ:
f74df6fb	153	*nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
f1dc5600	154	break;
57fbcce3	155	case NL80211_BAND_2GHZ:
f74df6fb	156	*nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
f1dc5600 S	157	break;
f1dc5600 S	158	default:
76061abb	159	BUG_ON(1);
f1dc5600 S	160	return false;
	161	}
	162
	163	return true;
	164	}
	165
795f5e2c LR	166	void ath9k_hw_reset_calibration(struct ath_hw *ah,
795f5e2c LR	167	struct ath9k_cal_list *currCal)
f1dc5600	168	{
f1dc5600 S	169	int i;
	170
	171	ath9k_hw_setup_calibration(ah, currCal);
	172
	173	currCal->calState = CAL_RUNNING;
	174
	175	for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2660b81a S	176	ah->meas0.sign[i] = 0;
	177	ah->meas1.sign[i] = 0;
	178	ah->meas2.sign[i] = 0;
	179	ah->meas3.sign[i] = 0;
f1dc5600 S	180	}
f1dc5600 S	181
2660b81a	182	ah->cal_samples = 0;
f1dc5600 S	183	}
f1dc5600 S	184
c9e27d94	185	/* This is done for the currently configured channel */
cbe61d8a	186	bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
f1dc5600	187	{
c46917bb	188	struct ath_common *common = ath9k_hw_common(ah);
cbfe9468	189	struct ath9k_cal_list *currCal = ah->cal_list_curr;
f1dc5600	190
20bd2a09	191	if (!ah->caldata)
c9e27d94	192	return true;
f1dc5600 S	193
f1dc5600 S	194	if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
c9e27d94	195	return true;
f1dc5600 S	196
f1dc5600 S	197	if (currCal == NULL)
c9e27d94	198	return true;
f1dc5600 S	199
f1dc5600 S	200	if (currCal->calState != CAL_DONE) {
d2182b69	201	ath_dbg(common, CALIBRATE, "Calibration state incorrect, %d\n",
226afe68	202	currCal->calState);
c9e27d94	203	return true;
f1dc5600 S	204	}
f1dc5600 S	205
6497827f	206	if (!(ah->supp_cals & currCal->calData->calType))
c9e27d94	207	return true;
f1dc5600	208
d2182b69	209	ath_dbg(common, CALIBRATE, "Resetting Cal %d state for channel %u\n",
e4744ec7	210	currCal->calData->calType, ah->curchan->chan->center_freq);
f1dc5600	211
20bd2a09	212	ah->caldata->CalValid &= ~currCal->calData->calType;
f1dc5600 S	213	currCal->calState = CAL_WAITING;
f1dc5600 S	214
c9e27d94	215	return false;
f1dc5600	216	}
7322fd19	217	EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
f1dc5600	218
00c86590	219	void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update)
f1dc5600	220	{
4254bc1c	221	if (ah->caldata)
4b9b42bf	222	set_bit(NFCAL_PENDING, &ah->caldata->cal_flags);
4254bc1c	223
f1dc5600 S	224	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
f1dc5600 S	225	AR_PHY_AGC_CONTROL_ENABLE_NF);
00c86590 FF	226
	227	if (update)
	228	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
f1dc5600	229	AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
00c86590 FF	230	else
	231	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
	232	AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
	233
f1dc5600 S	234	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
	235	}
	236
7b8aaead	237	int ath9k_hw_loadnf(struct ath_hw ah, struct ath9k_channel chan)
bbacee13	238	{
20bd2a09	239	struct ath9k_nfcal_hist *h = NULL;
bbacee13	240	unsigned i, j;
487f0e01	241	u8 chainmask = (ah->rxchainmask << 3) \| ah->rxchainmask;
bbacee13	242	struct ath_common *common = ath9k_hw_common(ah);
20bd2a09	243	s16 default_nf = ath9k_hw_get_default_nf(ah, chan);
82def495	244	u32 bb_agc_ctl = REG_READ(ah, AR_PHY_AGC_CONTROL);
bbacee13	245
20bd2a09 FF	246	if (ah->caldata)
20bd2a09 FF	247	h = ah->caldata->nfCalHist;
bbacee13	248
9830ba6c	249	ENABLE_REG_RMW_BUFFER(ah);
bbacee13 FF	250	for (i = 0; i < NUM_NF_READINGS; i++) {
bbacee13 FF	251	if (chainmask & (1 << i)) {
20bd2a09 FF	252	s16 nfval;
20bd2a09 FF	253
e4744ec7	254	if ((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(chan))
28ef6450 RM	255	continue;
28ef6450 RM	256
20bd2a09 FF	257	if (h)
	258	nfval = h[i].privNF;
	259	else
	260	nfval = default_nf;
	261
9830ba6c OR	262	REG_RMW(ah, ah->nf_regs[i],
9830ba6c OR	263	(((u32) nfval << 1) & 0x1ff), 0x1ff);
bbacee13 FF	264	}
	265	}
	266
82def495 MP	267	/*
	268	* stop NF cal if ongoing to ensure NF load completes immediately
	269	* (or after end rx/tx frame if ongoing)
	270	*/
	271	if (bb_agc_ctl & AR_PHY_AGC_CONTROL_NF) {
	272	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
	273	REG_RMW_BUFFER_FLUSH(ah);
	274	ENABLE_REG_RMW_BUFFER(ah);
	275	}
	276
bbacee13 FF	277	/*
	278	* Load software filtered NF value into baseband internal minCCApwr
	279	* variable.
	280	*/
	281	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
	282	AR_PHY_AGC_CONTROL_ENABLE_NF);
	283	REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
	284	AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
	285	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
9830ba6c	286	REG_RMW_BUFFER_FLUSH(ah);
bbacee13 FF	287
	288	/*
	289	* Wait for load to complete, should be fast, a few 10s of us.
82def495 MP	290	* The max delay was changed from an original 250us to 22.2 msec.
	291	* This would increase timeout to the longest possible frame
	292	* (11n max length 22.1 msec)
bbacee13	293	*/
82def495	294	for (j = 0; j < 22200; j++) {
bbacee13	295	if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
82def495	296	AR_PHY_AGC_CONTROL_NF) == 0)
bbacee13 FF	297	break;
	298	udelay(10);
	299	}
	300
82def495 MP	301	/*
	302	* Restart NF so it can continue.
	303	*/
	304	if (bb_agc_ctl & AR_PHY_AGC_CONTROL_NF) {
	305	ENABLE_REG_RMW_BUFFER(ah);
	306	if (bb_agc_ctl & AR_PHY_AGC_CONTROL_ENABLE_NF)
	307	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
	308	AR_PHY_AGC_CONTROL_ENABLE_NF);
	309	if (bb_agc_ctl & AR_PHY_AGC_CONTROL_NO_UPDATE_NF)
	310	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
	311	AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
	312	REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
	313	REG_RMW_BUFFER_FLUSH(ah);
	314	}
	315
bbacee13 FF	316	/*
	317	* We timed out waiting for the noisefloor to load, probably due to an
	318	* in-progress rx. Simply return here and allow the load plenty of time
	319	* to complete before the next calibration interval. We need to avoid
	320	* trying to load -50 (which happens below) while the previous load is
	321	* still in progress as this can cause rx deafness. Instead by returning
	322	* here, the baseband nf cal will just be capped by our present
	323	* noisefloor until the next calibration timer.
	324	*/
82def495	325	if (j == 22200) {
d2182b69	326	ath_dbg(common, ANY,
226afe68 JP	327	"Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
226afe68 JP	328	REG_READ(ah, AR_PHY_AGC_CONTROL));
7b8aaead	329	return -ETIMEDOUT;
bbacee13 FF	330	}
	331
	332	/*
	333	* Restore maxCCAPower register parameter again so that we're not capped
	334	* by the median we just loaded. This will be initial (and max) value
	335	* of next noise floor calibration the baseband does.
	336	*/
9830ba6c	337	ENABLE_REG_RMW_BUFFER(ah);
bbacee13 FF	338	for (i = 0; i < NUM_NF_READINGS; i++) {
bbacee13 FF	339	if (chainmask & (1 << i)) {
e4744ec7	340	if ((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(chan))
28ef6450 RM	341	continue;
28ef6450 RM	342
9830ba6c OR	343	REG_RMW(ah, ah->nf_regs[i],
9830ba6c OR	344	(((u32) (-50) << 1) & 0x1ff), 0x1ff);
bbacee13 FF	345	}
bbacee13 FF	346	}
9830ba6c	347	REG_RMW_BUFFER_FLUSH(ah);
7b8aaead FF	348
7b8aaead FF	349	return 0;
bbacee13 FF	350	}
	351
	352
f2552e28 FF	353	static void ath9k_hw_nf_sanitize(struct ath_hw ah, s16 nf)
	354	{
	355	struct ath_common *common = ath9k_hw_common(ah);
	356	struct ath_nf_limits *limit;
	357	int i;
	358
	359	if (IS_CHAN_2GHZ(ah->curchan))
	360	limit = &ah->nf_2g;
	361	else
	362	limit = &ah->nf_5g;
	363
	364	for (i = 0; i < NUM_NF_READINGS; i++) {
	365	if (!nf[i])
	366	continue;
	367
d2182b69	368	ath_dbg(common, CALIBRATE,
226afe68 JP	369	"NF calibrated [%s] [chain %d] is %d\n",
226afe68 JP	370	(i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
54bd5006	371
2ee0a070	372	if (nf[i] > limit->max) {
d2182b69	373	ath_dbg(common, CALIBRATE,
226afe68	374	"NF[%d] (%d) > MAX (%d), correcting to MAX\n",
2ee0a070	375	i, nf[i], limit->max);
f2552e28 FF	376	nf[i] = limit->max;
f2552e28 FF	377	} else if (nf[i] < limit->min) {
d2182b69	378	ath_dbg(common, CALIBRATE,
226afe68 JP	379	"NF[%d] (%d) < MIN (%d), correcting to NOM\n",
226afe68 JP	380	i, nf[i], limit->min);
f2552e28 FF	381	nf[i] = limit->nominal;
	382	}
	383	}
	384	}
	385
4254bc1c	386	bool ath9k_hw_getnf(struct ath_hw ah, struct ath9k_channel chan)
f1dc5600	387	{
c46917bb	388	struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 S	389	int16_t nf, nfThresh;
	390	int16_t nfarray[NUM_NF_READINGS] = { 0 };
	391	struct ath9k_nfcal_hist *h;
76061abb	392	struct ieee80211_channel *c = chan->chan;
20bd2a09 FF	393	struct ath9k_hw_cal_data *caldata = ah->caldata;
20bd2a09 FF	394
f1dc5600	395	if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
d2182b69	396	ath_dbg(common, CALIBRATE,
226afe68	397	"NF did not complete in calibration window\n");
4254bc1c	398	return false;
d9891c78 FF	399	}
	400
	401	ath9k_hw_do_getnf(ah, nfarray);
	402	ath9k_hw_nf_sanitize(ah, nfarray);
	403	nf = nfarray[0];
	404	if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
	405	&& nf > nfThresh) {
d2182b69	406	ath_dbg(common, CALIBRATE,
226afe68 JP	407	"noise floor failed detected; detected %d, threshold %d\n",
226afe68 JP	408	nf, nfThresh);
d9891c78 FF	409	}
	410
	411	if (!caldata) {
	412	chan->noisefloor = nf;
	413	return false;
f1dc5600 S	414	}
f1dc5600 S	415
20bd2a09	416	h = caldata->nfCalHist;
4b9b42bf	417	clear_bit(NFCAL_PENDING, &caldata->cal_flags);
70cf1533	418	ath9k_hw_update_nfcal_hist_buffer(ah, caldata, nfarray);
d9891c78	419	chan->noisefloor = h[0].privNF;
5bc225ac	420	ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
4254bc1c	421	return true;
f1dc5600	422	}
1a19f77f	423	EXPORT_SYMBOL(ath9k_hw_getnf);
f1dc5600	424
20bd2a09 FF	425	void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
20bd2a09 FF	426	struct ath9k_channel *chan)
f1dc5600	427	{
20bd2a09 FF	428	struct ath9k_nfcal_hist *h;
20bd2a09 FF	429	s16 default_nf;
f1dc5600	430	int i, j;
f2552e28	431
bdd196a3	432	ah->caldata->channel = chan->channel;
fcb9a3de	433	ah->caldata->channelFlags = chan->channelFlags;
20bd2a09 FF	434	h = ah->caldata->nfCalHist;
20bd2a09 FF	435	default_nf = ath9k_hw_get_default_nf(ah, chan);
f1dc5600	436	for (i = 0; i < NUM_NF_READINGS; i++) {
20bd2a09 FF	437	h[i].currIndex = 0;
	438	h[i].privNF = default_nf;
	439	h[i].invalidNFcount = AR_PHY_CCA_FILTERWINDOW_LENGTH;
f1dc5600	440	for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
20bd2a09	441	h[i].nfCalBuffer[j] = default_nf;
f1dc5600 S	442	}
f1dc5600 S	443	}
f1dc5600 S	444	}
f1dc5600 S	445
70cf1533 FF	446
	447	void ath9k_hw_bstuck_nfcal(struct ath_hw *ah)
	448	{
	449	struct ath9k_hw_cal_data *caldata = ah->caldata;
	450
	451	if (unlikely(!caldata))
	452	return;
	453
	454	/*
	455	* If beacons are stuck, the most likely cause is interference.
	456	* Triggering a noise floor calibration at this point helps the
	457	* hardware adapt to a noisy environment much faster.
	458	* To ensure that we recover from stuck beacons quickly, let
	459	* the baseband update the internal NF value itself, similar to
	460	* what is being done after a full reset.
	461	*/
4b9b42bf	462	if (!test_bit(NFCAL_PENDING, &caldata->cal_flags))
70cf1533 FF	463	ath9k_hw_start_nfcal(ah, true);
	464	else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
	465	ath9k_hw_getnf(ah, ah->curchan);
	466
4b9b42bf	467	set_bit(NFCAL_INTF, &caldata->cal_flags);
70cf1533 FF	468	}
	469	EXPORT_SYMBOL(ath9k_hw_bstuck_nfcal);
	470