[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / ath / ath9k / eeprom.c

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include "hw.h"

void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
{
        REG_WRITE(ah, reg, val);

        if (ah->config.analog_shiftreg)
		udelay(100);
}

void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
			       u32 shift, u32 val)
{
	REG_RMW(ah, reg, ((val << shift) & mask), mask);

	if (ah->config.analog_shiftreg)
		udelay(100);
}

int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
			     int16_t targetLeft, int16_t targetRight)
{
	int16_t rv;

	if (srcRight == srcLeft) {
		rv = targetLeft;
	} else {
		rv = (int16_t) (((target - srcLeft) * targetRight +
				 (srcRight - target) * targetLeft) /
				(srcRight - srcLeft));
	}
	return rv;
}

bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
				    u16 *indexL, u16 *indexR)
{
	u16 i;

	if (target <= pList[0]) {
		*indexL = *indexR = 0;
		return true;
	}
	if (target >= pList[listSize - 1]) {
		*indexL = *indexR = (u16) (listSize - 1);
		return true;
	}

	for (i = 0; i < listSize - 1; i++) {
		if (pList[i] == target) {
			*indexL = *indexR = i;
			return true;
		}
		if (target < pList[i + 1]) {
			*indexL = i;
			*indexR = (u16) (i + 1);
			return false;
		}
	}
	return false;
}

void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data,
				  int eep_start_loc, int size)
{
	int i = 0, j, addr;
	u32 addrdata[8];
	u32 data[8];

	for (addr = 0; addr < size; addr++) {
		addrdata[i] = AR5416_EEPROM_OFFSET +
			((addr + eep_start_loc) << AR5416_EEPROM_S);
		i++;
		if (i == 8) {
			REG_READ_MULTI(ah, addrdata, data, i);

			for (j = 0; j < i; j++) {
				*eep_data = data[j];
				eep_data++;
			}
			i = 0;
		}
	}

	if (i != 0) {
		REG_READ_MULTI(ah, addrdata, data, i);

		for (j = 0; j < i; j++) {
			*eep_data = data[j];
			eep_data++;
		}
	}
}

static bool ath9k_hw_nvram_read_blob(struct ath_hw *ah, u32 off,
				     u16 *data)
{
	u16 *blob_data;

	if (off * sizeof(u16) > ah->eeprom_blob->size)
		return false;

	blob_data = (u16 *)ah->eeprom_blob->data;
	*data =  blob_data[off];
	return true;
}

bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
{
	struct ath_common *common = ath9k_hw_common(ah);
	bool ret;

	if (ah->eeprom_blob)
		ret = ath9k_hw_nvram_read_blob(ah, off, data);
	else
		ret = common->bus_ops->eeprom_read(common, off, data);

	if (!ret)
		ath_dbg(common, EEPROM,
			"unable to read eeprom region at offset %u\n", off);

	return ret;
}

int ath9k_hw_nvram_swap_data(struct ath_hw *ah, bool *swap_needed, int size)
{
	u16 magic;
	u16 *eepdata;
	int i;
	struct ath_common *common = ath9k_hw_common(ah);

	if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
		ath_err(common, "Reading Magic # failed\n");
		return -EIO;
	}

	*swap_needed = false;
	if (swab16(magic) == AR5416_EEPROM_MAGIC) {
		if (ah->ah_flags & AH_NO_EEP_SWAP) {
			ath_info(common,
				 "Ignoring endianness difference in EEPROM magic bytes.\n");
		} else {
			*swap_needed = true;
		}
	} else if (magic != AR5416_EEPROM_MAGIC) {
		if (ath9k_hw_use_flash(ah))
			return 0;

		ath_err(common,
			"Invalid EEPROM Magic (0x%04x).\n", magic);
		return -EINVAL;
	}

	eepdata = (u16 *)(&ah->eeprom);

	if (*swap_needed) {
		ath_dbg(common, EEPROM,
			"EEPROM Endianness is not native.. Changing.\n");

		for (i = 0; i < size; i++)
			eepdata[i] = swab16(eepdata[i]);
	}

	return 0;
}

bool ath9k_hw_nvram_validate_checksum(struct ath_hw *ah, int size)
{
	u32 i, sum = 0;
	u16 *eepdata = (u16 *)(&ah->eeprom);
	struct ath_common *common = ath9k_hw_common(ah);

	for (i = 0; i < size; i++)
		sum ^= eepdata[i];

	if (sum != 0xffff) {
		ath_err(common, "Bad EEPROM checksum 0x%x\n", sum);
		return false;
	}

	return true;
}

bool ath9k_hw_nvram_check_version(struct ath_hw *ah, int version, int minrev)
{
	struct ath_common *common = ath9k_hw_common(ah);

	if (ah->eep_ops->get_eeprom_ver(ah) != version ||
	    ah->eep_ops->get_eeprom_rev(ah) < minrev) {
		ath_err(common, "Bad EEPROM VER 0x%04x or REV 0x%04x\n",
			ah->eep_ops->get_eeprom_ver(ah),
			ah->eep_ops->get_eeprom_rev(ah));
		return false;
	}

	return true;
}

void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
			     u8 *pVpdList, u16 numIntercepts,
			     u8 *pRetVpdList)
{
	u16 i, k;
	u8 currPwr = pwrMin;
	u16 idxL = 0, idxR = 0;

	for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
		ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
					       numIntercepts, &(idxL),
					       &(idxR));
		if (idxR < 1)
			idxR = 1;
		if (idxL == numIntercepts - 1)
			idxL = (u16) (numIntercepts - 2);
		if (pPwrList[idxL] == pPwrList[idxR])
			k = pVpdList[idxL];
		else
			k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
				   (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
				  (pPwrList[idxR] - pPwrList[idxL]));
		pRetVpdList[i] = (u8) k;
		currPwr += 2;
	}
}

void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
				       struct ath9k_channel *chan,
				       struct cal_target_power_leg *powInfo,
				       u16 numChannels,
				       struct cal_target_power_leg *pNewPower,
				       u16 numRates, bool isExtTarget)
{
	struct chan_centers centers;
	u16 clo, chi;
	int i;
	int matchIndex = -1, lowIndex = -1;
	u16 freq;

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;

	if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
				       IS_CHAN_2GHZ(chan))) {
		matchIndex = 0;
	} else {
		for (i = 0; (i < numChannels) &&
			     (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
			if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
						       IS_CHAN_2GHZ(chan))) {
				matchIndex = i;
				break;
			} else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
						IS_CHAN_2GHZ(chan)) && i > 0 &&
				   freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
						IS_CHAN_2GHZ(chan))) {
				lowIndex = i - 1;
				break;
			}
		}
		if ((matchIndex == -1) && (lowIndex == -1))
			matchIndex = i - 1;
	}

	if (matchIndex != -1) {
		*pNewPower = powInfo[matchIndex];
	} else {
		clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
					 IS_CHAN_2GHZ(chan));
		chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
					 IS_CHAN_2GHZ(chan));

		for (i = 0; i < numRates; i++) {
			pNewPower->tPow2x[i] =
				(u8)ath9k_hw_interpolate(freq, clo, chi,
						powInfo[lowIndex].tPow2x[i],
						powInfo[lowIndex + 1].tPow2x[i]);
		}
	}
}

void ath9k_hw_get_target_powers(struct ath_hw *ah,
				struct ath9k_channel *chan,
				struct cal_target_power_ht *powInfo,
				u16 numChannels,
				struct cal_target_power_ht *pNewPower,
				u16 numRates, bool isHt40Target)
{
	struct chan_centers centers;
	u16 clo, chi;
	int i;
	int matchIndex = -1, lowIndex = -1;
	u16 freq;

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	freq = isHt40Target ? centers.synth_center : centers.ctl_center;

	if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
		matchIndex = 0;
	} else {
		for (i = 0; (i < numChannels) &&
			     (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
			if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
						       IS_CHAN_2GHZ(chan))) {
				matchIndex = i;
				break;
			} else
				if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
						IS_CHAN_2GHZ(chan)) && i > 0 &&
				    freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
						IS_CHAN_2GHZ(chan))) {
					lowIndex = i - 1;
					break;
				}
		}
		if ((matchIndex == -1) && (lowIndex == -1))
			matchIndex = i - 1;
	}

	if (matchIndex != -1) {
		*pNewPower = powInfo[matchIndex];
	} else {
		clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
					 IS_CHAN_2GHZ(chan));
		chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
					 IS_CHAN_2GHZ(chan));

		for (i = 0; i < numRates; i++) {
			pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
						clo, chi,
						powInfo[lowIndex].tPow2x[i],
						powInfo[lowIndex + 1].tPow2x[i]);
		}
	}
}

u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
				bool is2GHz, int num_band_edges)
{
	u16 twiceMaxEdgePower = MAX_RATE_POWER;
	int i;

	for (i = 0; (i < num_band_edges) &&
		     (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
		if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
			twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
			break;
		} else if ((i > 0) &&
			   (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
						      is2GHz))) {
			if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
					       is2GHz) < freq &&
			    CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
				twiceMaxEdgePower =
					CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
			}
			break;
		}
	}

	return twiceMaxEdgePower;
}

u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit,
			      u8 antenna_reduction)
{
	u16 reduction = antenna_reduction;

	/*
	 * Reduce scaled Power by number of chains active
	 * to get the per chain tx power level.
	 */
	switch (ar5416_get_ntxchains(ah->txchainmask)) {
	case 1:
		break;
	case 2:
		reduction += POWER_CORRECTION_FOR_TWO_CHAIN;
		break;
	case 3:
		reduction += POWER_CORRECTION_FOR_THREE_CHAIN;
		break;
	}

	if (power_limit > reduction)
		power_limit -= reduction;
	else
		power_limit = 0;

	return power_limit;
}

void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
{
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);

	switch (ar5416_get_ntxchains(ah->txchainmask)) {
	case 1:
		break;
	case 2:
		regulatory->max_power_level += POWER_CORRECTION_FOR_TWO_CHAIN;
		break;
	case 3:
		regulatory->max_power_level += POWER_CORRECTION_FOR_THREE_CHAIN;
		break;
	default:
		ath_dbg(common, EEPROM, "Invalid chainmask configuration\n");
		break;
	}
}

void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
				struct ath9k_channel *chan,
				void *pRawDataSet,
				u8 *bChans, u16 availPiers,
				u16 tPdGainOverlap,
				u16 *pPdGainBoundaries, u8 *pPDADCValues,
				u16 numXpdGains)
{
	int i, j, k;
	int16_t ss;
	u16 idxL = 0, idxR = 0, numPiers;
	static u8 vpdTableL[AR5416_NUM_PD_GAINS]
		[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
	static u8 vpdTableR[AR5416_NUM_PD_GAINS]
		[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
	static u8 vpdTableI[AR5416_NUM_PD_GAINS]
		[AR5416_MAX_PWR_RANGE_IN_HALF_DB];

	u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
	u8 minPwrT4[AR5416_NUM_PD_GAINS];
	u8 maxPwrT4[AR5416_NUM_PD_GAINS];
	int16_t vpdStep;
	int16_t tmpVal;
	u16 sizeCurrVpdTable, maxIndex, tgtIndex;
	bool match;
	int16_t minDelta = 0;
	struct chan_centers centers;
	int pdgain_boundary_default;
	struct cal_data_per_freq *data_def = pRawDataSet;
	struct cal_data_per_freq_4k *data_4k = pRawDataSet;
	struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
	bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
	int intercepts;

	if (AR_SREV_9287(ah))
		intercepts = AR9287_PD_GAIN_ICEPTS;
	else
		intercepts = AR5416_PD_GAIN_ICEPTS;

	memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
	ath9k_hw_get_channel_centers(ah, chan, &centers);

	for (numPiers = 0; numPiers < availPiers; numPiers++) {
		if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
			break;
	}

	match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
							     IS_CHAN_2GHZ(chan)),
					       bChans, numPiers, &idxL, &idxR);

	if (match) {
		if (AR_SREV_9287(ah)) {
			/* FIXME: array overrun? */
			for (i = 0; i < numXpdGains; i++) {
				minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
				maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
				ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
						data_9287[idxL].pwrPdg[i],
						data_9287[idxL].vpdPdg[i],
						intercepts,
						vpdTableI[i]);
			}
		} else if (eeprom_4k) {
			for (i = 0; i < numXpdGains; i++) {
				minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
				maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
				ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
						data_4k[idxL].pwrPdg[i],
						data_4k[idxL].vpdPdg[i],
						intercepts,
						vpdTableI[i]);
			}
		} else {
			for (i = 0; i < numXpdGains; i++) {
				minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
				maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
				ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
						data_def[idxL].pwrPdg[i],
						data_def[idxL].vpdPdg[i],
						intercepts,
						vpdTableI[i]);
			}
		}
	} else {
		for (i = 0; i < numXpdGains; i++) {
			if (AR_SREV_9287(ah)) {
				pVpdL = data_9287[idxL].vpdPdg[i];
				pPwrL = data_9287[idxL].pwrPdg[i];
				pVpdR = data_9287[idxR].vpdPdg[i];
				pPwrR = data_9287[idxR].pwrPdg[i];
			} else if (eeprom_4k) {
				pVpdL = data_4k[idxL].vpdPdg[i];
				pPwrL = data_4k[idxL].pwrPdg[i];
				pVpdR = data_4k[idxR].vpdPdg[i];
				pPwrR = data_4k[idxR].pwrPdg[i];
			} else {
				pVpdL = data_def[idxL].vpdPdg[i];
				pPwrL = data_def[idxL].pwrPdg[i];
				pVpdR = data_def[idxR].vpdPdg[i];
				pPwrR = data_def[idxR].pwrPdg[i];
			}

			minPwrT4[i] = max(pPwrL[0], pPwrR[0]);

			maxPwrT4[i] =
				min(pPwrL[intercepts - 1],
				    pPwrR[intercepts - 1]);


			ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
						pPwrL, pVpdL,
						intercepts,
						vpdTableL[i]);
			ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
						pPwrR, pVpdR,
						intercepts,
						vpdTableR[i]);

			for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
				vpdTableI[i][j] =
					(u8)(ath9k_hw_interpolate((u16)
					     FREQ2FBIN(centers.
						       synth_center,
						       IS_CHAN_2GHZ
						       (chan)),
					     bChans[idxL], bChans[idxR],
					     vpdTableL[i][j], vpdTableR[i][j]));
			}
		}
	}

	k = 0;

	for (i = 0; i < numXpdGains; i++) {
		if (i == (numXpdGains - 1))
			pPdGainBoundaries[i] =
				(u16)(maxPwrT4[i] / 2);
		else
			pPdGainBoundaries[i] =
				(u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);

		pPdGainBoundaries[i] =
			min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);

		minDelta = 0;

		if (i == 0) {
			if (AR_SREV_9280_20_OR_LATER(ah))
				ss = (int16_t)(0 - (minPwrT4[i] / 2));
			else
				ss = 0;
		} else {
			ss = (int16_t)((pPdGainBoundaries[i - 1] -
					(minPwrT4[i] / 2)) -
				       tPdGainOverlap + 1 + minDelta);
		}
		vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
		vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);

		while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
			tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
			pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
			ss++;
		}

		sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
		tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
				(minPwrT4[i] / 2));
		maxIndex = (tgtIndex < sizeCurrVpdTable) ?
			tgtIndex : sizeCurrVpdTable;

		while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
			pPDADCValues[k++] = vpdTableI[i][ss++];
		}

		vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
				    vpdTableI[i][sizeCurrVpdTable - 2]);
		vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);

		if (tgtIndex >= maxIndex) {
			while ((ss <= tgtIndex) &&
			       (k < (AR5416_NUM_PDADC_VALUES - 1))) {
				tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
						    (ss - maxIndex + 1) * vpdStep));
				pPDADCValues[k++] = (u8)((tmpVal > 255) ?
							 255 : tmpVal);
				ss++;
			}
		}
	}

	if (eeprom_4k)
		pdgain_boundary_default = 58;
	else
		pdgain_boundary_default = pPdGainBoundaries[i - 1];

	while (i < AR5416_PD_GAINS_IN_MASK) {
		pPdGainBoundaries[i] = pdgain_boundary_default;
		i++;
	}

	while (k < AR5416_NUM_PDADC_VALUES) {
		pPDADCValues[k] = pPDADCValues[k - 1];
		k++;
	}
}

int ath9k_hw_eeprom_init(struct ath_hw *ah)
{
	int status;

	if (AR_SREV_9300_20_OR_LATER(ah))
		ah->eep_ops = &eep_ar9300_ops;
	else if (AR_SREV_9287(ah)) {
		ah->eep_ops = &eep_ar9287_ops;
	} else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
		ah->eep_ops = &eep_4k_ops;
	} else {
		ah->eep_ops = &eep_def_ops;
	}

	if (!ah->eep_ops->fill_eeprom(ah))
		return -EIO;

	status = ah->eep_ops->check_eeprom(ah);

	return status;
}
Commit	Line	Data
f1dc5600	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
f1dc5600 S	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
5bb12791	17	#include "hw.h"
f1dc5600	18
79d7f4bc S	19	void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
	20	{
	21	REG_WRITE(ah, reg, val);
	22
	23	if (ah->config.analog_shiftreg)
	24	udelay(100);
	25	}
	26
b5aec950 S	27	void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
b5aec950 S	28	u32 shift, u32 val)
f1dc5600	29	{
2028523b	30	REG_RMW(ah, reg, ((val << shift) & mask), mask);
f1dc5600	31
2660b81a	32	if (ah->config.analog_shiftreg)
f1dc5600	33	udelay(100);
f1dc5600 S	34	}
f1dc5600 S	35
b5aec950 S	36	int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
b5aec950 S	37	int16_t targetLeft, int16_t targetRight)
f1dc5600 S	38	{
	39	int16_t rv;
	40
	41	if (srcRight == srcLeft) {
	42	rv = targetLeft;
	43	} else {
	44	rv = (int16_t) (((target - srcLeft) * targetRight +
	45	(srcRight - target) * targetLeft) /
	46	(srcRight - srcLeft));
	47	}
	48	return rv;
	49	}
	50
b5aec950 S	51	bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
b5aec950 S	52	u16 indexL, u16 indexR)
f1dc5600 S	53	{
	54	u16 i;
	55
	56	if (target <= pList[0]) {
	57	indexL = indexR = 0;
	58	return true;
	59	}
	60	if (target >= pList[listSize - 1]) {
	61	indexL = indexR = (u16) (listSize - 1);
	62	return true;
	63	}
	64
	65	for (i = 0; i < listSize - 1; i++) {
	66	if (pList[i] == target) {
	67	indexL = indexR = i;
	68	return true;
	69	}
	70	if (target < pList[i + 1]) {
	71	*indexL = i;
	72	*indexR = (u16) (i + 1);
	73	return false;
	74	}
	75	}
	76	return false;
	77	}
	78
04cf53f4 SM	79	void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw ah, u16 eep_data,
	80	int eep_start_loc, int size)
	81	{
	82	int i = 0, j, addr;
	83	u32 addrdata[8];
	84	u32 data[8];
	85
	86	for (addr = 0; addr < size; addr++) {
	87	addrdata[i] = AR5416_EEPROM_OFFSET +
	88	((addr + eep_start_loc) << AR5416_EEPROM_S);
	89	i++;
	90	if (i == 8) {
	91	REG_READ_MULTI(ah, addrdata, data, i);
	92
	93	for (j = 0; j < i; j++) {
	94	*eep_data = data[j];
	95	eep_data++;
	96	}
	97	i = 0;
	98	}
	99	}
	100
	101	if (i != 0) {
	102	REG_READ_MULTI(ah, addrdata, data, i);
	103
	104	for (j = 0; j < i; j++) {
	105	*eep_data = data[j];
	106	eep_data++;
	107	}
	108	}
	109	}
	110
ab5c4f71 GJ	111	static bool ath9k_hw_nvram_read_blob(struct ath_hw *ah, u32 off,
	112	u16 *data)
	113	{
	114	u16 *blob_data;
	115
	116	if (off * sizeof(u16) > ah->eeprom_blob->size)
	117	return false;
	118
	119	blob_data = (u16 *)ah->eeprom_blob->data;
	120	*data = blob_data[off];
	121	return true;
	122	}
	123
0e4b9f2f	124	bool ath9k_hw_nvram_read(struct ath_hw ah, u32 off, u16 data)
f1dc5600	125	{
0e4b9f2f	126	struct ath_common *common = ath9k_hw_common(ah);
2fd2cdfb GJ	127	bool ret;
2fd2cdfb GJ	128
ab5c4f71 GJ	129	if (ah->eeprom_blob)
	130	ret = ath9k_hw_nvram_read_blob(ah, off, data);
	131	else
	132	ret = common->bus_ops->eeprom_read(common, off, data);
	133
2fd2cdfb	134	if (!ret)
7177d8f9 GJ	135	ath_dbg(common, EEPROM,
7177d8f9 GJ	136	"unable to read eeprom region at offset %u\n", off);
2fd2cdfb GJ	137
2fd2cdfb GJ	138	return ret;
f1dc5600 S	139	}
f1dc5600 S	140
6fa658fd MB	141	int ath9k_hw_nvram_swap_data(struct ath_hw ah, bool swap_needed, int size)
	142	{
	143	u16 magic;
	144	u16 *eepdata;
	145	int i;
	146	struct ath_common *common = ath9k_hw_common(ah);
	147
	148	if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
	149	ath_err(common, "Reading Magic # failed\n");
	150	return -EIO;
	151	}
	152
65dc1a5d FF	153	*swap_needed = false;
65dc1a5d FF	154	if (swab16(magic) == AR5416_EEPROM_MAGIC) {
6fa658fd MB	155	if (ah->ah_flags & AH_NO_EEP_SWAP) {
	156	ath_info(common,
	157	"Ignoring endianness difference in EEPROM magic bytes.\n");
6fa658fd MB	158	} else {
	159	*swap_needed = true;
	160	}
65dc1a5d FF	161	} else if (magic != AR5416_EEPROM_MAGIC) {
	162	if (ath9k_hw_use_flash(ah))
	163	return 0;
	164
6fa658fd MB	165	ath_err(common,
	166	"Invalid EEPROM Magic (0x%04x).\n", magic);
	167	return -EINVAL;
	168	}
	169
	170	eepdata = (u16 *)(&ah->eeprom);
	171
	172	if (*swap_needed) {
	173	ath_dbg(common, EEPROM,
	174	"EEPROM Endianness is not native.. Changing.\n");
	175
	176	for (i = 0; i < size; i++)
	177	eepdata[i] = swab16(eepdata[i]);
	178	}
	179
	180	return 0;
	181	}
	182
	183	bool ath9k_hw_nvram_validate_checksum(struct ath_hw *ah, int size)
	184	{
	185	u32 i, sum = 0;
	186	u16 eepdata = (u16 )(&ah->eeprom);
	187	struct ath_common *common = ath9k_hw_common(ah);
	188
	189	for (i = 0; i < size; i++)
	190	sum ^= eepdata[i];
	191
	192	if (sum != 0xffff) {
	193	ath_err(common, "Bad EEPROM checksum 0x%x\n", sum);
	194	return false;
	195	}
	196
	197	return true;
	198	}
	199
	200	bool ath9k_hw_nvram_check_version(struct ath_hw *ah, int version, int minrev)
	201	{
	202	struct ath_common *common = ath9k_hw_common(ah);
	203
	204	if (ah->eep_ops->get_eeprom_ver(ah) != version \|\|
	205	ah->eep_ops->get_eeprom_rev(ah) < minrev) {
	206	ath_err(common, "Bad EEPROM VER 0x%04x or REV 0x%04x\n",
	207	ah->eep_ops->get_eeprom_ver(ah),
	208	ah->eep_ops->get_eeprom_rev(ah));
19f2ce3f	209	return false;
6fa658fd MB	210	}
	211
	212	return true;
	213	}
	214
b5aec950 S	215	void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
	216	u8 *pVpdList, u16 numIntercepts,
	217	u8 *pRetVpdList)
f74df6fb S	218	{
	219	u16 i, k;
	220	u8 currPwr = pwrMin;
	221	u16 idxL = 0, idxR = 0;
	222
	223	for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
	224	ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
	225	numIntercepts, &(idxL),
	226	&(idxR));
	227	if (idxR < 1)
	228	idxR = 1;
	229	if (idxL == numIntercepts - 1)
	230	idxL = (u16) (numIntercepts - 2);
	231	if (pPwrList[idxL] == pPwrList[idxR])
	232	k = pVpdList[idxL];
	233	else
	234	k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
	235	(pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
	236	(pPwrList[idxR] - pPwrList[idxL]));
	237	pRetVpdList[i] = (u8) k;
	238	currPwr += 2;
	239	}
f74df6fb S	240	}
f74df6fb S	241
b5aec950 S	242	void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
	243	struct ath9k_channel *chan,
	244	struct cal_target_power_leg *powInfo,
	245	u16 numChannels,
	246	struct cal_target_power_leg *pNewPower,
	247	u16 numRates, bool isExtTarget)
f74df6fb S	248	{
	249	struct chan_centers centers;
	250	u16 clo, chi;
	251	int i;
	252	int matchIndex = -1, lowIndex = -1;
	253	u16 freq;
	254
	255	ath9k_hw_get_channel_centers(ah, chan, &centers);
	256	freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
	257
	258	if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
	259	IS_CHAN_2GHZ(chan))) {
	260	matchIndex = 0;
	261	} else {
	262	for (i = 0; (i < numChannels) &&
	263	(powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
	264	if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
	265	IS_CHAN_2GHZ(chan))) {
	266	matchIndex = i;
	267	break;
73f57f83 RK	268	} else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
	269	IS_CHAN_2GHZ(chan)) && i > 0 &&
	270	freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
	271	IS_CHAN_2GHZ(chan))) {
f74df6fb S	272	lowIndex = i - 1;
	273	break;
	274	}
	275	}
	276	if ((matchIndex == -1) && (lowIndex == -1))
	277	matchIndex = i - 1;
	278	}
	279
	280	if (matchIndex != -1) {
	281	*pNewPower = powInfo[matchIndex];
	282	} else {
	283	clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
	284	IS_CHAN_2GHZ(chan));
	285	chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
	286	IS_CHAN_2GHZ(chan));
	287
	288	for (i = 0; i < numRates; i++) {
	289	pNewPower->tPow2x[i] =
	290	(u8)ath9k_hw_interpolate(freq, clo, chi,
	291	powInfo[lowIndex].tPow2x[i],
	292	powInfo[lowIndex + 1].tPow2x[i]);
	293	}
	294	}
	295	}
	296
b5aec950 S	297	void ath9k_hw_get_target_powers(struct ath_hw *ah,
	298	struct ath9k_channel *chan,
	299	struct cal_target_power_ht *powInfo,
	300	u16 numChannels,
	301	struct cal_target_power_ht *pNewPower,
	302	u16 numRates, bool isHt40Target)
f74df6fb S	303	{
	304	struct chan_centers centers;
	305	u16 clo, chi;
	306	int i;
	307	int matchIndex = -1, lowIndex = -1;
	308	u16 freq;
	309
	310	ath9k_hw_get_channel_centers(ah, chan, &centers);
	311	freq = isHt40Target ? centers.synth_center : centers.ctl_center;
	312
	313	if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
	314	matchIndex = 0;
	315	} else {
	316	for (i = 0; (i < numChannels) &&
	317	(powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
	318	if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
	319	IS_CHAN_2GHZ(chan))) {
	320	matchIndex = i;
	321	break;
	322	} else
73f57f83 RK	323	if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
	324	IS_CHAN_2GHZ(chan)) && i > 0 &&
	325	freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
	326	IS_CHAN_2GHZ(chan))) {
f74df6fb S	327	lowIndex = i - 1;
	328	break;
	329	}
	330	}
	331	if ((matchIndex == -1) && (lowIndex == -1))
	332	matchIndex = i - 1;
	333	}
	334
	335	if (matchIndex != -1) {
	336	*pNewPower = powInfo[matchIndex];
	337	} else {
	338	clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
	339	IS_CHAN_2GHZ(chan));
	340	chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
	341	IS_CHAN_2GHZ(chan));
	342
	343	for (i = 0; i < numRates; i++) {
	344	pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
	345	clo, chi,
	346	powInfo[lowIndex].tPow2x[i],
	347	powInfo[lowIndex + 1].tPow2x[i]);
	348	}
	349	}
	350	}
	351
b5aec950 S	352	u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
b5aec950 S	353	bool is2GHz, int num_band_edges)
f74df6fb	354	{
4ddfcd7d	355	u16 twiceMaxEdgePower = MAX_RATE_POWER;
f74df6fb S	356	int i;
	357
	358	for (i = 0; (i < num_band_edges) &&
	359	(pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
	360	if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
e702ba18	361	twiceMaxEdgePower = CTL_EDGE_TPOWER(pRdEdgesPower[i].ctl);
f74df6fb S	362	break;
	363	} else if ((i > 0) &&
	364	(freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
	365	is2GHz))) {
	366	if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
	367	is2GHz) < freq &&
e702ba18	368	CTL_EDGE_FLAGS(pRdEdgesPower[i - 1].ctl)) {
f74df6fb	369	twiceMaxEdgePower =
e702ba18	370	CTL_EDGE_TPOWER(pRdEdgesPower[i - 1].ctl);
f74df6fb S	371	}
	372	break;
	373	}
	374	}
	375
	376	return twiceMaxEdgePower;
	377	}
	378
ea6f792b GJ	379	u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit,
	380	u8 antenna_reduction)
	381	{
8f942b9b	382	u16 reduction = antenna_reduction;
ea6f792b GJ	383
	384	/*
	385	* Reduce scaled Power by number of chains active
	386	* to get the per chain tx power level.
	387	*/
	388	switch (ar5416_get_ntxchains(ah->txchainmask)) {
	389	case 1:
	390	break;
	391	case 2:
6010e72c	392	reduction += POWER_CORRECTION_FOR_TWO_CHAIN;
ea6f792b GJ	393	break;
ea6f792b GJ	394	case 3:
6010e72c	395	reduction += POWER_CORRECTION_FOR_THREE_CHAIN;
ea6f792b GJ	396	break;
	397	}
	398
8f942b9b GJ	399	if (power_limit > reduction)
	400	power_limit -= reduction;
	401	else
	402	power_limit = 0;
ea6f792b	403
8f942b9b	404	return power_limit;
ea6f792b GJ	405	}
ea6f792b GJ	406
a55f8588 S	407	void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
	408	{
	409	struct ath_common *common = ath9k_hw_common(ah);
	410	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
	411
	412	switch (ar5416_get_ntxchains(ah->txchainmask)) {
	413	case 1:
	414	break;
	415	case 2:
6010e72c	416	regulatory->max_power_level += POWER_CORRECTION_FOR_TWO_CHAIN;
a55f8588 S	417	break;
a55f8588 S	418	case 3:
6010e72c	419	regulatory->max_power_level += POWER_CORRECTION_FOR_THREE_CHAIN;
a55f8588 S	420	break;
a55f8588 S	421	default:
d2182b69	422	ath_dbg(common, EEPROM, "Invalid chainmask configuration\n");
a55f8588 S	423	break;
	424	}
	425	}
	426
115277a3 FF	427	void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
	428	struct ath9k_channel *chan,
	429	void *pRawDataSet,
	430	u8 *bChans, u16 availPiers,
	431	u16 tPdGainOverlap,
	432	u16 pPdGainBoundaries, u8 pPDADCValues,
	433	u16 numXpdGains)
	434	{
	435	int i, j, k;
	436	int16_t ss;
	437	u16 idxL = 0, idxR = 0, numPiers;
	438	static u8 vpdTableL[AR5416_NUM_PD_GAINS]
	439	[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
	440	static u8 vpdTableR[AR5416_NUM_PD_GAINS]
	441	[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
	442	static u8 vpdTableI[AR5416_NUM_PD_GAINS]
	443	[AR5416_MAX_PWR_RANGE_IN_HALF_DB];
	444
	445	u8 pVpdL, pVpdR, pPwrL, pPwrR;
	446	u8 minPwrT4[AR5416_NUM_PD_GAINS];
	447	u8 maxPwrT4[AR5416_NUM_PD_GAINS];
	448	int16_t vpdStep;
	449	int16_t tmpVal;
	450	u16 sizeCurrVpdTable, maxIndex, tgtIndex;
	451	bool match;
	452	int16_t minDelta = 0;
	453	struct chan_centers centers;
	454	int pdgain_boundary_default;
	455	struct cal_data_per_freq *data_def = pRawDataSet;
	456	struct cal_data_per_freq_4k *data_4k = pRawDataSet;
940cd2c1	457	struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
115277a3	458	bool eeprom_4k = AR_SREV_9285(ah) \|\| AR_SREV_9271(ah);
940cd2c1 FF	459	int intercepts;
	460
	461	if (AR_SREV_9287(ah))
	462	intercepts = AR9287_PD_GAIN_ICEPTS;
	463	else
	464	intercepts = AR5416_PD_GAIN_ICEPTS;
115277a3 FF	465
	466	memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
	467	ath9k_hw_get_channel_centers(ah, chan, &centers);
	468
	469	for (numPiers = 0; numPiers < availPiers; numPiers++) {
	470	if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
	471	break;
	472	}
	473
	474	match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
	475	IS_CHAN_2GHZ(chan)),
	476	bChans, numPiers, &idxL, &idxR);
	477
	478	if (match) {
940cd2c1 FF	479	if (AR_SREV_9287(ah)) {
	480	/* FIXME: array overrun? */
	481	for (i = 0; i < numXpdGains; i++) {
	482	minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
	483	maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
	484	ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
	485	data_9287[idxL].pwrPdg[i],
	486	data_9287[idxL].vpdPdg[i],
	487	intercepts,
	488	vpdTableI[i]);
	489	}
	490	} else if (eeprom_4k) {
115277a3 FF	491	for (i = 0; i < numXpdGains; i++) {
	492	minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
	493	maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
	494	ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
	495	data_4k[idxL].pwrPdg[i],
	496	data_4k[idxL].vpdPdg[i],
940cd2c1	497	intercepts,
115277a3 FF	498	vpdTableI[i]);
	499	}
	500	} else {
	501	for (i = 0; i < numXpdGains; i++) {
	502	minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
	503	maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
	504	ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
	505	data_def[idxL].pwrPdg[i],
	506	data_def[idxL].vpdPdg[i],
940cd2c1	507	intercepts,
115277a3 FF	508	vpdTableI[i]);
	509	}
	510	}
	511	} else {
	512	for (i = 0; i < numXpdGains; i++) {
940cd2c1 FF	513	if (AR_SREV_9287(ah)) {
	514	pVpdL = data_9287[idxL].vpdPdg[i];
	515	pPwrL = data_9287[idxL].pwrPdg[i];
	516	pVpdR = data_9287[idxR].vpdPdg[i];
	517	pPwrR = data_9287[idxR].pwrPdg[i];
	518	} else if (eeprom_4k) {
115277a3 FF	519	pVpdL = data_4k[idxL].vpdPdg[i];
	520	pPwrL = data_4k[idxL].pwrPdg[i];
	521	pVpdR = data_4k[idxR].vpdPdg[i];
	522	pPwrR = data_4k[idxR].pwrPdg[i];
	523	} else {
	524	pVpdL = data_def[idxL].vpdPdg[i];
	525	pPwrL = data_def[idxL].pwrPdg[i];
	526	pVpdR = data_def[idxR].vpdPdg[i];
	527	pPwrR = data_def[idxR].pwrPdg[i];
	528	}
	529
	530	minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
	531
	532	maxPwrT4[i] =
940cd2c1 FF	533	min(pPwrL[intercepts - 1],
940cd2c1 FF	534	pPwrR[intercepts - 1]);
115277a3 FF	535
	536
	537	ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
	538	pPwrL, pVpdL,
940cd2c1	539	intercepts,
115277a3 FF	540	vpdTableL[i]);
	541	ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
	542	pPwrR, pVpdR,
940cd2c1	543	intercepts,
115277a3 FF	544	vpdTableR[i]);
	545
	546	for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
	547	vpdTableI[i][j] =
	548	(u8)(ath9k_hw_interpolate((u16)
	549	FREQ2FBIN(centers.
	550	synth_center,
	551	IS_CHAN_2GHZ
	552	(chan)),
	553	bChans[idxL], bChans[idxR],
	554	vpdTableL[i][j], vpdTableR[i][j]));
	555	}
	556	}
	557	}
	558
	559	k = 0;
	560
	561	for (i = 0; i < numXpdGains; i++) {
	562	if (i == (numXpdGains - 1))
	563	pPdGainBoundaries[i] =
	564	(u16)(maxPwrT4[i] / 2);
	565	else
	566	pPdGainBoundaries[i] =
	567	(u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
	568
	569	pPdGainBoundaries[i] =
	570	min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
	571
1b8714f7	572	minDelta = 0;
115277a3 FF	573
	574	if (i == 0) {
	575	if (AR_SREV_9280_20_OR_LATER(ah))
	576	ss = (int16_t)(0 - (minPwrT4[i] / 2));
	577	else
	578	ss = 0;
	579	} else {
	580	ss = (int16_t)((pPdGainBoundaries[i - 1] -
	581	(minPwrT4[i] / 2)) -
	582	tPdGainOverlap + 1 + minDelta);
	583	}
	584	vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
	585	vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
	586
	587	while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
	588	tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
	589	pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
	590	ss++;
	591	}
	592
	593	sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
	594	tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
	595	(minPwrT4[i] / 2));
	596	maxIndex = (tgtIndex < sizeCurrVpdTable) ?
	597	tgtIndex : sizeCurrVpdTable;
	598
	599	while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
	600	pPDADCValues[k++] = vpdTableI[i][ss++];
	601	}
	602
	603	vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
	604	vpdTableI[i][sizeCurrVpdTable - 2]);
	605	vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
	606
	607	if (tgtIndex >= maxIndex) {
	608	while ((ss <= tgtIndex) &&
	609	(k < (AR5416_NUM_PDADC_VALUES - 1))) {
	610	tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
	611	(ss - maxIndex + 1) * vpdStep));
	612	pPDADCValues[k++] = (u8)((tmpVal > 255) ?
	613	255 : tmpVal);
	614	ss++;
	615	}
	616	}
	617	}
	618
	619	if (eeprom_4k)
	620	pdgain_boundary_default = 58;
	621	else
	622	pdgain_boundary_default = pPdGainBoundaries[i - 1];
	623
	624	while (i < AR5416_PD_GAINS_IN_MASK) {
	625	pPdGainBoundaries[i] = pdgain_boundary_default;
	626	i++;
	627	}
	628
	629	while (k < AR5416_NUM_PDADC_VALUES) {
	630	pPDADCValues[k] = pPDADCValues[k - 1];
	631	k++;
	632	}
	633	}
	634
f637cfd6	635	int ath9k_hw_eeprom_init(struct ath_hw *ah)
f1dc5600 S	636	{
f1dc5600 S	637	int status;
c16c9d06	638
15c9ee7a SB	639	if (AR_SREV_9300_20_OR_LATER(ah))
	640	ah->eep_ops = &eep_ar9300_ops;
	641	else if (AR_SREV_9287(ah)) {
0b8f6f2b	642	ah->eep_ops = &eep_ar9287_ops;
d7e7d229	643	} else if (AR_SREV_9285(ah) \|\| AR_SREV_9271(ah)) {
f74df6fb S	644	ah->eep_ops = &eep_4k_ops;
f74df6fb S	645	} else {
f74df6fb S	646	ah->eep_ops = &eep_def_ops;
f74df6fb S	647	}
e7594072	648
f74df6fb	649	if (!ah->eep_ops->fill_eeprom(ah))
f1dc5600 S	650	return -EIO;
f1dc5600 S	651
f74df6fb	652	status = ah->eep_ops->check_eeprom(ah);
f1dc5600 S	653
	654	return status;
	655	}