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Merge branch 'wireless-2.6' into wireless-next-2.6
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / eeprom_def.c
CommitLineData
b5aec950
S		 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
c46917bb 17#include "hw.h"
8fe65368 18#include "ar9002_phy.h"
b5aec950
S		 19
20static void ath9k_get_txgain_index(struct ath_hw *ah,
21 struct ath9k_channel *chan,
22 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
23 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
24{
25 u8 pcdac, i = 0;
26 u16 idxL = 0, idxR = 0, numPiers;
27 bool match;
28 struct chan_centers centers;
29
30 ath9k_hw_get_channel_centers(ah, chan, &centers);
31
32 for (numPiers = 0; numPiers < availPiers; numPiers++)
33 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
34 break;
35
36 match = ath9k_hw_get_lower_upper_index(
37 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
38 calChans, numPiers, &idxL, &idxR);
39 if (match) {
40 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
41 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
42 } else {
43 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
44 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
45 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
46 }
47
48 while (pcdac > ah->originalGain[i] &&
49 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
50 i++;
51
52 *pcdacIdx = i;
53 return;
54}
55
56static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
57 u32 initTxGain,
58 int txPower,
59 u8 *pPDADCValues)
60{
61 u32 i;
62 u32 offset;
63
64 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
65 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
66 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
67 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
68
69 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
70 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
71
72 offset = txPower;
73 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
74 if (i < offset)
75 pPDADCValues[i] = 0x0;
76 else
77 pPDADCValues[i] = 0xFF;
78}
79
80static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
81{
82 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
83}
84
85static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
86{
87 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
88}
89
90static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
91{
92#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
5bb12791 93 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 94 u16 *eep_data = (u16 *)&ah->eeprom.def;
95 int addr, ar5416_eep_start_loc = 0x100;
96
97 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
5bb12791 98 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
b5aec950 99 eep_data)) {
c46917bb
LR		 100 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
101 "Unable to read eeprom region\n");
b5aec950
S		 102 return false;
103 }
104 eep_data++;
105 }
106 return true;
107#undef SIZE_EEPROM_DEF
108}
109
110static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
111{
112 struct ar5416_eeprom_def *eep =
113 (struct ar5416_eeprom_def *) &ah->eeprom.def;
c46917bb 114 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 115 u16 *eepdata, temp, magic, magic2;
116 u32 sum = 0, el;
117 bool need_swap = false;
118 int i, addr, size;
119
5bb12791 120 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
c46917bb 121 ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
b5aec950
S		 122 return false;
123 }
124
125 if (!ath9k_hw_use_flash(ah)) {
c46917bb
LR		 126 ath_print(common, ATH_DBG_EEPROM,
127 "Read Magic = 0x%04X\n", magic);
b5aec950
S		 128
129 if (magic != AR5416_EEPROM_MAGIC) {
130 magic2 = swab16(magic);
131
132 if (magic2 == AR5416_EEPROM_MAGIC) {
133 size = sizeof(struct ar5416_eeprom_def);
134 need_swap = true;
135 eepdata = (u16 *) (&ah->eeprom);
136
137 for (addr = 0; addr < size / sizeof(u16); addr++) {
138 temp = swab16(*eepdata);
139 *eepdata = temp;
140 eepdata++;
141 }
142 } else {
c46917bb
LR		 143 ath_print(common, ATH_DBG_FATAL,
144 "Invalid EEPROM Magic. "
145 "Endianness mismatch.\n");
b5aec950
S		 146 return -EINVAL;
147 }
148 }
149 }
150
c46917bb
LR		 151 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
152 need_swap ? "True" : "False");
b5aec950
S		 153
154 if (need_swap)
155 el = swab16(ah->eeprom.def.baseEepHeader.length);
156 else
157 el = ah->eeprom.def.baseEepHeader.length;
158
159 if (el > sizeof(struct ar5416_eeprom_def))
160 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
161 else
162 el = el / sizeof(u16);
163
164 eepdata = (u16 *)(&ah->eeprom);
165
166 for (i = 0; i < el; i++)
167 sum ^= *eepdata++;
168
169 if (need_swap) {
170 u32 integer, j;
171 u16 word;
172
c46917bb
LR		 173 ath_print(common, ATH_DBG_EEPROM,
174 "EEPROM Endianness is not native.. Changing.\n");
b5aec950
S		 175
176 word = swab16(eep->baseEepHeader.length);
177 eep->baseEepHeader.length = word;
178
179 word = swab16(eep->baseEepHeader.checksum);
180 eep->baseEepHeader.checksum = word;
181
182 word = swab16(eep->baseEepHeader.version);
183 eep->baseEepHeader.version = word;
184
185 word = swab16(eep->baseEepHeader.regDmn[0]);
186 eep->baseEepHeader.regDmn[0] = word;
187
188 word = swab16(eep->baseEepHeader.regDmn[1]);
189 eep->baseEepHeader.regDmn[1] = word;
190
191 word = swab16(eep->baseEepHeader.rfSilent);
192 eep->baseEepHeader.rfSilent = word;
193
194 word = swab16(eep->baseEepHeader.blueToothOptions);
195 eep->baseEepHeader.blueToothOptions = word;
196
197 word = swab16(eep->baseEepHeader.deviceCap);
198 eep->baseEepHeader.deviceCap = word;
199
200 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
201 struct modal_eep_header *pModal =
202 &eep->modalHeader[j];
203 integer = swab32(pModal->antCtrlCommon);
204 pModal->antCtrlCommon = integer;
205
206 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
207 integer = swab32(pModal->antCtrlChain[i]);
208 pModal->antCtrlChain[i] = integer;
209 }
210
211 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
212 word = swab16(pModal->spurChans[i].spurChan);
213 pModal->spurChans[i].spurChan = word;
214 }
215 }
216 }
217
218 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
219 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
c46917bb
LR		 220 ath_print(common, ATH_DBG_FATAL,
221 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
b5aec950
S		 222 sum, ah->eep_ops->get_eeprom_ver(ah));
223 return -EINVAL;
224 }
225
57b98384
FF		 226 /* Enable fixup for AR_AN_TOP2 if necessary */
227 if (AR_SREV_9280_10_OR_LATER(ah) &&
228 (eep->baseEepHeader.version & 0xff) > 0x0a &&
229 eep->baseEepHeader.pwdclkind == 0)
230 ah->need_an_top2_fixup = 1;
231
b5aec950
S		 232 return 0;
233}
234
235static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
236 enum eeprom_param param)
237{
238 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
239 struct modal_eep_header *pModal = eep->modalHeader;
240 struct base_eep_header *pBase = &eep->baseEepHeader;
241
242 switch (param) {
243 case EEP_NFTHRESH_5:
244 return pModal[0].noiseFloorThreshCh[0];
245 case EEP_NFTHRESH_2:
246 return pModal[1].noiseFloorThreshCh[0];
49101676 247 case EEP_MAC_LSW:
b5aec950 248 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
49101676 249 case EEP_MAC_MID:
b5aec950 250 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
49101676 251 case EEP_MAC_MSW:
b5aec950
S		 252 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
253 case EEP_REG_0:
254 return pBase->regDmn[0];
255 case EEP_REG_1:
256 return pBase->regDmn[1];
257 case EEP_OP_CAP:
258 return pBase->deviceCap;
259 case EEP_OP_MODE:
260 return pBase->opCapFlags;
261 case EEP_RF_SILENT:
262 return pBase->rfSilent;
263 case EEP_OB_5:
264 return pModal[0].ob;
265 case EEP_DB_5:
266 return pModal[0].db;
267 case EEP_OB_2:
268 return pModal[1].ob;
269 case EEP_DB_2:
270 return pModal[1].db;
271 case EEP_MINOR_REV:
272 return AR5416_VER_MASK;
273 case EEP_TX_MASK:
274 return pBase->txMask;
275 case EEP_RX_MASK:
276 return pBase->rxMask;
5b75d0fc
FF		 277 case EEP_FSTCLK_5G:
278 return pBase->fastClk5g;
b5aec950
S		 279 case EEP_RXGAIN_TYPE:
280 return pBase->rxGainType;
281 case EEP_TXGAIN_TYPE:
282 return pBase->txGainType;
283 case EEP_OL_PWRCTRL:
284 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
285 return pBase->openLoopPwrCntl ? true : false;
286 else
287 return false;
288 case EEP_RC_CHAIN_MASK:
289 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
290 return pBase->rcChainMask;
291 else
292 return 0;
293 case EEP_DAC_HPWR_5G:
294 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
295 return pBase->dacHiPwrMode_5G;
296 else
297 return 0;
298 case EEP_FRAC_N_5G:
299 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
300 return pBase->frac_n_5g;
301 else
302 return 0;
e41f0bfc
SB		 303 case EEP_PWR_TABLE_OFFSET:
304 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
305 return pBase->pwr_table_offset;
306 else
307 return AR5416_PWR_TABLE_OFFSET_DB;
b5aec950
S		 308 default:
309 return 0;
310 }
311}
312
313static void ath9k_hw_def_set_gain(struct ath_hw *ah,
314 struct modal_eep_header *pModal,
315 struct ar5416_eeprom_def *eep,
316 u8 txRxAttenLocal, int regChainOffset, int i)
317{
318 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
319 txRxAttenLocal = pModal->txRxAttenCh[i];
320
321 if (AR_SREV_9280_10_OR_LATER(ah)) {
322 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
323 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
324 pModal->bswMargin[i]);
325 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
326 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
327 pModal->bswAtten[i]);
328 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
329 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
330 pModal->xatten2Margin[i]);
331 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
332 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
333 pModal->xatten2Db[i]);
334 } else {
335 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
336 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
337 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
338 | SM(pModal-> bswMargin[i],
339 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
340 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
341 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
342 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
343 | SM(pModal->bswAtten[i],
344 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
345 }
346 }
347
348 if (AR_SREV_9280_10_OR_LATER(ah)) {
349 REG_RMW_FIELD(ah,
350 AR_PHY_RXGAIN + regChainOffset,
351 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
352 REG_RMW_FIELD(ah,
353 AR_PHY_RXGAIN + regChainOffset,
354 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
355 } else {
356 REG_WRITE(ah,
357 AR_PHY_RXGAIN + regChainOffset,
358 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
359 ~AR_PHY_RXGAIN_TXRX_ATTEN)
360 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
361 REG_WRITE(ah,
362 AR_PHY_GAIN_2GHZ + regChainOffset,
363 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
364 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
365 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
366 }
367}
368
369static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
370 struct ath9k_channel *chan)
371{
372 struct modal_eep_header *pModal;
373 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
374 int i, regChainOffset;
375 u8 txRxAttenLocal;
376
377 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
378 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
379
380 REG_WRITE(ah, AR_PHY_SWITCH_COM,
381 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
382
383 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
384 if (AR_SREV_9280(ah)) {
385 if (i >= 2)
386 break;
387 }
388
389 if (AR_SREV_5416_20_OR_LATER(ah) &&
390 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
391 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
392 else
393 regChainOffset = i * 0x1000;
394
395 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
396 pModal->antCtrlChain[i]);
397
398 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
399 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
400 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
401 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
402 SM(pModal->iqCalICh[i],
403 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
404 SM(pModal->iqCalQCh[i],
405 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
406
407 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
408 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
409 regChainOffset, i);
410 }
411
412 if (AR_SREV_9280_10_OR_LATER(ah)) {
413 if (IS_CHAN_2GHZ(chan)) {
414 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
415 AR_AN_RF2G1_CH0_OB,
416 AR_AN_RF2G1_CH0_OB_S,
417 pModal->ob);
418 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
419 AR_AN_RF2G1_CH0_DB,
420 AR_AN_RF2G1_CH0_DB_S,
421 pModal->db);
422 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
423 AR_AN_RF2G1_CH1_OB,
424 AR_AN_RF2G1_CH1_OB_S,
425 pModal->ob_ch1);
426 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
427 AR_AN_RF2G1_CH1_DB,
428 AR_AN_RF2G1_CH1_DB_S,
429 pModal->db_ch1);
430 } else {
431 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
432 AR_AN_RF5G1_CH0_OB5,
433 AR_AN_RF5G1_CH0_OB5_S,
434 pModal->ob);
435 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
436 AR_AN_RF5G1_CH0_DB5,
437 AR_AN_RF5G1_CH0_DB5_S,
438 pModal->db);
439 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
440 AR_AN_RF5G1_CH1_OB5,
441 AR_AN_RF5G1_CH1_OB5_S,
442 pModal->ob_ch1);
443 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
444 AR_AN_RF5G1_CH1_DB5,
445 AR_AN_RF5G1_CH1_DB5_S,
446 pModal->db_ch1);
447 }
448 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
449 AR_AN_TOP2_XPABIAS_LVL,
450 AR_AN_TOP2_XPABIAS_LVL_S,
451 pModal->xpaBiasLvl);
452 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
453 AR_AN_TOP2_LOCALBIAS,
454 AR_AN_TOP2_LOCALBIAS_S,
455 pModal->local_bias);
456 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
457 pModal->force_xpaon);
458 }
459
460 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
461 pModal->switchSettling);
462 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
463 pModal->adcDesiredSize);
464
465 if (!AR_SREV_9280_10_OR_LATER(ah))
466 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
467 AR_PHY_DESIRED_SZ_PGA,
468 pModal->pgaDesiredSize);
469
470 REG_WRITE(ah, AR_PHY_RF_CTL4,
471 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
472 | SM(pModal->txEndToXpaOff,
473 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
474 | SM(pModal->txFrameToXpaOn,
475 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
476 | SM(pModal->txFrameToXpaOn,
477 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
478
479 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
480 pModal->txEndToRxOn);
481
482 if (AR_SREV_9280_10_OR_LATER(ah)) {
483 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
484 pModal->thresh62);
485 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
486 AR_PHY_EXT_CCA0_THRESH62,
487 pModal->thresh62);
488 } else {
489 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
490 pModal->thresh62);
491 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
492 AR_PHY_EXT_CCA_THRESH62,
493 pModal->thresh62);
494 }
495
496 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
497 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
498 AR_PHY_TX_END_DATA_START,
499 pModal->txFrameToDataStart);
500 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
501 pModal->txFrameToPaOn);
502 }
503
504 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
505 if (IS_CHAN_HT40(chan))
506 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
507 AR_PHY_SETTLING_SWITCH,
508 pModal->swSettleHt40);
509 }
510
511 if (AR_SREV_9280_20_OR_LATER(ah) &&
512 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
513 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
514 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
515 pModal->miscBits);
516
517
518 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
519 if (IS_CHAN_2GHZ(chan))
520 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
521 eep->baseEepHeader.dacLpMode);
522 else if (eep->baseEepHeader.dacHiPwrMode_5G)
523 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
524 else
525 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
526 eep->baseEepHeader.dacLpMode);
527
d865ca6c
SB		 528 udelay(100);
529
b5aec950
S		 530 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
531 pModal->miscBits >> 2);
532
533 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
534 AR_PHY_TX_DESIRED_SCALE_CCK,
535 eep->baseEepHeader.desiredScaleCCK);
536 }
537}
538
539static void ath9k_hw_def_set_addac(struct ath_hw *ah,
540 struct ath9k_channel *chan)
541{
542#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
543 struct modal_eep_header *pModal;
544 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
545 u8 biaslevel;
546
547 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
548 return;
549
550 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
551 return;
552
553 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
554
555 if (pModal->xpaBiasLvl != 0xff) {
556 biaslevel = pModal->xpaBiasLvl;
557 } else {
558 u16 resetFreqBin, freqBin, freqCount = 0;
559 struct chan_centers centers;
560
561 ath9k_hw_get_channel_centers(ah, chan, &centers);
562
563 resetFreqBin = FREQ2FBIN(centers.synth_center,
564 IS_CHAN_2GHZ(chan));
565 freqBin = XPA_LVL_FREQ(0) & 0xff;
566 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
567
568 freqCount++;
569
570 while (freqCount < 3) {
571 if (XPA_LVL_FREQ(freqCount) == 0x0)
572 break;
573
574 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
575 if (resetFreqBin >= freqBin)
576 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
577 else
578 break;
579 freqCount++;
580 }
581 }
582
583 if (IS_CHAN_2GHZ(chan)) {
584 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
585 7, 1) & (~0x18)) | biaslevel << 3;
586 } else {
587 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
588 6, 1) & (~0xc0)) | biaslevel << 6;
589 }
590#undef XPA_LVL_FREQ
591}
592
593static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
594 struct ath9k_channel *chan,
595 struct cal_data_per_freq *pRawDataSet,
596 u8 *bChans, u16 availPiers,
597 u16 tPdGainOverlap, int16_t *pMinCalPower,
598 u16 *pPdGainBoundaries, u8 *pPDADCValues,
599 u16 numXpdGains)
600{
601 int i, j, k;
602 int16_t ss;
603 u16 idxL = 0, idxR = 0, numPiers;
604 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
605 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
606 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
607 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
608 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
609 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
610
611 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
612 u8 minPwrT4[AR5416_NUM_PD_GAINS];
613 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
614 int16_t vpdStep;
615 int16_t tmpVal;
616 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
617 bool match;
618 int16_t minDelta = 0;
619 struct chan_centers centers;
620
621 ath9k_hw_get_channel_centers(ah, chan, &centers);
622
623 for (numPiers = 0; numPiers < availPiers; numPiers++) {
624 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
625 break;
626 }
627
628 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
629 IS_CHAN_2GHZ(chan)),
630 bChans, numPiers, &idxL, &idxR);
631
632 if (match) {
633 for (i = 0; i < numXpdGains; i++) {
634 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
635 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
636 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
637 pRawDataSet[idxL].pwrPdg[i],
638 pRawDataSet[idxL].vpdPdg[i],
639 AR5416_PD_GAIN_ICEPTS,
640 vpdTableI[i]);
641 }
642 } else {
643 for (i = 0; i < numXpdGains; i++) {
644 pVpdL = pRawDataSet[idxL].vpdPdg[i];
645 pPwrL = pRawDataSet[idxL].pwrPdg[i];
646 pVpdR = pRawDataSet[idxR].vpdPdg[i];
647 pPwrR = pRawDataSet[idxR].pwrPdg[i];
648
649 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
650
651 maxPwrT4[i] =
652 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
653 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
654
655
656 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
657 pPwrL, pVpdL,
658 AR5416_PD_GAIN_ICEPTS,
659 vpdTableL[i]);
660 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
661 pPwrR, pVpdR,
662 AR5416_PD_GAIN_ICEPTS,
663 vpdTableR[i]);
664
665 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
666 vpdTableI[i][j] =
667 (u8)(ath9k_hw_interpolate((u16)
668 FREQ2FBIN(centers.
669 synth_center,
670 IS_CHAN_2GHZ
671 (chan)),
672 bChans[idxL], bChans[idxR],
673 vpdTableL[i][j], vpdTableR[i][j]));
674 }
675 }
676 }
677
678 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
679
680 k = 0;
681
682 for (i = 0; i < numXpdGains; i++) {
683 if (i == (numXpdGains - 1))
684 pPdGainBoundaries[i] =
685 (u16)(maxPwrT4[i] / 2);
686 else
687 pPdGainBoundaries[i] =
688 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
689
690 pPdGainBoundaries[i] =
691 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
692
693 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
694 minDelta = pPdGainBoundaries[0] - 23;
695 pPdGainBoundaries[0] = 23;
696 } else {
697 minDelta = 0;
698 }
699
700 if (i == 0) {
701 if (AR_SREV_9280_10_OR_LATER(ah))
702 ss = (int16_t)(0 - (minPwrT4[i] / 2));
703 else
704 ss = 0;
705 } else {
706 ss = (int16_t)((pPdGainBoundaries[i - 1] -
707 (minPwrT4[i] / 2)) -
708 tPdGainOverlap + 1 + minDelta);
709 }
710 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
711 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
712
713 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
714 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
715 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
716 ss++;
717 }
718
719 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
720 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
721 (minPwrT4[i] / 2));
722 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
723 tgtIndex : sizeCurrVpdTable;
724
725 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
726 pPDADCValues[k++] = vpdTableI[i][ss++];
727 }
728
729 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
730 vpdTableI[i][sizeCurrVpdTable - 2]);
731 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
732
733 if (tgtIndex > maxIndex) {
734 while ((ss <= tgtIndex) &&
735 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
736 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
737 (ss - maxIndex + 1) * vpdStep));
738 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
739 255 : tmpVal);
740 ss++;
741 }
742 }
743 }
744
745 while (i < AR5416_PD_GAINS_IN_MASK) {
746 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
747 i++;
748 }
749
750 while (k < AR5416_NUM_PDADC_VALUES) {
751 pPDADCValues[k] = pPDADCValues[k - 1];
752 k++;
753 }
754
755 return;
756}
757
e41f0bfc
SB		 758static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
759 u16 *gb,
760 u16 numXpdGain,
761 u16 pdGainOverlap_t2,
762 int8_t pwr_table_offset,
763 int16_t *diff)
764
765{
766 u16 k;
767
768 /* Prior to writing the boundaries or the pdadc vs. power table
769 * into the chip registers the default starting point on the pdadc
770 * vs. power table needs to be checked and the curve boundaries
771 * adjusted accordingly
772 */
773 if (AR_SREV_9280_20_OR_LATER(ah)) {
774 u16 gb_limit;
775
776 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
777 /* get the difference in dB */
778 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
779 /* get the number of half dB steps */
780 *diff *= 2;
781 /* change the original gain boundary settings
782 * by the number of half dB steps
783 */
784 for (k = 0; k < numXpdGain; k++)
785 gb[k] = (u16)(gb[k] - *diff);
786 }
787 /* Because of a hardware limitation, ensure the gain boundary
788 * is not larger than (63 - overlap)
789 */
790 gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
791
792 for (k = 0; k < numXpdGain; k++)
793 gb[k] = (u16)min(gb_limit, gb[k]);
794 }
795
796 return *diff;
797}
798
799static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
800 int8_t pwr_table_offset,
801 int16_t diff,
802 u8 *pdadcValues)
803{
804#define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
805 u16 k;
806
807 /* If this is a board that has a pwrTableOffset that differs from
808 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
809 * pdadc vs pwr table needs to be adjusted prior to writing to the
810 * chip.
811 */
812 if (AR_SREV_9280_20_OR_LATER(ah)) {
813 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
814 /* shift the table to start at the new offset */
815 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
816 pdadcValues[k] = pdadcValues[k + diff];
817 }
818
819 /* fill the back of the table */
820 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
821 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
822 }
823 }
824 }
825#undef NUM_PDADC
826}
827
b5aec950
S		 828static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
829 struct ath9k_channel *chan,
830 int16_t *pTxPowerIndexOffset)
831{
832#define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
833#define SM_PDGAIN_B(x, y) \
834 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
c46917bb 835 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 836 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
837 struct cal_data_per_freq *pRawDataset;
838 u8 *pCalBChans = NULL;
839 u16 pdGainOverlap_t2;
840 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
841 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
842 u16 numPiers, i, j;
e41f0bfc 843 int16_t tMinCalPower, diff = 0;
b5aec950
S		 844 u16 numXpdGain, xpdMask;
845 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
846 u32 reg32, regOffset, regChainOffset;
847 int16_t modalIdx;
e41f0bfc 848 int8_t pwr_table_offset;
b5aec950
S		 849
850 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
851 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
852
e41f0bfc
SB		 853 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
854
b5aec950
S		 855 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
856 AR5416_EEP_MINOR_VER_2) {
857 pdGainOverlap_t2 =
858 pEepData->modalHeader[modalIdx].pdGainOverlap;
859 } else {
860 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
861 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
862 }
863
864 if (IS_CHAN_2GHZ(chan)) {
865 pCalBChans = pEepData->calFreqPier2G;
866 numPiers = AR5416_NUM_2G_CAL_PIERS;
867 } else {
868 pCalBChans = pEepData->calFreqPier5G;
869 numPiers = AR5416_NUM_5G_CAL_PIERS;
870 }
871
872 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
873 pRawDataset = pEepData->calPierData2G[0];
874 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
875 pRawDataset)->vpdPdg[0][0];
876 }
877
878 numXpdGain = 0;
879
880 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
881 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
882 if (numXpdGain >= AR5416_NUM_PD_GAINS)
883 break;
884 xpdGainValues[numXpdGain] =
885 (u16)(AR5416_PD_GAINS_IN_MASK - i);
886 numXpdGain++;
887 }
888 }
889
890 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
891 (numXpdGain - 1) & 0x3);
892 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
893 xpdGainValues[0]);
894 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
895 xpdGainValues[1]);
896 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
897 xpdGainValues[2]);
898
899 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
900 if (AR_SREV_5416_20_OR_LATER(ah) &&
901 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
902 (i != 0)) {
903 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
904 } else
905 regChainOffset = i * 0x1000;
906
907 if (pEepData->baseEepHeader.txMask & (1 << i)) {
908 if (IS_CHAN_2GHZ(chan))
909 pRawDataset = pEepData->calPierData2G[i];
910 else
911 pRawDataset = pEepData->calPierData5G[i];
912
913
914 if (OLC_FOR_AR9280_20_LATER) {
915 u8 pcdacIdx;
916 u8 txPower;
917
918 ath9k_get_txgain_index(ah, chan,
919 (struct calDataPerFreqOpLoop *)pRawDataset,
920 pCalBChans, numPiers, &txPower, &pcdacIdx);
921 ath9k_olc_get_pdadcs(ah, pcdacIdx,
922 txPower/2, pdadcValues);
923 } else {
924 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
925 chan, pRawDataset,
926 pCalBChans, numPiers,
927 pdGainOverlap_t2,
928 &tMinCalPower,
929 gainBoundaries,
930 pdadcValues,
931 numXpdGain);
932 }
933
e41f0bfc
SB		 934 diff = ath9k_change_gain_boundary_setting(ah,
935 gainBoundaries,
936 numXpdGain,
937 pdGainOverlap_t2,
938 pwr_table_offset,
939 &diff);
940
b5aec950
S		 941 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
942 if (OLC_FOR_AR9280_20_LATER) {
943 REG_WRITE(ah,
944 AR_PHY_TPCRG5 + regChainOffset,
945 SM(0x6,
946 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
947 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
948 SM_PD_GAIN(3) | SM_PD_GAIN(4));
949 } else {
950 REG_WRITE(ah,
951 AR_PHY_TPCRG5 + regChainOffset,
952 SM(pdGainOverlap_t2,
953 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
954 SM_PDGAIN_B(0, 1) |
955 SM_PDGAIN_B(1, 2) |
956 SM_PDGAIN_B(2, 3) |
957 SM_PDGAIN_B(3, 4));
958 }
959 }
960
e41f0bfc
SB		 961
962 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
963 diff, pdadcValues);
964
b5aec950
S		 965 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
966 for (j = 0; j < 32; j++) {
967 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
968 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
969 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
970 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
971 REG_WRITE(ah, regOffset, reg32);
972
c46917bb
LR		 973 ath_print(common, ATH_DBG_EEPROM,
974 "PDADC (%d,%4x): %4.4x %8.8x\n",
975 i, regChainOffset, regOffset,
976 reg32);
977 ath_print(common, ATH_DBG_EEPROM,
978 "PDADC: Chain %d | PDADC %3d "
979 "Value %3d | PDADC %3d Value %3d | "
980 "PDADC %3d Value %3d | PDADC %3d "
981 "Value %3d |\n",
982 i, 4 * j, pdadcValues[4 * j],
983 4 * j + 1, pdadcValues[4 * j + 1],
984 4 * j + 2, pdadcValues[4 * j + 2],
985 4 * j + 3,
986 pdadcValues[4 * j + 3]);
b5aec950
S		 987
988 regOffset += 4;
989 }
990 }
991 }
992
993 *pTxPowerIndexOffset = 0;
994#undef SM_PD_GAIN
995#undef SM_PDGAIN_B
996}
997
998static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
999 struct ath9k_channel *chan,
1000 int16_t *ratesArray,
1001 u16 cfgCtl,
1002 u16 AntennaReduction,
1003 u16 twiceMaxRegulatoryPower,
1004 u16 powerLimit)
1005{
1006#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
d865ca6c 1007#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
b5aec950 1008
608b88cb 1009 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 1010 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1011 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1012 static const u16 tpScaleReductionTable[5] =
1013 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1014
1015 int i;
1016 int16_t twiceLargestAntenna;
1017 struct cal_ctl_data *rep;
1018 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1019 0, { 0, 0, 0, 0}
1020 };
1021 struct cal_target_power_leg targetPowerOfdmExt = {
1022 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1023 0, { 0, 0, 0, 0 }
1024 };
1025 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1026 0, {0, 0, 0, 0}
1027 };
1028 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1029 u16 ctlModesFor11a[] =
1030 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
1031 u16 ctlModesFor11g[] =
1032 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
1033 CTL_2GHT40
1034 };
1035 u16 numCtlModes, *pCtlMode, ctlMode, freq;
1036 struct chan_centers centers;
1037 int tx_chainmask;
1038 u16 twiceMinEdgePower;
1039
1040 tx_chainmask = ah->txchainmask;
1041
1042 ath9k_hw_get_channel_centers(ah, chan, &centers);
1043
1044 twiceLargestAntenna = max(
1045 pEepData->modalHeader
1046 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1047 pEepData->modalHeader
1048 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1049
1050 twiceLargestAntenna = max((u8)twiceLargestAntenna,
1051 pEepData->modalHeader
1052 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1053
1054 twiceLargestAntenna = (int16_t)min(AntennaReduction -
1055 twiceLargestAntenna, 0);
1056
1057 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1058
608b88cb 1059 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
b5aec950 1060 maxRegAllowedPower -=
608b88cb 1061 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
b5aec950
S		 1062 }
1063
1064 scaledPower = min(powerLimit, maxRegAllowedPower);
1065
1066 switch (ar5416_get_ntxchains(tx_chainmask)) {
1067 case 1:
1068 break;
1069 case 2:
1070 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
1071 break;
1072 case 3:
1073 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
1074 break;
1075 }
1076
1077 scaledPower = max((u16)0, scaledPower);
1078
1079 if (IS_CHAN_2GHZ(chan)) {
1080 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1081 SUB_NUM_CTL_MODES_AT_2G_40;
1082 pCtlMode = ctlModesFor11g;
1083
1084 ath9k_hw_get_legacy_target_powers(ah, chan,
1085 pEepData->calTargetPowerCck,
1086 AR5416_NUM_2G_CCK_TARGET_POWERS,
1087 &targetPowerCck, 4, false);
1088 ath9k_hw_get_legacy_target_powers(ah, chan,
1089 pEepData->calTargetPower2G,
1090 AR5416_NUM_2G_20_TARGET_POWERS,
1091 &targetPowerOfdm, 4, false);
1092 ath9k_hw_get_target_powers(ah, chan,
1093 pEepData->calTargetPower2GHT20,
1094 AR5416_NUM_2G_20_TARGET_POWERS,
1095 &targetPowerHt20, 8, false);
1096
1097 if (IS_CHAN_HT40(chan)) {
1098 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1099 ath9k_hw_get_target_powers(ah, chan,
1100 pEepData->calTargetPower2GHT40,
1101 AR5416_NUM_2G_40_TARGET_POWERS,
1102 &targetPowerHt40, 8, true);
1103 ath9k_hw_get_legacy_target_powers(ah, chan,
1104 pEepData->calTargetPowerCck,
1105 AR5416_NUM_2G_CCK_TARGET_POWERS,
1106 &targetPowerCckExt, 4, true);
1107 ath9k_hw_get_legacy_target_powers(ah, chan,
1108 pEepData->calTargetPower2G,
1109 AR5416_NUM_2G_20_TARGET_POWERS,
1110 &targetPowerOfdmExt, 4, true);
1111 }
1112 } else {
1113 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1114 SUB_NUM_CTL_MODES_AT_5G_40;
1115 pCtlMode = ctlModesFor11a;
1116
1117 ath9k_hw_get_legacy_target_powers(ah, chan,
1118 pEepData->calTargetPower5G,
1119 AR5416_NUM_5G_20_TARGET_POWERS,
1120 &targetPowerOfdm, 4, false);
1121 ath9k_hw_get_target_powers(ah, chan,
1122 pEepData->calTargetPower5GHT20,
1123 AR5416_NUM_5G_20_TARGET_POWERS,
1124 &targetPowerHt20, 8, false);
1125
1126 if (IS_CHAN_HT40(chan)) {
1127 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1128 ath9k_hw_get_target_powers(ah, chan,
1129 pEepData->calTargetPower5GHT40,
1130 AR5416_NUM_5G_40_TARGET_POWERS,
1131 &targetPowerHt40, 8, true);
1132 ath9k_hw_get_legacy_target_powers(ah, chan,
1133 pEepData->calTargetPower5G,
1134 AR5416_NUM_5G_20_TARGET_POWERS,
1135 &targetPowerOfdmExt, 4, true);
1136 }
1137 }
1138
1139 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1140 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1141 (pCtlMode[ctlMode] == CTL_2GHT40);
1142 if (isHt40CtlMode)
1143 freq = centers.synth_center;
1144 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1145 freq = centers.ext_center;
1146 else
1147 freq = centers.ctl_center;
1148
1149 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1150 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1151 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1152
1153 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1154 if ((((cfgCtl & ~CTL_MODE_M) |
1155 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1156 pEepData->ctlIndex[i]) ||
1157 (((cfgCtl & ~CTL_MODE_M) |
1158 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1159 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1160 rep = &(pEepData->ctlData[i]);
1161
1162 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1163 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1164 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1165
1166 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1167 twiceMaxEdgePower = min(twiceMaxEdgePower,
1168 twiceMinEdgePower);
1169 } else {
1170 twiceMaxEdgePower = twiceMinEdgePower;
1171 break;
1172 }
1173 }
1174 }
1175
1176 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1177
1178 switch (pCtlMode[ctlMode]) {
1179 case CTL_11B:
1180 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1181 targetPowerCck.tPow2x[i] =
1182 min((u16)targetPowerCck.tPow2x[i],
1183 minCtlPower);
1184 }
1185 break;
1186 case CTL_11A:
1187 case CTL_11G:
1188 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1189 targetPowerOfdm.tPow2x[i] =
1190 min((u16)targetPowerOfdm.tPow2x[i],
1191 minCtlPower);
1192 }
1193 break;
1194 case CTL_5GHT20:
1195 case CTL_2GHT20:
1196 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1197 targetPowerHt20.tPow2x[i] =
1198 min((u16)targetPowerHt20.tPow2x[i],
1199 minCtlPower);
1200 }
1201 break;
1202 case CTL_11B_EXT:
1203 targetPowerCckExt.tPow2x[0] = min((u16)
1204 targetPowerCckExt.tPow2x[0],
1205 minCtlPower);
1206 break;
1207 case CTL_11A_EXT:
1208 case CTL_11G_EXT:
1209 targetPowerOfdmExt.tPow2x[0] = min((u16)
1210 targetPowerOfdmExt.tPow2x[0],
1211 minCtlPower);
1212 break;
1213 case CTL_5GHT40:
1214 case CTL_2GHT40:
1215 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1216 targetPowerHt40.tPow2x[i] =
1217 min((u16)targetPowerHt40.tPow2x[i],
1218 minCtlPower);
1219 }
1220 break;
1221 default:
1222 break;
1223 }
1224 }
1225
1226 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1227 ratesArray[rate18mb] = ratesArray[rate24mb] =
1228 targetPowerOfdm.tPow2x[0];
1229 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1230 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1231 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1232 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1233
1234 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1235 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1236
1237 if (IS_CHAN_2GHZ(chan)) {
1238 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1239 ratesArray[rate2s] = ratesArray[rate2l] =
1240 targetPowerCck.tPow2x[1];
1241 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1242 targetPowerCck.tPow2x[2];
1243 ratesArray[rate11s] = ratesArray[rate11l] =
1244 targetPowerCck.tPow2x[3];
1245 }
1246 if (IS_CHAN_HT40(chan)) {
1247 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1248 ratesArray[rateHt40_0 + i] =
1249 targetPowerHt40.tPow2x[i];
1250 }
1251 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1252 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1253 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1254 if (IS_CHAN_2GHZ(chan)) {
1255 ratesArray[rateExtCck] =
1256 targetPowerCckExt.tPow2x[0];
1257 }
1258 }
1259}
1260
1261static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1262 struct ath9k_channel *chan,
1263 u16 cfgCtl,
1264 u8 twiceAntennaReduction,
1265 u8 twiceMaxRegulatoryPower,
1266 u8 powerLimit)
1267{
1268#define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
608b88cb 1269 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 1270 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1271 struct modal_eep_header *pModal =
1272 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1273 int16_t ratesArray[Ar5416RateSize];
1274 int16_t txPowerIndexOffset = 0;
1275 u8 ht40PowerIncForPdadc = 2;
1276 int i, cck_ofdm_delta = 0;
1277
1278 memset(ratesArray, 0, sizeof(ratesArray));
1279
1280 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1281 AR5416_EEP_MINOR_VER_2) {
1282 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1283 }
1284
1285 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1286 &ratesArray[0], cfgCtl,
1287 twiceAntennaReduction,
1288 twiceMaxRegulatoryPower,
1289 powerLimit);
1290
1291 ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1292
1293 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1294 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1295 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1296 ratesArray[i] = AR5416_MAX_RATE_POWER;
1297 }
1298
1299 if (AR_SREV_9280_10_OR_LATER(ah)) {
e41f0bfc
SB		 1300 for (i = 0; i < Ar5416RateSize; i++) {
1301 int8_t pwr_table_offset;
1302
1303 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1304 EEP_PWR_TABLE_OFFSET);
1305 ratesArray[i] -= pwr_table_offset * 2;
1306 }
b5aec950
S		 1307 }
1308
1309 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1310 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1311 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1312 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1313 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1314 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1315 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1316 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1317 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1318 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1319
1320 if (IS_CHAN_2GHZ(chan)) {
1321 if (OLC_FOR_AR9280_20_LATER) {
1322 cck_ofdm_delta = 2;
1323 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1324 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1325 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1326 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1327 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1328 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1329 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1330 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1331 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1332 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1333 } else {
1334 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1335 ATH9K_POW_SM(ratesArray[rate2s], 24)
1336 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1337 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1338 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1339 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1340 ATH9K_POW_SM(ratesArray[rate11s], 24)
1341 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1342 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1343 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1344 }
1345 }
1346
1347 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1348 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1349 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1350 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1351 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1352 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1353 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1354 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1355 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1356 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1357
1358 if (IS_CHAN_HT40(chan)) {
1359 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1360 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1361 ht40PowerIncForPdadc, 24)
1362 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1363 ht40PowerIncForPdadc, 16)
1364 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1365 ht40PowerIncForPdadc, 8)
1366 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1367 ht40PowerIncForPdadc, 0));
1368 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1369 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1370 ht40PowerIncForPdadc, 24)
1371 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1372 ht40PowerIncForPdadc, 16)
1373 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1374 ht40PowerIncForPdadc, 8)
1375 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1376 ht40PowerIncForPdadc, 0));
1377 if (OLC_FOR_AR9280_20_LATER) {
1378 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1379 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1380 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1381 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1382 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1383 } else {
1384 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1385 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1386 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1387 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1388 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1389 }
1390 }
1391
1392 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1393 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1394 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1395
1396 i = rate6mb;
1397
1398 if (IS_CHAN_HT40(chan))
1399 i = rateHt40_0;
1400 else if (IS_CHAN_HT20(chan))
1401 i = rateHt20_0;
1402
1403 if (AR_SREV_9280_10_OR_LATER(ah))
608b88cb 1404 regulatory->max_power_level =
e41f0bfc 1405 ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
b5aec950 1406 else
608b88cb 1407 regulatory->max_power_level = ratesArray[i];
b5aec950
S		 1408
1409 switch(ar5416_get_ntxchains(ah->txchainmask)) {
1410 case 1:
1411 break;
1412 case 2:
608b88cb 1413 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
b5aec950
S		 1414 break;
1415 case 3:
608b88cb 1416 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
b5aec950
S		 1417 break;
1418 default:
c46917bb
LR		 1419 ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1420 "Invalid chainmask configuration\n");
b5aec950
S		 1421 break;
1422 }
1423}
1424
1425static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1426 enum ieee80211_band freq_band)
1427{
1428 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1429 struct modal_eep_header *pModal =
1430 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
1431 struct base_eep_header *pBase = &eep->baseEepHeader;
1432 u8 num_ant_config;
1433
1434 num_ant_config = 1;
1435
1436 if (pBase->version >= 0x0E0D)
1437 if (pModal->useAnt1)
1438 num_ant_config += 1;
1439
1440 return num_ant_config;
1441}
1442
1443static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1444 struct ath9k_channel *chan)
1445{
1446 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1447 struct modal_eep_header *pModal =
1448 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1449
1450 return pModal->antCtrlCommon & 0xFFFF;
1451}
1452
1453static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1454{
1455#define EEP_DEF_SPURCHAN \
1456 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
c46917bb 1457 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 1458
1459 u16 spur_val = AR_NO_SPUR;
1460
c46917bb
LR		 1461 ath_print(common, ATH_DBG_ANI,
1462 "Getting spur idx %d is2Ghz. %d val %x\n",
1463 i, is2GHz, ah->config.spurchans[i][is2GHz]);
b5aec950
S		 1464
1465 switch (ah->config.spurmode) {
1466 case SPUR_DISABLE:
1467 break;
1468 case SPUR_ENABLE_IOCTL:
1469 spur_val = ah->config.spurchans[i][is2GHz];
c46917bb
LR		 1470 ath_print(common, ATH_DBG_ANI,
1471 "Getting spur val from new loc. %d\n", spur_val);
b5aec950
S		 1472 break;
1473 case SPUR_ENABLE_EEPROM:
1474 spur_val = EEP_DEF_SPURCHAN;
1475 break;
1476 }
1477
1478 return spur_val;
1479
1480#undef EEP_DEF_SPURCHAN
1481}
1482
1483const struct eeprom_ops eep_def_ops = {
1484 .check_eeprom = ath9k_hw_def_check_eeprom,
1485 .get_eeprom = ath9k_hw_def_get_eeprom,
1486 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1487 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1488 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
1489 .get_num_ant_config = ath9k_hw_def_get_num_ant_config,
1490 .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1491 .set_board_values = ath9k_hw_def_set_board_values,
1492 .set_addac = ath9k_hw_def_set_addac,
1493 .set_txpower = ath9k_hw_def_set_txpower,
1494 .get_spur_channel = ath9k_hw_def_get_spur_channel
1495};
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