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mac80211: fix scan locking wrt. hw scan
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
f078f209
LR		 19#include <asm/unaligned.h>
20
af03abec 21#include "hw.h"
d70357d5 22#include "hw-ops.h"
cfe8cba9 23#include "rc.h"
b622a720 24#include "ar9003_mac.h"
f078f209 25
cbe61d8a 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 27
7322fd19
LR		 28MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static int __init ath9k_init(void)
34{
35 return 0;
36}
37module_init(ath9k_init);
38
39static void __exit ath9k_exit(void)
40{
41 return;
42}
43module_exit(ath9k_exit);
44
d70357d5
LR		 45/* Private hardware callbacks */
46
47static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48{
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50}
51
52static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55}
56
57static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
58{
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
60
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
62}
63
64773964
LR		 64static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan)
66{
67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
68}
69
991312d8
LR		 70static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
71{
72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
73 return;
74
75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
76}
77
e36b27af
LR		 78static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
79{
80 /* You will not have this callback if using the old ANI */
81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
82 return;
83
84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
85}
86
f1dc5600
S		 87/********************/
88/* Helper Functions */
89/********************/
f078f209 90
cbe61d8a 91static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 92{
b002a4a9 93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 94
2660b81a 95 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 96 return usecs *ATH9K_CLOCK_RATE_CCK;
97 if (conf->channel->band == IEEE80211_BAND_2GHZ)
98 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
e5553724
VT		 99
100 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
101 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
102 else
103 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 104}
105
cbe61d8a 106static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 107{
b002a4a9 108 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 109
4febf7b8 110 if (conf_is_ht40(conf))
f1dc5600
S		 111 return ath9k_hw_mac_clks(ah, usecs) * 2;
112 else
113 return ath9k_hw_mac_clks(ah, usecs);
114}
f078f209 115
0caa7b14 116bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 117{
118 int i;
119
0caa7b14
S		 120 BUG_ON(timeout < AH_TIME_QUANTUM);
121
122 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 123 if ((REG_READ(ah, reg) & mask) == val)
124 return true;
125
126 udelay(AH_TIME_QUANTUM);
127 }
04bd4638 128
c46917bb
LR		 129 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
131 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 132
f1dc5600 133 return false;
f078f209 134}
7322fd19 135EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 136
137u32 ath9k_hw_reverse_bits(u32 val, u32 n)
138{
139 u32 retval;
140 int i;
141
142 for (i = 0, retval = 0; i < n; i++) {
143 retval = (retval << 1) | (val & 1);
144 val >>= 1;
145 }
146 return retval;
147}
148
cbe61d8a 149bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 150 u16 flags, u16 *low,
151 u16 *high)
f078f209 152{
2660b81a 153 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 154
f1dc5600
S		 155 if (flags & CHANNEL_5GHZ) {
156 *low = pCap->low_5ghz_chan;
157 *high = pCap->high_5ghz_chan;
158 return true;
f078f209 159 }
f1dc5600
S		 160 if ((flags & CHANNEL_2GHZ)) {
161 *low = pCap->low_2ghz_chan;
162 *high = pCap->high_2ghz_chan;
163 return true;
164 }
165 return false;
f078f209
LR		 166}
167
cbe61d8a 168u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 169 u8 phy, int kbps,
f1dc5600
S		 170 u32 frameLen, u16 rateix,
171 bool shortPreamble)
f078f209 172{
f1dc5600 173 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 174
f1dc5600
S		 175 if (kbps == 0)
176 return 0;
f078f209 177
545750d3 178 switch (phy) {
46d14a58 179 case WLAN_RC_PHY_CCK:
f1dc5600 180 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 181 if (shortPreamble)
f1dc5600
S		 182 phyTime >>= 1;
183 numBits = frameLen << 3;
184 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
185 break;
46d14a58 186 case WLAN_RC_PHY_OFDM:
2660b81a 187 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 188 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
189 numBits = OFDM_PLCP_BITS + (frameLen << 3);
190 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
191 txTime = OFDM_SIFS_TIME_QUARTER
192 + OFDM_PREAMBLE_TIME_QUARTER
193 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 194 } else if (ah->curchan &&
195 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 196 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
197 numBits = OFDM_PLCP_BITS + (frameLen << 3);
198 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
199 txTime = OFDM_SIFS_TIME_HALF +
200 OFDM_PREAMBLE_TIME_HALF
201 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
202 } else {
203 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
204 numBits = OFDM_PLCP_BITS + (frameLen << 3);
205 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
206 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
207 + (numSymbols * OFDM_SYMBOL_TIME);
208 }
209 break;
210 default:
c46917bb 211 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 212 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 213 txTime = 0;
214 break;
215 }
f078f209 216
f1dc5600
S		 217 return txTime;
218}
7322fd19 219EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 220
cbe61d8a 221void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 222 struct ath9k_channel *chan,
223 struct chan_centers *centers)
f078f209 224{
f1dc5600 225 int8_t extoff;
f078f209 226
f1dc5600
S		 227 if (!IS_CHAN_HT40(chan)) {
228 centers->ctl_center = centers->ext_center =
229 centers->synth_center = chan->channel;
230 return;
f078f209 231 }
f078f209 232
f1dc5600
S		 233 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
234 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
235 centers->synth_center =
236 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
237 extoff = 1;
238 } else {
239 centers->synth_center =
240 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
241 extoff = -1;
242 }
f078f209 243
f1dc5600
S		 244 centers->ctl_center =
245 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 246 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 247 centers->ext_center =
6420014c 248 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 249}
250
f1dc5600
S		 251/******************/
252/* Chip Revisions */
253/******************/
254
cbe61d8a 255static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 256{
f1dc5600 257 u32 val;
f078f209 258
f1dc5600 259 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 260
f1dc5600
S		 261 if (val == 0xFF) {
262 val = REG_READ(ah, AR_SREV);
d535a42a
S		 263 ah->hw_version.macVersion =
264 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
265 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 266 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 267 } else {
268 if (!AR_SREV_9100(ah))
d535a42a 269 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 270
d535a42a 271 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 272
d535a42a 273 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 274 ah->is_pciexpress = true;
f1dc5600 275 }
f078f209
LR		 276}
277
f1dc5600
S		 278/************************************/
279/* HW Attach, Detach, Init Routines */
280/************************************/
281
cbe61d8a 282static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 283{
feed029c 284 if (AR_SREV_9100(ah))
f1dc5600 285 return;
f078f209 286
7d0d0df0
S		 287 ENABLE_REGWRITE_BUFFER(ah);
288
f1dc5600
S		 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 298
f1dc5600 299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
7d0d0df0
S		 300
301 REGWRITE_BUFFER_FLUSH(ah);
302 DISABLE_REGWRITE_BUFFER(ah);
f078f209
LR		 303}
304
1f3f0618 305/* This should work for all families including legacy */
cbe61d8a 306static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 307{
c46917bb 308 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 309 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600
S		 310 u32 regHold[2];
311 u32 patternData[4] = { 0x55555555,
312 0xaaaaaaaa,
313 0x66666666,
314 0x99999999 };
1f3f0618 315 int i, j, loop_max;
f078f209 316
1f3f0618
SB		 317 if (!AR_SREV_9300_20_OR_LATER(ah)) {
318 loop_max = 2;
319 regAddr[1] = AR_PHY_BASE + (8 << 2);
320 } else
321 loop_max = 1;
322
323 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 324 u32 addr = regAddr[i];
325 u32 wrData, rdData;
f078f209 326
f1dc5600
S		 327 regHold[i] = REG_READ(ah, addr);
328 for (j = 0; j < 0x100; j++) {
329 wrData = (j << 16) | j;
330 REG_WRITE(ah, addr, wrData);
331 rdData = REG_READ(ah, addr);
332 if (rdData != wrData) {
c46917bb
LR		 333 ath_print(common, ATH_DBG_FATAL,
334 "address test failed "
335 "addr: 0x%08x - wr:0x%08x != "
336 "rd:0x%08x\n",
337 addr, wrData, rdData);
f1dc5600
S		 338 return false;
339 }
340 }
341 for (j = 0; j < 4; j++) {
342 wrData = patternData[j];
343 REG_WRITE(ah, addr, wrData);
344 rdData = REG_READ(ah, addr);
345 if (wrData != rdData) {
c46917bb
LR		 346 ath_print(common, ATH_DBG_FATAL,
347 "address test failed "
348 "addr: 0x%08x - wr:0x%08x != "
349 "rd:0x%08x\n",
350 addr, wrData, rdData);
f1dc5600
S		 351 return false;
352 }
f078f209 353 }
f1dc5600 354 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 355 }
f1dc5600 356 udelay(100);
cbe61d8a 357
f078f209
LR		 358 return true;
359}
360
b8b0f377 361static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 362{
363 int i;
f078f209 364
2660b81a
S		 365 ah->config.dma_beacon_response_time = 2;
366 ah->config.sw_beacon_response_time = 10;
367 ah->config.additional_swba_backoff = 0;
368 ah->config.ack_6mb = 0x0;
369 ah->config.cwm_ignore_extcca = 0;
370 ah->config.pcie_powersave_enable = 0;
2660b81a 371 ah->config.pcie_clock_req = 0;
2660b81a
S		 372 ah->config.pcie_waen = 0;
373 ah->config.analog_shiftreg = 1;
2660b81a
S		 374 ah->config.ofdm_trig_low = 200;
375 ah->config.ofdm_trig_high = 500;
376 ah->config.cck_trig_high = 200;
377 ah->config.cck_trig_low = 100;
03c72518 378 ah->config.enable_ani = true;
f078f209 379
f1dc5600 380 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 381 ah->config.spurchans[i][0] = AR_NO_SPUR;
382 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 383 }
384
5ffaf8a3
LR		 385 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
386 ah->config.ht_enable = 1;
387 else
388 ah->config.ht_enable = 0;
389
0ce024cb 390 ah->config.rx_intr_mitigation = true;
6a0ec30a 391 ah->config.pcieSerDesWrite = true;
6158425b
LR		 392
393 /*
394 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
395 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
396 * This means we use it for all AR5416 devices, and the few
397 * minor PCI AR9280 devices out there.
398 *
399 * Serialization is required because these devices do not handle
400 * well the case of two concurrent reads/writes due to the latency
401 * involved. During one read/write another read/write can be issued
402 * on another CPU while the previous read/write may still be working
403 * on our hardware, if we hit this case the hardware poops in a loop.
404 * We prevent this by serializing reads and writes.
405 *
406 * This issue is not present on PCI-Express devices or pre-AR5416
407 * devices (legacy, 802.11abg).
408 */
409 if (num_possible_cpus() > 1)
2d6a5e95 410 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 411}
412
50aca25b 413static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 414{
608b88cb
LR		 415 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
416
417 regulatory->country_code = CTRY_DEFAULT;
418 regulatory->power_limit = MAX_RATE_POWER;
419 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
420
d535a42a 421 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 422 ah->hw_version.subvendorid = 0;
f078f209
LR		 423
424 ah->ah_flags = 0;
f078f209
LR		 425 if (!AR_SREV_9100(ah))
426 ah->ah_flags = AH_USE_EEPROM;
427
2660b81a 428 ah->atim_window = 0;
16f2411f
FF		 429 ah->sta_id1_defaults =
430 AR_STA_ID1_CRPT_MIC_ENABLE |
431 AR_STA_ID1_MCAST_KSRCH;
2660b81a
S		 432 ah->beacon_interval = 100;
433 ah->enable_32kHz_clock = DONT_USE_32KHZ;
434 ah->slottime = (u32) -1;
2660b81a 435 ah->globaltxtimeout = (u32) -1;
cbdec975 436 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 437}
438
cbe61d8a 439static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 440{
1510718d 441 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 442 u32 sum;
443 int i;
444 u16 eeval;
49101676 445 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 446
447 sum = 0;
448 for (i = 0; i < 3; i++) {
49101676 449 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 450 sum += eeval;
1510718d
LR		 451 common->macaddr[2 * i] = eeval >> 8;
452 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 453 }
d8baa939 454 if (sum == 0 || sum == 0xffff * 3)
f078f209 455 return -EADDRNOTAVAIL;
f078f209
LR		 456
457 return 0;
458}
459
f637cfd6 460static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 461{
f1dc5600 462 int ecode;
f078f209 463
527d485f
S		 464 if (!AR_SREV_9271(ah)) {
465 if (!ath9k_hw_chip_test(ah))
466 return -ENODEV;
467 }
f078f209 468
ebd5a14a
LR		 469 if (!AR_SREV_9300_20_OR_LATER(ah)) {
470 ecode = ar9002_hw_rf_claim(ah);
471 if (ecode != 0)
472 return ecode;
473 }
f078f209 474
f637cfd6 475 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 476 if (ecode != 0)
477 return ecode;
7d01b221 478
c46917bb
LR		 479 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
480 "Eeprom VER: %d, REV: %d\n",
481 ah->eep_ops->get_eeprom_ver(ah),
482 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 483
8fe65368
LR		 484 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
485 if (ecode) {
486 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
487 "Failed allocating banks for "
488 "external radio\n");
489 return ecode;
574d6b12 490 }
f078f209 491
f1dc5600
S		 492 if (!AR_SREV_9100(ah)) {
493 ath9k_hw_ani_setup(ah);
f637cfd6 494 ath9k_hw_ani_init(ah);
f078f209
LR		 495 }
496
f078f209
LR		 497 return 0;
498}
499
8525f280 500static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 501{
8525f280
LR		 502 if (AR_SREV_9300_20_OR_LATER(ah))
503 ar9003_hw_attach_ops(ah);
504 else
505 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 506}
507
d70357d5
LR		 508/* Called for all hardware families */
509static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 510{
c46917bb 511 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 512 int r = 0;
aa4058ae 513
bab1f62e
LR		 514 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
515 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
aa4058ae
LR		 516
517 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 518 ath_print(common, ATH_DBG_FATAL,
519 "Couldn't reset chip\n");
95fafca2 520 return -EIO;
aa4058ae
LR		 521 }
522
bab1f62e
LR		 523 ath9k_hw_init_defaults(ah);
524 ath9k_hw_init_config(ah);
525
8525f280 526 ath9k_hw_attach_ops(ah);
d70357d5 527
9ecdef4b 528 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 529 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 530 return -EIO;
aa4058ae
LR		 531 }
532
533 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
534 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
4c85ab11
JL		 535 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
536 !ah->is_pciexpress)) {
aa4058ae
LR		 537 ah->config.serialize_regmode =
538 SER_REG_MODE_ON;
539 } else {
540 ah->config.serialize_regmode =
541 SER_REG_MODE_OFF;
542 }
543 }
544
c46917bb 545 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 546 ah->config.serialize_regmode);
547
f4709fdf
LR		 548 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
549 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
550 else
551 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
552
d70357d5 553 if (!ath9k_hw_macversion_supported(ah)) {
c46917bb
LR		 554 ath_print(common, ATH_DBG_FATAL,
555 "Mac Chip Rev 0x%02x.%x is not supported by "
556 "this driver\n", ah->hw_version.macVersion,
557 ah->hw_version.macRev);
95fafca2 558 return -EOPNOTSUPP;
aa4058ae
LR		 559 }
560
0df13da4 561 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
d7e7d229
LR		 562 ah->is_pciexpress = false;
563
aa4058ae 564 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 565 ath9k_hw_init_cal_settings(ah);
566
567 ah->ani_function = ATH9K_ANI_ALL;
31a0bd3c 568 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 569 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 570 if (!AR_SREV_9300_20_OR_LATER(ah))
571 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae
LR		 572
573 ath9k_hw_init_mode_regs(ah);
574
9a658d2b
LR		 575 /*
576 * Read back AR_WA into a permanent copy and set bits 14 and 17.
577 * We need to do this to avoid RMW of this register. We cannot
578 * read the reg when chip is asleep.
579 */
580 ah->WARegVal = REG_READ(ah, AR_WA);
581 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
582 AR_WA_ASPM_TIMER_BASED_DISABLE);
583
aa4058ae 584 if (ah->is_pciexpress)
93b1b37f 585 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 586 else
587 ath9k_hw_disablepcie(ah);
588
d8f492b7
LR		 589 if (!AR_SREV_9300_20_OR_LATER(ah))
590 ar9002_hw_cck_chan14_spread(ah);
193cd458 591
f637cfd6 592 r = ath9k_hw_post_init(ah);
aa4058ae 593 if (r)
95fafca2 594 return r;
aa4058ae
LR		 595
596 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 597 r = ath9k_hw_fill_cap_info(ah);
598 if (r)
599 return r;
600
4f3acf81
LR		 601 r = ath9k_hw_init_macaddr(ah);
602 if (r) {
c46917bb
LR		 603 ath_print(common, ATH_DBG_FATAL,
604 "Failed to initialize MAC address\n");
95fafca2 605 return r;
f078f209
LR		 606 }
607
d7e7d229 608 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 609 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 610 else
2660b81a 611 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 612
f1dc5600 613 ath9k_init_nfcal_hist_buffer(ah);
aea702b7 614 ah->bb_watchdog_timeout_ms = 25;
f078f209 615
211f5859
LR		 616 common->state = ATH_HW_INITIALIZED;
617
4f3acf81 618 return 0;
f078f209
LR		 619}
620
d70357d5 621int ath9k_hw_init(struct ath_hw *ah)
f078f209 622{
d70357d5
LR		 623 int ret;
624 struct ath_common *common = ath9k_hw_common(ah);
f078f209 625
d70357d5
LR		 626 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
627 switch (ah->hw_version.devid) {
628 case AR5416_DEVID_PCI:
629 case AR5416_DEVID_PCIE:
630 case AR5416_AR9100_DEVID:
631 case AR9160_DEVID_PCI:
632 case AR9280_DEVID_PCI:
633 case AR9280_DEVID_PCIE:
634 case AR9285_DEVID_PCIE:
db3cc53a
SB		 635 case AR9287_DEVID_PCI:
636 case AR9287_DEVID_PCIE:
d70357d5 637 case AR2427_DEVID_PCIE:
db3cc53a 638 case AR9300_DEVID_PCIE:
d70357d5
LR		 639 break;
640 default:
641 if (common->bus_ops->ath_bus_type == ATH_USB)
642 break;
643 ath_print(common, ATH_DBG_FATAL,
644 "Hardware device ID 0x%04x not supported\n",
645 ah->hw_version.devid);
646 return -EOPNOTSUPP;
647 }
f078f209 648
d70357d5
LR		 649 ret = __ath9k_hw_init(ah);
650 if (ret) {
651 ath_print(common, ATH_DBG_FATAL,
652 "Unable to initialize hardware; "
653 "initialization status: %d\n", ret);
654 return ret;
655 }
f078f209 656
d70357d5 657 return 0;
f078f209 658}
d70357d5 659EXPORT_SYMBOL(ath9k_hw_init);
f078f209 660
cbe61d8a 661static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 662{
7d0d0df0
S		 663 ENABLE_REGWRITE_BUFFER(ah);
664
f1dc5600
S		 665 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
666 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 667
f1dc5600
S		 668 REG_WRITE(ah, AR_QOS_NO_ACK,
669 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
670 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
671 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
672
673 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
674 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
675 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
676 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
677 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 678
679 REGWRITE_BUFFER_FLUSH(ah);
680 DISABLE_REGWRITE_BUFFER(ah);
f078f209
LR		 681}
682
cbe61d8a 683static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 684 struct ath9k_channel *chan)
f078f209 685{
64773964 686 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 687
d03a66c1 688 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 689
c75724d1
LR		 690 /* Switch the core clock for ar9271 to 117Mhz */
691 if (AR_SREV_9271(ah)) {
25e2ab17
S		 692 udelay(500);
693 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 694 }
695
f1dc5600
S		 696 udelay(RTC_PLL_SETTLE_DELAY);
697
698 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 699}
700
cbe61d8a 701static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 702 enum nl80211_iftype opmode)
f078f209 703{
152d530d 704 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 705 AR_IMR_TXURN |
706 AR_IMR_RXERR |
707 AR_IMR_RXORN |
708 AR_IMR_BCNMISC;
f078f209 709
66860240
VT		 710 if (AR_SREV_9300_20_OR_LATER(ah)) {
711 imr_reg |= AR_IMR_RXOK_HP;
712 if (ah->config.rx_intr_mitigation)
713 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
714 else
715 imr_reg |= AR_IMR_RXOK_LP;
f078f209 716
66860240
VT		 717 } else {
718 if (ah->config.rx_intr_mitigation)
719 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
720 else
721 imr_reg |= AR_IMR_RXOK;
722 }
f078f209 723
66860240
VT		 724 if (ah->config.tx_intr_mitigation)
725 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
726 else
727 imr_reg |= AR_IMR_TXOK;
f078f209 728
d97809db 729 if (opmode == NL80211_IFTYPE_AP)
152d530d 730 imr_reg |= AR_IMR_MIB;
f078f209 731
7d0d0df0
S		 732 ENABLE_REGWRITE_BUFFER(ah);
733
152d530d 734 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 735 ah->imrs2_reg |= AR_IMR_S2_GTT;
736 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 737
f1dc5600
S		 738 if (!AR_SREV_9100(ah)) {
739 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
740 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
741 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
742 }
66860240 743
7d0d0df0
S		 744 REGWRITE_BUFFER_FLUSH(ah);
745 DISABLE_REGWRITE_BUFFER(ah);
746
66860240
VT		 747 if (AR_SREV_9300_20_OR_LATER(ah)) {
748 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
749 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
750 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
751 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
752 }
f078f209
LR		 753}
754
0005baf4 755static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 756{
0005baf4
FF		 757 u32 val = ath9k_hw_mac_to_clks(ah, us);
758 val = min(val, (u32) 0xFFFF);
759 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 760}
761
0005baf4 762static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 763{
0005baf4
FF		 764 u32 val = ath9k_hw_mac_to_clks(ah, us);
765 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
766 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
767}
768
769static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
770{
771 u32 val = ath9k_hw_mac_to_clks(ah, us);
772 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
773 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 774}
f1dc5600 775
cbe61d8a 776static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 777{
f078f209 778 if (tu > 0xFFFF) {
c46917bb
LR		 779 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
780 "bad global tx timeout %u\n", tu);
2660b81a 781 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 782 return false;
783 } else {
784 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 785 ah->globaltxtimeout = tu;
f078f209
LR		 786 return true;
787 }
788}
789
0005baf4 790void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 791{
0005baf4
FF		 792 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
793 int acktimeout;
e239d859 794 int slottime;
0005baf4
FF		 795 int sifstime;
796
c46917bb
LR		 797 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
798 ah->misc_mode);
f078f209 799
2660b81a 800 if (ah->misc_mode != 0)
f1dc5600 801 REG_WRITE(ah, AR_PCU_MISC,
2660b81a 802 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
0005baf4
FF		 803
804 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
805 sifstime = 16;
806 else
807 sifstime = 10;
808
e239d859
FF		 809 /* As defined by IEEE 802.11-2007 17.3.8.6 */
810 slottime = ah->slottime + 3 * ah->coverage_class;
811 acktimeout = slottime + sifstime;
42c4568a
FF		 812
813 /*
814 * Workaround for early ACK timeouts, add an offset to match the
815 * initval's 64us ack timeout value.
816 * This was initially only meant to work around an issue with delayed
817 * BA frames in some implementations, but it has been found to fix ACK
818 * timeout issues in other cases as well.
819 */
820 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
821 acktimeout += 64 - sifstime - ah->slottime;
822
e239d859 823 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 824 ath9k_hw_set_ack_timeout(ah, acktimeout);
825 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 826 if (ah->globaltxtimeout != (u32) -1)
827 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 828}
0005baf4 829EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 830
285f2dda 831void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 832{
211f5859
LR		 833 struct ath_common *common = ath9k_hw_common(ah);
834
736b3a27 835 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 836 goto free_hw;
837
9ecdef4b 838 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 839
840free_hw:
8fe65368 841 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 842}
285f2dda 843EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 844
f1dc5600
S		 845/*******/
846/* INI */
847/*******/
848
8fe65368 849u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 850{
851 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
852
853 if (IS_CHAN_B(chan))
854 ctl |= CTL_11B;
855 else if (IS_CHAN_G(chan))
856 ctl |= CTL_11G;
857 else
858 ctl |= CTL_11A;
859
860 return ctl;
861}
862
f1dc5600
S		 863/****************************************/
864/* Reset and Channel Switching Routines */
865/****************************************/
f1dc5600 866
cbe61d8a 867static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 868{
57b32227 869 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 870 u32 regval;
871
7d0d0df0
S		 872 ENABLE_REGWRITE_BUFFER(ah);
873
d7e7d229
LR		 874 /*
875 * set AHB_MODE not to do cacheline prefetches
876 */
57b32227
FF		 877 if (!AR_SREV_9300_20_OR_LATER(ah)) {
878 regval = REG_READ(ah, AR_AHB_MODE);
879 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
880 }
f1dc5600 881
d7e7d229
LR		 882 /*
883 * let mac dma reads be in 128 byte chunks
884 */
f1dc5600
S		 885 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
886 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
887
7d0d0df0
S		 888 REGWRITE_BUFFER_FLUSH(ah);
889 DISABLE_REGWRITE_BUFFER(ah);
890
d7e7d229
LR		 891 /*
892 * Restore TX Trigger Level to its pre-reset value.
893 * The initial value depends on whether aggregation is enabled, and is
894 * adjusted whenever underruns are detected.
895 */
57b32227
FF		 896 if (!AR_SREV_9300_20_OR_LATER(ah))
897 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 898
7d0d0df0 899 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 900
d7e7d229
LR		 901 /*
902 * let mac dma writes be in 128 byte chunks
903 */
f1dc5600
S		 904 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
905 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
906
d7e7d229
LR		 907 /*
908 * Setup receive FIFO threshold to hold off TX activities
909 */
f1dc5600
S		 910 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
911
57b32227
FF		 912 if (AR_SREV_9300_20_OR_LATER(ah)) {
913 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
914 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
915
916 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
917 ah->caps.rx_status_len);
918 }
919
d7e7d229
LR		 920 /*
921 * reduce the number of usable entries in PCU TXBUF to avoid
922 * wrap around issues.
923 */
f1dc5600 924 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 925 /* For AR9285 the number of Fifos are reduced to half.
926 * So set the usable tx buf size also to half to
927 * avoid data/delimiter underruns
928 */
f1dc5600
S		 929 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
930 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 931 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 932 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
933 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
934 }
744d4025 935
7d0d0df0
S		 936 REGWRITE_BUFFER_FLUSH(ah);
937 DISABLE_REGWRITE_BUFFER(ah);
938
744d4025
VT		 939 if (AR_SREV_9300_20_OR_LATER(ah))
940 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 941}
942
cbe61d8a 943static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 944{
945 u32 val;
946
947 val = REG_READ(ah, AR_STA_ID1);
948 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
949 switch (opmode) {
d97809db 950 case NL80211_IFTYPE_AP:
f1dc5600
S		 951 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
952 | AR_STA_ID1_KSRCH_MODE);
953 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 954 break;
d97809db 955 case NL80211_IFTYPE_ADHOC:
9cb5412b 956 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 957 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
958 | AR_STA_ID1_KSRCH_MODE);
959 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 960 break;
d97809db
CM		 961 case NL80211_IFTYPE_STATION:
962 case NL80211_IFTYPE_MONITOR:
f1dc5600 963 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 964 break;
f1dc5600
S		 965 }
966}
967
8fe65368
LR		 968void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
969 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 970{
971 u32 coef_exp, coef_man;
972
973 for (coef_exp = 31; coef_exp > 0; coef_exp--)
974 if ((coef_scaled >> coef_exp) & 0x1)
975 break;
976
977 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
978
979 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
980
981 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
982 *coef_exponent = coef_exp - 16;
983}
984
cbe61d8a 985static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 986{
987 u32 rst_flags;
988 u32 tmpReg;
989
70768496
S		 990 if (AR_SREV_9100(ah)) {
991 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
992 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
993 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
994 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
995 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
996 }
997
7d0d0df0
S		 998 ENABLE_REGWRITE_BUFFER(ah);
999
9a658d2b
LR		 1000 if (AR_SREV_9300_20_OR_LATER(ah)) {
1001 REG_WRITE(ah, AR_WA, ah->WARegVal);
1002 udelay(10);
1003 }
1004
f1dc5600
S		 1005 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1006 AR_RTC_FORCE_WAKE_ON_INT);
1007
1008 if (AR_SREV_9100(ah)) {
1009 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1010 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1011 } else {
1012 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1013 if (tmpReg &
1014 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1015 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1016 u32 val;
f1dc5600 1017 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1018
1019 val = AR_RC_HOSTIF;
1020 if (!AR_SREV_9300_20_OR_LATER(ah))
1021 val |= AR_RC_AHB;
1022 REG_WRITE(ah, AR_RC, val);
1023
1024 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1025 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1026
1027 rst_flags = AR_RTC_RC_MAC_WARM;
1028 if (type == ATH9K_RESET_COLD)
1029 rst_flags |= AR_RTC_RC_MAC_COLD;
1030 }
1031
d03a66c1 1032 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1033
1034 REGWRITE_BUFFER_FLUSH(ah);
1035 DISABLE_REGWRITE_BUFFER(ah);
1036
f1dc5600
S		 1037 udelay(50);
1038
d03a66c1 1039 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1040 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1041 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1042 "RTC stuck in MAC reset\n");
f1dc5600
S		 1043 return false;
1044 }
1045
1046 if (!AR_SREV_9100(ah))
1047 REG_WRITE(ah, AR_RC, 0);
1048
f1dc5600
S		 1049 if (AR_SREV_9100(ah))
1050 udelay(50);
1051
1052 return true;
1053}
1054
cbe61d8a 1055static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1056{
7d0d0df0
S		 1057 ENABLE_REGWRITE_BUFFER(ah);
1058
9a658d2b
LR		 1059 if (AR_SREV_9300_20_OR_LATER(ah)) {
1060 REG_WRITE(ah, AR_WA, ah->WARegVal);
1061 udelay(10);
1062 }
1063
f1dc5600
S		 1064 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1065 AR_RTC_FORCE_WAKE_ON_INT);
1066
42d5bc3f 1067 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1068 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1069
d03a66c1 1070 REG_WRITE(ah, AR_RTC_RESET, 0);
ee031112 1071 udelay(2);
1c29ce67 1072
7d0d0df0
S		 1073 REGWRITE_BUFFER_FLUSH(ah);
1074 DISABLE_REGWRITE_BUFFER(ah);
1075
84e2169b
SB		 1076 if (!AR_SREV_9300_20_OR_LATER(ah))
1077 udelay(2);
1078
1079 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1080 REG_WRITE(ah, AR_RC, 0);
1081
d03a66c1 1082 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1083
1084 if (!ath9k_hw_wait(ah,
1085 AR_RTC_STATUS,
1086 AR_RTC_STATUS_M,
0caa7b14
S		 1087 AR_RTC_STATUS_ON,
1088 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1089 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1090 "RTC not waking up\n");
f1dc5600 1091 return false;
f078f209
LR		 1092 }
1093
f1dc5600
S		 1094 ath9k_hw_read_revisions(ah);
1095
1096 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1097}
1098
cbe61d8a 1099static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1100{
9a658d2b
LR		 1101 if (AR_SREV_9300_20_OR_LATER(ah)) {
1102 REG_WRITE(ah, AR_WA, ah->WARegVal);
1103 udelay(10);
1104 }
1105
f1dc5600
S		 1106 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1107 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1108
1109 switch (type) {
1110 case ATH9K_RESET_POWER_ON:
1111 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1112 case ATH9K_RESET_WARM:
1113 case ATH9K_RESET_COLD:
1114 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1115 default:
1116 return false;
1117 }
f078f209
LR		 1118}
1119
cbe61d8a 1120static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1121 struct ath9k_channel *chan)
f078f209 1122{
42abfbee 1123 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1124 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1125 return false;
1126 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1127 return false;
f078f209 1128
9ecdef4b 1129 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1130 return false;
f078f209 1131
2660b81a 1132 ah->chip_fullsleep = false;
f1dc5600 1133 ath9k_hw_init_pll(ah, chan);
f1dc5600 1134 ath9k_hw_set_rfmode(ah, chan);
f078f209 1135
f1dc5600 1136 return true;
f078f209
LR		 1137}
1138
cbe61d8a 1139static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1140 struct ath9k_channel *chan)
f078f209 1141{
608b88cb 1142 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1143 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1144 struct ieee80211_channel *channel = chan->chan;
8fe65368 1145 u32 qnum;
0a3b7bac 1146 int r;
f078f209
LR		 1147
1148 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1149 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1150 ath_print(common, ATH_DBG_QUEUE,
1151 "Transmit frames pending on "
1152 "queue %d\n", qnum);
f078f209
LR		 1153 return false;
1154 }
1155 }
1156
8fe65368 1157 if (!ath9k_hw_rfbus_req(ah)) {
c46917bb
LR		 1158 ath_print(common, ATH_DBG_FATAL,
1159 "Could not kill baseband RX\n");
f078f209
LR		 1160 return false;
1161 }
1162
8fe65368 1163 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1164
8fe65368 1165 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1166 if (r) {
1167 ath_print(common, ATH_DBG_FATAL,
1168 "Failed to set channel\n");
1169 return false;
f078f209
LR		 1170 }
1171
8fbff4b8 1172 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1173 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1174 channel->max_antenna_gain * 2,
1175 channel->max_power * 2,
1176 min((u32) MAX_RATE_POWER,
608b88cb 1177 (u32) regulatory->power_limit));
f078f209 1178
8fe65368 1179 ath9k_hw_rfbus_done(ah);
f078f209 1180
f1dc5600
S		 1181 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1182 ath9k_hw_set_delta_slope(ah, chan);
1183
8fe65368 1184 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600
S		 1185
1186 if (!chan->oneTimeCalsDone)
1187 chan->oneTimeCalsDone = true;
1188
1189 return true;
1190}
1191
c9c99e5e 1192bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1193{
c9c99e5e
FF		 1194 int count = 50;
1195 u32 reg;
1196
1197 if (AR_SREV_9285_10_OR_LATER(ah))
1198 return true;
1199
1200 do {
1201 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1202
c9c99e5e
FF		 1203 if ((reg & 0x7E7FFFEF) == 0x00702400)
1204 continue;
1205
1206 switch (reg & 0x7E000B00) {
1207 case 0x1E000000:
1208 case 0x52000B00:
1209 case 0x18000B00:
1210 continue;
1211 default:
1212 return true;
1213 }
1214 } while (count-- > 0);
3b319aae 1215
c9c99e5e 1216 return false;
3b319aae 1217}
c9c99e5e 1218EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1219
cbe61d8a 1220int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 1221 bool bChannelChange)
f078f209 1222{
1510718d 1223 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1224 u32 saveLedState;
2660b81a 1225 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1226 u32 saveDefAntenna;
1227 u32 macStaId1;
46fe782c 1228 u64 tsf = 0;
8fe65368 1229 int i, r;
f078f209 1230
43c27613
LR		 1231 ah->txchainmask = common->tx_chainmask;
1232 ah->rxchainmask = common->rx_chainmask;
f078f209 1233
9b9cc61c
VT		 1234 if (!ah->chip_fullsleep) {
1235 ath9k_hw_abortpcurecv(ah);
9cc2f3e8 1236 if (!ath9k_hw_stopdmarecv(ah)) {
9b9cc61c
VT		 1237 ath_print(common, ATH_DBG_XMIT,
1238 "Failed to stop receive dma\n");
9cc2f3e8
FF		 1239 bChannelChange = false;
1240 }
9b9cc61c
VT		 1241 }
1242
9ecdef4b 1243 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1244 return -EIO;
f078f209 1245
9ebef799 1246 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1247 ath9k_hw_getnf(ah, curchan);
1248
1249 if (bChannelChange &&
2660b81a
S		 1250 (ah->chip_fullsleep != true) &&
1251 (ah->curchan != NULL) &&
1252 (chan->channel != ah->curchan->channel) &&
f078f209 1253 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1254 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
6b42e8d0 1255 !AR_SREV_9280(ah)) {
f078f209 1256
25c56eec 1257 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1258 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 1259 ath9k_hw_start_nfcal(ah);
ae8d2858 1260 return 0;
f078f209
LR		 1261 }
1262 }
1263
1264 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1265 if (saveDefAntenna == 0)
1266 saveDefAntenna = 1;
1267
1268 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1269
46fe782c 1270 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1271 if (AR_SREV_9100(ah) ||
1272 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1273 tsf = ath9k_hw_gettsf64(ah);
1274
f078f209
LR		 1275 saveLedState = REG_READ(ah, AR_CFG_LED) &
1276 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1277 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1278
1279 ath9k_hw_mark_phy_inactive(ah);
1280
05020d23 1281 /* Only required on the first reset */
d7e7d229
LR		 1282 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1283 REG_WRITE(ah,
1284 AR9271_RESET_POWER_DOWN_CONTROL,
1285 AR9271_RADIO_RF_RST);
1286 udelay(50);
1287 }
1288
f078f209 1289 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1290 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1291 return -EINVAL;
f078f209
LR		 1292 }
1293
05020d23 1294 /* Only required on the first reset */
d7e7d229
LR		 1295 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1296 ah->htc_reset_init = false;
1297 REG_WRITE(ah,
1298 AR9271_RESET_POWER_DOWN_CONTROL,
1299 AR9271_GATE_MAC_CTL);
1300 udelay(50);
1301 }
1302
46fe782c 1303 /* Restore TSF */
f860d526 1304 if (tsf)
46fe782c
S		 1305 ath9k_hw_settsf64(ah, tsf);
1306
369391db
VT		 1307 if (AR_SREV_9280_10_OR_LATER(ah))
1308 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1309
e9141f71
S		 1310 if (!AR_SREV_9300_20_OR_LATER(ah))
1311 ar9002_hw_enable_async_fifo(ah);
1312
25c56eec 1313 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1314 if (r)
1315 return r;
f078f209 1316
f860d526
FF		 1317 /*
1318 * Some AR91xx SoC devices frequently fail to accept TSF writes
1319 * right after the chip reset. When that happens, write a new
1320 * value after the initvals have been applied, with an offset
1321 * based on measured time difference
1322 */
1323 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1324 tsf += 1500;
1325 ath9k_hw_settsf64(ah, tsf);
1326 }
1327
0ced0e17
JM		 1328 /* Setup MFP options for CCMP */
1329 if (AR_SREV_9280_20_OR_LATER(ah)) {
1330 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1331 * frames when constructing CCMP AAD. */
1332 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1333 0xc7ff);
1334 ah->sw_mgmt_crypto = false;
1335 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1336 /* Disable hardware crypto for management frames */
1337 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1338 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1339 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1340 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1341 ah->sw_mgmt_crypto = true;
1342 } else
1343 ah->sw_mgmt_crypto = true;
1344
f078f209
LR		 1345 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1346 ath9k_hw_set_delta_slope(ah, chan);
1347
8fe65368 1348 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1349 ah->eep_ops->set_board_values(ah, chan);
a7765828 1350
6819d57f
S		 1351 ath9k_hw_set_operating_mode(ah, ah->opmode);
1352
7d0d0df0
S		 1353 ENABLE_REGWRITE_BUFFER(ah);
1354
1510718d
LR		 1355 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1356 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1357 | macStaId1
1358 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1359 | (ah->config.
60b67f51 1360 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1361 | ah->sta_id1_defaults);
13b81559 1362 ath_hw_setbssidmask(common);
f078f209 1363 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1364 ath9k_hw_write_associd(ah);
f078f209 1365 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1366 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1367
7d0d0df0
S		 1368 REGWRITE_BUFFER_FLUSH(ah);
1369 DISABLE_REGWRITE_BUFFER(ah);
1370
8fe65368 1371 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1372 if (r)
1373 return r;
f078f209 1374
7d0d0df0
S		 1375 ENABLE_REGWRITE_BUFFER(ah);
1376
f078f209
LR		 1377 for (i = 0; i < AR_NUM_DCU; i++)
1378 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1379
7d0d0df0
S		 1380 REGWRITE_BUFFER_FLUSH(ah);
1381 DISABLE_REGWRITE_BUFFER(ah);
1382
2660b81a
S		 1383 ah->intr_txqs = 0;
1384 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 1385 ath9k_hw_resettxqueue(ah, i);
1386
2660b81a 1387 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1388 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1389 ath9k_hw_init_qos(ah);
1390
2660b81a 1391 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 1392 ath9k_enable_rfkill(ah);
3b319aae 1393
0005baf4 1394 ath9k_hw_init_global_settings(ah);
f078f209 1395
6c94fdc9 1396 if (!AR_SREV_9300_20_OR_LATER(ah)) {
e9141f71 1397 ar9002_hw_update_async_fifo(ah);
6c94fdc9 1398 ar9002_hw_enable_wep_aggregation(ah);
ac88b6ec
VN		 1399 }
1400
f078f209
LR		 1401 REG_WRITE(ah, AR_STA_ID1,
1402 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1403
1404 ath9k_hw_set_dma(ah);
1405
1406 REG_WRITE(ah, AR_OBS, 8);
1407
0ce024cb 1408 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1409 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1410 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1411 }
1412
7f62a136
VT		 1413 if (ah->config.tx_intr_mitigation) {
1414 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1415 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1416 }
1417
f078f209
LR		 1418 ath9k_hw_init_bb(ah, chan);
1419
ae8d2858 1420 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1421 return -EIO;
f078f209 1422
7d0d0df0 1423 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1424
8fe65368 1425 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1426 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1427
7d0d0df0
S		 1428 REGWRITE_BUFFER_FLUSH(ah);
1429 DISABLE_REGWRITE_BUFFER(ah);
1430
d7e7d229
LR		 1431 /*
1432 * For big endian systems turn on swapping for descriptors
1433 */
f078f209
LR		 1434 if (AR_SREV_9100(ah)) {
1435 u32 mask;
1436 mask = REG_READ(ah, AR_CFG);
1437 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 1438 ath_print(common, ATH_DBG_RESET,
04bd4638 1439 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1440 } else {
1441 mask =
1442 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1443 REG_WRITE(ah, AR_CFG, mask);
c46917bb 1444 ath_print(common, ATH_DBG_RESET,
04bd4638 1445 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1446 }
1447 } else {
cbba8cd1
S		 1448 if (common->bus_ops->ath_bus_type == ATH_USB) {
1449 /* Configure AR9271 target WLAN */
1450 if (AR_SREV_9271(ah))
1451 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1452 else
1453 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1454 }
f078f209 1455#ifdef __BIG_ENDIAN
d7e7d229
LR		 1456 else
1457 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1458#endif
1459 }
1460
766ec4a9 1461 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1462 ath9k_hw_btcoex_enable(ah);
1463
d8903a53
VT		 1464 if (AR_SREV_9300_20_OR_LATER(ah)) {
1465 ath9k_hw_loadnf(ah, curchan);
1466 ath9k_hw_start_nfcal(ah);
aea702b7 1467 ar9003_hw_bb_watchdog_config(ah);
d8903a53
VT		 1468 }
1469
ae8d2858 1470 return 0;
f078f209 1471}
7322fd19 1472EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1473
f1dc5600
S		 1474/************************/
1475/* Key Cache Management */
1476/************************/
f078f209 1477
cbe61d8a 1478bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 1479{
f1dc5600 1480 u32 keyType;
f078f209 1481
2660b81a 1482 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1483 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1484 "keychache entry %u out of range\n", entry);
f078f209
LR		 1485 return false;
1486 }
1487
f1dc5600 1488 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 1489
f1dc5600
S		 1490 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1491 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1492 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1493 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1494 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1495 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1496 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1497 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 1498
f1dc5600
S		 1499 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1500 u16 micentry = entry + 64;
f078f209 1501
f1dc5600
S		 1502 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1503 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1504 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1505 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 1506
f078f209
LR		 1507 }
1508
f078f209
LR		 1509 return true;
1510}
7322fd19 1511EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 1512
f35376a4 1513static bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 1514{
f1dc5600 1515 u32 macHi, macLo;
1d0bb42d 1516 u32 unicast_flag = AR_KEYTABLE_VALID;
f078f209 1517
2660b81a 1518 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1519 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1520 "keychache entry %u out of range\n", entry);
f1dc5600 1521 return false;
f078f209
LR		 1522 }
1523
f1dc5600 1524 if (mac != NULL) {
1d0bb42d
FF		 1525 /*
1526 * AR_KEYTABLE_VALID indicates that the address is a unicast
1527 * address, which must match the transmitter address for
1528 * decrypting frames.
1529 * Not setting this bit allows the hardware to use the key
1530 * for multicast frame decryption.
1531 */
1532 if (mac[0] & 0x01)
1533 unicast_flag = 0;
1534
f1dc5600
S		 1535 macHi = (mac[5] << 8) | mac[4];
1536 macLo = (mac[3] << 24) |
1537 (mac[2] << 16) |
1538 (mac[1] << 8) |
1539 mac[0];
1540 macLo >>= 1;
1541 macLo |= (macHi & 1) << 31;
1542 macHi >>= 1;
f078f209 1543 } else {
f1dc5600 1544 macLo = macHi = 0;
f078f209 1545 }
f1dc5600 1546 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1d0bb42d 1547 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
f078f209 1548
f1dc5600 1549 return true;
f078f209
LR		 1550}
1551
cbe61d8a 1552bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 1553 const struct ath9k_keyval *k,
e0caf9ea 1554 const u8 *mac)
f078f209 1555{
2660b81a 1556 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1557 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 1558 u32 key0, key1, key2, key3, key4;
1559 u32 keyType;
f078f209 1560
f1dc5600 1561 if (entry >= pCap->keycache_size) {
c46917bb
LR		 1562 ath_print(common, ATH_DBG_FATAL,
1563 "keycache entry %u out of range\n", entry);
f1dc5600 1564 return false;
f078f209
LR		 1565 }
1566
f1dc5600
S		 1567 switch (k->kv_type) {
1568 case ATH9K_CIPHER_AES_OCB:
1569 keyType = AR_KEYTABLE_TYPE_AES;
1570 break;
1571 case ATH9K_CIPHER_AES_CCM:
1572 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 1573 ath_print(common, ATH_DBG_ANY,
1574 "AES-CCM not supported by mac rev 0x%x\n",
1575 ah->hw_version.macRev);
f1dc5600
S		 1576 return false;
1577 }
1578 keyType = AR_KEYTABLE_TYPE_CCM;
1579 break;
1580 case ATH9K_CIPHER_TKIP:
1581 keyType = AR_KEYTABLE_TYPE_TKIP;
1582 if (ATH9K_IS_MIC_ENABLED(ah)
1583 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 1584 ath_print(common, ATH_DBG_ANY,
1585 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 1586 return false;
1587 }
1588 break;
1589 case ATH9K_CIPHER_WEP:
e31a16d6 1590 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 1591 ath_print(common, ATH_DBG_ANY,
1592 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 1593 return false;
1594 }
e31a16d6 1595 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 1596 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 1597 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 1598 keyType = AR_KEYTABLE_TYPE_104;
1599 else
1600 keyType = AR_KEYTABLE_TYPE_128;
1601 break;
1602 case ATH9K_CIPHER_CLR:
1603 keyType = AR_KEYTABLE_TYPE_CLR;
1604 break;
1605 default:
c46917bb
LR		 1606 ath_print(common, ATH_DBG_FATAL,
1607 "cipher %u not supported\n", k->kv_type);
f1dc5600 1608 return false;
f078f209
LR		 1609 }
1610
e0caf9ea
JM		 1611 key0 = get_unaligned_le32(k->kv_val + 0);
1612 key1 = get_unaligned_le16(k->kv_val + 4);
1613 key2 = get_unaligned_le32(k->kv_val + 6);
1614 key3 = get_unaligned_le16(k->kv_val + 10);
1615 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 1616 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 1617 key4 &= 0xff;
f078f209 1618
672903b3
JM		 1619 /*
1620 * Note: Key cache registers access special memory area that requires
1621 * two 32-bit writes to actually update the values in the internal
1622 * memory. Consequently, the exact order and pairs used here must be
1623 * maintained.
1624 */
1625
f1dc5600
S		 1626 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1627 u16 micentry = entry + 64;
f078f209 1628
672903b3
JM		 1629 /*
1630 * Write inverted key[47:0] first to avoid Michael MIC errors
1631 * on frames that could be sent or received at the same time.
1632 * The correct key will be written in the end once everything
1633 * else is ready.
1634 */
f1dc5600
S		 1635 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1636 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 1637
1638 /* Write key[95:48] */
f1dc5600
S		 1639 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1640 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1641
1642 /* Write key[127:96] and key type */
f1dc5600
S		 1643 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1644 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 1645
1646 /* Write MAC address for the entry */
f1dc5600 1647 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 1648
2660b81a 1649 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 1650 /*
1651 * TKIP uses two key cache entries:
1652 * Michael MIC TX/RX keys in the same key cache entry
1653 * (idx = main index + 64):
1654 * key0 [31:0] = RX key [31:0]
1655 * key1 [15:0] = TX key [31:16]
1656 * key1 [31:16] = reserved
1657 * key2 [31:0] = RX key [63:32]
1658 * key3 [15:0] = TX key [15:0]
1659 * key3 [31:16] = reserved
1660 * key4 [31:0] = TX key [63:32]
1661 */
f1dc5600 1662 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 1663
f1dc5600
S		 1664 mic0 = get_unaligned_le32(k->kv_mic + 0);
1665 mic2 = get_unaligned_le32(k->kv_mic + 4);
1666 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1667 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1668 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 1669
1670 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 1671 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1672 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 1673
1674 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 1675 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1676 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 1677
1678 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1679 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1680 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1681 AR_KEYTABLE_TYPE_CLR);
f078f209 1682
f1dc5600 1683 } else {
672903b3
JM		 1684 /*
1685 * TKIP uses four key cache entries (two for group
1686 * keys):
1687 * Michael MIC TX/RX keys are in different key cache
1688 * entries (idx = main index + 64 for TX and
1689 * main index + 32 + 96 for RX):
1690 * key0 [31:0] = TX/RX MIC key [31:0]
1691 * key1 [31:0] = reserved
1692 * key2 [31:0] = TX/RX MIC key [63:32]
1693 * key3 [31:0] = reserved
1694 * key4 [31:0] = reserved
1695 *
1696 * Upper layer code will call this function separately
1697 * for TX and RX keys when these registers offsets are
1698 * used.
1699 */
f1dc5600 1700 u32 mic0, mic2;
f078f209 1701
f1dc5600
S		 1702 mic0 = get_unaligned_le32(k->kv_mic + 0);
1703 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 1704
1705 /* Write MIC key[31:0] */
f1dc5600
S		 1706 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1707 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 1708
1709 /* Write MIC key[63:32] */
f1dc5600
S		 1710 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1711 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 1712
1713 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1714 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1715 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1716 AR_KEYTABLE_TYPE_CLR);
1717 }
672903b3
JM		 1718
1719 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 1720 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1721 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 1722
1723 /*
1724 * Write the correct (un-inverted) key[47:0] last to enable
1725 * TKIP now that all other registers are set with correct
1726 * values.
1727 */
f1dc5600
S		 1728 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1729 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1730 } else {
672903b3 1731 /* Write key[47:0] */
f1dc5600
S		 1732 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1733 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 1734
1735 /* Write key[95:48] */
f1dc5600
S		 1736 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1737 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1738
1739 /* Write key[127:96] and key type */
f1dc5600
S		 1740 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1741 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 1742
672903b3 1743 /* Write MAC address for the entry */
f1dc5600
S		 1744 (void) ath9k_hw_keysetmac(ah, entry, mac);
1745 }
f078f209 1746
f078f209
LR		 1747 return true;
1748}
7322fd19 1749EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 1750
f1dc5600
S		 1751/******************************/
1752/* Power Management (Chipset) */
1753/******************************/
1754
42d5bc3f
LR		 1755/*
1756 * Notify Power Mgt is disabled in self-generated frames.
1757 * If requested, force chip to sleep.
1758 */
cbe61d8a 1759static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1760{
f1dc5600
S		 1761 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1762 if (setChip) {
42d5bc3f
LR		 1763 /*
1764 * Clear the RTC force wake bit to allow the
1765 * mac to go to sleep.
1766 */
f1dc5600
S		 1767 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1768 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1769 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1770 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1771
42d5bc3f 1772 /* Shutdown chip. Active low */
14b3af38 1773 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1774 REG_CLR_BIT(ah, (AR_RTC_RESET),
1775 AR_RTC_RESET_EN);
f1dc5600 1776 }
9a658d2b
LR		 1777
1778 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1779 if (AR_SREV_9300_20_OR_LATER(ah))
1780 REG_WRITE(ah, AR_WA,
1781 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1782}
1783
bbd79af5
LR		 1784/*
1785 * Notify Power Management is enabled in self-generating
1786 * frames. If request, set power mode of chip to
1787 * auto/normal. Duration in units of 128us (1/8 TU).
1788 */
cbe61d8a 1789static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1790{
f1dc5600
S		 1791 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1792 if (setChip) {
2660b81a 1793 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1794
f1dc5600 1795 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1796 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1797 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1798 AR_RTC_FORCE_WAKE_ON_INT);
1799 } else {
bbd79af5
LR		 1800 /*
1801 * Clear the RTC force wake bit to allow the
1802 * mac to go to sleep.
1803 */
f1dc5600
S		 1804 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1805 AR_RTC_FORCE_WAKE_EN);
f078f209 1806 }
f078f209 1807 }
9a658d2b
LR		 1808
1809 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1810 if (AR_SREV_9300_20_OR_LATER(ah))
1811 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1812}
1813
cbe61d8a 1814static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1815{
f1dc5600
S		 1816 u32 val;
1817 int i;
f078f209 1818
9a658d2b
LR		 1819 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1820 if (AR_SREV_9300_20_OR_LATER(ah)) {
1821 REG_WRITE(ah, AR_WA, ah->WARegVal);
1822 udelay(10);
1823 }
1824
f1dc5600
S		 1825 if (setChip) {
1826 if ((REG_READ(ah, AR_RTC_STATUS) &
1827 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1828 if (ath9k_hw_set_reset_reg(ah,
1829 ATH9K_RESET_POWER_ON) != true) {
1830 return false;
1831 }
e041228f
LR		 1832 if (!AR_SREV_9300_20_OR_LATER(ah))
1833 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1834 }
1835 if (AR_SREV_9100(ah))
1836 REG_SET_BIT(ah, AR_RTC_RESET,
1837 AR_RTC_RESET_EN);
f078f209 1838
f1dc5600
S		 1839 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1840 AR_RTC_FORCE_WAKE_EN);
1841 udelay(50);
f078f209 1842
f1dc5600
S		 1843 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1844 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1845 if (val == AR_RTC_STATUS_ON)
1846 break;
1847 udelay(50);
1848 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1849 AR_RTC_FORCE_WAKE_EN);
f078f209 1850 }
f1dc5600 1851 if (i == 0) {
c46917bb
LR		 1852 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1853 "Failed to wakeup in %uus\n",
1854 POWER_UP_TIME / 20);
f1dc5600 1855 return false;
f078f209 1856 }
f078f209
LR		 1857 }
1858
f1dc5600 1859 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1860
f1dc5600 1861 return true;
f078f209
LR		 1862}
1863
9ecdef4b 1864bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1865{
c46917bb 1866 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1867 int status = true, setChip = true;
f1dc5600
S		 1868 static const char *modes[] = {
1869 "AWAKE",
1870 "FULL-SLEEP",
1871 "NETWORK SLEEP",
1872 "UNDEFINED"
1873 };
f1dc5600 1874
cbdec975
GJ		 1875 if (ah->power_mode == mode)
1876 return status;
1877
c46917bb
LR		 1878 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1879 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1880
1881 switch (mode) {
1882 case ATH9K_PM_AWAKE:
1883 status = ath9k_hw_set_power_awake(ah, setChip);
1884 break;
1885 case ATH9K_PM_FULL_SLEEP:
1886 ath9k_set_power_sleep(ah, setChip);
2660b81a 1887 ah->chip_fullsleep = true;
f1dc5600
S		 1888 break;
1889 case ATH9K_PM_NETWORK_SLEEP:
1890 ath9k_set_power_network_sleep(ah, setChip);
1891 break;
f078f209 1892 default:
c46917bb
LR		 1893 ath_print(common, ATH_DBG_FATAL,
1894 "Unknown power mode %u\n", mode);
f078f209
LR		 1895 return false;
1896 }
2660b81a 1897 ah->power_mode = mode;
f1dc5600
S		 1898
1899 return status;
f078f209 1900}
7322fd19 1901EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1902
f1dc5600
S		 1903/*******************/
1904/* Beacon Handling */
1905/*******************/
1906
cbe61d8a 1907void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1908{
f078f209
LR		 1909 int flags = 0;
1910
2660b81a 1911 ah->beacon_interval = beacon_period;
f078f209 1912
7d0d0df0
S		 1913 ENABLE_REGWRITE_BUFFER(ah);
1914
2660b81a 1915 switch (ah->opmode) {
d97809db
CM		 1916 case NL80211_IFTYPE_STATION:
1917 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 1918 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1919 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1920 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1921 flags |= AR_TBTT_TIMER_EN;
1922 break;
d97809db 1923 case NL80211_IFTYPE_ADHOC:
9cb5412b 1924 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1925 REG_SET_BIT(ah, AR_TXCFG,
1926 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1927 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1928 TU_TO_USEC(next_beacon +
2660b81a
S		 1929 (ah->atim_window ? ah->
1930 atim_window : 1)));
f078f209 1931 flags |= AR_NDP_TIMER_EN;
d97809db 1932 case NL80211_IFTYPE_AP:
f078f209
LR		 1933 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1934 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1935 TU_TO_USEC(next_beacon -
2660b81a 1936 ah->config.
60b67f51 1937 dma_beacon_response_time));
f078f209
LR		 1938 REG_WRITE(ah, AR_NEXT_SWBA,
1939 TU_TO_USEC(next_beacon -
2660b81a 1940 ah->config.
60b67f51 1941 sw_beacon_response_time));
f078f209
LR		 1942 flags |=
1943 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1944 break;
d97809db 1945 default:
c46917bb
LR		 1946 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1947 "%s: unsupported opmode: %d\n",
1948 __func__, ah->opmode);
d97809db
CM		 1949 return;
1950 break;
f078f209
LR		 1951 }
1952
1953 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1954 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1955 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1956 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1957
7d0d0df0
S		 1958 REGWRITE_BUFFER_FLUSH(ah);
1959 DISABLE_REGWRITE_BUFFER(ah);
1960
f078f209
LR		 1961 beacon_period &= ~ATH9K_BEACON_ENA;
1962 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 1963 ath9k_hw_reset_tsf(ah);
1964 }
1965
1966 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1967}
7322fd19 1968EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1969
cbe61d8a 1970void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1971 const struct ath9k_beacon_state *bs)
f078f209
LR		 1972{
1973 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1974 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1975 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1976
7d0d0df0
S		 1977 ENABLE_REGWRITE_BUFFER(ah);
1978
f078f209
LR		 1979 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1980
1981 REG_WRITE(ah, AR_BEACON_PERIOD,
1982 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1983 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1984 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1985
7d0d0df0
S		 1986 REGWRITE_BUFFER_FLUSH(ah);
1987 DISABLE_REGWRITE_BUFFER(ah);
1988
f078f209
LR		 1989 REG_RMW_FIELD(ah, AR_RSSI_THR,
1990 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1991
1992 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1993
1994 if (bs->bs_sleepduration > beaconintval)
1995 beaconintval = bs->bs_sleepduration;
1996
1997 dtimperiod = bs->bs_dtimperiod;
1998 if (bs->bs_sleepduration > dtimperiod)
1999 dtimperiod = bs->bs_sleepduration;
2000
2001 if (beaconintval == dtimperiod)
2002 nextTbtt = bs->bs_nextdtim;
2003 else
2004 nextTbtt = bs->bs_nexttbtt;
2005
c46917bb
LR		 2006 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2007 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
2008 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
2009 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2010
7d0d0df0
S		 2011 ENABLE_REGWRITE_BUFFER(ah);
2012
f1dc5600
S		 2013 REG_WRITE(ah, AR_NEXT_DTIM,
2014 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
2015 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 2016
f1dc5600
S		 2017 REG_WRITE(ah, AR_SLEEP1,
2018 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2019 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2020
f1dc5600
S		 2021 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2022 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2023 else
2024 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2025
f1dc5600
S		 2026 REG_WRITE(ah, AR_SLEEP2,
2027 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2028
f1dc5600
S		 2029 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2030 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 2031
7d0d0df0
S		 2032 REGWRITE_BUFFER_FLUSH(ah);
2033 DISABLE_REGWRITE_BUFFER(ah);
2034
f1dc5600
S		 2035 REG_SET_BIT(ah, AR_TIMER_MODE,
2036 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2037 AR_DTIM_TIMER_EN);
f078f209 2038
4af9cf4f
S		 2039 /* TSF Out of Range Threshold */
2040 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2041}
7322fd19 2042EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2043
f1dc5600
S		 2044/*******************/
2045/* HW Capabilities */
2046/*******************/
2047
a9a29ce6 2048int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2049{
2660b81a 2050 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2051 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2052 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 2053 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 2054
f1dc5600 2055 u16 capField = 0, eeval;
f078f209 2056
f74df6fb 2057 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2058 regulatory->current_rd = eeval;
f078f209 2059
f74df6fb 2060 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 2061 if (AR_SREV_9285_10_OR_LATER(ah))
2062 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 2063 regulatory->current_rd_ext = eeval;
f078f209 2064
f74df6fb 2065 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 2066
2660b81a 2067 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2068 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2069 if (regulatory->current_rd == 0x64 ||
2070 regulatory->current_rd == 0x65)
2071 regulatory->current_rd += 5;
2072 else if (regulatory->current_rd == 0x41)
2073 regulatory->current_rd = 0x43;
c46917bb
LR		 2074 ath_print(common, ATH_DBG_REGULATORY,
2075 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 2076 }
f078f209 2077
f74df6fb 2078 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 2079 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2080 ath_print(common, ATH_DBG_FATAL,
2081 "no band has been marked as supported in EEPROM.\n");
2082 return -EINVAL;
2083 }
2084
f1dc5600 2085 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 2086
f1dc5600
S		 2087 if (eeval & AR5416_OPFLAGS_11A) {
2088 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 2089 if (ah->config.ht_enable) {
f1dc5600
S		 2090 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2091 set_bit(ATH9K_MODE_11NA_HT20,
2092 pCap->wireless_modes);
2093 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2094 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2095 pCap->wireless_modes);
2096 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2097 pCap->wireless_modes);
2098 }
f078f209 2099 }
f078f209
LR		 2100 }
2101
f1dc5600 2102 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 2103 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 2104 if (ah->config.ht_enable) {
f1dc5600
S		 2105 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2106 set_bit(ATH9K_MODE_11NG_HT20,
2107 pCap->wireless_modes);
2108 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2109 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2110 pCap->wireless_modes);
2111 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2112 pCap->wireless_modes);
2113 }
2114 }
f078f209 2115 }
f1dc5600 2116
f74df6fb 2117 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2118 /*
2119 * For AR9271 we will temporarilly uses the rx chainmax as read from
2120 * the EEPROM.
2121 */
8147f5de 2122 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2123 !(eeval & AR5416_OPFLAGS_11A) &&
2124 !(AR_SREV_9271(ah)))
2125 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 2126 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2127 else
d7e7d229 2128 /* Use rx_chainmask from EEPROM. */
8147f5de 2129 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2130
d535a42a 2131 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 2132 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2133
f1dc5600
S		 2134 pCap->low_2ghz_chan = 2312;
2135 pCap->high_2ghz_chan = 2732;
f078f209 2136
f1dc5600
S		 2137 pCap->low_5ghz_chan = 4920;
2138 pCap->high_5ghz_chan = 6100;
f078f209 2139
f1dc5600
S		 2140 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2141 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2142 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 2143
f1dc5600
S		 2144 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2145 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2146 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 2147
2660b81a 2148 if (ah->config.ht_enable)
f1dc5600
S		 2149 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2150 else
2151 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2152
f1dc5600
S		 2153 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2154 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2155 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2156 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 2157
f1dc5600
S		 2158 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2159 pCap->total_queues =
2160 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2161 else
2162 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 2163
f1dc5600
S		 2164 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2165 pCap->keycache_size =
2166 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2167 else
2168 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 2169
f1dc5600 2170 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f4709fdf
LR		 2171
2172 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2173 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2174 else
2175 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 2176
5b5fa355
S		 2177 if (AR_SREV_9271(ah))
2178 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2179 else if (AR_DEVID_7010(ah))
2180 pCap->num_gpio_pins = AR7010_NUM_GPIO;
5b5fa355 2181 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2182 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2183 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 2184 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2185 else
2186 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2187
f1dc5600
S		 2188 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2189 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2190 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2191 } else {
2192 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 2193 }
2194
f1dc5600
S		 2195 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2196
e97275cb 2197#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2198 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2199 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2200 ah->rfkill_gpio =
2201 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2202 ah->rfkill_polarity =
2203 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2204
2205 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2206 }
f1dc5600 2207#endif
d5d1154f 2208 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2209 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2210 else
2211 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2212
e7594072 2213 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2214 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2215 else
2216 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2217
608b88cb 2218 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 2219 pCap->reg_cap =
2220 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2221 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2222 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2223 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 2224 } else {
f1dc5600
S		 2225 pCap->reg_cap =
2226 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2227 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 2228 }
f078f209 2229
ebb90cfc
SB		 2230 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2231 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2232 AR_SREV_5416(ah))
2233 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 2234
2235 pCap->num_antcfg_5ghz =
f74df6fb 2236 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 2237 pCap->num_antcfg_2ghz =
f74df6fb 2238 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 2239
fe12946e 2240 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 2241 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 2242 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2243 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 2244
8c8f9ba7 2245 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 2246 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2247 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 2248 } else {
766ec4a9 2249 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 2250 }
22f25d0d 2251 } else {
766ec4a9 2252 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 2253 }
a9a29ce6 2254
ceb26445 2255 if (AR_SREV_9300_20_OR_LATER(ah)) {
e5553724
VT		 2256 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2257 ATH9K_HW_CAP_FASTCLOCK;
ceb26445
VT		 2258 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2259 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2260 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2261 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2262 pCap->txs_len = sizeof(struct ar9003_txs);
4935250a
FF		 2263 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2264 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2265 } else {
2266 pCap->tx_desc_len = sizeof(struct ath_desc);
6b42e8d0
FF		 2267 if (AR_SREV_9280_20(ah) &&
2268 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2269 AR5416_EEP_MINOR_VER_16) ||
2270 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2271 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2272 }
1adf02ff 2273
6c84ce08
VT		 2274 if (AR_SREV_9300_20_OR_LATER(ah))
2275 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2276
b4dec5e8 2277 if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2278 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2279
a9a29ce6 2280 return 0;
f078f209
LR		 2281}
2282
f1dc5600
S		 2283/****************************/
2284/* GPIO / RFKILL / Antennae */
2285/****************************/
f078f209 2286
cbe61d8a 2287static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2288 u32 gpio, u32 type)
2289{
2290 int addr;
2291 u32 gpio_shift, tmp;
f078f209 2292
f1dc5600
S		 2293 if (gpio > 11)
2294 addr = AR_GPIO_OUTPUT_MUX3;
2295 else if (gpio > 5)
2296 addr = AR_GPIO_OUTPUT_MUX2;
2297 else
2298 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2299
f1dc5600 2300 gpio_shift = (gpio % 6) * 5;
f078f209 2301
f1dc5600
S		 2302 if (AR_SREV_9280_20_OR_LATER(ah)
2303 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2304 REG_RMW(ah, addr, (type << gpio_shift),
2305 (0x1f << gpio_shift));
f078f209 2306 } else {
f1dc5600
S		 2307 tmp = REG_READ(ah, addr);
2308 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2309 tmp &= ~(0x1f << gpio_shift);
2310 tmp |= (type << gpio_shift);
2311 REG_WRITE(ah, addr, tmp);
f078f209 2312 }
f078f209
LR		 2313}
2314
cbe61d8a 2315void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2316{
f1dc5600 2317 u32 gpio_shift;
f078f209 2318
9680e8a3 2319 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2320
88c1f4f6
S		 2321 if (AR_DEVID_7010(ah)) {
2322 gpio_shift = gpio;
2323 REG_RMW(ah, AR7010_GPIO_OE,
2324 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2325 (AR7010_GPIO_OE_MASK << gpio_shift));
2326 return;
2327 }
f078f209 2328
88c1f4f6 2329 gpio_shift = gpio << 1;
f1dc5600
S		 2330 REG_RMW(ah,
2331 AR_GPIO_OE_OUT,
2332 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2333 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2334}
7322fd19 2335EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2336
cbe61d8a 2337u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2338{
cb33c412
SB		 2339#define MS_REG_READ(x, y) \
2340 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2341
2660b81a 2342 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2343 return 0xffffffff;
f078f209 2344
88c1f4f6
S		 2345 if (AR_DEVID_7010(ah)) {
2346 u32 val;
2347 val = REG_READ(ah, AR7010_GPIO_IN);
2348 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2349 } else if (AR_SREV_9300_20_OR_LATER(ah))
783dfca1
FF		 2350 return MS_REG_READ(AR9300, gpio) != 0;
2351 else if (AR_SREV_9271(ah))
5b5fa355
S		 2352 return MS_REG_READ(AR9271, gpio) != 0;
2353 else if (AR_SREV_9287_10_OR_LATER(ah))
ac88b6ec
VN		 2354 return MS_REG_READ(AR9287, gpio) != 0;
2355 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2356 return MS_REG_READ(AR9285, gpio) != 0;
2357 else if (AR_SREV_9280_10_OR_LATER(ah))
2358 return MS_REG_READ(AR928X, gpio) != 0;
2359 else
2360 return MS_REG_READ(AR, gpio) != 0;
f078f209 2361}
7322fd19 2362EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2363
cbe61d8a 2364void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2365 u32 ah_signal_type)
f078f209 2366{
f1dc5600 2367 u32 gpio_shift;
f078f209 2368
88c1f4f6
S		 2369 if (AR_DEVID_7010(ah)) {
2370 gpio_shift = gpio;
2371 REG_RMW(ah, AR7010_GPIO_OE,
2372 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2373 (AR7010_GPIO_OE_MASK << gpio_shift));
2374 return;
2375 }
f078f209 2376
88c1f4f6 2377 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2378 gpio_shift = 2 * gpio;
f1dc5600
S		 2379 REG_RMW(ah,
2380 AR_GPIO_OE_OUT,
2381 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2382 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2383}
7322fd19 2384EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2385
cbe61d8a 2386void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2387{
88c1f4f6
S		 2388 if (AR_DEVID_7010(ah)) {
2389 val = val ? 0 : 1;
2390 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2391 AR_GPIO_BIT(gpio));
2392 return;
2393 }
2394
5b5fa355
S		 2395 if (AR_SREV_9271(ah))
2396 val = ~val;
2397
f1dc5600
S		 2398 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2399 AR_GPIO_BIT(gpio));
f078f209 2400}
7322fd19 2401EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2402
cbe61d8a 2403u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2404{
f1dc5600 2405 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2406}
7322fd19 2407EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2408
cbe61d8a 2409void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2410{
f1dc5600 2411 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2412}
7322fd19 2413EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2414
f1dc5600
S		 2415/*********************/
2416/* General Operation */
2417/*********************/
2418
cbe61d8a 2419u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2420{
f1dc5600
S		 2421 u32 bits = REG_READ(ah, AR_RX_FILTER);
2422 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2423
f1dc5600
S		 2424 if (phybits & AR_PHY_ERR_RADAR)
2425 bits |= ATH9K_RX_FILTER_PHYRADAR;
2426 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2427 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2428
f1dc5600 2429 return bits;
f078f209 2430}
7322fd19 2431EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2432
cbe61d8a 2433void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2434{
f1dc5600 2435 u32 phybits;
f078f209 2436
7d0d0df0
S		 2437 ENABLE_REGWRITE_BUFFER(ah);
2438
7ea310be
S		 2439 REG_WRITE(ah, AR_RX_FILTER, bits);
2440
f1dc5600
S		 2441 phybits = 0;
2442 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2443 phybits |= AR_PHY_ERR_RADAR;
2444 if (bits & ATH9K_RX_FILTER_PHYERR)
2445 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2446 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2447
f1dc5600
S		 2448 if (phybits)
2449 REG_WRITE(ah, AR_RXCFG,
2450 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2451 else
2452 REG_WRITE(ah, AR_RXCFG,
2453 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2454
2455 REGWRITE_BUFFER_FLUSH(ah);
2456 DISABLE_REGWRITE_BUFFER(ah);
f1dc5600 2457}
7322fd19 2458EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2459
cbe61d8a 2460bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2461{
63a75b91
SB		 2462 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2463 return false;
2464
2465 ath9k_hw_init_pll(ah, NULL);
2466 return true;
f1dc5600 2467}
7322fd19 2468EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2469
cbe61d8a 2470bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2471{
9ecdef4b 2472 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2473 return false;
f078f209 2474
63a75b91
SB		 2475 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2476 return false;
2477
2478 ath9k_hw_init_pll(ah, NULL);
2479 return true;
f078f209 2480}
7322fd19 2481EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2482
8fbff4b8 2483void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 2484{
608b88cb 2485 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2486 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2487 struct ieee80211_channel *channel = chan->chan;
f078f209 2488
608b88cb 2489 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2490
8fbff4b8 2491 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2492 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2493 channel->max_antenna_gain * 2,
2494 channel->max_power * 2,
2495 min((u32) MAX_RATE_POWER,
608b88cb 2496 (u32) regulatory->power_limit));
6f255425 2497}
7322fd19 2498EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2499
cbe61d8a 2500void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2501{
2660b81a 2502 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2503}
7322fd19 2504EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2505
cbe61d8a 2506void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2507{
f1dc5600
S		 2508 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2509 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2510}
7322fd19 2511EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2512
f2b2143e 2513void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2514{
1510718d
LR		 2515 struct ath_common *common = ath9k_hw_common(ah);
2516
2517 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2518 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2519 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2520}
7322fd19 2521EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2522
1c0fc65e
BP		 2523#define ATH9K_MAX_TSF_READ 10
2524
cbe61d8a 2525u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2526{
1c0fc65e
BP		 2527 u32 tsf_lower, tsf_upper1, tsf_upper2;
2528 int i;
2529
2530 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2531 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2532 tsf_lower = REG_READ(ah, AR_TSF_L32);
2533 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2534 if (tsf_upper2 == tsf_upper1)
2535 break;
2536 tsf_upper1 = tsf_upper2;
2537 }
f078f209 2538
1c0fc65e 2539 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2540
1c0fc65e 2541 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2542}
7322fd19 2543EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2544
cbe61d8a 2545void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2546{
27abe060 2547 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2548 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2549}
7322fd19 2550EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2551
cbe61d8a 2552void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2553{
f9b604f6
GJ		 2554 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2555 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 2556 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2557 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2558
f1dc5600
S		 2559 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2560}
7322fd19 2561EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2562
54e4cec6 2563void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2564{
f1dc5600 2565 if (setting)
2660b81a 2566 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2567 else
2660b81a 2568 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2569}
7322fd19 2570EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2571
25c56eec 2572void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2573{
25c56eec 2574 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2575 u32 macmode;
2576
25c56eec 2577 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2578 macmode = AR_2040_JOINED_RX_CLEAR;
2579 else
2580 macmode = 0;
f078f209 2581
f1dc5600 2582 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2583}
ff155a45
VT		 2584
2585/* HW Generic timers configuration */
2586
2587static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2588{
2589 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2590 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2591 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2592 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2593 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2594 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2595 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2596 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2597 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2598 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2599 AR_NDP2_TIMER_MODE, 0x0002},
2600 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2601 AR_NDP2_TIMER_MODE, 0x0004},
2602 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2603 AR_NDP2_TIMER_MODE, 0x0008},
2604 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2605 AR_NDP2_TIMER_MODE, 0x0010},
2606 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2607 AR_NDP2_TIMER_MODE, 0x0020},
2608 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2609 AR_NDP2_TIMER_MODE, 0x0040},
2610 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2611 AR_NDP2_TIMER_MODE, 0x0080}
2612};
2613
2614/* HW generic timer primitives */
2615
2616/* compute and clear index of rightmost 1 */
2617static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2618{
2619 u32 b;
2620
2621 b = *mask;
2622 b &= (0-b);
2623 *mask &= ~b;
2624 b *= debruijn32;
2625 b >>= 27;
2626
2627 return timer_table->gen_timer_index[b];
2628}
2629
1773912b 2630u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2631{
2632 return REG_READ(ah, AR_TSF_L32);
2633}
7322fd19 2634EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2635
2636struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2637 void (*trigger)(void *),
2638 void (*overflow)(void *),
2639 void *arg,
2640 u8 timer_index)
2641{
2642 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2643 struct ath_gen_timer *timer;
2644
2645 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2646
2647 if (timer == NULL) {
c46917bb
LR		 2648 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2649 "Failed to allocate memory"
2650 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 2651 return NULL;
2652 }
2653
2654 /* allocate a hardware generic timer slot */
2655 timer_table->timers[timer_index] = timer;
2656 timer->index = timer_index;
2657 timer->trigger = trigger;
2658 timer->overflow = overflow;
2659 timer->arg = arg;
2660
2661 return timer;
2662}
7322fd19 2663EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2664
cd9bf689
LR		 2665void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2666 struct ath_gen_timer *timer,
2667 u32 timer_next,
2668 u32 timer_period)
ff155a45
VT		 2669{
2670 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2671 u32 tsf;
2672
2673 BUG_ON(!timer_period);
2674
2675 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2676
2677 tsf = ath9k_hw_gettsf32(ah);
2678
c46917bb
LR		 2679 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2680 "curent tsf %x period %x"
2681 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 2682
2683 /*
2684 * Pull timer_next forward if the current TSF already passed it
2685 * because of software latency
2686 */
2687 if (timer_next < tsf)
2688 timer_next = tsf + timer_period;
2689
2690 /*
2691 * Program generic timer registers
2692 */
2693 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2694 timer_next);
2695 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2696 timer_period);
2697 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2698 gen_tmr_configuration[timer->index].mode_mask);
2699
2700 /* Enable both trigger and thresh interrupt masks */
2701 REG_SET_BIT(ah, AR_IMR_S5,
2702 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2703 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2704}
7322fd19 2705EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2706
cd9bf689 2707void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2708{
2709 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2710
2711 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2712 (timer->index >= ATH_MAX_GEN_TIMER)) {
2713 return;
2714 }
2715
2716 /* Clear generic timer enable bits. */
2717 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2718 gen_tmr_configuration[timer->index].mode_mask);
2719
2720 /* Disable both trigger and thresh interrupt masks */
2721 REG_CLR_BIT(ah, AR_IMR_S5,
2722 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2723 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2724
2725 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2726}
7322fd19 2727EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2728
2729void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2730{
2731 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2732
2733 /* free the hardware generic timer slot */
2734 timer_table->timers[timer->index] = NULL;
2735 kfree(timer);
2736}
7322fd19 2737EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2738
2739/*
2740 * Generic Timer Interrupts handling
2741 */
2742void ath_gen_timer_isr(struct ath_hw *ah)
2743{
2744 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2745 struct ath_gen_timer *timer;
c46917bb 2746 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2747 u32 trigger_mask, thresh_mask, index;
2748
2749 /* get hardware generic timer interrupt status */
2750 trigger_mask = ah->intr_gen_timer_trigger;
2751 thresh_mask = ah->intr_gen_timer_thresh;
2752 trigger_mask &= timer_table->timer_mask.val;
2753 thresh_mask &= timer_table->timer_mask.val;
2754
2755 trigger_mask &= ~thresh_mask;
2756
2757 while (thresh_mask) {
2758 index = rightmost_index(timer_table, &thresh_mask);
2759 timer = timer_table->timers[index];
2760 BUG_ON(!timer);
c46917bb
LR		 2761 ath_print(common, ATH_DBG_HWTIMER,
2762 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2763 timer->overflow(timer->arg);
2764 }
2765
2766 while (trigger_mask) {
2767 index = rightmost_index(timer_table, &trigger_mask);
2768 timer = timer_table->timers[index];
2769 BUG_ON(!timer);
c46917bb
LR		 2770 ath_print(common, ATH_DBG_HWTIMER,
2771 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2772 timer->trigger(timer->arg);
2773 }
2774}
7322fd19 2775EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2776
05020d23
S		 2777/********/
2778/* HTC */
2779/********/
2780
2781void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2782{
2783 ah->htc_reset_init = true;
2784}
2785EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2786
2da4f01a
LR		 2787static struct {
2788 u32 version;
2789 const char * name;
2790} ath_mac_bb_names[] = {
2791 /* Devices with external radios */
2792 { AR_SREV_VERSION_5416_PCI, "5416" },
2793 { AR_SREV_VERSION_5416_PCIE, "5418" },
2794 { AR_SREV_VERSION_9100, "9100" },
2795 { AR_SREV_VERSION_9160, "9160" },
2796 /* Single-chip solutions */
2797 { AR_SREV_VERSION_9280, "9280" },
2798 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2799 { AR_SREV_VERSION_9287, "9287" },
2800 { AR_SREV_VERSION_9271, "9271" },
ec83903e 2801 { AR_SREV_VERSION_9300, "9300" },
2da4f01a
LR		 2802};
2803
2804/* For devices with external radios */
2805static struct {
2806 u16 version;
2807 const char * name;
2808} ath_rf_names[] = {
2809 { 0, "5133" },
2810 { AR_RAD5133_SREV_MAJOR, "5133" },
2811 { AR_RAD5122_SREV_MAJOR, "5122" },
2812 { AR_RAD2133_SREV_MAJOR, "2133" },
2813 { AR_RAD2122_SREV_MAJOR, "2122" }
2814};
2815
2816/*
2817 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2818 */
f934c4d9 2819static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2820{
2821 int i;
2822
2823 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2824 if (ath_mac_bb_names[i].version == mac_bb_version) {
2825 return ath_mac_bb_names[i].name;
2826 }
2827 }
2828
2829 return "????";
2830}
2da4f01a
LR		 2831
2832/*
2833 * Return the RF name. "????" is returned if the RF is unknown.
2834 * Used for devices with external radios.
2835 */
f934c4d9 2836static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2837{
2838 int i;
2839
2840 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2841 if (ath_rf_names[i].version == rf_version) {
2842 return ath_rf_names[i].name;
2843 }
2844 }
2845
2846 return "????";
2847}
f934c4d9
LR		 2848
2849void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2850{
2851 int used;
2852
2853 /* chipsets >= AR9280 are single-chip */
2854 if (AR_SREV_9280_10_OR_LATER(ah)) {
2855 used = snprintf(hw_name, len,
2856 "Atheros AR%s Rev:%x",
2857 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2858 ah->hw_version.macRev);
2859 }
2860 else {
2861 used = snprintf(hw_name, len,
2862 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2863 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2864 ah->hw_version.macRev,
2865 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2866 AR_RADIO_SREV_MAJOR)),
2867 ah->hw_version.phyRev);
2868 }
2869
2870 hw_name[used] = '\0';
2871}
2872EXPORT_SYMBOL(ath9k_hw_name);
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