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ath9k: Cleanup Powersave flags
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
cfe8cba9 21#include "rc.h"
f078f209
LR		 22#include "initvals.h"
23
4febf7b8
LR		 24#define ATH9K_CLOCK_RATE_CCK 22
25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 27
cbe61d8a 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
25c56eec 29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
cbe61d8a 30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072 31 struct ar5416_eeprom_def *pEepData,
f1dc5600 32 u32 reg, u32 value);
f078f209 33
7322fd19
LR		 34MODULE_AUTHOR("Atheros Communications");
35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
36MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
37MODULE_LICENSE("Dual BSD/GPL");
38
39static int __init ath9k_init(void)
40{
41 return 0;
42}
43module_init(ath9k_init);
44
45static void __exit ath9k_exit(void)
46{
47 return;
48}
49module_exit(ath9k_exit);
50
f1dc5600
S		 51/********************/
52/* Helper Functions */
53/********************/
f078f209 54
cbe61d8a 55static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
f1dc5600 56{
b002a4a9 57 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 58
2660b81a 59 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 60 return clks / ATH9K_CLOCK_RATE_CCK;
61 if (conf->channel->band == IEEE80211_BAND_2GHZ)
62 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
cbe61d8a 63
4febf7b8 64 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 65}
f078f209 66
cbe61d8a 67static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
f1dc5600 68{
b002a4a9 69 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 70
4febf7b8 71 if (conf_is_ht40(conf))
f1dc5600
S		 72 return ath9k_hw_mac_usec(ah, clks) / 2;
73 else
74 return ath9k_hw_mac_usec(ah, clks);
75}
f078f209 76
cbe61d8a 77static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 78{
b002a4a9 79 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 80
2660b81a 81 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 82 return usecs *ATH9K_CLOCK_RATE_CCK;
83 if (conf->channel->band == IEEE80211_BAND_2GHZ)
84 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
85 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 86}
87
cbe61d8a 88static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 89{
b002a4a9 90 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 91
4febf7b8 92 if (conf_is_ht40(conf))
f1dc5600
S		 93 return ath9k_hw_mac_clks(ah, usecs) * 2;
94 else
95 return ath9k_hw_mac_clks(ah, usecs);
96}
f078f209 97
0caa7b14 98bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 99{
100 int i;
101
0caa7b14
S		 102 BUG_ON(timeout < AH_TIME_QUANTUM);
103
104 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 105 if ((REG_READ(ah, reg) & mask) == val)
106 return true;
107
108 udelay(AH_TIME_QUANTUM);
109 }
04bd4638 110
c46917bb
LR		 111 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
112 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
113 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 114
f1dc5600 115 return false;
f078f209 116}
7322fd19 117EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 118
119u32 ath9k_hw_reverse_bits(u32 val, u32 n)
120{
121 u32 retval;
122 int i;
123
124 for (i = 0, retval = 0; i < n; i++) {
125 retval = (retval << 1) | (val & 1);
126 val >>= 1;
127 }
128 return retval;
129}
130
cbe61d8a 131bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 132 u16 flags, u16 *low,
133 u16 *high)
f078f209 134{
2660b81a 135 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 136
f1dc5600
S		 137 if (flags & CHANNEL_5GHZ) {
138 *low = pCap->low_5ghz_chan;
139 *high = pCap->high_5ghz_chan;
140 return true;
f078f209 141 }
f1dc5600
S		 142 if ((flags & CHANNEL_2GHZ)) {
143 *low = pCap->low_2ghz_chan;
144 *high = pCap->high_2ghz_chan;
145 return true;
146 }
147 return false;
f078f209
LR		 148}
149
cbe61d8a 150u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 151 u8 phy, int kbps,
f1dc5600
S		 152 u32 frameLen, u16 rateix,
153 bool shortPreamble)
f078f209 154{
f1dc5600 155 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 156
f1dc5600
S		 157 if (kbps == 0)
158 return 0;
f078f209 159
545750d3 160 switch (phy) {
46d14a58 161 case WLAN_RC_PHY_CCK:
f1dc5600 162 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 163 if (shortPreamble)
f1dc5600
S		 164 phyTime >>= 1;
165 numBits = frameLen << 3;
166 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
167 break;
46d14a58 168 case WLAN_RC_PHY_OFDM:
2660b81a 169 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
171 numBits = OFDM_PLCP_BITS + (frameLen << 3);
172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
173 txTime = OFDM_SIFS_TIME_QUARTER
174 + OFDM_PREAMBLE_TIME_QUARTER
175 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 176 } else if (ah->curchan &&
177 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 178 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
179 numBits = OFDM_PLCP_BITS + (frameLen << 3);
180 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
181 txTime = OFDM_SIFS_TIME_HALF +
182 OFDM_PREAMBLE_TIME_HALF
183 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
184 } else {
185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
189 + (numSymbols * OFDM_SYMBOL_TIME);
190 }
191 break;
192 default:
c46917bb 193 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 194 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 195 txTime = 0;
196 break;
197 }
f078f209 198
f1dc5600
S		 199 return txTime;
200}
7322fd19 201EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 202
cbe61d8a 203void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 204 struct ath9k_channel *chan,
205 struct chan_centers *centers)
f078f209 206{
f1dc5600 207 int8_t extoff;
f078f209 208
f1dc5600
S		 209 if (!IS_CHAN_HT40(chan)) {
210 centers->ctl_center = centers->ext_center =
211 centers->synth_center = chan->channel;
212 return;
f078f209 213 }
f078f209 214
f1dc5600
S		 215 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
216 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
217 centers->synth_center =
218 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
219 extoff = 1;
220 } else {
221 centers->synth_center =
222 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
223 extoff = -1;
224 }
f078f209 225
f1dc5600
S		 226 centers->ctl_center =
227 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 228 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 229 centers->ext_center =
6420014c 230 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 231}
232
f1dc5600
S		 233/******************/
234/* Chip Revisions */
235/******************/
236
cbe61d8a 237static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 238{
f1dc5600 239 u32 val;
f078f209 240
f1dc5600 241 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 242
f1dc5600
S		 243 if (val == 0xFF) {
244 val = REG_READ(ah, AR_SREV);
d535a42a
S		 245 ah->hw_version.macVersion =
246 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
247 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 248 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 249 } else {
250 if (!AR_SREV_9100(ah))
d535a42a 251 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 252
d535a42a 253 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 254
d535a42a 255 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 256 ah->is_pciexpress = true;
f1dc5600 257 }
f078f209
LR		 258}
259
cbe61d8a 260static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 261{
f1dc5600
S		 262 u32 val;
263 int i;
f078f209 264
f1dc5600 265 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 266
f1dc5600
S		 267 for (i = 0; i < 8; i++)
268 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
269 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
270 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 271
f1dc5600 272 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 273}
274
f1dc5600
S		 275/************************************/
276/* HW Attach, Detach, Init Routines */
277/************************************/
278
cbe61d8a 279static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 280{
feed029c 281 if (AR_SREV_9100(ah))
f1dc5600 282 return;
f078f209 283
f1dc5600
S		 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 293
f1dc5600 294 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 295}
296
cbe61d8a 297static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 298{
c46917bb 299 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 300 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
301 u32 regHold[2];
302 u32 patternData[4] = { 0x55555555,
303 0xaaaaaaaa,
304 0x66666666,
305 0x99999999 };
306 int i, j;
f078f209 307
f1dc5600
S		 308 for (i = 0; i < 2; i++) {
309 u32 addr = regAddr[i];
310 u32 wrData, rdData;
f078f209 311
f1dc5600
S		 312 regHold[i] = REG_READ(ah, addr);
313 for (j = 0; j < 0x100; j++) {
314 wrData = (j << 16) | j;
315 REG_WRITE(ah, addr, wrData);
316 rdData = REG_READ(ah, addr);
317 if (rdData != wrData) {
c46917bb
LR		 318 ath_print(common, ATH_DBG_FATAL,
319 "address test failed "
320 "addr: 0x%08x - wr:0x%08x != "
321 "rd:0x%08x\n",
322 addr, wrData, rdData);
f1dc5600
S		 323 return false;
324 }
325 }
326 for (j = 0; j < 4; j++) {
327 wrData = patternData[j];
328 REG_WRITE(ah, addr, wrData);
329 rdData = REG_READ(ah, addr);
330 if (wrData != rdData) {
c46917bb
LR		 331 ath_print(common, ATH_DBG_FATAL,
332 "address test failed "
333 "addr: 0x%08x - wr:0x%08x != "
334 "rd:0x%08x\n",
335 addr, wrData, rdData);
f1dc5600
S		 336 return false;
337 }
f078f209 338 }
f1dc5600 339 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 340 }
f1dc5600 341 udelay(100);
cbe61d8a 342
f078f209
LR		 343 return true;
344}
345
b8b0f377 346static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 347{
348 int i;
f078f209 349
2660b81a
S		 350 ah->config.dma_beacon_response_time = 2;
351 ah->config.sw_beacon_response_time = 10;
352 ah->config.additional_swba_backoff = 0;
353 ah->config.ack_6mb = 0x0;
354 ah->config.cwm_ignore_extcca = 0;
355 ah->config.pcie_powersave_enable = 0;
2660b81a 356 ah->config.pcie_clock_req = 0;
2660b81a
S		 357 ah->config.pcie_waen = 0;
358 ah->config.analog_shiftreg = 1;
359 ah->config.ht_enable = 1;
360 ah->config.ofdm_trig_low = 200;
361 ah->config.ofdm_trig_high = 500;
362 ah->config.cck_trig_high = 200;
363 ah->config.cck_trig_low = 100;
364 ah->config.enable_ani = 1;
f078f209 365
f1dc5600 366 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 367 ah->config.spurchans[i][0] = AR_NO_SPUR;
368 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 369 }
370
0ce024cb 371 ah->config.rx_intr_mitigation = true;
6158425b
LR		 372
373 /*
374 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
375 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
376 * This means we use it for all AR5416 devices, and the few
377 * minor PCI AR9280 devices out there.
378 *
379 * Serialization is required because these devices do not handle
380 * well the case of two concurrent reads/writes due to the latency
381 * involved. During one read/write another read/write can be issued
382 * on another CPU while the previous read/write may still be working
383 * on our hardware, if we hit this case the hardware poops in a loop.
384 * We prevent this by serializing reads and writes.
385 *
386 * This issue is not present on PCI-Express devices or pre-AR5416
387 * devices (legacy, 802.11abg).
388 */
389 if (num_possible_cpus() > 1)
2d6a5e95 390 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209 391}
7322fd19 392EXPORT_SYMBOL(ath9k_hw_init);
f078f209 393
50aca25b 394static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 395{
608b88cb
LR		 396 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
397
398 regulatory->country_code = CTRY_DEFAULT;
399 regulatory->power_limit = MAX_RATE_POWER;
400 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
401
d535a42a 402 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 403 ah->hw_version.subvendorid = 0;
f078f209
LR		 404
405 ah->ah_flags = 0;
8df5d1b7 406 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
d535a42a 407 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
f078f209
LR		 408 if (!AR_SREV_9100(ah))
409 ah->ah_flags = AH_USE_EEPROM;
410
2660b81a 411 ah->atim_window = 0;
2660b81a
S		 412 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
413 ah->beacon_interval = 100;
414 ah->enable_32kHz_clock = DONT_USE_32KHZ;
415 ah->slottime = (u32) -1;
416 ah->acktimeout = (u32) -1;
417 ah->ctstimeout = (u32) -1;
418 ah->globaltxtimeout = (u32) -1;
cbdec975 419 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 420}
421
cbe61d8a 422static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 423{
f1dc5600
S		 424 u32 val;
425
426 REG_WRITE(ah, AR_PHY(0), 0x00000007);
427
428 val = ath9k_hw_get_radiorev(ah);
429 switch (val & AR_RADIO_SREV_MAJOR) {
430 case 0:
431 val = AR_RAD5133_SREV_MAJOR;
432 break;
433 case AR_RAD5133_SREV_MAJOR:
434 case AR_RAD5122_SREV_MAJOR:
435 case AR_RAD2133_SREV_MAJOR:
436 case AR_RAD2122_SREV_MAJOR:
437 break;
f078f209 438 default:
c46917bb
LR		 439 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
440 "Radio Chip Rev 0x%02X not supported\n",
441 val & AR_RADIO_SREV_MAJOR);
f1dc5600 442 return -EOPNOTSUPP;
f078f209 443 }
f078f209 444
d535a42a 445 ah->hw_version.analog5GhzRev = val;
f078f209 446
f1dc5600 447 return 0;
f078f209
LR		 448}
449
cbe61d8a 450static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 451{
1510718d 452 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 453 u32 sum;
454 int i;
455 u16 eeval;
f078f209
LR		 456
457 sum = 0;
458 for (i = 0; i < 3; i++) {
f74df6fb 459 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 460 sum += eeval;
1510718d
LR		 461 common->macaddr[2 * i] = eeval >> 8;
462 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 463 }
d8baa939 464 if (sum == 0 || sum == 0xffff * 3)
f078f209 465 return -EADDRNOTAVAIL;
f078f209
LR		 466
467 return 0;
468}
469
cbe61d8a 470static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 471{
472 u32 rxgain_type;
9f804202 473
f74df6fb
S		 474 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
475 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 476
477 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 478 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 479 ar9280Modes_backoff_13db_rxgain_9280_2,
480 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
481 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 482 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 483 ar9280Modes_backoff_23db_rxgain_9280_2,
484 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
485 else
2660b81a 486 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 487 ar9280Modes_original_rxgain_9280_2,
488 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 489 } else {
2660b81a 490 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 491 ar9280Modes_original_rxgain_9280_2,
492 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 493 }
9f804202
SB		 494}
495
cbe61d8a 496static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 497{
498 u32 txgain_type;
9f804202 499
f74df6fb
S		 500 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
501 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 502
503 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 504 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 505 ar9280Modes_high_power_tx_gain_9280_2,
506 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
507 else
2660b81a 508 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 509 ar9280Modes_original_tx_gain_9280_2,
510 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 511 } else {
2660b81a 512 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 513 ar9280Modes_original_tx_gain_9280_2,
514 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 515 }
9f804202
SB		 516}
517
f637cfd6 518static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 519{
f1dc5600 520 int ecode;
f078f209 521
d8baa939 522 if (!ath9k_hw_chip_test(ah))
f1dc5600 523 return -ENODEV;
f078f209 524
f1dc5600
S		 525 ecode = ath9k_hw_rf_claim(ah);
526 if (ecode != 0)
f078f209 527 return ecode;
f078f209 528
f637cfd6 529 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 530 if (ecode != 0)
531 return ecode;
7d01b221 532
c46917bb
LR		 533 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
534 "Eeprom VER: %d, REV: %d\n",
535 ah->eep_ops->get_eeprom_ver(ah),
536 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 537
574d6b12
LR		 538 if (!AR_SREV_9280_10_OR_LATER(ah)) {
539 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
540 if (ecode) {
541 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
542 "Failed allocating banks for "
543 "external radio\n");
544 return ecode;
545 }
546 }
f078f209 547
f1dc5600
S		 548 if (!AR_SREV_9100(ah)) {
549 ath9k_hw_ani_setup(ah);
f637cfd6 550 ath9k_hw_ani_init(ah);
f078f209
LR		 551 }
552
f078f209
LR		 553 return 0;
554}
555
ee2bb460
LR		 556static bool ath9k_hw_devid_supported(u16 devid)
557{
558 switch (devid) {
559 case AR5416_DEVID_PCI:
560 case AR5416_DEVID_PCIE:
561 case AR5416_AR9100_DEVID:
562 case AR9160_DEVID_PCI:
563 case AR9280_DEVID_PCI:
564 case AR9280_DEVID_PCIE:
565 case AR9285_DEVID_PCIE:
566 case AR5416_DEVID_AR9287_PCI:
567 case AR5416_DEVID_AR9287_PCIE:
7976b426 568 case AR9271_USB:
ee2bb460
LR		 569 return true;
570 default:
571 break;
572 }
573 return false;
574}
575
f9d4a668
LR		 576static bool ath9k_hw_macversion_supported(u32 macversion)
577{
578 switch (macversion) {
579 case AR_SREV_VERSION_5416_PCI:
580 case AR_SREV_VERSION_5416_PCIE:
581 case AR_SREV_VERSION_9160:
582 case AR_SREV_VERSION_9100:
583 case AR_SREV_VERSION_9280:
584 case AR_SREV_VERSION_9285:
585 case AR_SREV_VERSION_9287:
d7e7d229 586 case AR_SREV_VERSION_9271:
7976b426 587 return true;
f9d4a668
LR		 588 default:
589 break;
590 }
591 return false;
592}
593
aa4058ae 594static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
f078f209 595{
f1dc5600
S		 596 if (AR_SREV_9160_10_OR_LATER(ah)) {
597 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a
S		 598 ah->iq_caldata.calData = &iq_cal_single_sample;
599 ah->adcgain_caldata.calData =
f1dc5600 600 &adc_gain_cal_single_sample;
2660b81a 601 ah->adcdc_caldata.calData =
f1dc5600 602 &adc_dc_cal_single_sample;
2660b81a 603 ah->adcdc_calinitdata.calData =
f1dc5600
S		 604 &adc_init_dc_cal;
605 } else {
2660b81a
S		 606 ah->iq_caldata.calData = &iq_cal_multi_sample;
607 ah->adcgain_caldata.calData =
f1dc5600 608 &adc_gain_cal_multi_sample;
2660b81a 609 ah->adcdc_caldata.calData =
f1dc5600 610 &adc_dc_cal_multi_sample;
2660b81a 611 ah->adcdc_calinitdata.calData =
f1dc5600
S		 612 &adc_init_dc_cal;
613 }
2660b81a 614 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
f1dc5600 615 }
aa4058ae 616}
f078f209 617
aa4058ae
LR		 618static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
619{
d7e7d229 620 if (AR_SREV_9271(ah)) {
8564328d
LR		 621 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
622 ARRAY_SIZE(ar9271Modes_9271), 6);
623 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
624 ARRAY_SIZE(ar9271Common_9271), 2);
625 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
626 ar9271Modes_9271_1_0_only,
627 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
d7e7d229
LR		 628 return;
629 }
630
ac88b6ec
VN		 631 if (AR_SREV_9287_11_OR_LATER(ah)) {
632 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
633 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
634 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
635 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
636 if (ah->config.pcie_clock_req)
637 INIT_INI_ARRAY(&ah->iniPcieSerdes,
638 ar9287PciePhy_clkreq_off_L1_9287_1_1,
639 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
640 else
641 INIT_INI_ARRAY(&ah->iniPcieSerdes,
642 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
643 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
644 2);
645 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
646 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
647 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
648 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
649 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
650
651 if (ah->config.pcie_clock_req)
652 INIT_INI_ARRAY(&ah->iniPcieSerdes,
653 ar9287PciePhy_clkreq_off_L1_9287_1_0,
654 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
655 else
656 INIT_INI_ARRAY(&ah->iniPcieSerdes,
657 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
658 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
659 2);
660 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
f078f209 661
4e845168 662
2660b81a 663 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
e7594072 664 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
2660b81a 665 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
e7594072
SB		 666 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
667
2660b81a
S		 668 if (ah->config.pcie_clock_req) {
669 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 670 ar9285PciePhy_clkreq_off_L1_9285_1_2,
671 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
672 } else {
2660b81a 673 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 674 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
675 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
676 2);
677 }
678 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
2660b81a 679 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
e7594072 680 ARRAY_SIZE(ar9285Modes_9285), 6);
2660b81a 681 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
e7594072
SB		 682 ARRAY_SIZE(ar9285Common_9285), 2);
683
2660b81a
S		 684 if (ah->config.pcie_clock_req) {
685 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 686 ar9285PciePhy_clkreq_off_L1_9285,
687 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
688 } else {
2660b81a 689 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 690 ar9285PciePhy_clkreq_always_on_L1_9285,
691 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
692 }
693 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a 694 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
f1dc5600 695 ARRAY_SIZE(ar9280Modes_9280_2), 6);
2660b81a 696 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
f1dc5600 697 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 698
2660b81a
S		 699 if (ah->config.pcie_clock_req) {
700 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 701 ar9280PciePhy_clkreq_off_L1_9280,
702 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
703 } else {
2660b81a 704 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 705 ar9280PciePhy_clkreq_always_on_L1_9280,
706 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
707 }
2660b81a 708 INIT_INI_ARRAY(&ah->iniModesAdditional,
f1dc5600
S		 709 ar9280Modes_fast_clock_9280_2,
710 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
711 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 712 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
f1dc5600 713 ARRAY_SIZE(ar9280Modes_9280), 6);
2660b81a 714 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
f1dc5600
S		 715 ARRAY_SIZE(ar9280Common_9280), 2);
716 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2660b81a 717 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
f1dc5600 718 ARRAY_SIZE(ar5416Modes_9160), 6);
2660b81a 719 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
f1dc5600 720 ARRAY_SIZE(ar5416Common_9160), 2);
2660b81a 721 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
f1dc5600 722 ARRAY_SIZE(ar5416Bank0_9160), 2);
2660b81a 723 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
f1dc5600 724 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
2660b81a 725 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
f1dc5600 726 ARRAY_SIZE(ar5416Bank1_9160), 2);
2660b81a 727 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
f1dc5600 728 ARRAY_SIZE(ar5416Bank2_9160), 2);
2660b81a 729 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
f1dc5600 730 ARRAY_SIZE(ar5416Bank3_9160), 3);
2660b81a 731 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
f1dc5600 732 ARRAY_SIZE(ar5416Bank6_9160), 3);
2660b81a 733 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
f1dc5600 734 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
2660b81a 735 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
f1dc5600
S		 736 ARRAY_SIZE(ar5416Bank7_9160), 2);
737 if (AR_SREV_9160_11(ah)) {
2660b81a 738 INIT_INI_ARRAY(&ah->iniAddac,
f1dc5600
S		 739 ar5416Addac_91601_1,
740 ARRAY_SIZE(ar5416Addac_91601_1), 2);
741 } else {
2660b81a 742 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
f1dc5600
S		 743 ARRAY_SIZE(ar5416Addac_9160), 2);
744 }
745 } else if (AR_SREV_9100_OR_LATER(ah)) {
2660b81a 746 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
f1dc5600 747 ARRAY_SIZE(ar5416Modes_9100), 6);
2660b81a 748 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
f1dc5600 749 ARRAY_SIZE(ar5416Common_9100), 2);
2660b81a 750 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
f1dc5600 751 ARRAY_SIZE(ar5416Bank0_9100), 2);
2660b81a 752 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
f1dc5600 753 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
2660b81a 754 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
f1dc5600 755 ARRAY_SIZE(ar5416Bank1_9100), 2);
2660b81a 756 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
f1dc5600 757 ARRAY_SIZE(ar5416Bank2_9100), 2);
2660b81a 758 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
f1dc5600 759 ARRAY_SIZE(ar5416Bank3_9100), 3);
2660b81a 760 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
f1dc5600 761 ARRAY_SIZE(ar5416Bank6_9100), 3);
2660b81a 762 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
f1dc5600 763 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
2660b81a 764 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
f1dc5600 765 ARRAY_SIZE(ar5416Bank7_9100), 2);
2660b81a 766 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
f1dc5600
S		 767 ARRAY_SIZE(ar5416Addac_9100), 2);
768 } else {
2660b81a 769 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
f1dc5600 770 ARRAY_SIZE(ar5416Modes), 6);
2660b81a 771 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
f1dc5600 772 ARRAY_SIZE(ar5416Common), 2);
2660b81a 773 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
f1dc5600 774 ARRAY_SIZE(ar5416Bank0), 2);
2660b81a 775 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
f1dc5600 776 ARRAY_SIZE(ar5416BB_RfGain), 3);
2660b81a 777 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
f1dc5600 778 ARRAY_SIZE(ar5416Bank1), 2);
2660b81a 779 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
f1dc5600 780 ARRAY_SIZE(ar5416Bank2), 2);
2660b81a 781 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
f1dc5600 782 ARRAY_SIZE(ar5416Bank3), 3);
2660b81a 783 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
f1dc5600 784 ARRAY_SIZE(ar5416Bank6), 3);
2660b81a 785 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
f1dc5600 786 ARRAY_SIZE(ar5416Bank6TPC), 3);
2660b81a 787 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
f1dc5600 788 ARRAY_SIZE(ar5416Bank7), 2);
2660b81a 789 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
f1dc5600 790 ARRAY_SIZE(ar5416Addac), 2);
f078f209 791 }
aa4058ae 792}
f078f209 793
aa4058ae
LR		 794static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
795{
b37fa870 796 if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec
VN		 797 INIT_INI_ARRAY(&ah->iniModesRxGain,
798 ar9287Modes_rx_gain_9287_1_1,
799 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
800 else if (AR_SREV_9287_10(ah))
801 INIT_INI_ARRAY(&ah->iniModesRxGain,
802 ar9287Modes_rx_gain_9287_1_0,
803 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
804 else if (AR_SREV_9280_20(ah))
805 ath9k_hw_init_rxgain_ini(ah);
806
b37fa870 807 if (AR_SREV_9287_11_OR_LATER(ah)) {
ac88b6ec
VN		 808 INIT_INI_ARRAY(&ah->iniModesTxGain,
809 ar9287Modes_tx_gain_9287_1_1,
810 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
811 } else if (AR_SREV_9287_10(ah)) {
812 INIT_INI_ARRAY(&ah->iniModesTxGain,
813 ar9287Modes_tx_gain_9287_1_0,
814 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
815 } else if (AR_SREV_9280_20(ah)) {
816 ath9k_hw_init_txgain_ini(ah);
817 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4e845168
SB		 818 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
819
820 /* txgain table */
821 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
822 INIT_INI_ARRAY(&ah->iniModesTxGain,
823 ar9285Modes_high_power_tx_gain_9285_1_2,
824 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
825 } else {
826 INIT_INI_ARRAY(&ah->iniModesTxGain,
827 ar9285Modes_original_tx_gain_9285_1_2,
828 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
829 }
830
831 }
aa4058ae 832}
4e845168 833
aa4058ae
LR		 834static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
835{
836 u32 i, j;
06d0f066
S		 837
838 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
839 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
840
841 /* EEPROM Fixup */
2660b81a
S		 842 for (i = 0; i < ah->iniModes.ia_rows; i++) {
843 u32 reg = INI_RA(&ah->iniModes, i, 0);
f078f209 844
2660b81a
S		 845 for (j = 1; j < ah->iniModes.ia_columns; j++) {
846 u32 val = INI_RA(&ah->iniModes, i, j);
f078f209 847
2660b81a 848 INI_RA(&ah->iniModes, i, j) =
e7594072 849 ath9k_hw_ini_fixup(ah,
2660b81a 850 &ah->eeprom.def,
f1dc5600
S		 851 reg, val);
852 }
f078f209 853 }
f1dc5600 854 }
aa4058ae
LR		 855}
856
f637cfd6 857int ath9k_hw_init(struct ath_hw *ah)
aa4058ae 858{
c46917bb 859 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 860 int r = 0;
aa4058ae 861
3ca34038
LR		 862 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
863 ath_print(common, ATH_DBG_FATAL,
864 "Unsupported device ID: 0x%0x\n",
865 ah->hw_version.devid);
95fafca2 866 return -EOPNOTSUPP;
3ca34038 867 }
aa4058ae
LR		 868
869 ath9k_hw_init_defaults(ah);
870 ath9k_hw_init_config(ah);
871
872 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 873 ath_print(common, ATH_DBG_FATAL,
874 "Couldn't reset chip\n");
95fafca2 875 return -EIO;
aa4058ae
LR		 876 }
877
9ecdef4b 878 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 879 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 880 return -EIO;
aa4058ae
LR		 881 }
882
883 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
884 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
885 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
886 ah->config.serialize_regmode =
887 SER_REG_MODE_ON;
888 } else {
889 ah->config.serialize_regmode =
890 SER_REG_MODE_OFF;
891 }
892 }
893
c46917bb 894 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 895 ah->config.serialize_regmode);
896
f4709fdf
LR		 897 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
898 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
899 else
900 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
901
aa4058ae 902 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
c46917bb
LR		 903 ath_print(common, ATH_DBG_FATAL,
904 "Mac Chip Rev 0x%02x.%x is not supported by "
905 "this driver\n", ah->hw_version.macVersion,
906 ah->hw_version.macRev);
95fafca2 907 return -EOPNOTSUPP;
aa4058ae
LR		 908 }
909
910 if (AR_SREV_9100(ah)) {
911 ah->iq_caldata.calData = &iq_cal_multi_sample;
912 ah->supp_cals = IQ_MISMATCH_CAL;
913 ah->is_pciexpress = false;
914 }
d7e7d229
LR		 915
916 if (AR_SREV_9271(ah))
917 ah->is_pciexpress = false;
918
aa4058ae
LR		 919 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
920
921 ath9k_hw_init_cal_settings(ah);
922
923 ah->ani_function = ATH9K_ANI_ALL;
e68a060b 924 if (AR_SREV_9280_10_OR_LATER(ah)) {
aa4058ae 925 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e68a060b 926 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
ae478cf6
LR		 927 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
928 } else {
e68a060b 929 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
ae478cf6
LR		 930 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
931 }
aa4058ae
LR		 932
933 ath9k_hw_init_mode_regs(ah);
934
935 if (ah->is_pciexpress)
93b1b37f 936 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 937 else
938 ath9k_hw_disablepcie(ah);
939
193cd458
S		 940 /* Support for Japan ch.14 (2484) spread */
941 if (AR_SREV_9287_11_OR_LATER(ah)) {
942 INIT_INI_ARRAY(&ah->iniCckfirNormal,
943 ar9287Common_normal_cck_fir_coeff_92871_1,
944 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
945 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
946 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
947 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
948 }
949
f637cfd6 950 r = ath9k_hw_post_init(ah);
aa4058ae 951 if (r)
95fafca2 952 return r;
aa4058ae
LR		 953
954 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 955 r = ath9k_hw_fill_cap_info(ah);
956 if (r)
957 return r;
958
aa4058ae 959 ath9k_hw_init_11a_eeprom_fix(ah);
f6688cd8 960
4f3acf81
LR		 961 r = ath9k_hw_init_macaddr(ah);
962 if (r) {
c46917bb
LR		 963 ath_print(common, ATH_DBG_FATAL,
964 "Failed to initialize MAC address\n");
95fafca2 965 return r;
f078f209
LR		 966 }
967
d7e7d229 968 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 969 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 970 else
2660b81a 971 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 972
f1dc5600 973 ath9k_init_nfcal_hist_buffer(ah);
f078f209 974
211f5859
LR		 975 common->state = ATH_HW_INITIALIZED;
976
4f3acf81 977 return 0;
f078f209
LR		 978}
979
cbe61d8a 980static void ath9k_hw_init_bb(struct ath_hw *ah,
f1dc5600 981 struct ath9k_channel *chan)
f078f209 982{
f1dc5600 983 u32 synthDelay;
f078f209 984
f1dc5600 985 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 986 if (IS_CHAN_B(chan))
f1dc5600
S		 987 synthDelay = (4 * synthDelay) / 22;
988 else
989 synthDelay /= 10;
f078f209 990
f1dc5600 991 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 992
f1dc5600 993 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 994}
995
cbe61d8a 996static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 997{
f1dc5600
S		 998 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
999 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 1000
f1dc5600
S		 1001 REG_WRITE(ah, AR_QOS_NO_ACK,
1002 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1003 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1004 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1005
1006 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1007 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1008 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1009 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1010 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 1011}
1012
c75724d1
LR		 1013static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
1014{
1015 u32 lcr;
1016 u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
1017
1018 lcr = REG_READ(ah , 0x5100c);
1019 lcr |= 0x80;
1020
1021 REG_WRITE(ah, 0x5100c, lcr);
1022 REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1023 REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1024
1025 lcr &= ~0x80;
1026 REG_WRITE(ah, 0x5100c, lcr);
1027}
1028
cbe61d8a 1029static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 1030 struct ath9k_channel *chan)
f078f209 1031{
f1dc5600 1032 u32 pll;
f078f209 1033
f1dc5600
S		 1034 if (AR_SREV_9100(ah)) {
1035 if (chan && IS_CHAN_5GHZ(chan))
1036 pll = 0x1450;
f078f209 1037 else
f1dc5600
S		 1038 pll = 0x1458;
1039 } else {
1040 if (AR_SREV_9280_10_OR_LATER(ah)) {
1041 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1042
f1dc5600
S		 1043 if (chan && IS_CHAN_HALF_RATE(chan))
1044 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1045 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1046 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1047
f1dc5600
S		 1048 if (chan && IS_CHAN_5GHZ(chan)) {
1049 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 1050
f078f209 1051
f1dc5600
S		 1052 if (AR_SREV_9280_20(ah)) {
1053 if (((chan->channel % 20) == 0)
1054 || ((chan->channel % 10) == 0))
1055 pll = 0x2850;
1056 else
1057 pll = 0x142c;
1058 }
1059 } else {
1060 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1061 }
f078f209 1062
f1dc5600 1063 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 1064
f1dc5600 1065 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1066
f1dc5600
S		 1067 if (chan && IS_CHAN_HALF_RATE(chan))
1068 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1069 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1070 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1071
f1dc5600
S		 1072 if (chan && IS_CHAN_5GHZ(chan))
1073 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1074 else
1075 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1076 } else {
1077 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 1078
f1dc5600
S		 1079 if (chan && IS_CHAN_HALF_RATE(chan))
1080 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1081 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1082 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 1083
f1dc5600
S		 1084 if (chan && IS_CHAN_5GHZ(chan))
1085 pll |= SM(0xa, AR_RTC_PLL_DIV);
1086 else
1087 pll |= SM(0xb, AR_RTC_PLL_DIV);
1088 }
1089 }
d03a66c1 1090 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 1091
c75724d1
LR		 1092 /* Switch the core clock for ar9271 to 117Mhz */
1093 if (AR_SREV_9271(ah)) {
1094 if ((pll == 0x142c) || (pll == 0x2850) ) {
1095 udelay(500);
1096 /* set CLKOBS to output AHB clock */
1097 REG_WRITE(ah, 0x7020, 0xe);
1098 /*
1099 * 0x304: 117Mhz, ahb_ratio: 1x1
1100 * 0x306: 40Mhz, ahb_ratio: 1x1
1101 */
1102 REG_WRITE(ah, 0x50040, 0x304);
1103 /*
1104 * makes adjustments for the baud dividor to keep the
1105 * targetted baud rate based on the used core clock.
1106 */
1107 ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1108 AR9271_TARGET_BAUD_RATE);
1109 }
1110 }
1111
f1dc5600
S		 1112 udelay(RTC_PLL_SETTLE_DELAY);
1113
1114 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1115}
1116
cbe61d8a 1117static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
f078f209 1118{
f078f209
LR		 1119 int rx_chainmask, tx_chainmask;
1120
2660b81a
S		 1121 rx_chainmask = ah->rxchainmask;
1122 tx_chainmask = ah->txchainmask;
f078f209
LR		 1123
1124 switch (rx_chainmask) {
1125 case 0x5:
1126 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1127 AR_PHY_SWAP_ALT_CHAIN);
1128 case 0x3:
cb53a150 1129 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
f078f209
LR		 1130 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1131 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1132 break;
1133 }
1134 case 0x1:
1135 case 0x2:
f078f209
LR		 1136 case 0x7:
1137 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1138 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1139 break;
1140 default:
1141 break;
1142 }
1143
1144 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1145 if (tx_chainmask == 0x5) {
1146 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1147 AR_PHY_SWAP_ALT_CHAIN);
1148 }
1149 if (AR_SREV_9100(ah))
1150 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1151 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1152}
1153
cbe61d8a 1154static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 1155 enum nl80211_iftype opmode)
f078f209 1156{
2660b81a 1157 ah->mask_reg = AR_IMR_TXERR |
f1dc5600
S		 1158 AR_IMR_TXURN |
1159 AR_IMR_RXERR |
1160 AR_IMR_RXORN |
1161 AR_IMR_BCNMISC;
f078f209 1162
0ce024cb 1163 if (ah->config.rx_intr_mitigation)
2660b81a 1164 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1165 else
2660b81a 1166 ah->mask_reg |= AR_IMR_RXOK;
f078f209 1167
2660b81a 1168 ah->mask_reg |= AR_IMR_TXOK;
f078f209 1169
d97809db 1170 if (opmode == NL80211_IFTYPE_AP)
2660b81a 1171 ah->mask_reg |= AR_IMR_MIB;
f078f209 1172
2660b81a 1173 REG_WRITE(ah, AR_IMR, ah->mask_reg);
f1dc5600 1174 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1175
f1dc5600
S		 1176 if (!AR_SREV_9100(ah)) {
1177 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1178 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1179 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1180 }
f078f209
LR		 1181}
1182
cbe61d8a 1183static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1184{
f078f209 1185 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
c46917bb
LR		 1186 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1187 "bad ack timeout %u\n", us);
2660b81a 1188 ah->acktimeout = (u32) -1;
f078f209
LR		 1189 return false;
1190 } else {
1191 REG_RMW_FIELD(ah, AR_TIME_OUT,
1192 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1193 ah->acktimeout = us;
f078f209
LR		 1194 return true;
1195 }
1196}
1197
cbe61d8a 1198static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
f078f209 1199{
f078f209 1200 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
c46917bb
LR		 1201 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1202 "bad cts timeout %u\n", us);
2660b81a 1203 ah->ctstimeout = (u32) -1;
f078f209
LR		 1204 return false;
1205 } else {
1206 REG_RMW_FIELD(ah, AR_TIME_OUT,
1207 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1208 ah->ctstimeout = us;
f078f209
LR		 1209 return true;
1210 }
1211}
f1dc5600 1212
cbe61d8a 1213static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1214{
f078f209 1215 if (tu > 0xFFFF) {
c46917bb
LR		 1216 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1217 "bad global tx timeout %u\n", tu);
2660b81a 1218 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1219 return false;
1220 } else {
1221 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1222 ah->globaltxtimeout = tu;
f078f209
LR		 1223 return true;
1224 }
1225}
1226
cbe61d8a 1227static void ath9k_hw_init_user_settings(struct ath_hw *ah)
f078f209 1228{
c46917bb
LR		 1229 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1230 ah->misc_mode);
f078f209 1231
2660b81a 1232 if (ah->misc_mode != 0)
f1dc5600 1233 REG_WRITE(ah, AR_PCU_MISC,
2660b81a
S		 1234 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1235 if (ah->slottime != (u32) -1)
1236 ath9k_hw_setslottime(ah, ah->slottime);
1237 if (ah->acktimeout != (u32) -1)
1238 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1239 if (ah->ctstimeout != (u32) -1)
1240 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1241 if (ah->globaltxtimeout != (u32) -1)
1242 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600
S		 1243}
1244
cbe61d8a 1245void ath9k_hw_detach(struct ath_hw *ah)
f1dc5600 1246{
211f5859
LR		 1247 struct ath_common *common = ath9k_hw_common(ah);
1248
1249 if (common->state <= ATH_HW_INITIALIZED)
1250 goto free_hw;
1251
f1dc5600 1252 if (!AR_SREV_9100(ah))
e70c0cfd 1253 ath9k_hw_ani_disable(ah);
f1dc5600 1254
9ecdef4b 1255 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 1256
1257free_hw:
dc51dd50
LR		 1258 if (!AR_SREV_9280_10_OR_LATER(ah))
1259 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 1260 kfree(ah);
9db6b6a2 1261 ah = NULL;
f1dc5600 1262}
7322fd19 1263EXPORT_SYMBOL(ath9k_hw_detach);
f1dc5600 1264
f1dc5600
S		 1265/*******/
1266/* INI */
1267/*******/
1268
cbe61d8a 1269static void ath9k_hw_override_ini(struct ath_hw *ah,
f1dc5600
S		 1270 struct ath9k_channel *chan)
1271{
d7e7d229
LR		 1272 u32 val;
1273
1274 if (AR_SREV_9271(ah)) {
1275 /*
1276 * Enable spectral scan to solution for issues with stuck
1277 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1278 * AR9271 1.1
1279 */
1280 if (AR_SREV_9271_10(ah)) {
ec11bb88
LR		 1281 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) |
1282 AR_PHY_SPECTRAL_SCAN_ENABLE;
d7e7d229
LR		 1283 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1284 }
1285 else if (AR_SREV_9271_11(ah))
1286 /*
1287 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1288 * present on AR9271 1.1
1289 */
1290 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1291 return;
1292 }
1293
8aa15e15
SB		 1294 /*
1295 * Set the RX_ABORT and RX_DIS and clear if off only after
1296 * RXE is set for MAC. This prevents frames with corrupted
1297 * descriptor status.
1298 */
1299 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1300
204d7940
VT		 1301 if (AR_SREV_9280_10_OR_LATER(ah)) {
1302 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1303 (~AR_PCU_MISC_MODE2_HWWAR1);
1304
1305 if (AR_SREV_9287_10_OR_LATER(ah))
1306 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1307
1308 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1309 }
8aa15e15 1310
a8c96d3b 1311 if (!AR_SREV_5416_20_OR_LATER(ah) ||
f1dc5600
S		 1312 AR_SREV_9280_10_OR_LATER(ah))
1313 return;
d7e7d229
LR		 1314 /*
1315 * Disable BB clock gating
1316 * Necessary to avoid issues on AR5416 2.0
1317 */
f1dc5600 1318 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1319}
1320
cbe61d8a 1321static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
e7594072 1322 struct ar5416_eeprom_def *pEepData,
f1dc5600 1323 u32 reg, u32 value)
f078f209 1324{
f1dc5600 1325 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
c46917bb 1326 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1327
d535a42a 1328 switch (ah->hw_version.devid) {
f1dc5600
S		 1329 case AR9280_DEVID_PCI:
1330 if (reg == 0x7894) {
c46917bb 1331 ath_print(common, ATH_DBG_EEPROM,
f1dc5600
S		 1332 "ini VAL: %x EEPROM: %x\n", value,
1333 (pBase->version & 0xff));
1334
1335 if ((pBase->version & 0xff) > 0x0a) {
c46917bb
LR		 1336 ath_print(common, ATH_DBG_EEPROM,
1337 "PWDCLKIND: %d\n",
1338 pBase->pwdclkind);
f1dc5600
S		 1339 value &= ~AR_AN_TOP2_PWDCLKIND;
1340 value |= AR_AN_TOP2_PWDCLKIND &
1341 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1342 } else {
c46917bb
LR		 1343 ath_print(common, ATH_DBG_EEPROM,
1344 "PWDCLKIND Earlier Rev\n");
f1dc5600
S		 1345 }
1346
c46917bb
LR		 1347 ath_print(common, ATH_DBG_EEPROM,
1348 "final ini VAL: %x\n", value);
f1dc5600
S		 1349 }
1350 break;
1351 }
1352
1353 return value;
f078f209
LR		 1354}
1355
cbe61d8a 1356static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072
SB		 1357 struct ar5416_eeprom_def *pEepData,
1358 u32 reg, u32 value)
1359{
2660b81a 1360 if (ah->eep_map == EEP_MAP_4KBITS)
e7594072
SB		 1361 return value;
1362 else
1363 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1364}
1365
8bd1d07f
SB		 1366static void ath9k_olc_init(struct ath_hw *ah)
1367{
1368 u32 i;
1369
db91f2e4
VN		 1370 if (OLC_FOR_AR9287_10_LATER) {
1371 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1372 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1373 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1374 AR9287_AN_TXPC0_TXPCMODE,
1375 AR9287_AN_TXPC0_TXPCMODE_S,
1376 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1377 udelay(100);
1378 } else {
1379 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1380 ah->originalGain[i] =
1381 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1382 AR_PHY_TX_GAIN);
1383 ah->PDADCdelta = 0;
1384 }
8bd1d07f
SB		 1385}
1386
3a702e49
BC		 1387static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1388 struct ath9k_channel *chan)
1389{
1390 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1391
1392 if (IS_CHAN_B(chan))
1393 ctl |= CTL_11B;
1394 else if (IS_CHAN_G(chan))
1395 ctl |= CTL_11G;
1396 else
1397 ctl |= CTL_11A;
1398
1399 return ctl;
1400}
1401
cbe61d8a 1402static int ath9k_hw_process_ini(struct ath_hw *ah,
25c56eec 1403 struct ath9k_channel *chan)
f078f209 1404{
608b88cb 1405 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f078f209 1406 int i, regWrites = 0;
5f8e077c 1407 struct ieee80211_channel *channel = chan->chan;
f078f209 1408 u32 modesIndex, freqIndex;
f078f209
LR		 1409
1410 switch (chan->chanmode) {
1411 case CHANNEL_A:
1412 case CHANNEL_A_HT20:
1413 modesIndex = 1;
1414 freqIndex = 1;
1415 break;
1416 case CHANNEL_A_HT40PLUS:
1417 case CHANNEL_A_HT40MINUS:
1418 modesIndex = 2;
1419 freqIndex = 1;
1420 break;
1421 case CHANNEL_G:
1422 case CHANNEL_G_HT20:
1423 case CHANNEL_B:
1424 modesIndex = 4;
1425 freqIndex = 2;
1426 break;
1427 case CHANNEL_G_HT40PLUS:
1428 case CHANNEL_G_HT40MINUS:
1429 modesIndex = 3;
1430 freqIndex = 2;
1431 break;
1432
1433 default:
1434 return -EINVAL;
1435 }
1436
1437 REG_WRITE(ah, AR_PHY(0), 0x00000007);
f078f209 1438 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
f74df6fb 1439 ah->eep_ops->set_addac(ah, chan);
f078f209 1440
a8c96d3b 1441 if (AR_SREV_5416_22_OR_LATER(ah)) {
2660b81a 1442 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
f078f209
LR		 1443 } else {
1444 struct ar5416IniArray temp;
1445 u32 addacSize =
2660b81a
S		 1446 sizeof(u32) * ah->iniAddac.ia_rows *
1447 ah->iniAddac.ia_columns;
f078f209 1448
2660b81a
S		 1449 memcpy(ah->addac5416_21,
1450 ah->iniAddac.ia_array, addacSize);
f078f209 1451
2660b81a 1452 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
f078f209 1453
2660b81a
S		 1454 temp.ia_array = ah->addac5416_21;
1455 temp.ia_columns = ah->iniAddac.ia_columns;
1456 temp.ia_rows = ah->iniAddac.ia_rows;
f078f209
LR		 1457 REG_WRITE_ARRAY(&temp, 1, regWrites);
1458 }
f1dc5600 1459
f078f209
LR		 1460 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1461
2660b81a
S		 1462 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1463 u32 reg = INI_RA(&ah->iniModes, i, 0);
1464 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
f078f209 1465
f078f209
LR		 1466 REG_WRITE(ah, reg, val);
1467
1468 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1469 && ah->config.analog_shiftreg) {
f078f209
LR		 1470 udelay(100);
1471 }
1472
1473 DO_DELAY(regWrites);
1474 }
1475
ac88b6ec 1476 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1477 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
9f804202 1478
ac88b6ec
VN		 1479 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1480 AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1481 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
9f804202 1482
2660b81a
S		 1483 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1484 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1485 u32 val = INI_RA(&ah->iniCommon, i, 1);
f078f209
LR		 1486
1487 REG_WRITE(ah, reg, val);
1488
1489 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1490 && ah->config.analog_shiftreg) {
f078f209
LR		 1491 udelay(100);
1492 }
1493
1494 DO_DELAY(regWrites);
1495 }
1496
896ff260 1497 ath9k_hw_write_regs(ah, freqIndex, regWrites);
f078f209 1498
8564328d
LR		 1499 if (AR_SREV_9271_10(ah))
1500 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1501 modesIndex, regWrites);
1502
f078f209 1503 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
2660b81a 1504 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
f078f209
LR		 1505 regWrites);
1506 }
1507
1508 ath9k_hw_override_ini(ah, chan);
25c56eec 1509 ath9k_hw_set_regs(ah, chan);
f078f209
LR		 1510 ath9k_hw_init_chain_masks(ah);
1511
8bd1d07f
SB		 1512 if (OLC_FOR_AR9280_20_LATER)
1513 ath9k_olc_init(ah);
1514
8fbff4b8 1515 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1516 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 1517 channel->max_antenna_gain * 2,
1518 channel->max_power * 2,
1519 min((u32) MAX_RATE_POWER,
608b88cb 1520 (u32) regulatory->power_limit));
f078f209
LR		 1521
1522 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
c46917bb
LR		 1523 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1524 "ar5416SetRfRegs failed\n");
f078f209
LR		 1525 return -EIO;
1526 }
1527
1528 return 0;
1529}
1530
f1dc5600
S		 1531/****************************************/
1532/* Reset and Channel Switching Routines */
1533/****************************************/
1534
cbe61d8a 1535static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1536{
f1dc5600
S		 1537 u32 rfMode = 0;
1538
1539 if (chan == NULL)
1540 return;
1541
1542 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1543 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1544
1545 if (!AR_SREV_9280_10_OR_LATER(ah))
1546 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1547 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1548
1549 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1550 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1551
1552 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1553}
1554
cbe61d8a 1555static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
f1dc5600
S		 1556{
1557 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1558}
1559
cbe61d8a 1560static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 1561{
1562 u32 regval;
1563
d7e7d229
LR		 1564 /*
1565 * set AHB_MODE not to do cacheline prefetches
1566 */
f1dc5600
S		 1567 regval = REG_READ(ah, AR_AHB_MODE);
1568 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1569
d7e7d229
LR		 1570 /*
1571 * let mac dma reads be in 128 byte chunks
1572 */
f1dc5600
S		 1573 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1574 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1575
d7e7d229
LR		 1576 /*
1577 * Restore TX Trigger Level to its pre-reset value.
1578 * The initial value depends on whether aggregation is enabled, and is
1579 * adjusted whenever underruns are detected.
1580 */
2660b81a 1581 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1582
d7e7d229
LR		 1583 /*
1584 * let mac dma writes be in 128 byte chunks
1585 */
f1dc5600
S		 1586 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1587 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1588
d7e7d229
LR		 1589 /*
1590 * Setup receive FIFO threshold to hold off TX activities
1591 */
f1dc5600
S		 1592 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1593
d7e7d229
LR		 1594 /*
1595 * reduce the number of usable entries in PCU TXBUF to avoid
1596 * wrap around issues.
1597 */
f1dc5600 1598 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1599 /* For AR9285 the number of Fifos are reduced to half.
1600 * So set the usable tx buf size also to half to
1601 * avoid data/delimiter underruns
1602 */
f1dc5600
S		 1603 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1604 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1605 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1606 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1607 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1608 }
1609}
1610
cbe61d8a 1611static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1612{
1613 u32 val;
1614
1615 val = REG_READ(ah, AR_STA_ID1);
1616 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1617 switch (opmode) {
d97809db 1618 case NL80211_IFTYPE_AP:
f1dc5600
S		 1619 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1620 | AR_STA_ID1_KSRCH_MODE);
1621 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1622 break;
d97809db 1623 case NL80211_IFTYPE_ADHOC:
9cb5412b 1624 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 1625 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1626 | AR_STA_ID1_KSRCH_MODE);
1627 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1628 break;
d97809db
CM		 1629 case NL80211_IFTYPE_STATION:
1630 case NL80211_IFTYPE_MONITOR:
f1dc5600 1631 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1632 break;
f1dc5600
S		 1633 }
1634}
1635
cbe61d8a 1636static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
f1dc5600
S		 1637 u32 coef_scaled,
1638 u32 *coef_mantissa,
1639 u32 *coef_exponent)
1640{
1641 u32 coef_exp, coef_man;
1642
1643 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1644 if ((coef_scaled >> coef_exp) & 0x1)
1645 break;
1646
1647 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1648
1649 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1650
1651 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1652 *coef_exponent = coef_exp - 16;
1653}
1654
cbe61d8a 1655static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
f1dc5600
S		 1656 struct ath9k_channel *chan)
1657{
1658 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1659 u32 clockMhzScaled = 0x64000000;
1660 struct chan_centers centers;
1661
1662 if (IS_CHAN_HALF_RATE(chan))
1663 clockMhzScaled = clockMhzScaled >> 1;
1664 else if (IS_CHAN_QUARTER_RATE(chan))
1665 clockMhzScaled = clockMhzScaled >> 2;
1666
1667 ath9k_hw_get_channel_centers(ah, chan, &centers);
1668 coef_scaled = clockMhzScaled / centers.synth_center;
1669
1670 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1671 &ds_coef_exp);
1672
1673 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1674 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1675 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1676 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1677
1678 coef_scaled = (9 * coef_scaled) / 10;
1679
1680 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1681 &ds_coef_exp);
1682
1683 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1684 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1685 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1686 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1687}
1688
cbe61d8a 1689static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1690{
1691 u32 rst_flags;
1692 u32 tmpReg;
1693
70768496
S		 1694 if (AR_SREV_9100(ah)) {
1695 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1696 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1697 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1698 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1699 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1700 }
1701
f1dc5600
S		 1702 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1703 AR_RTC_FORCE_WAKE_ON_INT);
1704
1705 if (AR_SREV_9100(ah)) {
1706 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1707 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1708 } else {
1709 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1710 if (tmpReg &
1711 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1712 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1713 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1714 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1715 } else {
1716 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1717 }
1718
1719 rst_flags = AR_RTC_RC_MAC_WARM;
1720 if (type == ATH9K_RESET_COLD)
1721 rst_flags |= AR_RTC_RC_MAC_COLD;
1722 }
1723
d03a66c1 1724 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1725 udelay(50);
1726
d03a66c1 1727 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1728 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1729 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1730 "RTC stuck in MAC reset\n");
f1dc5600
S		 1731 return false;
1732 }
1733
1734 if (!AR_SREV_9100(ah))
1735 REG_WRITE(ah, AR_RC, 0);
1736
f1dc5600
S		 1737 if (AR_SREV_9100(ah))
1738 udelay(50);
1739
1740 return true;
1741}
1742
cbe61d8a 1743static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1744{
1745 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1746 AR_RTC_FORCE_WAKE_ON_INT);
1747
1c29ce67
VT		 1748 if (!AR_SREV_9100(ah))
1749 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1750
d03a66c1 1751 REG_WRITE(ah, AR_RTC_RESET, 0);
8bd1d07f 1752 udelay(2);
1c29ce67
VT		 1753
1754 if (!AR_SREV_9100(ah))
1755 REG_WRITE(ah, AR_RC, 0);
1756
d03a66c1 1757 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1758
1759 if (!ath9k_hw_wait(ah,
1760 AR_RTC_STATUS,
1761 AR_RTC_STATUS_M,
0caa7b14
S		 1762 AR_RTC_STATUS_ON,
1763 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1764 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1765 "RTC not waking up\n");
f1dc5600 1766 return false;
f078f209
LR		 1767 }
1768
f1dc5600
S		 1769 ath9k_hw_read_revisions(ah);
1770
1771 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1772}
1773
cbe61d8a 1774static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1775{
1776 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1777 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1778
1779 switch (type) {
1780 case ATH9K_RESET_POWER_ON:
1781 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1782 case ATH9K_RESET_WARM:
1783 case ATH9K_RESET_COLD:
1784 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1785 default:
1786 return false;
1787 }
f078f209
LR		 1788}
1789
25c56eec 1790static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1791{
f1dc5600 1792 u32 phymode;
e7594072 1793 u32 enableDacFifo = 0;
f078f209 1794
e7594072
SB		 1795 if (AR_SREV_9285_10_OR_LATER(ah))
1796 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1797 AR_PHY_FC_ENABLE_DAC_FIFO);
1798
f1dc5600 1799 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1800 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1801
1802 if (IS_CHAN_HT40(chan)) {
1803 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1804
f1dc5600
S		 1805 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1806 (chan->chanmode == CHANNEL_G_HT40PLUS))
1807 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1808
f078f209 1809 }
f1dc5600
S		 1810 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1811
25c56eec 1812 ath9k_hw_set11nmac2040(ah);
f078f209 1813
f1dc5600
S		 1814 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1815 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1816}
1817
cbe61d8a 1818static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1819 struct ath9k_channel *chan)
f078f209 1820{
42abfbee 1821 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1822 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1823 return false;
1824 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1825 return false;
f078f209 1826
9ecdef4b 1827 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1828 return false;
f078f209 1829
2660b81a 1830 ah->chip_fullsleep = false;
f1dc5600 1831 ath9k_hw_init_pll(ah, chan);
f1dc5600 1832 ath9k_hw_set_rfmode(ah, chan);
f078f209 1833
f1dc5600 1834 return true;
f078f209
LR		 1835}
1836
cbe61d8a 1837static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1838 struct ath9k_channel *chan)
f078f209 1839{
608b88cb 1840 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1841 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1842 struct ieee80211_channel *channel = chan->chan;
f078f209 1843 u32 synthDelay, qnum;
0a3b7bac 1844 int r;
f078f209
LR		 1845
1846 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1847 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1848 ath_print(common, ATH_DBG_QUEUE,
1849 "Transmit frames pending on "
1850 "queue %d\n", qnum);
f078f209
LR		 1851 return false;
1852 }
1853 }
1854
1855 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1856 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
0caa7b14 1857 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1858 ath_print(common, ATH_DBG_FATAL,
1859 "Could not kill baseband RX\n");
f078f209
LR		 1860 return false;
1861 }
1862
25c56eec 1863 ath9k_hw_set_regs(ah, chan);
f078f209 1864
e68a060b 1865 r = ah->ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1866 if (r) {
1867 ath_print(common, ATH_DBG_FATAL,
1868 "Failed to set channel\n");
1869 return false;
f078f209
LR		 1870 }
1871
8fbff4b8 1872 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1873 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1874 channel->max_antenna_gain * 2,
1875 channel->max_power * 2,
1876 min((u32) MAX_RATE_POWER,
608b88cb 1877 (u32) regulatory->power_limit));
f078f209
LR		 1878
1879 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1880 if (IS_CHAN_B(chan))
f078f209
LR		 1881 synthDelay = (4 * synthDelay) / 22;
1882 else
1883 synthDelay /= 10;
1884
1885 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1886
1887 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1888
f1dc5600
S		 1889 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1890 ath9k_hw_set_delta_slope(ah, chan);
1891
ae478cf6 1892 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600
S		 1893
1894 if (!chan->oneTimeCalsDone)
1895 chan->oneTimeCalsDone = true;
1896
1897 return true;
1898}
1899
3b319aae
JB		 1900static void ath9k_enable_rfkill(struct ath_hw *ah)
1901{
1902 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1903 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1904
1905 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1906 AR_GPIO_INPUT_MUX2_RFSILENT);
1907
1908 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1909 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1910}
1911
cbe61d8a 1912int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 1913 bool bChannelChange)
f078f209 1914{
1510718d 1915 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1916 u32 saveLedState;
2660b81a 1917 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1918 u32 saveDefAntenna;
1919 u32 macStaId1;
46fe782c 1920 u64 tsf = 0;
ae8d2858 1921 int i, rx_chainmask, r;
f078f209 1922
43c27613
LR		 1923 ah->txchainmask = common->tx_chainmask;
1924 ah->rxchainmask = common->rx_chainmask;
f078f209 1925
9ecdef4b 1926 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1927 return -EIO;
f078f209 1928
9ebef799 1929 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1930 ath9k_hw_getnf(ah, curchan);
1931
1932 if (bChannelChange &&
2660b81a
S		 1933 (ah->chip_fullsleep != true) &&
1934 (ah->curchan != NULL) &&
1935 (chan->channel != ah->curchan->channel) &&
f078f209 1936 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1937 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 1938 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1939 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 1940
25c56eec 1941 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1942 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 1943 ath9k_hw_start_nfcal(ah);
ae8d2858 1944 return 0;
f078f209
LR		 1945 }
1946 }
1947
1948 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1949 if (saveDefAntenna == 0)
1950 saveDefAntenna = 1;
1951
1952 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1953
46fe782c
S		 1954 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1955 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1956 tsf = ath9k_hw_gettsf64(ah);
1957
f078f209
LR		 1958 saveLedState = REG_READ(ah, AR_CFG_LED) &
1959 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1960 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1961
1962 ath9k_hw_mark_phy_inactive(ah);
1963
d7e7d229
LR		 1964 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1965 REG_WRITE(ah,
1966 AR9271_RESET_POWER_DOWN_CONTROL,
1967 AR9271_RADIO_RF_RST);
1968 udelay(50);
1969 }
1970
f078f209 1971 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1972 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1973 return -EINVAL;
f078f209
LR		 1974 }
1975
d7e7d229
LR		 1976 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1977 ah->htc_reset_init = false;
1978 REG_WRITE(ah,
1979 AR9271_RESET_POWER_DOWN_CONTROL,
1980 AR9271_GATE_MAC_CTL);
1981 udelay(50);
1982 }
1983
46fe782c
S		 1984 /* Restore TSF */
1985 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1986 ath9k_hw_settsf64(ah, tsf);
1987
369391db
VT		 1988 if (AR_SREV_9280_10_OR_LATER(ah))
1989 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1990
326bebbc 1991 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 1992 /* Enable ASYNC FIFO */
1993 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1994 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1995 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1996 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1997 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1998 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1999 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2000 }
25c56eec 2001 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 2002 if (r)
2003 return r;
f078f209 2004
0ced0e17
JM		 2005 /* Setup MFP options for CCMP */
2006 if (AR_SREV_9280_20_OR_LATER(ah)) {
2007 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2008 * frames when constructing CCMP AAD. */
2009 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2010 0xc7ff);
2011 ah->sw_mgmt_crypto = false;
2012 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2013 /* Disable hardware crypto for management frames */
2014 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2015 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2016 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2017 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2018 ah->sw_mgmt_crypto = true;
2019 } else
2020 ah->sw_mgmt_crypto = true;
2021
f078f209
LR		 2022 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2023 ath9k_hw_set_delta_slope(ah, chan);
2024
ae478cf6 2025 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 2026 ah->eep_ops->set_board_values(ah, chan);
a7765828 2027
1510718d
LR		 2028 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2029 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 2030 | macStaId1
2031 | AR_STA_ID1_RTS_USE_DEF
2660b81a 2032 | (ah->config.
60b67f51 2033 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 2034 | ah->sta_id1_defaults);
2035 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2036
13b81559 2037 ath_hw_setbssidmask(common);
f078f209
LR		 2038
2039 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2040
3453ad88 2041 ath9k_hw_write_associd(ah);
f078f209
LR		 2042
2043 REG_WRITE(ah, AR_ISR, ~0);
2044
2045 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2046
e68a060b 2047 r = ah->ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 2048 if (r)
2049 return r;
f078f209
LR		 2050
2051 for (i = 0; i < AR_NUM_DCU; i++)
2052 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2053
2660b81a
S		 2054 ah->intr_txqs = 0;
2055 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 2056 ath9k_hw_resettxqueue(ah, i);
2057
2660b81a 2058 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 2059 ath9k_hw_init_qos(ah);
2060
2660b81a 2061 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 2062 ath9k_enable_rfkill(ah);
3b319aae 2063
f078f209
LR		 2064 ath9k_hw_init_user_settings(ah);
2065
326bebbc 2066 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2067 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2068 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2069 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2070 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2071 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2072 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2073
2074 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2075 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2076
2077 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2078 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2079 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2080 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2081 }
326bebbc 2082 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2083 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2084 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2085 }
2086
f078f209
LR		 2087 REG_WRITE(ah, AR_STA_ID1,
2088 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2089
2090 ath9k_hw_set_dma(ah);
2091
2092 REG_WRITE(ah, AR_OBS, 8);
2093
0ce024cb 2094 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 2095 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2096 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2097 }
2098
2099 ath9k_hw_init_bb(ah, chan);
2100
ae8d2858 2101 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2102 return -EIO;
f078f209 2103
2660b81a 2104 rx_chainmask = ah->rxchainmask;
f078f209
LR		 2105 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2106 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2107 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2108 }
2109
2110 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2111
d7e7d229
LR		 2112 /*
2113 * For big endian systems turn on swapping for descriptors
2114 */
f078f209
LR		 2115 if (AR_SREV_9100(ah)) {
2116 u32 mask;
2117 mask = REG_READ(ah, AR_CFG);
2118 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 2119 ath_print(common, ATH_DBG_RESET,
04bd4638 2120 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2121 } else {
2122 mask =
2123 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2124 REG_WRITE(ah, AR_CFG, mask);
c46917bb 2125 ath_print(common, ATH_DBG_RESET,
04bd4638 2126 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2127 }
2128 } else {
d7e7d229
LR		 2129 /* Configure AR9271 target WLAN */
2130 if (AR_SREV_9271(ah))
2131 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 2132#ifdef __BIG_ENDIAN
d7e7d229
LR		 2133 else
2134 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 2135#endif
2136 }
2137
766ec4a9 2138 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 2139 ath9k_hw_btcoex_enable(ah);
2140
ae8d2858 2141 return 0;
f078f209 2142}
7322fd19 2143EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2144
f1dc5600
S		 2145/************************/
2146/* Key Cache Management */
2147/************************/
f078f209 2148
cbe61d8a 2149bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 2150{
f1dc5600 2151 u32 keyType;
f078f209 2152
2660b81a 2153 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 2154 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2155 "keychache entry %u out of range\n", entry);
f078f209
LR		 2156 return false;
2157 }
2158
f1dc5600 2159 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2160
f1dc5600
S		 2161 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2162 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2163 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2164 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2165 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2166 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2167 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2168 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2169
f1dc5600
S		 2170 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2171 u16 micentry = entry + 64;
f078f209 2172
f1dc5600
S		 2173 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2174 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2175 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2176 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2177
f078f209
LR		 2178 }
2179
f078f209
LR		 2180 return true;
2181}
7322fd19 2182EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 2183
cbe61d8a 2184bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 2185{
f1dc5600 2186 u32 macHi, macLo;
f078f209 2187
2660b81a 2188 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 2189 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2190 "keychache entry %u out of range\n", entry);
f1dc5600 2191 return false;
f078f209
LR		 2192 }
2193
f1dc5600
S		 2194 if (mac != NULL) {
2195 macHi = (mac[5] << 8) | mac[4];
2196 macLo = (mac[3] << 24) |
2197 (mac[2] << 16) |
2198 (mac[1] << 8) |
2199 mac[0];
2200 macLo >>= 1;
2201 macLo |= (macHi & 1) << 31;
2202 macHi >>= 1;
f078f209 2203 } else {
f1dc5600 2204 macLo = macHi = 0;
f078f209 2205 }
f1dc5600
S		 2206 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2207 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2208
f1dc5600 2209 return true;
f078f209 2210}
7322fd19 2211EXPORT_SYMBOL(ath9k_hw_keysetmac);
f078f209 2212
cbe61d8a 2213bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 2214 const struct ath9k_keyval *k,
e0caf9ea 2215 const u8 *mac)
f078f209 2216{
2660b81a 2217 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2218 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 2219 u32 key0, key1, key2, key3, key4;
2220 u32 keyType;
f078f209 2221
f1dc5600 2222 if (entry >= pCap->keycache_size) {
c46917bb
LR		 2223 ath_print(common, ATH_DBG_FATAL,
2224 "keycache entry %u out of range\n", entry);
f1dc5600 2225 return false;
f078f209
LR		 2226 }
2227
f1dc5600
S		 2228 switch (k->kv_type) {
2229 case ATH9K_CIPHER_AES_OCB:
2230 keyType = AR_KEYTABLE_TYPE_AES;
2231 break;
2232 case ATH9K_CIPHER_AES_CCM:
2233 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 2234 ath_print(common, ATH_DBG_ANY,
2235 "AES-CCM not supported by mac rev 0x%x\n",
2236 ah->hw_version.macRev);
f1dc5600
S		 2237 return false;
2238 }
2239 keyType = AR_KEYTABLE_TYPE_CCM;
2240 break;
2241 case ATH9K_CIPHER_TKIP:
2242 keyType = AR_KEYTABLE_TYPE_TKIP;
2243 if (ATH9K_IS_MIC_ENABLED(ah)
2244 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 2245 ath_print(common, ATH_DBG_ANY,
2246 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2247 return false;
2248 }
2249 break;
2250 case ATH9K_CIPHER_WEP:
e31a16d6 2251 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 2252 ath_print(common, ATH_DBG_ANY,
2253 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2254 return false;
2255 }
e31a16d6 2256 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 2257 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 2258 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 2259 keyType = AR_KEYTABLE_TYPE_104;
2260 else
2261 keyType = AR_KEYTABLE_TYPE_128;
2262 break;
2263 case ATH9K_CIPHER_CLR:
2264 keyType = AR_KEYTABLE_TYPE_CLR;
2265 break;
2266 default:
c46917bb
LR		 2267 ath_print(common, ATH_DBG_FATAL,
2268 "cipher %u not supported\n", k->kv_type);
f1dc5600 2269 return false;
f078f209
LR		 2270 }
2271
e0caf9ea
JM		 2272 key0 = get_unaligned_le32(k->kv_val + 0);
2273 key1 = get_unaligned_le16(k->kv_val + 4);
2274 key2 = get_unaligned_le32(k->kv_val + 6);
2275 key3 = get_unaligned_le16(k->kv_val + 10);
2276 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 2277 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 2278 key4 &= 0xff;
f078f209 2279
672903b3
JM		 2280 /*
2281 * Note: Key cache registers access special memory area that requires
2282 * two 32-bit writes to actually update the values in the internal
2283 * memory. Consequently, the exact order and pairs used here must be
2284 * maintained.
2285 */
2286
f1dc5600
S		 2287 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2288 u16 micentry = entry + 64;
f078f209 2289
672903b3
JM		 2290 /*
2291 * Write inverted key[47:0] first to avoid Michael MIC errors
2292 * on frames that could be sent or received at the same time.
2293 * The correct key will be written in the end once everything
2294 * else is ready.
2295 */
f1dc5600
S		 2296 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2297 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 2298
2299 /* Write key[95:48] */
f1dc5600
S		 2300 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2301 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2302
2303 /* Write key[127:96] and key type */
f1dc5600
S		 2304 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2305 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 2306
2307 /* Write MAC address for the entry */
f1dc5600 2308 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2309
2660b81a 2310 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 2311 /*
2312 * TKIP uses two key cache entries:
2313 * Michael MIC TX/RX keys in the same key cache entry
2314 * (idx = main index + 64):
2315 * key0 [31:0] = RX key [31:0]
2316 * key1 [15:0] = TX key [31:16]
2317 * key1 [31:16] = reserved
2318 * key2 [31:0] = RX key [63:32]
2319 * key3 [15:0] = TX key [15:0]
2320 * key3 [31:16] = reserved
2321 * key4 [31:0] = TX key [63:32]
2322 */
f1dc5600 2323 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2324
f1dc5600
S		 2325 mic0 = get_unaligned_le32(k->kv_mic + 0);
2326 mic2 = get_unaligned_le32(k->kv_mic + 4);
2327 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2328 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2329 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 2330
2331 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 2332 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2333 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 2334
2335 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 2336 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2337 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 2338
2339 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2340 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2341 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2342 AR_KEYTABLE_TYPE_CLR);
f078f209 2343
f1dc5600 2344 } else {
672903b3
JM		 2345 /*
2346 * TKIP uses four key cache entries (two for group
2347 * keys):
2348 * Michael MIC TX/RX keys are in different key cache
2349 * entries (idx = main index + 64 for TX and
2350 * main index + 32 + 96 for RX):
2351 * key0 [31:0] = TX/RX MIC key [31:0]
2352 * key1 [31:0] = reserved
2353 * key2 [31:0] = TX/RX MIC key [63:32]
2354 * key3 [31:0] = reserved
2355 * key4 [31:0] = reserved
2356 *
2357 * Upper layer code will call this function separately
2358 * for TX and RX keys when these registers offsets are
2359 * used.
2360 */
f1dc5600 2361 u32 mic0, mic2;
f078f209 2362
f1dc5600
S		 2363 mic0 = get_unaligned_le32(k->kv_mic + 0);
2364 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 2365
2366 /* Write MIC key[31:0] */
f1dc5600
S		 2367 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2368 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 2369
2370 /* Write MIC key[63:32] */
f1dc5600
S		 2371 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2372 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 2373
2374 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2375 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2376 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2377 AR_KEYTABLE_TYPE_CLR);
2378 }
672903b3
JM		 2379
2380 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 2381 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2382 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 2383
2384 /*
2385 * Write the correct (un-inverted) key[47:0] last to enable
2386 * TKIP now that all other registers are set with correct
2387 * values.
2388 */
f1dc5600
S		 2389 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2390 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2391 } else {
672903b3 2392 /* Write key[47:0] */
f1dc5600
S		 2393 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2394 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 2395
2396 /* Write key[95:48] */
f1dc5600
S		 2397 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2398 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2399
2400 /* Write key[127:96] and key type */
f1dc5600
S		 2401 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2402 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2403
672903b3 2404 /* Write MAC address for the entry */
f1dc5600
S		 2405 (void) ath9k_hw_keysetmac(ah, entry, mac);
2406 }
f078f209 2407
f078f209
LR		 2408 return true;
2409}
7322fd19 2410EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 2411
cbe61d8a 2412bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 2413{
2660b81a 2414 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 2415 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2416 if (val & AR_KEYTABLE_VALID)
2417 return true;
2418 }
2419 return false;
f078f209 2420}
7322fd19 2421EXPORT_SYMBOL(ath9k_hw_keyisvalid);
f078f209 2422
f1dc5600
S		 2423/******************************/
2424/* Power Management (Chipset) */
2425/******************************/
2426
cbe61d8a 2427static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2428{
f1dc5600
S		 2429 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2430 if (setChip) {
2431 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2432 AR_RTC_FORCE_WAKE_EN);
2433 if (!AR_SREV_9100(ah))
2434 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2435
4921be80
S		 2436 if(!AR_SREV_5416(ah))
2437 REG_CLR_BIT(ah, (AR_RTC_RESET),
2438 AR_RTC_RESET_EN);
f1dc5600 2439 }
f078f209
LR		 2440}
2441
cbe61d8a 2442static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2443{
f1dc5600
S		 2444 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2445 if (setChip) {
2660b81a 2446 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2447
f1dc5600
S		 2448 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2449 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2450 AR_RTC_FORCE_WAKE_ON_INT);
2451 } else {
2452 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2453 AR_RTC_FORCE_WAKE_EN);
f078f209 2454 }
f078f209 2455 }
f078f209
LR		 2456}
2457
cbe61d8a 2458static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2459{
f1dc5600
S		 2460 u32 val;
2461 int i;
f078f209 2462
f1dc5600
S		 2463 if (setChip) {
2464 if ((REG_READ(ah, AR_RTC_STATUS) &
2465 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2466 if (ath9k_hw_set_reset_reg(ah,
2467 ATH9K_RESET_POWER_ON) != true) {
2468 return false;
2469 }
63a75b91 2470 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 2471 }
2472 if (AR_SREV_9100(ah))
2473 REG_SET_BIT(ah, AR_RTC_RESET,
2474 AR_RTC_RESET_EN);
f078f209 2475
f1dc5600
S		 2476 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2477 AR_RTC_FORCE_WAKE_EN);
2478 udelay(50);
f078f209 2479
f1dc5600
S		 2480 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2481 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2482 if (val == AR_RTC_STATUS_ON)
2483 break;
2484 udelay(50);
2485 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2486 AR_RTC_FORCE_WAKE_EN);
f078f209 2487 }
f1dc5600 2488 if (i == 0) {
c46917bb
LR		 2489 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2490 "Failed to wakeup in %uus\n",
2491 POWER_UP_TIME / 20);
f1dc5600 2492 return false;
f078f209 2493 }
f078f209
LR		 2494 }
2495
f1dc5600 2496 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2497
f1dc5600 2498 return true;
f078f209
LR		 2499}
2500
9ecdef4b 2501bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2502{
c46917bb 2503 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 2504 int status = true, setChip = true;
f1dc5600
S		 2505 static const char *modes[] = {
2506 "AWAKE",
2507 "FULL-SLEEP",
2508 "NETWORK SLEEP",
2509 "UNDEFINED"
2510 };
f1dc5600 2511
cbdec975
GJ		 2512 if (ah->power_mode == mode)
2513 return status;
2514
c46917bb
LR		 2515 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2516 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2517
2518 switch (mode) {
2519 case ATH9K_PM_AWAKE:
2520 status = ath9k_hw_set_power_awake(ah, setChip);
2521 break;
2522 case ATH9K_PM_FULL_SLEEP:
2523 ath9k_set_power_sleep(ah, setChip);
2660b81a 2524 ah->chip_fullsleep = true;
f1dc5600
S		 2525 break;
2526 case ATH9K_PM_NETWORK_SLEEP:
2527 ath9k_set_power_network_sleep(ah, setChip);
2528 break;
f078f209 2529 default:
c46917bb
LR		 2530 ath_print(common, ATH_DBG_FATAL,
2531 "Unknown power mode %u\n", mode);
f078f209
LR		 2532 return false;
2533 }
2660b81a 2534 ah->power_mode = mode;
f1dc5600
S		 2535
2536 return status;
f078f209 2537}
7322fd19 2538EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2539
24c1a280
LR		 2540/*
2541 * Helper for ASPM support.
2542 *
2543 * Disable PLL when in L0s as well as receiver clock when in L1.
2544 * This power saving option must be enabled through the SerDes.
2545 *
2546 * Programming the SerDes must go through the same 288 bit serial shift
2547 * register as the other analog registers. Hence the 9 writes.
2548 */
93b1b37f 2549void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
f078f209 2550{
f1dc5600 2551 u8 i;
93b1b37f 2552 u32 val;
f078f209 2553
2660b81a 2554 if (ah->is_pciexpress != true)
f1dc5600 2555 return;
f078f209 2556
24c1a280 2557 /* Do not touch SerDes registers */
2660b81a 2558 if (ah->config.pcie_powersave_enable == 2)
f1dc5600
S		 2559 return;
2560
24c1a280 2561 /* Nothing to do on restore for 11N */
93b1b37f
VN		 2562 if (!restore) {
2563 if (AR_SREV_9280_20_OR_LATER(ah)) {
2564 /*
2565 * AR9280 2.0 or later chips use SerDes values from the
2566 * initvals.h initialized depending on chipset during
2567 * ath9k_hw_init()
2568 */
2569 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2570 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2571 INI_RA(&ah->iniPcieSerdes, i, 1));
2572 }
2573 } else if (AR_SREV_9280(ah) &&
2574 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2575 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2576 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2577
2578 /* RX shut off when elecidle is asserted */
2579 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2580 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2581 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2582
2583 /* Shut off CLKREQ active in L1 */
2584 if (ah->config.pcie_clock_req)
2585 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2586 else
2587 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
f1dc5600 2588
93b1b37f
VN		 2589 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2590 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2591 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
f1dc5600 2592
93b1b37f
VN		 2593 /* Load the new settings */
2594 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f1dc5600 2595
93b1b37f
VN		 2596 } else {
2597 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2598 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
f1dc5600 2599
93b1b37f
VN		 2600 /* RX shut off when elecidle is asserted */
2601 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2602 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2603 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
f1dc5600 2604
93b1b37f
VN		 2605 /*
2606 * Ignore ah->ah_config.pcie_clock_req setting for
2607 * pre-AR9280 11n
2608 */
2609 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
24c1a280 2610
93b1b37f
VN		 2611 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2612 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2613 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
24c1a280 2614
93b1b37f
VN		 2615 /* Load the new settings */
2616 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2617 }
24c1a280 2618
93b1b37f 2619 udelay(1000);
24c1a280 2620
93b1b37f
VN		 2621 /* set bit 19 to allow forcing of pcie core into L1 state */
2622 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
f078f209 2623
93b1b37f
VN		 2624 /* Several PCIe massages to ensure proper behaviour */
2625 if (ah->config.pcie_waen) {
2626 val = ah->config.pcie_waen;
2627 if (!power_off)
2628 val &= (~AR_WA_D3_L1_DISABLE);
2629 } else {
2630 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2631 AR_SREV_9287(ah)) {
2632 val = AR9285_WA_DEFAULT;
2633 if (!power_off)
2634 val &= (~AR_WA_D3_L1_DISABLE);
2635 } else if (AR_SREV_9280(ah)) {
2636 /*
2637 * On AR9280 chips bit 22 of 0x4004 needs to be
2638 * set otherwise card may disappear.
2639 */
2640 val = AR9280_WA_DEFAULT;
2641 if (!power_off)
2642 val &= (~AR_WA_D3_L1_DISABLE);
2643 } else
2644 val = AR_WA_DEFAULT;
2645 }
6d08b9b9 2646
93b1b37f
VN		 2647 REG_WRITE(ah, AR_WA, val);
2648 }
f1dc5600 2649
93b1b37f 2650 if (power_off) {
24c1a280 2651 /*
93b1b37f
VN		 2652 * Set PCIe workaround bits
2653 * bit 14 in WA register (disable L1) should only
2654 * be set when device enters D3 and be cleared
2655 * when device comes back to D0.
24c1a280 2656 */
93b1b37f
VN		 2657 if (ah->config.pcie_waen) {
2658 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2659 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2660 } else {
2661 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2662 AR_SREV_9287(ah)) &&
2663 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2664 (AR_SREV_9280(ah) &&
2665 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2666 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2667 }
2668 }
f1dc5600 2669 }
f078f209 2670}
7322fd19 2671EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
f078f209 2672
f1dc5600
S		 2673/**********************/
2674/* Interrupt Handling */
2675/**********************/
2676
cbe61d8a 2677bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 2678{
2679 u32 host_isr;
2680
2681 if (AR_SREV_9100(ah))
2682 return true;
2683
2684 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2685 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2686 return true;
2687
2688 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2689 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2690 && (host_isr != AR_INTR_SPURIOUS))
2691 return true;
2692
2693 return false;
2694}
7322fd19 2695EXPORT_SYMBOL(ath9k_hw_intrpend);
f078f209 2696
cbe61d8a 2697bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 2698{
2699 u32 isr = 0;
2700 u32 mask2 = 0;
2660b81a 2701 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 2702 u32 sync_cause = 0;
2703 bool fatal_int = false;
c46917bb 2704 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 2705
2706 if (!AR_SREV_9100(ah)) {
2707 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2708 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2709 == AR_RTC_STATUS_ON) {
2710 isr = REG_READ(ah, AR_ISR);
2711 }
2712 }
2713
f1dc5600
S		 2714 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2715 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 2716
2717 *masked = 0;
2718
2719 if (!isr && !sync_cause)
2720 return false;
2721 } else {
2722 *masked = 0;
2723 isr = REG_READ(ah, AR_ISR);
2724 }
2725
2726 if (isr) {
f078f209
LR		 2727 if (isr & AR_ISR_BCNMISC) {
2728 u32 isr2;
2729 isr2 = REG_READ(ah, AR_ISR_S2);
2730 if (isr2 & AR_ISR_S2_TIM)
2731 mask2 |= ATH9K_INT_TIM;
2732 if (isr2 & AR_ISR_S2_DTIM)
2733 mask2 |= ATH9K_INT_DTIM;
2734 if (isr2 & AR_ISR_S2_DTIMSYNC)
2735 mask2 |= ATH9K_INT_DTIMSYNC;
2736 if (isr2 & (AR_ISR_S2_CABEND))
2737 mask2 |= ATH9K_INT_CABEND;
2738 if (isr2 & AR_ISR_S2_GTT)
2739 mask2 |= ATH9K_INT_GTT;
2740 if (isr2 & AR_ISR_S2_CST)
2741 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 2742 if (isr2 & AR_ISR_S2_TSFOOR)
2743 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 2744 }
2745
2746 isr = REG_READ(ah, AR_ISR_RAC);
2747 if (isr == 0xffffffff) {
2748 *masked = 0;
2749 return false;
2750 }
2751
2752 *masked = isr & ATH9K_INT_COMMON;
2753
0ce024cb 2754 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 2755 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2756 *masked |= ATH9K_INT_RX;
2757 }
2758
2759 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2760 *masked |= ATH9K_INT_RX;
2761 if (isr &
2762 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2763 AR_ISR_TXEOL)) {
2764 u32 s0_s, s1_s;
2765
2766 *masked |= ATH9K_INT_TX;
2767
2768 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 2769 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2770 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 2771
2772 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 2773 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2774 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 2775 }
2776
2777 if (isr & AR_ISR_RXORN) {
c46917bb
LR		 2778 ath_print(common, ATH_DBG_INTERRUPT,
2779 "receive FIFO overrun interrupt\n");
f078f209
LR		 2780 }
2781
2782 if (!AR_SREV_9100(ah)) {
60b67f51 2783 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2784 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2785 if (isr5 & AR_ISR_S5_TIM_TIMER)
2786 *masked |= ATH9K_INT_TIM_TIMER;
2787 }
2788 }
2789
2790 *masked |= mask2;
2791 }
f1dc5600 2792
f078f209
LR		 2793 if (AR_SREV_9100(ah))
2794 return true;
f1dc5600 2795
ff155a45
VT		 2796 if (isr & AR_ISR_GENTMR) {
2797 u32 s5_s;
2798
2799 s5_s = REG_READ(ah, AR_ISR_S5_S);
2800 if (isr & AR_ISR_GENTMR) {
2801 ah->intr_gen_timer_trigger =
2802 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2803
2804 ah->intr_gen_timer_thresh =
2805 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2806
2807 if (ah->intr_gen_timer_trigger)
2808 *masked |= ATH9K_INT_GENTIMER;
2809
2810 }
2811 }
2812
f078f209
LR		 2813 if (sync_cause) {
2814 fatal_int =
2815 (sync_cause &
2816 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2817 ? true : false;
2818
2819 if (fatal_int) {
2820 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
c46917bb
LR		 2821 ath_print(common, ATH_DBG_ANY,
2822 "received PCI FATAL interrupt\n");
f078f209
LR		 2823 }
2824 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
c46917bb
LR		 2825 ath_print(common, ATH_DBG_ANY,
2826 "received PCI PERR interrupt\n");
f078f209 2827 }
a89bff9a 2828 *masked |= ATH9K_INT_FATAL;
f078f209
LR		 2829 }
2830 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
c46917bb
LR		 2831 ath_print(common, ATH_DBG_INTERRUPT,
2832 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 2833 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2834 REG_WRITE(ah, AR_RC, 0);
2835 *masked |= ATH9K_INT_FATAL;
2836 }
2837 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
c46917bb
LR		 2838 ath_print(common, ATH_DBG_INTERRUPT,
2839 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 2840 }
2841
2842 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2843 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2844 }
f1dc5600 2845
f078f209
LR		 2846 return true;
2847}
7322fd19 2848EXPORT_SYMBOL(ath9k_hw_getisr);
f078f209 2849
cbe61d8a 2850enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 2851{
2660b81a 2852 u32 omask = ah->mask_reg;
f078f209 2853 u32 mask, mask2;
2660b81a 2854 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2855 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2856
c46917bb 2857 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 2858
2859 if (omask & ATH9K_INT_GLOBAL) {
c46917bb 2860 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 2861 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2862 (void) REG_READ(ah, AR_IER);
2863 if (!AR_SREV_9100(ah)) {
2864 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2865 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2866
2867 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2868 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2869 }
2870 }
2871
2872 mask = ints & ATH9K_INT_COMMON;
2873 mask2 = 0;
2874
2875 if (ints & ATH9K_INT_TX) {
2660b81a 2876 if (ah->txok_interrupt_mask)
f078f209 2877 mask |= AR_IMR_TXOK;
2660b81a 2878 if (ah->txdesc_interrupt_mask)
f078f209 2879 mask |= AR_IMR_TXDESC;
2660b81a 2880 if (ah->txerr_interrupt_mask)
f078f209 2881 mask |= AR_IMR_TXERR;
2660b81a 2882 if (ah->txeol_interrupt_mask)
f078f209
LR		 2883 mask |= AR_IMR_TXEOL;
2884 }
2885 if (ints & ATH9K_INT_RX) {
2886 mask |= AR_IMR_RXERR;
0ce024cb 2887 if (ah->config.rx_intr_mitigation)
f078f209
LR		 2888 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2889 else
2890 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 2891 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 2892 mask |= AR_IMR_GENTMR;
2893 }
2894
2895 if (ints & (ATH9K_INT_BMISC)) {
2896 mask |= AR_IMR_BCNMISC;
2897 if (ints & ATH9K_INT_TIM)
2898 mask2 |= AR_IMR_S2_TIM;
2899 if (ints & ATH9K_INT_DTIM)
2900 mask2 |= AR_IMR_S2_DTIM;
2901 if (ints & ATH9K_INT_DTIMSYNC)
2902 mask2 |= AR_IMR_S2_DTIMSYNC;
2903 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 2904 mask2 |= AR_IMR_S2_CABEND;
2905 if (ints & ATH9K_INT_TSFOOR)
2906 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 2907 }
2908
2909 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2910 mask |= AR_IMR_BCNMISC;
2911 if (ints & ATH9K_INT_GTT)
2912 mask2 |= AR_IMR_S2_GTT;
2913 if (ints & ATH9K_INT_CST)
2914 mask2 |= AR_IMR_S2_CST;
2915 }
2916
c46917bb 2917 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 2918 REG_WRITE(ah, AR_IMR, mask);
2919 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2920 AR_IMR_S2_DTIM |
2921 AR_IMR_S2_DTIMSYNC |
2922 AR_IMR_S2_CABEND |
2923 AR_IMR_S2_CABTO |
2924 AR_IMR_S2_TSFOOR |
2925 AR_IMR_S2_GTT | AR_IMR_S2_CST);
2926 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2660b81a 2927 ah->mask_reg = ints;
f078f209 2928
60b67f51 2929 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 2930 if (ints & ATH9K_INT_TIM_TIMER)
2931 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2932 else
2933 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2934 }
2935
2936 if (ints & ATH9K_INT_GLOBAL) {
c46917bb 2937 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 2938 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2939 if (!AR_SREV_9100(ah)) {
2940 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2941 AR_INTR_MAC_IRQ);
2942 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2943
2944
2945 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2946 AR_INTR_SYNC_DEFAULT);
2947 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2948 AR_INTR_SYNC_DEFAULT);
2949 }
c46917bb
LR		 2950 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2951 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
f078f209
LR		 2952 }
2953
2954 return omask;
2955}
7322fd19 2956EXPORT_SYMBOL(ath9k_hw_set_interrupts);
f078f209 2957
f1dc5600
S		 2958/*******************/
2959/* Beacon Handling */
2960/*******************/
2961
cbe61d8a 2962void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2963{
f078f209
LR		 2964 int flags = 0;
2965
2660b81a 2966 ah->beacon_interval = beacon_period;
f078f209 2967
2660b81a 2968 switch (ah->opmode) {
d97809db
CM		 2969 case NL80211_IFTYPE_STATION:
2970 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 2971 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2972 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2973 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2974 flags |= AR_TBTT_TIMER_EN;
2975 break;
d97809db 2976 case NL80211_IFTYPE_ADHOC:
9cb5412b 2977 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 2978 REG_SET_BIT(ah, AR_TXCFG,
2979 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2980 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2981 TU_TO_USEC(next_beacon +
2660b81a
S		 2982 (ah->atim_window ? ah->
2983 atim_window : 1)));
f078f209 2984 flags |= AR_NDP_TIMER_EN;
d97809db 2985 case NL80211_IFTYPE_AP:
f078f209
LR		 2986 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2987 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2988 TU_TO_USEC(next_beacon -
2660b81a 2989 ah->config.
60b67f51 2990 dma_beacon_response_time));
f078f209
LR		 2991 REG_WRITE(ah, AR_NEXT_SWBA,
2992 TU_TO_USEC(next_beacon -
2660b81a 2993 ah->config.
60b67f51 2994 sw_beacon_response_time));
f078f209
LR		 2995 flags |=
2996 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2997 break;
d97809db 2998 default:
c46917bb
LR		 2999 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3000 "%s: unsupported opmode: %d\n",
3001 __func__, ah->opmode);
d97809db
CM		 3002 return;
3003 break;
f078f209
LR		 3004 }
3005
3006 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3007 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3008 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3009 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3010
3011 beacon_period &= ~ATH9K_BEACON_ENA;
3012 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 3013 ath9k_hw_reset_tsf(ah);
3014 }
3015
3016 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3017}
7322fd19 3018EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 3019
cbe61d8a 3020void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 3021 const struct ath9k_beacon_state *bs)
f078f209
LR		 3022{
3023 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 3024 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 3025 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 3026
3027 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3028
3029 REG_WRITE(ah, AR_BEACON_PERIOD,
3030 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3031 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3032 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3033
3034 REG_RMW_FIELD(ah, AR_RSSI_THR,
3035 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3036
3037 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3038
3039 if (bs->bs_sleepduration > beaconintval)
3040 beaconintval = bs->bs_sleepduration;
3041
3042 dtimperiod = bs->bs_dtimperiod;
3043 if (bs->bs_sleepduration > dtimperiod)
3044 dtimperiod = bs->bs_sleepduration;
3045
3046 if (beaconintval == dtimperiod)
3047 nextTbtt = bs->bs_nextdtim;
3048 else
3049 nextTbtt = bs->bs_nexttbtt;
3050
c46917bb
LR		 3051 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3052 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3053 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3054 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3055
f1dc5600
S		 3056 REG_WRITE(ah, AR_NEXT_DTIM,
3057 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3058 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3059
f1dc5600
S		 3060 REG_WRITE(ah, AR_SLEEP1,
3061 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3062 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3063
f1dc5600
S		 3064 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3065 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3066 else
3067 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3068
f1dc5600
S		 3069 REG_WRITE(ah, AR_SLEEP2,
3070 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3071
f1dc5600
S		 3072 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3073 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3074
f1dc5600
S		 3075 REG_SET_BIT(ah, AR_TIMER_MODE,
3076 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3077 AR_DTIM_TIMER_EN);
f078f209 3078
4af9cf4f
S		 3079 /* TSF Out of Range Threshold */
3080 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 3081}
7322fd19 3082EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 3083
f1dc5600
S		 3084/*******************/
3085/* HW Capabilities */
3086/*******************/
3087
a9a29ce6 3088int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 3089{
2660b81a 3090 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 3091 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 3092 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 3093 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 3094
f1dc5600 3095 u16 capField = 0, eeval;
f078f209 3096
f74df6fb 3097 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 3098 regulatory->current_rd = eeval;
f078f209 3099
f74df6fb 3100 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 3101 if (AR_SREV_9285_10_OR_LATER(ah))
3102 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 3103 regulatory->current_rd_ext = eeval;
f078f209 3104
f74df6fb 3105 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 3106
2660b81a 3107 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 3108 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 3109 if (regulatory->current_rd == 0x64 ||
3110 regulatory->current_rd == 0x65)
3111 regulatory->current_rd += 5;
3112 else if (regulatory->current_rd == 0x41)
3113 regulatory->current_rd = 0x43;
c46917bb
LR		 3114 ath_print(common, ATH_DBG_REGULATORY,
3115 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 3116 }
f078f209 3117
f74df6fb 3118 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 3119 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3120 ath_print(common, ATH_DBG_FATAL,
3121 "no band has been marked as supported in EEPROM.\n");
3122 return -EINVAL;
3123 }
3124
f1dc5600 3125 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3126
f1dc5600
S		 3127 if (eeval & AR5416_OPFLAGS_11A) {
3128 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 3129 if (ah->config.ht_enable) {
f1dc5600
S		 3130 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3131 set_bit(ATH9K_MODE_11NA_HT20,
3132 pCap->wireless_modes);
3133 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3134 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3135 pCap->wireless_modes);
3136 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3137 pCap->wireless_modes);
3138 }
f078f209 3139 }
f078f209
LR		 3140 }
3141
f1dc5600 3142 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 3143 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 3144 if (ah->config.ht_enable) {
f1dc5600
S		 3145 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3146 set_bit(ATH9K_MODE_11NG_HT20,
3147 pCap->wireless_modes);
3148 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3149 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3150 pCap->wireless_modes);
3151 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3152 pCap->wireless_modes);
3153 }
3154 }
f078f209 3155 }
f1dc5600 3156
f74df6fb 3157 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 3158 /*
3159 * For AR9271 we will temporarilly uses the rx chainmax as read from
3160 * the EEPROM.
3161 */
8147f5de 3162 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 3163 !(eeval & AR5416_OPFLAGS_11A) &&
3164 !(AR_SREV_9271(ah)))
3165 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 3166 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3167 else
d7e7d229 3168 /* Use rx_chainmask from EEPROM. */
8147f5de 3169 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 3170
d535a42a 3171 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 3172 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3173
f1dc5600
S		 3174 pCap->low_2ghz_chan = 2312;
3175 pCap->high_2ghz_chan = 2732;
f078f209 3176
f1dc5600
S		 3177 pCap->low_5ghz_chan = 4920;
3178 pCap->high_5ghz_chan = 6100;
f078f209 3179
f1dc5600
S		 3180 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3181 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3182 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3183
f1dc5600
S		 3184 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3185 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3186 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3187
2660b81a 3188 if (ah->config.ht_enable)
f1dc5600
S		 3189 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3190 else
3191 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3192
f1dc5600
S		 3193 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3194 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3195 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3196 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3197
f1dc5600
S		 3198 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3199 pCap->total_queues =
3200 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3201 else
3202 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3203
f1dc5600
S		 3204 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3205 pCap->keycache_size =
3206 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3207 else
3208 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3209
f1dc5600 3210 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f4709fdf
LR		 3211
3212 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3213 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3214 else
3215 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3216
cb33c412
SB		 3217 if (AR_SREV_9285_10_OR_LATER(ah))
3218 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3219 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3220 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3221 else
3222 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3223
f1dc5600
S		 3224 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3225 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3226 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3227 } else {
3228 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3229 }
3230
f1dc5600
S		 3231 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3232
e97275cb 3233#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 3234 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3235 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3236 ah->rfkill_gpio =
3237 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3238 ah->rfkill_polarity =
3239 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 3240
3241 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3242 }
f1dc5600 3243#endif
f078f209 3244
a3ca95fb 3245 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3246
e7594072 3247 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3248 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3249 else
3250 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3251
608b88cb 3252 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 3253 pCap->reg_cap =
3254 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3255 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3256 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3257 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3258 } else {
f1dc5600
S		 3259 pCap->reg_cap =
3260 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3261 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3262 }
f078f209 3263
ebb90cfc
SB		 3264 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3265 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3266 AR_SREV_5416(ah))
3267 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 3268
3269 pCap->num_antcfg_5ghz =
f74df6fb 3270 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3271 pCap->num_antcfg_2ghz =
f74df6fb 3272 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3273
fe12946e 3274 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 3275 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 3276 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3277 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 3278
8c8f9ba7 3279 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 3280 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3281 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 3282 } else {
766ec4a9 3283 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 3284 }
22f25d0d 3285 } else {
766ec4a9 3286 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 3287 }
a9a29ce6
GJ		 3288
3289 return 0;
f078f209
LR		 3290}
3291
cbe61d8a 3292bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3293 u32 capability, u32 *result)
f078f209 3294{
608b88cb 3295 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 3296 switch (type) {
3297 case ATH9K_CAP_CIPHER:
3298 switch (capability) {
3299 case ATH9K_CIPHER_AES_CCM:
3300 case ATH9K_CIPHER_AES_OCB:
3301 case ATH9K_CIPHER_TKIP:
3302 case ATH9K_CIPHER_WEP:
3303 case ATH9K_CIPHER_MIC:
3304 case ATH9K_CIPHER_CLR:
3305 return true;
3306 default:
3307 return false;
3308 }
3309 case ATH9K_CAP_TKIP_MIC:
3310 switch (capability) {
3311 case 0:
3312 return true;
3313 case 1:
2660b81a 3314 return (ah->sta_id1_defaults &
f1dc5600
S		 3315 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3316 false;
3317 }
3318 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 3319 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 3320 false : true;
f1dc5600
S		 3321 case ATH9K_CAP_DIVERSITY:
3322 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3323 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3324 true : false;
f1dc5600
S		 3325 case ATH9K_CAP_MCAST_KEYSRCH:
3326 switch (capability) {
3327 case 0:
3328 return true;
3329 case 1:
3330 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3331 return false;
3332 } else {
2660b81a 3333 return (ah->sta_id1_defaults &
f1dc5600
S		 3334 AR_STA_ID1_MCAST_KSRCH) ? true :
3335 false;
3336 }
3337 }
3338 return false;
f1dc5600
S		 3339 case ATH9K_CAP_TXPOW:
3340 switch (capability) {
3341 case 0:
3342 return 0;
3343 case 1:
608b88cb 3344 *result = regulatory->power_limit;
f1dc5600
S		 3345 return 0;
3346 case 2:
608b88cb 3347 *result = regulatory->max_power_level;
f1dc5600
S		 3348 return 0;
3349 case 3:
608b88cb 3350 *result = regulatory->tp_scale;
f1dc5600
S		 3351 return 0;
3352 }
3353 return false;
8bd1d07f
SB		 3354 case ATH9K_CAP_DS:
3355 return (AR_SREV_9280_20_OR_LATER(ah) &&
3356 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3357 ? false : true;
f1dc5600
S		 3358 default:
3359 return false;
f078f209 3360 }
f078f209 3361}
7322fd19 3362EXPORT_SYMBOL(ath9k_hw_getcapability);
f078f209 3363
cbe61d8a 3364bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3365 u32 capability, u32 setting, int *status)
f078f209 3366{
f1dc5600 3367 u32 v;
f078f209 3368
f1dc5600
S		 3369 switch (type) {
3370 case ATH9K_CAP_TKIP_MIC:
3371 if (setting)
2660b81a 3372 ah->sta_id1_defaults |=
f1dc5600
S		 3373 AR_STA_ID1_CRPT_MIC_ENABLE;
3374 else
2660b81a 3375 ah->sta_id1_defaults &=
f1dc5600
S		 3376 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3377 return true;
3378 case ATH9K_CAP_DIVERSITY:
3379 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3380 if (setting)
3381 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3382 else
3383 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3384 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3385 return true;
3386 case ATH9K_CAP_MCAST_KEYSRCH:
3387 if (setting)
2660b81a 3388 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3389 else
2660b81a 3390 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3391 return true;
f1dc5600
S		 3392 default:
3393 return false;
f078f209
LR		 3394 }
3395}
7322fd19 3396EXPORT_SYMBOL(ath9k_hw_setcapability);
f078f209 3397
f1dc5600
S		 3398/****************************/
3399/* GPIO / RFKILL / Antennae */
3400/****************************/
f078f209 3401
cbe61d8a 3402static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 3403 u32 gpio, u32 type)
3404{
3405 int addr;
3406 u32 gpio_shift, tmp;
f078f209 3407
f1dc5600
S		 3408 if (gpio > 11)
3409 addr = AR_GPIO_OUTPUT_MUX3;
3410 else if (gpio > 5)
3411 addr = AR_GPIO_OUTPUT_MUX2;
3412 else
3413 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3414
f1dc5600 3415 gpio_shift = (gpio % 6) * 5;
f078f209 3416
f1dc5600
S		 3417 if (AR_SREV_9280_20_OR_LATER(ah)
3418 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3419 REG_RMW(ah, addr, (type << gpio_shift),
3420 (0x1f << gpio_shift));
f078f209 3421 } else {
f1dc5600
S		 3422 tmp = REG_READ(ah, addr);
3423 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3424 tmp &= ~(0x1f << gpio_shift);
3425 tmp |= (type << gpio_shift);
3426 REG_WRITE(ah, addr, tmp);
f078f209 3427 }
f078f209
LR		 3428}
3429
cbe61d8a 3430void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 3431{
f1dc5600 3432 u32 gpio_shift;
f078f209 3433
9680e8a3 3434 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 3435
f1dc5600 3436 gpio_shift = gpio << 1;
f078f209 3437
f1dc5600
S		 3438 REG_RMW(ah,
3439 AR_GPIO_OE_OUT,
3440 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3441 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 3442}
7322fd19 3443EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 3444
cbe61d8a 3445u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 3446{
cb33c412
SB		 3447#define MS_REG_READ(x, y) \
3448 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3449
2660b81a 3450 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 3451 return 0xffffffff;
f078f209 3452
ac88b6ec
VN		 3453 if (AR_SREV_9287_10_OR_LATER(ah))
3454 return MS_REG_READ(AR9287, gpio) != 0;
3455 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 3456 return MS_REG_READ(AR9285, gpio) != 0;
3457 else if (AR_SREV_9280_10_OR_LATER(ah))
3458 return MS_REG_READ(AR928X, gpio) != 0;
3459 else
3460 return MS_REG_READ(AR, gpio) != 0;
f078f209 3461}
7322fd19 3462EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 3463
cbe61d8a 3464void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 3465 u32 ah_signal_type)
f078f209 3466{
f1dc5600 3467 u32 gpio_shift;
f078f209 3468
f1dc5600 3469 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3470
f1dc5600 3471 gpio_shift = 2 * gpio;
f078f209 3472
f1dc5600
S		 3473 REG_RMW(ah,
3474 AR_GPIO_OE_OUT,
3475 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3476 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 3477}
7322fd19 3478EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 3479
cbe61d8a 3480void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 3481{
f1dc5600
S		 3482 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3483 AR_GPIO_BIT(gpio));
f078f209 3484}
7322fd19 3485EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 3486
cbe61d8a 3487u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 3488{
f1dc5600 3489 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 3490}
7322fd19 3491EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 3492
cbe61d8a 3493void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 3494{
f1dc5600 3495 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 3496}
7322fd19 3497EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 3498
f1dc5600
S		 3499/*********************/
3500/* General Operation */
3501/*********************/
3502
cbe61d8a 3503u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 3504{
f1dc5600
S		 3505 u32 bits = REG_READ(ah, AR_RX_FILTER);
3506 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3507
f1dc5600
S		 3508 if (phybits & AR_PHY_ERR_RADAR)
3509 bits |= ATH9K_RX_FILTER_PHYRADAR;
3510 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3511 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3512
f1dc5600 3513 return bits;
f078f209 3514}
7322fd19 3515EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 3516
cbe61d8a 3517void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 3518{
f1dc5600 3519 u32 phybits;
f078f209 3520
7ea310be
S		 3521 REG_WRITE(ah, AR_RX_FILTER, bits);
3522
f1dc5600
S		 3523 phybits = 0;
3524 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3525 phybits |= AR_PHY_ERR_RADAR;
3526 if (bits & ATH9K_RX_FILTER_PHYERR)
3527 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3528 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3529
f1dc5600
S		 3530 if (phybits)
3531 REG_WRITE(ah, AR_RXCFG,
3532 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3533 else
3534 REG_WRITE(ah, AR_RXCFG,
3535 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3536}
7322fd19 3537EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 3538
cbe61d8a 3539bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 3540{
63a75b91
SB		 3541 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3542 return false;
3543
3544 ath9k_hw_init_pll(ah, NULL);
3545 return true;
f1dc5600 3546}
7322fd19 3547EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 3548
cbe61d8a 3549bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 3550{
9ecdef4b 3551 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 3552 return false;
f078f209 3553
63a75b91
SB		 3554 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3555 return false;
3556
3557 ath9k_hw_init_pll(ah, NULL);
3558 return true;
f078f209 3559}
7322fd19 3560EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 3561
8fbff4b8 3562void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 3563{
608b88cb 3564 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 3565 struct ath9k_channel *chan = ah->curchan;
5f8e077c 3566 struct ieee80211_channel *channel = chan->chan;
f078f209 3567
608b88cb 3568 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 3569
8fbff4b8 3570 ah->eep_ops->set_txpower(ah, chan,
608b88cb 3571 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 3572 channel->max_antenna_gain * 2,
3573 channel->max_power * 2,
3574 min((u32) MAX_RATE_POWER,
608b88cb 3575 (u32) regulatory->power_limit));
6f255425 3576}
7322fd19 3577EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 3578
cbe61d8a 3579void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 3580{
1510718d 3581 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209 3582}
7322fd19 3583EXPORT_SYMBOL(ath9k_hw_setmac);
f078f209 3584
cbe61d8a 3585void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 3586{
2660b81a 3587 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 3588}
7322fd19 3589EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 3590
cbe61d8a 3591void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 3592{
f1dc5600
S		 3593 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3594 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 3595}
7322fd19 3596EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 3597
f2b2143e 3598void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 3599{
1510718d
LR		 3600 struct ath_common *common = ath9k_hw_common(ah);
3601
3602 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3603 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3604 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 3605}
7322fd19 3606EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 3607
cbe61d8a 3608u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 3609{
f1dc5600 3610 u64 tsf;
f078f209 3611
f1dc5600
S		 3612 tsf = REG_READ(ah, AR_TSF_U32);
3613 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 3614
f1dc5600
S		 3615 return tsf;
3616}
7322fd19 3617EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 3618
cbe61d8a 3619void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 3620{
27abe060 3621 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 3622 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 3623}
7322fd19 3624EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 3625
cbe61d8a 3626void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 3627{
f9b604f6
GJ		 3628 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3629 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 3630 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3631 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 3632
f1dc5600
S		 3633 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3634}
7322fd19 3635EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 3636
54e4cec6 3637void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 3638{
f1dc5600 3639 if (setting)
2660b81a 3640 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 3641 else
2660b81a 3642 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 3643}
7322fd19 3644EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 3645
30cbd422
LR		 3646/*
3647 * Extend 15-bit time stamp from rx descriptor to
3648 * a full 64-bit TSF using the current h/w TSF.
3649*/
3650u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3651{
3652 u64 tsf;
3653
3654 tsf = ath9k_hw_gettsf64(ah);
3655 if ((tsf & 0x7fff) < rstamp)
3656 tsf -= 0x8000;
3657 return (tsf & ~0x7fff) | rstamp;
3658}
3659EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3660
cbe61d8a 3661bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f1dc5600 3662{
f1dc5600 3663 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
c46917bb
LR		 3664 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3665 "bad slot time %u\n", us);
2660b81a 3666 ah->slottime = (u32) -1;
f1dc5600
S		 3667 return false;
3668 } else {
3669 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
2660b81a 3670 ah->slottime = us;
f1dc5600 3671 return true;
f078f209 3672 }
f1dc5600 3673}
7322fd19 3674EXPORT_SYMBOL(ath9k_hw_setslottime);
f1dc5600 3675
25c56eec 3676void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 3677{
25c56eec 3678 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 3679 u32 macmode;
3680
25c56eec 3681 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 3682 macmode = AR_2040_JOINED_RX_CLEAR;
3683 else
3684 macmode = 0;
f078f209 3685
f1dc5600 3686 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3687}
ff155a45
VT		 3688
3689/* HW Generic timers configuration */
3690
3691static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3692{
3693 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3694 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3695 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3696 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3697 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3698 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3699 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3700 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3701 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3702 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3703 AR_NDP2_TIMER_MODE, 0x0002},
3704 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3705 AR_NDP2_TIMER_MODE, 0x0004},
3706 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3707 AR_NDP2_TIMER_MODE, 0x0008},
3708 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3709 AR_NDP2_TIMER_MODE, 0x0010},
3710 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3711 AR_NDP2_TIMER_MODE, 0x0020},
3712 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3713 AR_NDP2_TIMER_MODE, 0x0040},
3714 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3715 AR_NDP2_TIMER_MODE, 0x0080}
3716};
3717
3718/* HW generic timer primitives */
3719
3720/* compute and clear index of rightmost 1 */
3721static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3722{
3723 u32 b;
3724
3725 b = *mask;
3726 b &= (0-b);
3727 *mask &= ~b;
3728 b *= debruijn32;
3729 b >>= 27;
3730
3731 return timer_table->gen_timer_index[b];
3732}
3733
1773912b 3734u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 3735{
3736 return REG_READ(ah, AR_TSF_L32);
3737}
7322fd19 3738EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 3739
3740struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3741 void (*trigger)(void *),
3742 void (*overflow)(void *),
3743 void *arg,
3744 u8 timer_index)
3745{
3746 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3747 struct ath_gen_timer *timer;
3748
3749 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3750
3751 if (timer == NULL) {
c46917bb
LR		 3752 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3753 "Failed to allocate memory"
3754 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 3755 return NULL;
3756 }
3757
3758 /* allocate a hardware generic timer slot */
3759 timer_table->timers[timer_index] = timer;
3760 timer->index = timer_index;
3761 timer->trigger = trigger;
3762 timer->overflow = overflow;
3763 timer->arg = arg;
3764
3765 return timer;
3766}
7322fd19 3767EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3768
cd9bf689
LR		 3769void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3770 struct ath_gen_timer *timer,
3771 u32 timer_next,
3772 u32 timer_period)
ff155a45
VT		 3773{
3774 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3775 u32 tsf;
3776
3777 BUG_ON(!timer_period);
3778
3779 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3780
3781 tsf = ath9k_hw_gettsf32(ah);
3782
c46917bb
LR		 3783 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3784 "curent tsf %x period %x"
3785 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 3786
3787 /*
3788 * Pull timer_next forward if the current TSF already passed it
3789 * because of software latency
3790 */
3791 if (timer_next < tsf)
3792 timer_next = tsf + timer_period;
3793
3794 /*
3795 * Program generic timer registers
3796 */
3797 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3798 timer_next);
3799 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3800 timer_period);
3801 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3802 gen_tmr_configuration[timer->index].mode_mask);
3803
3804 /* Enable both trigger and thresh interrupt masks */
3805 REG_SET_BIT(ah, AR_IMR_S5,
3806 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3807 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 3808}
7322fd19 3809EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3810
cd9bf689 3811void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3812{
3813 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3814
3815 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3816 (timer->index >= ATH_MAX_GEN_TIMER)) {
3817 return;
3818 }
3819
3820 /* Clear generic timer enable bits. */
3821 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3822 gen_tmr_configuration[timer->index].mode_mask);
3823
3824 /* Disable both trigger and thresh interrupt masks */
3825 REG_CLR_BIT(ah, AR_IMR_S5,
3826 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3827 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3828
3829 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 3830}
7322fd19 3831EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3832
3833void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3834{
3835 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3836
3837 /* free the hardware generic timer slot */
3838 timer_table->timers[timer->index] = NULL;
3839 kfree(timer);
3840}
7322fd19 3841EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3842
3843/*
3844 * Generic Timer Interrupts handling
3845 */
3846void ath_gen_timer_isr(struct ath_hw *ah)
3847{
3848 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3849 struct ath_gen_timer *timer;
c46917bb 3850 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 3851 u32 trigger_mask, thresh_mask, index;
3852
3853 /* get hardware generic timer interrupt status */
3854 trigger_mask = ah->intr_gen_timer_trigger;
3855 thresh_mask = ah->intr_gen_timer_thresh;
3856 trigger_mask &= timer_table->timer_mask.val;
3857 thresh_mask &= timer_table->timer_mask.val;
3858
3859 trigger_mask &= ~thresh_mask;
3860
3861 while (thresh_mask) {
3862 index = rightmost_index(timer_table, &thresh_mask);
3863 timer = timer_table->timers[index];
3864 BUG_ON(!timer);
c46917bb
LR		 3865 ath_print(common, ATH_DBG_HWTIMER,
3866 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 3867 timer->overflow(timer->arg);
3868 }
3869
3870 while (trigger_mask) {
3871 index = rightmost_index(timer_table, &trigger_mask);
3872 timer = timer_table->timers[index];
3873 BUG_ON(!timer);
c46917bb
LR		 3874 ath_print(common, ATH_DBG_HWTIMER,
3875 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 3876 timer->trigger(timer->arg);
3877 }
3878}
7322fd19 3879EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a
LR		 3880
3881static struct {
3882 u32 version;
3883 const char * name;
3884} ath_mac_bb_names[] = {
3885 /* Devices with external radios */
3886 { AR_SREV_VERSION_5416_PCI, "5416" },
3887 { AR_SREV_VERSION_5416_PCIE, "5418" },
3888 { AR_SREV_VERSION_9100, "9100" },
3889 { AR_SREV_VERSION_9160, "9160" },
3890 /* Single-chip solutions */
3891 { AR_SREV_VERSION_9280, "9280" },
3892 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3893 { AR_SREV_VERSION_9287, "9287" },
3894 { AR_SREV_VERSION_9271, "9271" },
2da4f01a
LR		 3895};
3896
3897/* For devices with external radios */
3898static struct {
3899 u16 version;
3900 const char * name;
3901} ath_rf_names[] = {
3902 { 0, "5133" },
3903 { AR_RAD5133_SREV_MAJOR, "5133" },
3904 { AR_RAD5122_SREV_MAJOR, "5122" },
3905 { AR_RAD2133_SREV_MAJOR, "2133" },
3906 { AR_RAD2122_SREV_MAJOR, "2122" }
3907};
3908
3909/*
3910 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3911 */
f934c4d9 3912static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3913{
3914 int i;
3915
3916 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3917 if (ath_mac_bb_names[i].version == mac_bb_version) {
3918 return ath_mac_bb_names[i].name;
3919 }
3920 }
3921
3922 return "????";
3923}
2da4f01a
LR		 3924
3925/*
3926 * Return the RF name. "????" is returned if the RF is unknown.
3927 * Used for devices with external radios.
3928 */
f934c4d9 3929static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3930{
3931 int i;
3932
3933 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3934 if (ath_rf_names[i].version == rf_version) {
3935 return ath_rf_names[i].name;
3936 }
3937 }
3938
3939 return "????";
3940}
f934c4d9
LR		 3941
3942void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3943{
3944 int used;
3945
3946 /* chipsets >= AR9280 are single-chip */
3947 if (AR_SREV_9280_10_OR_LATER(ah)) {
3948 used = snprintf(hw_name, len,
3949 "Atheros AR%s Rev:%x",
3950 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3951 ah->hw_version.macRev);
3952 }
3953 else {
3954 used = snprintf(hw_name, len,
3955 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3956 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3957 ah->hw_version.macRev,
3958 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3959 AR_RADIO_SREV_MAJOR)),
3960 ah->hw_version.phyRev);
3961 }
3962
3963 hw_name[used] = '\0';
3964}
3965EXPORT_SYMBOL(ath9k_hw_name);
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