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Commit | Line | Data |
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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
18 | #include <asm/unaligned.h> | |
19 | ||
af03abec | 20 | #include "hw.h" |
d70357d5 | 21 | #include "hw-ops.h" |
cfe8cba9 | 22 | #include "rc.h" |
f078f209 LR |
23 | #include "initvals.h" |
24 | ||
4febf7b8 LR |
25 | #define ATH9K_CLOCK_RATE_CCK 22 |
26 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 | |
27 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 | |
f078f209 | 28 | |
d70357d5 | 29 | static void ar9002_hw_attach_ops(struct ath_hw *ah); |
8525f280 | 30 | static void ar9003_hw_attach_ops(struct ath_hw *ah); |
d70357d5 | 31 | |
cbe61d8a | 32 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
f078f209 | 33 | |
7322fd19 LR |
34 | MODULE_AUTHOR("Atheros Communications"); |
35 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
36 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
37 | MODULE_LICENSE("Dual BSD/GPL"); | |
38 | ||
39 | static int __init ath9k_init(void) | |
40 | { | |
41 | return 0; | |
42 | } | |
43 | module_init(ath9k_init); | |
44 | ||
45 | static void __exit ath9k_exit(void) | |
46 | { | |
47 | return; | |
48 | } | |
49 | module_exit(ath9k_exit); | |
50 | ||
d70357d5 LR |
51 | /* Private hardware callbacks */ |
52 | ||
53 | static void ath9k_hw_init_cal_settings(struct ath_hw *ah) | |
54 | { | |
55 | ath9k_hw_private_ops(ah)->init_cal_settings(ah); | |
56 | } | |
57 | ||
58 | static void ath9k_hw_init_mode_regs(struct ath_hw *ah) | |
59 | { | |
60 | ath9k_hw_private_ops(ah)->init_mode_regs(ah); | |
61 | } | |
62 | ||
63 | static bool ath9k_hw_macversion_supported(struct ath_hw *ah) | |
64 | { | |
65 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
66 | ||
67 | return priv_ops->macversion_supported(ah->hw_version.macVersion); | |
68 | } | |
69 | ||
64773964 LR |
70 | static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, |
71 | struct ath9k_channel *chan) | |
72 | { | |
73 | return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); | |
74 | } | |
75 | ||
f1dc5600 S |
76 | /********************/ |
77 | /* Helper Functions */ | |
78 | /********************/ | |
f078f209 | 79 | |
cbe61d8a | 80 | static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) |
f1dc5600 | 81 | { |
b002a4a9 | 82 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
cbe61d8a | 83 | |
2660b81a | 84 | if (!ah->curchan) /* should really check for CCK instead */ |
4febf7b8 LR |
85 | return usecs *ATH9K_CLOCK_RATE_CCK; |
86 | if (conf->channel->band == IEEE80211_BAND_2GHZ) | |
87 | return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; | |
88 | return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; | |
f1dc5600 S |
89 | } |
90 | ||
cbe61d8a | 91 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
f1dc5600 | 92 | { |
b002a4a9 | 93 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
cbe61d8a | 94 | |
4febf7b8 | 95 | if (conf_is_ht40(conf)) |
f1dc5600 S |
96 | return ath9k_hw_mac_clks(ah, usecs) * 2; |
97 | else | |
98 | return ath9k_hw_mac_clks(ah, usecs); | |
99 | } | |
f078f209 | 100 | |
0caa7b14 | 101 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
f078f209 LR |
102 | { |
103 | int i; | |
104 | ||
0caa7b14 S |
105 | BUG_ON(timeout < AH_TIME_QUANTUM); |
106 | ||
107 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { | |
f078f209 LR |
108 | if ((REG_READ(ah, reg) & mask) == val) |
109 | return true; | |
110 | ||
111 | udelay(AH_TIME_QUANTUM); | |
112 | } | |
04bd4638 | 113 | |
c46917bb LR |
114 | ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, |
115 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", | |
116 | timeout, reg, REG_READ(ah, reg), mask, val); | |
f078f209 | 117 | |
f1dc5600 | 118 | return false; |
f078f209 | 119 | } |
7322fd19 | 120 | EXPORT_SYMBOL(ath9k_hw_wait); |
f078f209 LR |
121 | |
122 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) | |
123 | { | |
124 | u32 retval; | |
125 | int i; | |
126 | ||
127 | for (i = 0, retval = 0; i < n; i++) { | |
128 | retval = (retval << 1) | (val & 1); | |
129 | val >>= 1; | |
130 | } | |
131 | return retval; | |
132 | } | |
133 | ||
cbe61d8a | 134 | bool ath9k_get_channel_edges(struct ath_hw *ah, |
f1dc5600 S |
135 | u16 flags, u16 *low, |
136 | u16 *high) | |
f078f209 | 137 | { |
2660b81a | 138 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 139 | |
f1dc5600 S |
140 | if (flags & CHANNEL_5GHZ) { |
141 | *low = pCap->low_5ghz_chan; | |
142 | *high = pCap->high_5ghz_chan; | |
143 | return true; | |
f078f209 | 144 | } |
f1dc5600 S |
145 | if ((flags & CHANNEL_2GHZ)) { |
146 | *low = pCap->low_2ghz_chan; | |
147 | *high = pCap->high_2ghz_chan; | |
148 | return true; | |
149 | } | |
150 | return false; | |
f078f209 LR |
151 | } |
152 | ||
cbe61d8a | 153 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 154 | u8 phy, int kbps, |
f1dc5600 S |
155 | u32 frameLen, u16 rateix, |
156 | bool shortPreamble) | |
f078f209 | 157 | { |
f1dc5600 | 158 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
f078f209 | 159 | |
f1dc5600 S |
160 | if (kbps == 0) |
161 | return 0; | |
f078f209 | 162 | |
545750d3 | 163 | switch (phy) { |
46d14a58 | 164 | case WLAN_RC_PHY_CCK: |
f1dc5600 | 165 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
545750d3 | 166 | if (shortPreamble) |
f1dc5600 S |
167 | phyTime >>= 1; |
168 | numBits = frameLen << 3; | |
169 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); | |
170 | break; | |
46d14a58 | 171 | case WLAN_RC_PHY_OFDM: |
2660b81a | 172 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
f1dc5600 S |
173 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
174 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
175 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
176 | txTime = OFDM_SIFS_TIME_QUARTER | |
177 | + OFDM_PREAMBLE_TIME_QUARTER | |
178 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); | |
2660b81a S |
179 | } else if (ah->curchan && |
180 | IS_CHAN_HALF_RATE(ah->curchan)) { | |
f1dc5600 S |
181 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
182 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
183 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
184 | txTime = OFDM_SIFS_TIME_HALF + | |
185 | OFDM_PREAMBLE_TIME_HALF | |
186 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); | |
187 | } else { | |
188 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; | |
189 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
190 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
191 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME | |
192 | + (numSymbols * OFDM_SYMBOL_TIME); | |
193 | } | |
194 | break; | |
195 | default: | |
c46917bb | 196 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
545750d3 | 197 | "Unknown phy %u (rate ix %u)\n", phy, rateix); |
f1dc5600 S |
198 | txTime = 0; |
199 | break; | |
200 | } | |
f078f209 | 201 | |
f1dc5600 S |
202 | return txTime; |
203 | } | |
7322fd19 | 204 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
f078f209 | 205 | |
cbe61d8a | 206 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
f1dc5600 S |
207 | struct ath9k_channel *chan, |
208 | struct chan_centers *centers) | |
f078f209 | 209 | { |
f1dc5600 | 210 | int8_t extoff; |
f078f209 | 211 | |
f1dc5600 S |
212 | if (!IS_CHAN_HT40(chan)) { |
213 | centers->ctl_center = centers->ext_center = | |
214 | centers->synth_center = chan->channel; | |
215 | return; | |
f078f209 | 216 | } |
f078f209 | 217 | |
f1dc5600 S |
218 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
219 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { | |
220 | centers->synth_center = | |
221 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; | |
222 | extoff = 1; | |
223 | } else { | |
224 | centers->synth_center = | |
225 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; | |
226 | extoff = -1; | |
227 | } | |
f078f209 | 228 | |
f1dc5600 S |
229 | centers->ctl_center = |
230 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); | |
6420014c | 231 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
f1dc5600 | 232 | centers->ext_center = |
6420014c | 233 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
f078f209 LR |
234 | } |
235 | ||
f1dc5600 S |
236 | /******************/ |
237 | /* Chip Revisions */ | |
238 | /******************/ | |
239 | ||
cbe61d8a | 240 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
f078f209 | 241 | { |
f1dc5600 | 242 | u32 val; |
f078f209 | 243 | |
f1dc5600 | 244 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
f078f209 | 245 | |
f1dc5600 S |
246 | if (val == 0xFF) { |
247 | val = REG_READ(ah, AR_SREV); | |
d535a42a S |
248 | ah->hw_version.macVersion = |
249 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; | |
250 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
2660b81a | 251 | ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; |
f1dc5600 S |
252 | } else { |
253 | if (!AR_SREV_9100(ah)) | |
d535a42a | 254 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
f078f209 | 255 | |
d535a42a | 256 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
f078f209 | 257 | |
d535a42a | 258 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
2660b81a | 259 | ah->is_pciexpress = true; |
f1dc5600 | 260 | } |
f078f209 LR |
261 | } |
262 | ||
cbe61d8a | 263 | static int ath9k_hw_get_radiorev(struct ath_hw *ah) |
f078f209 | 264 | { |
f1dc5600 S |
265 | u32 val; |
266 | int i; | |
f078f209 | 267 | |
f1dc5600 | 268 | REG_WRITE(ah, AR_PHY(0x36), 0x00007058); |
f078f209 | 269 | |
f1dc5600 S |
270 | for (i = 0; i < 8; i++) |
271 | REG_WRITE(ah, AR_PHY(0x20), 0x00010000); | |
272 | val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; | |
273 | val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); | |
f078f209 | 274 | |
f1dc5600 | 275 | return ath9k_hw_reverse_bits(val, 8); |
f078f209 LR |
276 | } |
277 | ||
f1dc5600 S |
278 | /************************************/ |
279 | /* HW Attach, Detach, Init Routines */ | |
280 | /************************************/ | |
281 | ||
cbe61d8a | 282 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
f078f209 | 283 | { |
feed029c | 284 | if (AR_SREV_9100(ah)) |
f1dc5600 | 285 | return; |
f078f209 | 286 | |
f1dc5600 S |
287 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
288 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
289 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); | |
290 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); | |
291 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); | |
292 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); | |
293 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
294 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
295 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); | |
f078f209 | 296 | |
f1dc5600 | 297 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
f078f209 LR |
298 | } |
299 | ||
1f3f0618 | 300 | /* This should work for all families including legacy */ |
cbe61d8a | 301 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
f078f209 | 302 | { |
c46917bb | 303 | struct ath_common *common = ath9k_hw_common(ah); |
1f3f0618 | 304 | u32 regAddr[2] = { AR_STA_ID0 }; |
f1dc5600 S |
305 | u32 regHold[2]; |
306 | u32 patternData[4] = { 0x55555555, | |
307 | 0xaaaaaaaa, | |
308 | 0x66666666, | |
309 | 0x99999999 }; | |
1f3f0618 | 310 | int i, j, loop_max; |
f078f209 | 311 | |
1f3f0618 SB |
312 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
313 | loop_max = 2; | |
314 | regAddr[1] = AR_PHY_BASE + (8 << 2); | |
315 | } else | |
316 | loop_max = 1; | |
317 | ||
318 | for (i = 0; i < loop_max; i++) { | |
f1dc5600 S |
319 | u32 addr = regAddr[i]; |
320 | u32 wrData, rdData; | |
f078f209 | 321 | |
f1dc5600 S |
322 | regHold[i] = REG_READ(ah, addr); |
323 | for (j = 0; j < 0x100; j++) { | |
324 | wrData = (j << 16) | j; | |
325 | REG_WRITE(ah, addr, wrData); | |
326 | rdData = REG_READ(ah, addr); | |
327 | if (rdData != wrData) { | |
c46917bb LR |
328 | ath_print(common, ATH_DBG_FATAL, |
329 | "address test failed " | |
330 | "addr: 0x%08x - wr:0x%08x != " | |
331 | "rd:0x%08x\n", | |
332 | addr, wrData, rdData); | |
f1dc5600 S |
333 | return false; |
334 | } | |
335 | } | |
336 | for (j = 0; j < 4; j++) { | |
337 | wrData = patternData[j]; | |
338 | REG_WRITE(ah, addr, wrData); | |
339 | rdData = REG_READ(ah, addr); | |
340 | if (wrData != rdData) { | |
c46917bb LR |
341 | ath_print(common, ATH_DBG_FATAL, |
342 | "address test failed " | |
343 | "addr: 0x%08x - wr:0x%08x != " | |
344 | "rd:0x%08x\n", | |
345 | addr, wrData, rdData); | |
f1dc5600 S |
346 | return false; |
347 | } | |
f078f209 | 348 | } |
f1dc5600 | 349 | REG_WRITE(ah, regAddr[i], regHold[i]); |
f078f209 | 350 | } |
f1dc5600 | 351 | udelay(100); |
cbe61d8a | 352 | |
f078f209 LR |
353 | return true; |
354 | } | |
355 | ||
b8b0f377 | 356 | static void ath9k_hw_init_config(struct ath_hw *ah) |
f1dc5600 S |
357 | { |
358 | int i; | |
f078f209 | 359 | |
2660b81a S |
360 | ah->config.dma_beacon_response_time = 2; |
361 | ah->config.sw_beacon_response_time = 10; | |
362 | ah->config.additional_swba_backoff = 0; | |
363 | ah->config.ack_6mb = 0x0; | |
364 | ah->config.cwm_ignore_extcca = 0; | |
365 | ah->config.pcie_powersave_enable = 0; | |
2660b81a | 366 | ah->config.pcie_clock_req = 0; |
2660b81a S |
367 | ah->config.pcie_waen = 0; |
368 | ah->config.analog_shiftreg = 1; | |
2660b81a S |
369 | ah->config.ofdm_trig_low = 200; |
370 | ah->config.ofdm_trig_high = 500; | |
371 | ah->config.cck_trig_high = 200; | |
372 | ah->config.cck_trig_low = 100; | |
31a0bd3c LR |
373 | |
374 | /* | |
375 | * For now ANI is disabled for AR9003, it is still | |
376 | * being tested. | |
377 | */ | |
378 | if (!AR_SREV_9300_20_OR_LATER(ah)) | |
379 | ah->config.enable_ani = 1; | |
f078f209 | 380 | |
f1dc5600 | 381 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
2660b81a S |
382 | ah->config.spurchans[i][0] = AR_NO_SPUR; |
383 | ah->config.spurchans[i][1] = AR_NO_SPUR; | |
f078f209 LR |
384 | } |
385 | ||
5ffaf8a3 LR |
386 | if (ah->hw_version.devid != AR2427_DEVID_PCIE) |
387 | ah->config.ht_enable = 1; | |
388 | else | |
389 | ah->config.ht_enable = 0; | |
390 | ||
0ce024cb | 391 | ah->config.rx_intr_mitigation = true; |
6158425b LR |
392 | |
393 | /* | |
394 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) | |
395 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). | |
396 | * This means we use it for all AR5416 devices, and the few | |
397 | * minor PCI AR9280 devices out there. | |
398 | * | |
399 | * Serialization is required because these devices do not handle | |
400 | * well the case of two concurrent reads/writes due to the latency | |
401 | * involved. During one read/write another read/write can be issued | |
402 | * on another CPU while the previous read/write may still be working | |
403 | * on our hardware, if we hit this case the hardware poops in a loop. | |
404 | * We prevent this by serializing reads and writes. | |
405 | * | |
406 | * This issue is not present on PCI-Express devices or pre-AR5416 | |
407 | * devices (legacy, 802.11abg). | |
408 | */ | |
409 | if (num_possible_cpus() > 1) | |
2d6a5e95 | 410 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
f078f209 LR |
411 | } |
412 | ||
50aca25b | 413 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
f078f209 | 414 | { |
608b88cb LR |
415 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
416 | ||
417 | regulatory->country_code = CTRY_DEFAULT; | |
418 | regulatory->power_limit = MAX_RATE_POWER; | |
419 | regulatory->tp_scale = ATH9K_TP_SCALE_MAX; | |
420 | ||
d535a42a | 421 | ah->hw_version.magic = AR5416_MAGIC; |
d535a42a | 422 | ah->hw_version.subvendorid = 0; |
f078f209 LR |
423 | |
424 | ah->ah_flags = 0; | |
f078f209 LR |
425 | if (!AR_SREV_9100(ah)) |
426 | ah->ah_flags = AH_USE_EEPROM; | |
427 | ||
2660b81a | 428 | ah->atim_window = 0; |
2660b81a S |
429 | ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; |
430 | ah->beacon_interval = 100; | |
431 | ah->enable_32kHz_clock = DONT_USE_32KHZ; | |
432 | ah->slottime = (u32) -1; | |
2660b81a | 433 | ah->globaltxtimeout = (u32) -1; |
cbdec975 | 434 | ah->power_mode = ATH9K_PM_UNDEFINED; |
f078f209 LR |
435 | } |
436 | ||
cbe61d8a | 437 | static int ath9k_hw_rf_claim(struct ath_hw *ah) |
f078f209 | 438 | { |
f1dc5600 S |
439 | u32 val; |
440 | ||
441 | REG_WRITE(ah, AR_PHY(0), 0x00000007); | |
442 | ||
443 | val = ath9k_hw_get_radiorev(ah); | |
444 | switch (val & AR_RADIO_SREV_MAJOR) { | |
445 | case 0: | |
446 | val = AR_RAD5133_SREV_MAJOR; | |
447 | break; | |
448 | case AR_RAD5133_SREV_MAJOR: | |
449 | case AR_RAD5122_SREV_MAJOR: | |
450 | case AR_RAD2133_SREV_MAJOR: | |
451 | case AR_RAD2122_SREV_MAJOR: | |
452 | break; | |
f078f209 | 453 | default: |
c46917bb LR |
454 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
455 | "Radio Chip Rev 0x%02X not supported\n", | |
456 | val & AR_RADIO_SREV_MAJOR); | |
f1dc5600 | 457 | return -EOPNOTSUPP; |
f078f209 | 458 | } |
f078f209 | 459 | |
d535a42a | 460 | ah->hw_version.analog5GhzRev = val; |
f078f209 | 461 | |
f1dc5600 | 462 | return 0; |
f078f209 LR |
463 | } |
464 | ||
cbe61d8a | 465 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
f078f209 | 466 | { |
1510718d | 467 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
468 | u32 sum; |
469 | int i; | |
470 | u16 eeval; | |
f078f209 LR |
471 | |
472 | sum = 0; | |
473 | for (i = 0; i < 3; i++) { | |
f74df6fb | 474 | eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i)); |
f078f209 | 475 | sum += eeval; |
1510718d LR |
476 | common->macaddr[2 * i] = eeval >> 8; |
477 | common->macaddr[2 * i + 1] = eeval & 0xff; | |
f078f209 | 478 | } |
d8baa939 | 479 | if (sum == 0 || sum == 0xffff * 3) |
f078f209 | 480 | return -EADDRNOTAVAIL; |
f078f209 LR |
481 | |
482 | return 0; | |
483 | } | |
484 | ||
cbe61d8a | 485 | static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah) |
9f804202 SB |
486 | { |
487 | u32 rxgain_type; | |
9f804202 | 488 | |
f74df6fb S |
489 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) { |
490 | rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); | |
9f804202 SB |
491 | |
492 | if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) | |
2660b81a | 493 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
494 | ar9280Modes_backoff_13db_rxgain_9280_2, |
495 | ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6); | |
496 | else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) | |
2660b81a | 497 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
498 | ar9280Modes_backoff_23db_rxgain_9280_2, |
499 | ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6); | |
500 | else | |
2660b81a | 501 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
502 | ar9280Modes_original_rxgain_9280_2, |
503 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); | |
cbe61d8a | 504 | } else { |
2660b81a | 505 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
9f804202 SB |
506 | ar9280Modes_original_rxgain_9280_2, |
507 | ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6); | |
cbe61d8a | 508 | } |
9f804202 SB |
509 | } |
510 | ||
cbe61d8a | 511 | static void ath9k_hw_init_txgain_ini(struct ath_hw *ah) |
9f804202 SB |
512 | { |
513 | u32 txgain_type; | |
9f804202 | 514 | |
f74df6fb S |
515 | if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) { |
516 | txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); | |
9f804202 SB |
517 | |
518 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) | |
2660b81a | 519 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
9f804202 SB |
520 | ar9280Modes_high_power_tx_gain_9280_2, |
521 | ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6); | |
522 | else | |
2660b81a | 523 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
9f804202 SB |
524 | ar9280Modes_original_tx_gain_9280_2, |
525 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); | |
cbe61d8a | 526 | } else { |
2660b81a | 527 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
9f804202 SB |
528 | ar9280Modes_original_tx_gain_9280_2, |
529 | ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6); | |
cbe61d8a | 530 | } |
9f804202 SB |
531 | } |
532 | ||
f637cfd6 | 533 | static int ath9k_hw_post_init(struct ath_hw *ah) |
f078f209 | 534 | { |
f1dc5600 | 535 | int ecode; |
f078f209 | 536 | |
527d485f S |
537 | if (!AR_SREV_9271(ah)) { |
538 | if (!ath9k_hw_chip_test(ah)) | |
539 | return -ENODEV; | |
540 | } | |
f078f209 | 541 | |
f1dc5600 S |
542 | ecode = ath9k_hw_rf_claim(ah); |
543 | if (ecode != 0) | |
f078f209 | 544 | return ecode; |
f078f209 | 545 | |
f637cfd6 | 546 | ecode = ath9k_hw_eeprom_init(ah); |
f1dc5600 S |
547 | if (ecode != 0) |
548 | return ecode; | |
7d01b221 | 549 | |
c46917bb LR |
550 | ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, |
551 | "Eeprom VER: %d, REV: %d\n", | |
552 | ah->eep_ops->get_eeprom_ver(ah), | |
553 | ah->eep_ops->get_eeprom_rev(ah)); | |
7d01b221 | 554 | |
8fe65368 LR |
555 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); |
556 | if (ecode) { | |
557 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, | |
558 | "Failed allocating banks for " | |
559 | "external radio\n"); | |
560 | return ecode; | |
574d6b12 | 561 | } |
f078f209 | 562 | |
f1dc5600 S |
563 | if (!AR_SREV_9100(ah)) { |
564 | ath9k_hw_ani_setup(ah); | |
f637cfd6 | 565 | ath9k_hw_ani_init(ah); |
f078f209 LR |
566 | } |
567 | ||
f078f209 LR |
568 | return 0; |
569 | } | |
570 | ||
d70357d5 | 571 | static bool ar9002_hw_macversion_supported(u32 macversion) |
f9d4a668 LR |
572 | { |
573 | switch (macversion) { | |
574 | case AR_SREV_VERSION_5416_PCI: | |
575 | case AR_SREV_VERSION_5416_PCIE: | |
576 | case AR_SREV_VERSION_9160: | |
577 | case AR_SREV_VERSION_9100: | |
578 | case AR_SREV_VERSION_9280: | |
579 | case AR_SREV_VERSION_9285: | |
580 | case AR_SREV_VERSION_9287: | |
d7e7d229 | 581 | case AR_SREV_VERSION_9271: |
7976b426 | 582 | return true; |
f9d4a668 LR |
583 | default: |
584 | break; | |
585 | } | |
586 | return false; | |
587 | } | |
588 | ||
61accab9 LR |
589 | static bool ar9003_hw_macversion_supported(u32 macversion) |
590 | { | |
591 | switch (macversion) { | |
592 | case AR_SREV_VERSION_9300: | |
593 | return true; | |
594 | default: | |
595 | break; | |
596 | } | |
597 | return false; | |
598 | } | |
599 | ||
d70357d5 | 600 | static void ar9002_hw_init_cal_settings(struct ath_hw *ah) |
f078f209 | 601 | { |
f1dc5600 S |
602 | if (AR_SREV_9160_10_OR_LATER(ah)) { |
603 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
2660b81a S |
604 | ah->iq_caldata.calData = &iq_cal_single_sample; |
605 | ah->adcgain_caldata.calData = | |
f1dc5600 | 606 | &adc_gain_cal_single_sample; |
2660b81a | 607 | ah->adcdc_caldata.calData = |
f1dc5600 | 608 | &adc_dc_cal_single_sample; |
2660b81a | 609 | ah->adcdc_calinitdata.calData = |
f1dc5600 S |
610 | &adc_init_dc_cal; |
611 | } else { | |
2660b81a S |
612 | ah->iq_caldata.calData = &iq_cal_multi_sample; |
613 | ah->adcgain_caldata.calData = | |
f1dc5600 | 614 | &adc_gain_cal_multi_sample; |
2660b81a | 615 | ah->adcdc_caldata.calData = |
f1dc5600 | 616 | &adc_dc_cal_multi_sample; |
2660b81a | 617 | ah->adcdc_calinitdata.calData = |
f1dc5600 S |
618 | &adc_init_dc_cal; |
619 | } | |
2660b81a | 620 | ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; |
f1dc5600 | 621 | } |
aa4058ae | 622 | } |
f078f209 | 623 | |
d70357d5 | 624 | static void ar9002_hw_init_mode_regs(struct ath_hw *ah) |
aa4058ae | 625 | { |
d7e7d229 | 626 | if (AR_SREV_9271(ah)) { |
8564328d LR |
627 | INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, |
628 | ARRAY_SIZE(ar9271Modes_9271), 6); | |
629 | INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, | |
630 | ARRAY_SIZE(ar9271Common_9271), 2); | |
70807e99 S |
631 | INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271, |
632 | ar9271Common_normal_cck_fir_coeff_9271, | |
633 | ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2); | |
634 | INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271, | |
635 | ar9271Common_japan_2484_cck_fir_coeff_9271, | |
636 | ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2); | |
8564328d LR |
637 | INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only, |
638 | ar9271Modes_9271_1_0_only, | |
639 | ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6); | |
70807e99 S |
640 | INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg, |
641 | ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6); | |
642 | INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271, | |
643 | ar9271Modes_high_power_tx_gain_9271, | |
644 | ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6); | |
645 | INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271, | |
646 | ar9271Modes_normal_power_tx_gain_9271, | |
647 | ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6); | |
d7e7d229 LR |
648 | return; |
649 | } | |
650 | ||
ac88b6ec VN |
651 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
652 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, | |
653 | ARRAY_SIZE(ar9287Modes_9287_1_1), 6); | |
654 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1, | |
655 | ARRAY_SIZE(ar9287Common_9287_1_1), 2); | |
656 | if (ah->config.pcie_clock_req) | |
657 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
658 | ar9287PciePhy_clkreq_off_L1_9287_1_1, | |
659 | ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2); | |
660 | else | |
661 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
662 | ar9287PciePhy_clkreq_always_on_L1_9287_1_1, | |
663 | ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1), | |
664 | 2); | |
665 | } else if (AR_SREV_9287_10_OR_LATER(ah)) { | |
666 | INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0, | |
667 | ARRAY_SIZE(ar9287Modes_9287_1_0), 6); | |
668 | INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0, | |
669 | ARRAY_SIZE(ar9287Common_9287_1_0), 2); | |
670 | ||
671 | if (ah->config.pcie_clock_req) | |
672 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
673 | ar9287PciePhy_clkreq_off_L1_9287_1_0, | |
674 | ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2); | |
675 | else | |
676 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
677 | ar9287PciePhy_clkreq_always_on_L1_9287_1_0, | |
678 | ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0), | |
679 | 2); | |
680 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { | |
f078f209 | 681 | |
4e845168 | 682 | |
2660b81a | 683 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, |
e7594072 | 684 | ARRAY_SIZE(ar9285Modes_9285_1_2), 6); |
2660b81a | 685 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2, |
e7594072 SB |
686 | ARRAY_SIZE(ar9285Common_9285_1_2), 2); |
687 | ||
2660b81a S |
688 | if (ah->config.pcie_clock_req) { |
689 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
e7594072 SB |
690 | ar9285PciePhy_clkreq_off_L1_9285_1_2, |
691 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2); | |
692 | } else { | |
2660b81a | 693 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
e7594072 SB |
694 | ar9285PciePhy_clkreq_always_on_L1_9285_1_2, |
695 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2), | |
696 | 2); | |
697 | } | |
698 | } else if (AR_SREV_9285_10_OR_LATER(ah)) { | |
2660b81a | 699 | INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285, |
e7594072 | 700 | ARRAY_SIZE(ar9285Modes_9285), 6); |
2660b81a | 701 | INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285, |
e7594072 SB |
702 | ARRAY_SIZE(ar9285Common_9285), 2); |
703 | ||
2660b81a S |
704 | if (ah->config.pcie_clock_req) { |
705 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
e7594072 SB |
706 | ar9285PciePhy_clkreq_off_L1_9285, |
707 | ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2); | |
708 | } else { | |
2660b81a | 709 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
e7594072 SB |
710 | ar9285PciePhy_clkreq_always_on_L1_9285, |
711 | ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2); | |
712 | } | |
713 | } else if (AR_SREV_9280_20_OR_LATER(ah)) { | |
2660b81a | 714 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, |
f1dc5600 | 715 | ARRAY_SIZE(ar9280Modes_9280_2), 6); |
2660b81a | 716 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2, |
f1dc5600 | 717 | ARRAY_SIZE(ar9280Common_9280_2), 2); |
f078f209 | 718 | |
2660b81a S |
719 | if (ah->config.pcie_clock_req) { |
720 | INIT_INI_ARRAY(&ah->iniPcieSerdes, | |
f1dc5600 S |
721 | ar9280PciePhy_clkreq_off_L1_9280, |
722 | ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2); | |
723 | } else { | |
2660b81a | 724 | INIT_INI_ARRAY(&ah->iniPcieSerdes, |
f1dc5600 S |
725 | ar9280PciePhy_clkreq_always_on_L1_9280, |
726 | ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2); | |
727 | } | |
2660b81a | 728 | INIT_INI_ARRAY(&ah->iniModesAdditional, |
f1dc5600 S |
729 | ar9280Modes_fast_clock_9280_2, |
730 | ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3); | |
731 | } else if (AR_SREV_9280_10_OR_LATER(ah)) { | |
2660b81a | 732 | INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280, |
f1dc5600 | 733 | ARRAY_SIZE(ar9280Modes_9280), 6); |
2660b81a | 734 | INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280, |
f1dc5600 S |
735 | ARRAY_SIZE(ar9280Common_9280), 2); |
736 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | |
2660b81a | 737 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, |
f1dc5600 | 738 | ARRAY_SIZE(ar5416Modes_9160), 6); |
2660b81a | 739 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160, |
f1dc5600 | 740 | ARRAY_SIZE(ar5416Common_9160), 2); |
2660b81a | 741 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160, |
f1dc5600 | 742 | ARRAY_SIZE(ar5416Bank0_9160), 2); |
2660b81a | 743 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160, |
f1dc5600 | 744 | ARRAY_SIZE(ar5416BB_RfGain_9160), 3); |
2660b81a | 745 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160, |
f1dc5600 | 746 | ARRAY_SIZE(ar5416Bank1_9160), 2); |
2660b81a | 747 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160, |
f1dc5600 | 748 | ARRAY_SIZE(ar5416Bank2_9160), 2); |
2660b81a | 749 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160, |
f1dc5600 | 750 | ARRAY_SIZE(ar5416Bank3_9160), 3); |
2660b81a | 751 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160, |
f1dc5600 | 752 | ARRAY_SIZE(ar5416Bank6_9160), 3); |
2660b81a | 753 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160, |
f1dc5600 | 754 | ARRAY_SIZE(ar5416Bank6TPC_9160), 3); |
2660b81a | 755 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160, |
f1dc5600 S |
756 | ARRAY_SIZE(ar5416Bank7_9160), 2); |
757 | if (AR_SREV_9160_11(ah)) { | |
2660b81a | 758 | INIT_INI_ARRAY(&ah->iniAddac, |
f1dc5600 S |
759 | ar5416Addac_91601_1, |
760 | ARRAY_SIZE(ar5416Addac_91601_1), 2); | |
761 | } else { | |
2660b81a | 762 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, |
f1dc5600 S |
763 | ARRAY_SIZE(ar5416Addac_9160), 2); |
764 | } | |
765 | } else if (AR_SREV_9100_OR_LATER(ah)) { | |
2660b81a | 766 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, |
f1dc5600 | 767 | ARRAY_SIZE(ar5416Modes_9100), 6); |
2660b81a | 768 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, |
f1dc5600 | 769 | ARRAY_SIZE(ar5416Common_9100), 2); |
2660b81a | 770 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100, |
f1dc5600 | 771 | ARRAY_SIZE(ar5416Bank0_9100), 2); |
2660b81a | 772 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100, |
f1dc5600 | 773 | ARRAY_SIZE(ar5416BB_RfGain_9100), 3); |
2660b81a | 774 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100, |
f1dc5600 | 775 | ARRAY_SIZE(ar5416Bank1_9100), 2); |
2660b81a | 776 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100, |
f1dc5600 | 777 | ARRAY_SIZE(ar5416Bank2_9100), 2); |
2660b81a | 778 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100, |
f1dc5600 | 779 | ARRAY_SIZE(ar5416Bank3_9100), 3); |
2660b81a | 780 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100, |
f1dc5600 | 781 | ARRAY_SIZE(ar5416Bank6_9100), 3); |
2660b81a | 782 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, |
f1dc5600 | 783 | ARRAY_SIZE(ar5416Bank6TPC_9100), 3); |
2660b81a | 784 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100, |
f1dc5600 | 785 | ARRAY_SIZE(ar5416Bank7_9100), 2); |
2660b81a | 786 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100, |
f1dc5600 S |
787 | ARRAY_SIZE(ar5416Addac_9100), 2); |
788 | } else { | |
2660b81a | 789 | INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, |
f1dc5600 | 790 | ARRAY_SIZE(ar5416Modes), 6); |
2660b81a | 791 | INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, |
f1dc5600 | 792 | ARRAY_SIZE(ar5416Common), 2); |
2660b81a | 793 | INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, |
f1dc5600 | 794 | ARRAY_SIZE(ar5416Bank0), 2); |
2660b81a | 795 | INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, |
f1dc5600 | 796 | ARRAY_SIZE(ar5416BB_RfGain), 3); |
2660b81a | 797 | INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, |
f1dc5600 | 798 | ARRAY_SIZE(ar5416Bank1), 2); |
2660b81a | 799 | INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2, |
f1dc5600 | 800 | ARRAY_SIZE(ar5416Bank2), 2); |
2660b81a | 801 | INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3, |
f1dc5600 | 802 | ARRAY_SIZE(ar5416Bank3), 3); |
2660b81a | 803 | INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, |
f1dc5600 | 804 | ARRAY_SIZE(ar5416Bank6), 3); |
2660b81a | 805 | INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC, |
f1dc5600 | 806 | ARRAY_SIZE(ar5416Bank6TPC), 3); |
2660b81a | 807 | INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7, |
f1dc5600 | 808 | ARRAY_SIZE(ar5416Bank7), 2); |
2660b81a | 809 | INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac, |
f1dc5600 | 810 | ARRAY_SIZE(ar5416Addac), 2); |
f078f209 | 811 | } |
aa4058ae | 812 | } |
f078f209 | 813 | |
aa4058ae LR |
814 | static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) |
815 | { | |
b37fa870 | 816 | if (AR_SREV_9287_11_OR_LATER(ah)) |
ac88b6ec VN |
817 | INIT_INI_ARRAY(&ah->iniModesRxGain, |
818 | ar9287Modes_rx_gain_9287_1_1, | |
819 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6); | |
820 | else if (AR_SREV_9287_10(ah)) | |
821 | INIT_INI_ARRAY(&ah->iniModesRxGain, | |
822 | ar9287Modes_rx_gain_9287_1_0, | |
823 | ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6); | |
824 | else if (AR_SREV_9280_20(ah)) | |
825 | ath9k_hw_init_rxgain_ini(ah); | |
826 | ||
b37fa870 | 827 | if (AR_SREV_9287_11_OR_LATER(ah)) { |
ac88b6ec VN |
828 | INIT_INI_ARRAY(&ah->iniModesTxGain, |
829 | ar9287Modes_tx_gain_9287_1_1, | |
830 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6); | |
831 | } else if (AR_SREV_9287_10(ah)) { | |
832 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
833 | ar9287Modes_tx_gain_9287_1_0, | |
834 | ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6); | |
835 | } else if (AR_SREV_9280_20(ah)) { | |
836 | ath9k_hw_init_txgain_ini(ah); | |
837 | } else if (AR_SREV_9285_12_OR_LATER(ah)) { | |
4e845168 SB |
838 | u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); |
839 | ||
840 | /* txgain table */ | |
841 | if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { | |
53bc7aa0 VN |
842 | if (AR_SREV_9285E_20(ah)) { |
843 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
844 | ar9285Modes_XE2_0_high_power, | |
845 | ARRAY_SIZE( | |
846 | ar9285Modes_XE2_0_high_power), 6); | |
847 | } else { | |
848 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
849 | ar9285Modes_high_power_tx_gain_9285_1_2, | |
850 | ARRAY_SIZE( | |
851 | ar9285Modes_high_power_tx_gain_9285_1_2), 6); | |
852 | } | |
4e845168 | 853 | } else { |
53bc7aa0 VN |
854 | if (AR_SREV_9285E_20(ah)) { |
855 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
856 | ar9285Modes_XE2_0_normal_power, | |
857 | ARRAY_SIZE( | |
858 | ar9285Modes_XE2_0_normal_power), 6); | |
859 | } else { | |
860 | INIT_INI_ARRAY(&ah->iniModesTxGain, | |
861 | ar9285Modes_original_tx_gain_9285_1_2, | |
862 | ARRAY_SIZE( | |
863 | ar9285Modes_original_tx_gain_9285_1_2), 6); | |
864 | } | |
4e845168 | 865 | } |
4e845168 | 866 | } |
aa4058ae | 867 | } |
4e845168 | 868 | |
aa8bc9ef | 869 | static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah) |
aa4058ae | 870 | { |
2eb46d9b PR |
871 | struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader); |
872 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 873 | |
2eb46d9b PR |
874 | ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) && |
875 | (ah->eep_map != EEP_MAP_4KBITS) && | |
876 | ((pBase->version & 0xff) > 0x0a) && | |
877 | (pBase->pwdclkind == 0); | |
f078f209 | 878 | |
2eb46d9b PR |
879 | if (ah->need_an_top2_fixup) |
880 | ath_print(common, ATH_DBG_EEPROM, | |
881 | "needs fixup for AR_AN_TOP2 register\n"); | |
aa4058ae LR |
882 | } |
883 | ||
8525f280 LR |
884 | static void ath9k_hw_attach_ops(struct ath_hw *ah) |
885 | { | |
886 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
887 | ar9003_hw_attach_ops(ah); | |
888 | else | |
889 | ar9002_hw_attach_ops(ah); | |
890 | } | |
891 | ||
d70357d5 LR |
892 | /* Called for all hardware families */ |
893 | static int __ath9k_hw_init(struct ath_hw *ah) | |
aa4058ae | 894 | { |
c46917bb | 895 | struct ath_common *common = ath9k_hw_common(ah); |
95fafca2 | 896 | int r = 0; |
aa4058ae | 897 | |
bab1f62e LR |
898 | if (ah->hw_version.devid == AR5416_AR9100_DEVID) |
899 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; | |
aa4058ae LR |
900 | |
901 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { | |
c46917bb LR |
902 | ath_print(common, ATH_DBG_FATAL, |
903 | "Couldn't reset chip\n"); | |
95fafca2 | 904 | return -EIO; |
aa4058ae LR |
905 | } |
906 | ||
bab1f62e LR |
907 | ath9k_hw_init_defaults(ah); |
908 | ath9k_hw_init_config(ah); | |
909 | ||
8525f280 | 910 | ath9k_hw_attach_ops(ah); |
d70357d5 | 911 | |
9ecdef4b | 912 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
c46917bb | 913 | ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); |
95fafca2 | 914 | return -EIO; |
aa4058ae LR |
915 | } |
916 | ||
917 | if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { | |
918 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || | |
919 | (AR_SREV_9280(ah) && !ah->is_pciexpress)) { | |
920 | ah->config.serialize_regmode = | |
921 | SER_REG_MODE_ON; | |
922 | } else { | |
923 | ah->config.serialize_regmode = | |
924 | SER_REG_MODE_OFF; | |
925 | } | |
926 | } | |
927 | ||
c46917bb | 928 | ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", |
aa4058ae LR |
929 | ah->config.serialize_regmode); |
930 | ||
f4709fdf LR |
931 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
932 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; | |
933 | else | |
934 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; | |
935 | ||
d70357d5 | 936 | if (!ath9k_hw_macversion_supported(ah)) { |
c46917bb LR |
937 | ath_print(common, ATH_DBG_FATAL, |
938 | "Mac Chip Rev 0x%02x.%x is not supported by " | |
939 | "this driver\n", ah->hw_version.macVersion, | |
940 | ah->hw_version.macRev); | |
95fafca2 | 941 | return -EOPNOTSUPP; |
aa4058ae LR |
942 | } |
943 | ||
944 | if (AR_SREV_9100(ah)) { | |
945 | ah->iq_caldata.calData = &iq_cal_multi_sample; | |
946 | ah->supp_cals = IQ_MISMATCH_CAL; | |
947 | ah->is_pciexpress = false; | |
948 | } | |
d7e7d229 LR |
949 | |
950 | if (AR_SREV_9271(ah)) | |
951 | ah->is_pciexpress = false; | |
952 | ||
aa4058ae | 953 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
aa4058ae LR |
954 | ath9k_hw_init_cal_settings(ah); |
955 | ||
956 | ah->ani_function = ATH9K_ANI_ALL; | |
31a0bd3c | 957 | if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
aa4058ae LR |
958 | ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; |
959 | ||
960 | ath9k_hw_init_mode_regs(ah); | |
961 | ||
962 | if (ah->is_pciexpress) | |
93b1b37f | 963 | ath9k_hw_configpcipowersave(ah, 0, 0); |
aa4058ae LR |
964 | else |
965 | ath9k_hw_disablepcie(ah); | |
966 | ||
193cd458 S |
967 | /* Support for Japan ch.14 (2484) spread */ |
968 | if (AR_SREV_9287_11_OR_LATER(ah)) { | |
969 | INIT_INI_ARRAY(&ah->iniCckfirNormal, | |
970 | ar9287Common_normal_cck_fir_coeff_92871_1, | |
971 | ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2); | |
972 | INIT_INI_ARRAY(&ah->iniCckfirJapan2484, | |
973 | ar9287Common_japan_2484_cck_fir_coeff_92871_1, | |
974 | ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2); | |
975 | } | |
976 | ||
f637cfd6 | 977 | r = ath9k_hw_post_init(ah); |
aa4058ae | 978 | if (r) |
95fafca2 | 979 | return r; |
aa4058ae LR |
980 | |
981 | ath9k_hw_init_mode_gain_regs(ah); | |
a9a29ce6 GJ |
982 | r = ath9k_hw_fill_cap_info(ah); |
983 | if (r) | |
984 | return r; | |
985 | ||
aa8bc9ef | 986 | ath9k_hw_init_eeprom_fix(ah); |
f6688cd8 | 987 | |
4f3acf81 LR |
988 | r = ath9k_hw_init_macaddr(ah); |
989 | if (r) { | |
c46917bb LR |
990 | ath_print(common, ATH_DBG_FATAL, |
991 | "Failed to initialize MAC address\n"); | |
95fafca2 | 992 | return r; |
f078f209 LR |
993 | } |
994 | ||
d7e7d229 | 995 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
2660b81a | 996 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); |
f1dc5600 | 997 | else |
2660b81a | 998 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); |
f078f209 | 999 | |
f1dc5600 | 1000 | ath9k_init_nfcal_hist_buffer(ah); |
f078f209 | 1001 | |
211f5859 LR |
1002 | common->state = ATH_HW_INITIALIZED; |
1003 | ||
4f3acf81 | 1004 | return 0; |
f078f209 LR |
1005 | } |
1006 | ||
d70357d5 LR |
1007 | int ath9k_hw_init(struct ath_hw *ah) |
1008 | { | |
1009 | int ret; | |
1010 | struct ath_common *common = ath9k_hw_common(ah); | |
1011 | ||
1012 | /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ | |
1013 | switch (ah->hw_version.devid) { | |
1014 | case AR5416_DEVID_PCI: | |
1015 | case AR5416_DEVID_PCIE: | |
1016 | case AR5416_AR9100_DEVID: | |
1017 | case AR9160_DEVID_PCI: | |
1018 | case AR9280_DEVID_PCI: | |
1019 | case AR9280_DEVID_PCIE: | |
1020 | case AR9285_DEVID_PCIE: | |
db3cc53a SB |
1021 | case AR9287_DEVID_PCI: |
1022 | case AR9287_DEVID_PCIE: | |
d70357d5 | 1023 | case AR2427_DEVID_PCIE: |
db3cc53a | 1024 | case AR9300_DEVID_PCIE: |
d70357d5 LR |
1025 | break; |
1026 | default: | |
1027 | if (common->bus_ops->ath_bus_type == ATH_USB) | |
1028 | break; | |
1029 | ath_print(common, ATH_DBG_FATAL, | |
1030 | "Hardware device ID 0x%04x not supported\n", | |
1031 | ah->hw_version.devid); | |
1032 | return -EOPNOTSUPP; | |
1033 | } | |
1034 | ||
1035 | ret = __ath9k_hw_init(ah); | |
1036 | if (ret) { | |
1037 | ath_print(common, ATH_DBG_FATAL, | |
1038 | "Unable to initialize hardware; " | |
1039 | "initialization status: %d\n", ret); | |
1040 | return ret; | |
1041 | } | |
1042 | ||
1043 | return 0; | |
1044 | } | |
1045 | EXPORT_SYMBOL(ath9k_hw_init); | |
1046 | ||
cbe61d8a | 1047 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
f078f209 | 1048 | { |
f1dc5600 S |
1049 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
1050 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); | |
f078f209 | 1051 | |
f1dc5600 S |
1052 | REG_WRITE(ah, AR_QOS_NO_ACK, |
1053 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | | |
1054 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | | |
1055 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); | |
1056 | ||
1057 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); | |
1058 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); | |
1059 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); | |
1060 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); | |
1061 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); | |
f078f209 LR |
1062 | } |
1063 | ||
cbe61d8a | 1064 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
f1dc5600 | 1065 | struct ath9k_channel *chan) |
f078f209 | 1066 | { |
64773964 | 1067 | u32 pll = ath9k_hw_compute_pll_control(ah, chan); |
f078f209 | 1068 | |
d03a66c1 | 1069 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
f078f209 | 1070 | |
c75724d1 LR |
1071 | /* Switch the core clock for ar9271 to 117Mhz */ |
1072 | if (AR_SREV_9271(ah)) { | |
25e2ab17 S |
1073 | udelay(500); |
1074 | REG_WRITE(ah, 0x50040, 0x304); | |
c75724d1 LR |
1075 | } |
1076 | ||
f1dc5600 S |
1077 | udelay(RTC_PLL_SETTLE_DELAY); |
1078 | ||
1079 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | |
f078f209 LR |
1080 | } |
1081 | ||
cbe61d8a | 1082 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
d97809db | 1083 | enum nl80211_iftype opmode) |
f078f209 | 1084 | { |
152d530d | 1085 | u32 imr_reg = AR_IMR_TXERR | |
f1dc5600 S |
1086 | AR_IMR_TXURN | |
1087 | AR_IMR_RXERR | | |
1088 | AR_IMR_RXORN | | |
1089 | AR_IMR_BCNMISC; | |
f078f209 | 1090 | |
0ce024cb | 1091 | if (ah->config.rx_intr_mitigation) |
152d530d | 1092 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; |
f078f209 | 1093 | else |
152d530d | 1094 | imr_reg |= AR_IMR_RXOK; |
f078f209 | 1095 | |
152d530d | 1096 | imr_reg |= AR_IMR_TXOK; |
f078f209 | 1097 | |
d97809db | 1098 | if (opmode == NL80211_IFTYPE_AP) |
152d530d | 1099 | imr_reg |= AR_IMR_MIB; |
f078f209 | 1100 | |
152d530d | 1101 | REG_WRITE(ah, AR_IMR, imr_reg); |
74bad5cb PR |
1102 | ah->imrs2_reg |= AR_IMR_S2_GTT; |
1103 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); | |
f078f209 | 1104 | |
f1dc5600 S |
1105 | if (!AR_SREV_9100(ah)) { |
1106 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); | |
1107 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); | |
1108 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); | |
1109 | } | |
f078f209 LR |
1110 | } |
1111 | ||
0005baf4 | 1112 | static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
f078f209 | 1113 | { |
0005baf4 FF |
1114 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
1115 | val = min(val, (u32) 0xFFFF); | |
1116 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); | |
f078f209 LR |
1117 | } |
1118 | ||
0005baf4 | 1119 | static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
f078f209 | 1120 | { |
0005baf4 FF |
1121 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
1122 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); | |
1123 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); | |
1124 | } | |
1125 | ||
1126 | static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) | |
1127 | { | |
1128 | u32 val = ath9k_hw_mac_to_clks(ah, us); | |
1129 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); | |
1130 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); | |
f078f209 | 1131 | } |
f1dc5600 | 1132 | |
cbe61d8a | 1133 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
f078f209 | 1134 | { |
f078f209 | 1135 | if (tu > 0xFFFF) { |
c46917bb LR |
1136 | ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, |
1137 | "bad global tx timeout %u\n", tu); | |
2660b81a | 1138 | ah->globaltxtimeout = (u32) -1; |
f078f209 LR |
1139 | return false; |
1140 | } else { | |
1141 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); | |
2660b81a | 1142 | ah->globaltxtimeout = tu; |
f078f209 LR |
1143 | return true; |
1144 | } | |
1145 | } | |
1146 | ||
0005baf4 | 1147 | void ath9k_hw_init_global_settings(struct ath_hw *ah) |
f078f209 | 1148 | { |
0005baf4 FF |
1149 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
1150 | int acktimeout; | |
e239d859 | 1151 | int slottime; |
0005baf4 FF |
1152 | int sifstime; |
1153 | ||
c46917bb LR |
1154 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", |
1155 | ah->misc_mode); | |
f078f209 | 1156 | |
2660b81a | 1157 | if (ah->misc_mode != 0) |
f1dc5600 | 1158 | REG_WRITE(ah, AR_PCU_MISC, |
2660b81a | 1159 | REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); |
0005baf4 FF |
1160 | |
1161 | if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) | |
1162 | sifstime = 16; | |
1163 | else | |
1164 | sifstime = 10; | |
1165 | ||
e239d859 FF |
1166 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
1167 | slottime = ah->slottime + 3 * ah->coverage_class; | |
1168 | acktimeout = slottime + sifstime; | |
42c4568a FF |
1169 | |
1170 | /* | |
1171 | * Workaround for early ACK timeouts, add an offset to match the | |
1172 | * initval's 64us ack timeout value. | |
1173 | * This was initially only meant to work around an issue with delayed | |
1174 | * BA frames in some implementations, but it has been found to fix ACK | |
1175 | * timeout issues in other cases as well. | |
1176 | */ | |
1177 | if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) | |
1178 | acktimeout += 64 - sifstime - ah->slottime; | |
1179 | ||
e239d859 | 1180 | ath9k_hw_setslottime(ah, slottime); |
0005baf4 FF |
1181 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
1182 | ath9k_hw_set_cts_timeout(ah, acktimeout); | |
2660b81a S |
1183 | if (ah->globaltxtimeout != (u32) -1) |
1184 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); | |
f1dc5600 | 1185 | } |
0005baf4 | 1186 | EXPORT_SYMBOL(ath9k_hw_init_global_settings); |
f1dc5600 | 1187 | |
285f2dda | 1188 | void ath9k_hw_deinit(struct ath_hw *ah) |
f1dc5600 | 1189 | { |
211f5859 LR |
1190 | struct ath_common *common = ath9k_hw_common(ah); |
1191 | ||
736b3a27 | 1192 | if (common->state < ATH_HW_INITIALIZED) |
211f5859 LR |
1193 | goto free_hw; |
1194 | ||
f1dc5600 | 1195 | if (!AR_SREV_9100(ah)) |
e70c0cfd | 1196 | ath9k_hw_ani_disable(ah); |
f1dc5600 | 1197 | |
9ecdef4b | 1198 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
211f5859 LR |
1199 | |
1200 | free_hw: | |
8fe65368 | 1201 | ath9k_hw_rf_free_ext_banks(ah); |
f1dc5600 | 1202 | } |
285f2dda | 1203 | EXPORT_SYMBOL(ath9k_hw_deinit); |
f1dc5600 | 1204 | |
f1dc5600 S |
1205 | /*******/ |
1206 | /* INI */ | |
1207 | /*******/ | |
1208 | ||
8fe65368 | 1209 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) |
3a702e49 BC |
1210 | { |
1211 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); | |
1212 | ||
1213 | if (IS_CHAN_B(chan)) | |
1214 | ctl |= CTL_11B; | |
1215 | else if (IS_CHAN_G(chan)) | |
1216 | ctl |= CTL_11G; | |
1217 | else | |
1218 | ctl |= CTL_11A; | |
1219 | ||
1220 | return ctl; | |
1221 | } | |
1222 | ||
f1dc5600 S |
1223 | /****************************************/ |
1224 | /* Reset and Channel Switching Routines */ | |
1225 | /****************************************/ | |
1226 | ||
cbe61d8a | 1227 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
f1dc5600 S |
1228 | { |
1229 | u32 regval; | |
1230 | ||
d7e7d229 LR |
1231 | /* |
1232 | * set AHB_MODE not to do cacheline prefetches | |
1233 | */ | |
f1dc5600 S |
1234 | regval = REG_READ(ah, AR_AHB_MODE); |
1235 | REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); | |
1236 | ||
d7e7d229 LR |
1237 | /* |
1238 | * let mac dma reads be in 128 byte chunks | |
1239 | */ | |
f1dc5600 S |
1240 | regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; |
1241 | REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); | |
1242 | ||
d7e7d229 LR |
1243 | /* |
1244 | * Restore TX Trigger Level to its pre-reset value. | |
1245 | * The initial value depends on whether aggregation is enabled, and is | |
1246 | * adjusted whenever underruns are detected. | |
1247 | */ | |
2660b81a | 1248 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); |
f1dc5600 | 1249 | |
d7e7d229 LR |
1250 | /* |
1251 | * let mac dma writes be in 128 byte chunks | |
1252 | */ | |
f1dc5600 S |
1253 | regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; |
1254 | REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); | |
1255 | ||
d7e7d229 LR |
1256 | /* |
1257 | * Setup receive FIFO threshold to hold off TX activities | |
1258 | */ | |
f1dc5600 S |
1259 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
1260 | ||
d7e7d229 LR |
1261 | /* |
1262 | * reduce the number of usable entries in PCU TXBUF to avoid | |
1263 | * wrap around issues. | |
1264 | */ | |
f1dc5600 | 1265 | if (AR_SREV_9285(ah)) { |
d7e7d229 LR |
1266 | /* For AR9285 the number of Fifos are reduced to half. |
1267 | * So set the usable tx buf size also to half to | |
1268 | * avoid data/delimiter underruns | |
1269 | */ | |
f1dc5600 S |
1270 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
1271 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); | |
d7e7d229 | 1272 | } else if (!AR_SREV_9271(ah)) { |
f1dc5600 S |
1273 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
1274 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); | |
1275 | } | |
1276 | } | |
1277 | ||
cbe61d8a | 1278 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
f1dc5600 S |
1279 | { |
1280 | u32 val; | |
1281 | ||
1282 | val = REG_READ(ah, AR_STA_ID1); | |
1283 | val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); | |
1284 | switch (opmode) { | |
d97809db | 1285 | case NL80211_IFTYPE_AP: |
f1dc5600 S |
1286 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
1287 | | AR_STA_ID1_KSRCH_MODE); | |
1288 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 1289 | break; |
d97809db | 1290 | case NL80211_IFTYPE_ADHOC: |
9cb5412b | 1291 | case NL80211_IFTYPE_MESH_POINT: |
f1dc5600 S |
1292 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
1293 | | AR_STA_ID1_KSRCH_MODE); | |
1294 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 1295 | break; |
d97809db CM |
1296 | case NL80211_IFTYPE_STATION: |
1297 | case NL80211_IFTYPE_MONITOR: | |
f1dc5600 | 1298 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); |
f078f209 | 1299 | break; |
f1dc5600 S |
1300 | } |
1301 | } | |
1302 | ||
8fe65368 LR |
1303 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
1304 | u32 *coef_mantissa, u32 *coef_exponent) | |
f1dc5600 S |
1305 | { |
1306 | u32 coef_exp, coef_man; | |
1307 | ||
1308 | for (coef_exp = 31; coef_exp > 0; coef_exp--) | |
1309 | if ((coef_scaled >> coef_exp) & 0x1) | |
1310 | break; | |
1311 | ||
1312 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); | |
1313 | ||
1314 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); | |
1315 | ||
1316 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); | |
1317 | *coef_exponent = coef_exp - 16; | |
1318 | } | |
1319 | ||
cbe61d8a | 1320 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
f1dc5600 S |
1321 | { |
1322 | u32 rst_flags; | |
1323 | u32 tmpReg; | |
1324 | ||
70768496 S |
1325 | if (AR_SREV_9100(ah)) { |
1326 | u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); | |
1327 | val &= ~AR_RTC_DERIVED_CLK_PERIOD; | |
1328 | val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); | |
1329 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); | |
1330 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); | |
1331 | } | |
1332 | ||
f1dc5600 S |
1333 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
1334 | AR_RTC_FORCE_WAKE_ON_INT); | |
1335 | ||
1336 | if (AR_SREV_9100(ah)) { | |
1337 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | | |
1338 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; | |
1339 | } else { | |
1340 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
1341 | if (tmpReg & | |
1342 | (AR_INTR_SYNC_LOCAL_TIMEOUT | | |
1343 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { | |
42d5bc3f | 1344 | u32 val; |
f1dc5600 | 1345 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
42d5bc3f LR |
1346 | |
1347 | val = AR_RC_HOSTIF; | |
1348 | if (!AR_SREV_9300_20_OR_LATER(ah)) | |
1349 | val |= AR_RC_AHB; | |
1350 | REG_WRITE(ah, AR_RC, val); | |
1351 | ||
1352 | } else if (!AR_SREV_9300_20_OR_LATER(ah)) | |
f1dc5600 | 1353 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
f1dc5600 S |
1354 | |
1355 | rst_flags = AR_RTC_RC_MAC_WARM; | |
1356 | if (type == ATH9K_RESET_COLD) | |
1357 | rst_flags |= AR_RTC_RC_MAC_COLD; | |
1358 | } | |
1359 | ||
d03a66c1 | 1360 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
f1dc5600 S |
1361 | udelay(50); |
1362 | ||
d03a66c1 | 1363 | REG_WRITE(ah, AR_RTC_RC, 0); |
0caa7b14 | 1364 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
c46917bb LR |
1365 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
1366 | "RTC stuck in MAC reset\n"); | |
f1dc5600 S |
1367 | return false; |
1368 | } | |
1369 | ||
1370 | if (!AR_SREV_9100(ah)) | |
1371 | REG_WRITE(ah, AR_RC, 0); | |
1372 | ||
f1dc5600 S |
1373 | if (AR_SREV_9100(ah)) |
1374 | udelay(50); | |
1375 | ||
1376 | return true; | |
1377 | } | |
1378 | ||
cbe61d8a | 1379 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
f1dc5600 S |
1380 | { |
1381 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | | |
1382 | AR_RTC_FORCE_WAKE_ON_INT); | |
1383 | ||
42d5bc3f | 1384 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
1c29ce67 VT |
1385 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
1386 | ||
d03a66c1 | 1387 | REG_WRITE(ah, AR_RTC_RESET, 0); |
8bd1d07f | 1388 | udelay(2); |
1c29ce67 VT |
1389 | |
1390 | if (!AR_SREV_9100(ah)) | |
1391 | REG_WRITE(ah, AR_RC, 0); | |
1392 | ||
d03a66c1 | 1393 | REG_WRITE(ah, AR_RTC_RESET, 1); |
f1dc5600 S |
1394 | |
1395 | if (!ath9k_hw_wait(ah, | |
1396 | AR_RTC_STATUS, | |
1397 | AR_RTC_STATUS_M, | |
0caa7b14 S |
1398 | AR_RTC_STATUS_ON, |
1399 | AH_WAIT_TIMEOUT)) { | |
c46917bb LR |
1400 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
1401 | "RTC not waking up\n"); | |
f1dc5600 | 1402 | return false; |
f078f209 LR |
1403 | } |
1404 | ||
f1dc5600 S |
1405 | ath9k_hw_read_revisions(ah); |
1406 | ||
1407 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); | |
1408 | } | |
1409 | ||
cbe61d8a | 1410 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
f1dc5600 S |
1411 | { |
1412 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | |
1413 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); | |
1414 | ||
1415 | switch (type) { | |
1416 | case ATH9K_RESET_POWER_ON: | |
1417 | return ath9k_hw_set_reset_power_on(ah); | |
f1dc5600 S |
1418 | case ATH9K_RESET_WARM: |
1419 | case ATH9K_RESET_COLD: | |
1420 | return ath9k_hw_set_reset(ah, type); | |
f1dc5600 S |
1421 | default: |
1422 | return false; | |
1423 | } | |
f078f209 LR |
1424 | } |
1425 | ||
cbe61d8a | 1426 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
f1dc5600 | 1427 | struct ath9k_channel *chan) |
f078f209 | 1428 | { |
42abfbee | 1429 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { |
8bd1d07f SB |
1430 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) |
1431 | return false; | |
1432 | } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) | |
f1dc5600 | 1433 | return false; |
f078f209 | 1434 | |
9ecdef4b | 1435 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 1436 | return false; |
f078f209 | 1437 | |
2660b81a | 1438 | ah->chip_fullsleep = false; |
f1dc5600 | 1439 | ath9k_hw_init_pll(ah, chan); |
f1dc5600 | 1440 | ath9k_hw_set_rfmode(ah, chan); |
f078f209 | 1441 | |
f1dc5600 | 1442 | return true; |
f078f209 LR |
1443 | } |
1444 | ||
cbe61d8a | 1445 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
25c56eec | 1446 | struct ath9k_channel *chan) |
f078f209 | 1447 | { |
608b88cb | 1448 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
c46917bb | 1449 | struct ath_common *common = ath9k_hw_common(ah); |
5f8e077c | 1450 | struct ieee80211_channel *channel = chan->chan; |
8fe65368 | 1451 | u32 qnum; |
0a3b7bac | 1452 | int r; |
f078f209 LR |
1453 | |
1454 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | |
1455 | if (ath9k_hw_numtxpending(ah, qnum)) { | |
c46917bb LR |
1456 | ath_print(common, ATH_DBG_QUEUE, |
1457 | "Transmit frames pending on " | |
1458 | "queue %d\n", qnum); | |
f078f209 LR |
1459 | return false; |
1460 | } | |
1461 | } | |
1462 | ||
8fe65368 | 1463 | if (!ath9k_hw_rfbus_req(ah)) { |
c46917bb LR |
1464 | ath_print(common, ATH_DBG_FATAL, |
1465 | "Could not kill baseband RX\n"); | |
f078f209 LR |
1466 | return false; |
1467 | } | |
1468 | ||
8fe65368 | 1469 | ath9k_hw_set_channel_regs(ah, chan); |
f078f209 | 1470 | |
8fe65368 | 1471 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac LR |
1472 | if (r) { |
1473 | ath_print(common, ATH_DBG_FATAL, | |
1474 | "Failed to set channel\n"); | |
1475 | return false; | |
f078f209 LR |
1476 | } |
1477 | ||
8fbff4b8 | 1478 | ah->eep_ops->set_txpower(ah, chan, |
608b88cb | 1479 | ath9k_regd_get_ctl(regulatory, chan), |
f74df6fb S |
1480 | channel->max_antenna_gain * 2, |
1481 | channel->max_power * 2, | |
1482 | min((u32) MAX_RATE_POWER, | |
608b88cb | 1483 | (u32) regulatory->power_limit)); |
f078f209 | 1484 | |
8fe65368 | 1485 | ath9k_hw_rfbus_done(ah); |
f078f209 | 1486 | |
f1dc5600 S |
1487 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1488 | ath9k_hw_set_delta_slope(ah, chan); | |
1489 | ||
8fe65368 | 1490 | ath9k_hw_spur_mitigate_freq(ah, chan); |
f1dc5600 S |
1491 | |
1492 | if (!chan->oneTimeCalsDone) | |
1493 | chan->oneTimeCalsDone = true; | |
1494 | ||
1495 | return true; | |
1496 | } | |
1497 | ||
cbe61d8a | 1498 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
ae8d2858 | 1499 | bool bChannelChange) |
f078f209 | 1500 | { |
1510718d | 1501 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1502 | u32 saveLedState; |
2660b81a | 1503 | struct ath9k_channel *curchan = ah->curchan; |
f078f209 LR |
1504 | u32 saveDefAntenna; |
1505 | u32 macStaId1; | |
46fe782c | 1506 | u64 tsf = 0; |
8fe65368 | 1507 | int i, r; |
f078f209 | 1508 | |
43c27613 LR |
1509 | ah->txchainmask = common->tx_chainmask; |
1510 | ah->rxchainmask = common->rx_chainmask; | |
f078f209 | 1511 | |
9ecdef4b | 1512 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
ae8d2858 | 1513 | return -EIO; |
f078f209 | 1514 | |
9ebef799 | 1515 | if (curchan && !ah->chip_fullsleep) |
f078f209 LR |
1516 | ath9k_hw_getnf(ah, curchan); |
1517 | ||
1518 | if (bChannelChange && | |
2660b81a S |
1519 | (ah->chip_fullsleep != true) && |
1520 | (ah->curchan != NULL) && | |
1521 | (chan->channel != ah->curchan->channel) && | |
f078f209 | 1522 | ((chan->channelFlags & CHANNEL_ALL) == |
2660b81a | 1523 | (ah->curchan->channelFlags & CHANNEL_ALL)) && |
0a475cc6 VT |
1524 | !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || |
1525 | IS_CHAN_A_5MHZ_SPACED(ah->curchan))) { | |
f078f209 | 1526 | |
25c56eec | 1527 | if (ath9k_hw_channel_change(ah, chan)) { |
2660b81a | 1528 | ath9k_hw_loadnf(ah, ah->curchan); |
f078f209 | 1529 | ath9k_hw_start_nfcal(ah); |
ae8d2858 | 1530 | return 0; |
f078f209 LR |
1531 | } |
1532 | } | |
1533 | ||
1534 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); | |
1535 | if (saveDefAntenna == 0) | |
1536 | saveDefAntenna = 1; | |
1537 | ||
1538 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; | |
1539 | ||
46fe782c S |
1540 | /* For chips on which RTC reset is done, save TSF before it gets cleared */ |
1541 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) | |
1542 | tsf = ath9k_hw_gettsf64(ah); | |
1543 | ||
f078f209 LR |
1544 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
1545 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | | |
1546 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); | |
1547 | ||
1548 | ath9k_hw_mark_phy_inactive(ah); | |
1549 | ||
05020d23 | 1550 | /* Only required on the first reset */ |
d7e7d229 LR |
1551 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1552 | REG_WRITE(ah, | |
1553 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1554 | AR9271_RADIO_RF_RST); | |
1555 | udelay(50); | |
1556 | } | |
1557 | ||
f078f209 | 1558 | if (!ath9k_hw_chip_reset(ah, chan)) { |
c46917bb | 1559 | ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); |
ae8d2858 | 1560 | return -EINVAL; |
f078f209 LR |
1561 | } |
1562 | ||
05020d23 | 1563 | /* Only required on the first reset */ |
d7e7d229 LR |
1564 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1565 | ah->htc_reset_init = false; | |
1566 | REG_WRITE(ah, | |
1567 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1568 | AR9271_GATE_MAC_CTL); | |
1569 | udelay(50); | |
1570 | } | |
1571 | ||
46fe782c S |
1572 | /* Restore TSF */ |
1573 | if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) | |
1574 | ath9k_hw_settsf64(ah, tsf); | |
1575 | ||
369391db VT |
1576 | if (AR_SREV_9280_10_OR_LATER(ah)) |
1577 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); | |
f078f209 | 1578 | |
25c56eec | 1579 | r = ath9k_hw_process_ini(ah, chan); |
ae8d2858 LR |
1580 | if (r) |
1581 | return r; | |
f078f209 | 1582 | |
0ced0e17 JM |
1583 | /* Setup MFP options for CCMP */ |
1584 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
1585 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt | |
1586 | * frames when constructing CCMP AAD. */ | |
1587 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, | |
1588 | 0xc7ff); | |
1589 | ah->sw_mgmt_crypto = false; | |
1590 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | |
1591 | /* Disable hardware crypto for management frames */ | |
1592 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, | |
1593 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); | |
1594 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | |
1595 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); | |
1596 | ah->sw_mgmt_crypto = true; | |
1597 | } else | |
1598 | ah->sw_mgmt_crypto = true; | |
1599 | ||
f078f209 LR |
1600 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1601 | ath9k_hw_set_delta_slope(ah, chan); | |
1602 | ||
8fe65368 | 1603 | ath9k_hw_spur_mitigate_freq(ah, chan); |
d6509151 | 1604 | ah->eep_ops->set_board_values(ah, chan); |
a7765828 | 1605 | |
1510718d LR |
1606 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); |
1607 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) | |
f078f209 LR |
1608 | | macStaId1 |
1609 | | AR_STA_ID1_RTS_USE_DEF | |
2660b81a | 1610 | | (ah->config. |
60b67f51 | 1611 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
2660b81a S |
1612 | | ah->sta_id1_defaults); |
1613 | ath9k_hw_set_operating_mode(ah, ah->opmode); | |
f078f209 | 1614 | |
13b81559 | 1615 | ath_hw_setbssidmask(common); |
f078f209 LR |
1616 | |
1617 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); | |
1618 | ||
3453ad88 | 1619 | ath9k_hw_write_associd(ah); |
f078f209 LR |
1620 | |
1621 | REG_WRITE(ah, AR_ISR, ~0); | |
1622 | ||
1623 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); | |
1624 | ||
8fe65368 | 1625 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac LR |
1626 | if (r) |
1627 | return r; | |
f078f209 LR |
1628 | |
1629 | for (i = 0; i < AR_NUM_DCU; i++) | |
1630 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); | |
1631 | ||
2660b81a S |
1632 | ah->intr_txqs = 0; |
1633 | for (i = 0; i < ah->caps.total_queues; i++) | |
f078f209 LR |
1634 | ath9k_hw_resettxqueue(ah, i); |
1635 | ||
2660b81a | 1636 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
f078f209 LR |
1637 | ath9k_hw_init_qos(ah); |
1638 | ||
2660b81a | 1639 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
500c064d | 1640 | ath9k_enable_rfkill(ah); |
3b319aae | 1641 | |
0005baf4 | 1642 | ath9k_hw_init_global_settings(ah); |
f078f209 | 1643 | |
326bebbc | 1644 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
ac88b6ec VN |
1645 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, |
1646 | AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR); | |
1647 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, | |
1648 | AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR); | |
1649 | REG_WRITE(ah, AR_D_GBL_IFS_EIFS, | |
1650 | AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR); | |
1651 | ||
1652 | REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR); | |
1653 | REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR); | |
1654 | ||
1655 | REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, | |
1656 | AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); | |
1657 | REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, | |
1658 | AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); | |
1659 | } | |
326bebbc | 1660 | if (AR_SREV_9287_12_OR_LATER(ah)) { |
ac88b6ec VN |
1661 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, |
1662 | AR_PCU_MISC_MODE2_ENABLE_AGGWEP); | |
1663 | } | |
1664 | ||
f078f209 LR |
1665 | REG_WRITE(ah, AR_STA_ID1, |
1666 | REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); | |
1667 | ||
1668 | ath9k_hw_set_dma(ah); | |
1669 | ||
1670 | REG_WRITE(ah, AR_OBS, 8); | |
1671 | ||
0ce024cb | 1672 | if (ah->config.rx_intr_mitigation) { |
f078f209 LR |
1673 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); |
1674 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); | |
1675 | } | |
1676 | ||
1677 | ath9k_hw_init_bb(ah, chan); | |
1678 | ||
ae8d2858 | 1679 | if (!ath9k_hw_init_cal(ah, chan)) |
6badaaf7 | 1680 | return -EIO; |
f078f209 | 1681 | |
8fe65368 | 1682 | ath9k_hw_restore_chainmask(ah); |
f078f209 LR |
1683 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
1684 | ||
d7e7d229 LR |
1685 | /* |
1686 | * For big endian systems turn on swapping for descriptors | |
1687 | */ | |
f078f209 LR |
1688 | if (AR_SREV_9100(ah)) { |
1689 | u32 mask; | |
1690 | mask = REG_READ(ah, AR_CFG); | |
1691 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | |
c46917bb | 1692 | ath_print(common, ATH_DBG_RESET, |
04bd4638 | 1693 | "CFG Byte Swap Set 0x%x\n", mask); |
f078f209 LR |
1694 | } else { |
1695 | mask = | |
1696 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | |
1697 | REG_WRITE(ah, AR_CFG, mask); | |
c46917bb | 1698 | ath_print(common, ATH_DBG_RESET, |
04bd4638 | 1699 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); |
f078f209 LR |
1700 | } |
1701 | } else { | |
d7e7d229 LR |
1702 | /* Configure AR9271 target WLAN */ |
1703 | if (AR_SREV_9271(ah)) | |
1704 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); | |
f078f209 | 1705 | #ifdef __BIG_ENDIAN |
d7e7d229 LR |
1706 | else |
1707 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
f078f209 LR |
1708 | #endif |
1709 | } | |
1710 | ||
766ec4a9 | 1711 | if (ah->btcoex_hw.enabled) |
42cc41ed VT |
1712 | ath9k_hw_btcoex_enable(ah); |
1713 | ||
ae8d2858 | 1714 | return 0; |
f078f209 | 1715 | } |
7322fd19 | 1716 | EXPORT_SYMBOL(ath9k_hw_reset); |
f078f209 | 1717 | |
f1dc5600 S |
1718 | /************************/ |
1719 | /* Key Cache Management */ | |
1720 | /************************/ | |
f078f209 | 1721 | |
cbe61d8a | 1722 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) |
f078f209 | 1723 | { |
f1dc5600 | 1724 | u32 keyType; |
f078f209 | 1725 | |
2660b81a | 1726 | if (entry >= ah->caps.keycache_size) { |
c46917bb LR |
1727 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
1728 | "keychache entry %u out of range\n", entry); | |
f078f209 LR |
1729 | return false; |
1730 | } | |
1731 | ||
f1dc5600 | 1732 | keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); |
f078f209 | 1733 | |
f1dc5600 S |
1734 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); |
1735 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); | |
1736 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); | |
1737 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); | |
1738 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); | |
1739 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); | |
1740 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); | |
1741 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); | |
f078f209 | 1742 | |
f1dc5600 S |
1743 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
1744 | u16 micentry = entry + 64; | |
f078f209 | 1745 | |
f1dc5600 S |
1746 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); |
1747 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); | |
1748 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); | |
1749 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); | |
f078f209 | 1750 | |
f078f209 LR |
1751 | } |
1752 | ||
f078f209 LR |
1753 | return true; |
1754 | } | |
7322fd19 | 1755 | EXPORT_SYMBOL(ath9k_hw_keyreset); |
f078f209 | 1756 | |
cbe61d8a | 1757 | bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) |
f078f209 | 1758 | { |
f1dc5600 | 1759 | u32 macHi, macLo; |
f078f209 | 1760 | |
2660b81a | 1761 | if (entry >= ah->caps.keycache_size) { |
c46917bb LR |
1762 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
1763 | "keychache entry %u out of range\n", entry); | |
f1dc5600 | 1764 | return false; |
f078f209 LR |
1765 | } |
1766 | ||
f1dc5600 S |
1767 | if (mac != NULL) { |
1768 | macHi = (mac[5] << 8) | mac[4]; | |
1769 | macLo = (mac[3] << 24) | | |
1770 | (mac[2] << 16) | | |
1771 | (mac[1] << 8) | | |
1772 | mac[0]; | |
1773 | macLo >>= 1; | |
1774 | macLo |= (macHi & 1) << 31; | |
1775 | macHi >>= 1; | |
f078f209 | 1776 | } else { |
f1dc5600 | 1777 | macLo = macHi = 0; |
f078f209 | 1778 | } |
f1dc5600 S |
1779 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); |
1780 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); | |
f078f209 | 1781 | |
f1dc5600 | 1782 | return true; |
f078f209 | 1783 | } |
7322fd19 | 1784 | EXPORT_SYMBOL(ath9k_hw_keysetmac); |
f078f209 | 1785 | |
cbe61d8a | 1786 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, |
f1dc5600 | 1787 | const struct ath9k_keyval *k, |
e0caf9ea | 1788 | const u8 *mac) |
f078f209 | 1789 | { |
2660b81a | 1790 | const struct ath9k_hw_capabilities *pCap = &ah->caps; |
c46917bb | 1791 | struct ath_common *common = ath9k_hw_common(ah); |
f1dc5600 S |
1792 | u32 key0, key1, key2, key3, key4; |
1793 | u32 keyType; | |
f078f209 | 1794 | |
f1dc5600 | 1795 | if (entry >= pCap->keycache_size) { |
c46917bb LR |
1796 | ath_print(common, ATH_DBG_FATAL, |
1797 | "keycache entry %u out of range\n", entry); | |
f1dc5600 | 1798 | return false; |
f078f209 LR |
1799 | } |
1800 | ||
f1dc5600 S |
1801 | switch (k->kv_type) { |
1802 | case ATH9K_CIPHER_AES_OCB: | |
1803 | keyType = AR_KEYTABLE_TYPE_AES; | |
1804 | break; | |
1805 | case ATH9K_CIPHER_AES_CCM: | |
1806 | if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { | |
c46917bb LR |
1807 | ath_print(common, ATH_DBG_ANY, |
1808 | "AES-CCM not supported by mac rev 0x%x\n", | |
1809 | ah->hw_version.macRev); | |
f1dc5600 S |
1810 | return false; |
1811 | } | |
1812 | keyType = AR_KEYTABLE_TYPE_CCM; | |
1813 | break; | |
1814 | case ATH9K_CIPHER_TKIP: | |
1815 | keyType = AR_KEYTABLE_TYPE_TKIP; | |
1816 | if (ATH9K_IS_MIC_ENABLED(ah) | |
1817 | && entry + 64 >= pCap->keycache_size) { | |
c46917bb LR |
1818 | ath_print(common, ATH_DBG_ANY, |
1819 | "entry %u inappropriate for TKIP\n", entry); | |
f1dc5600 S |
1820 | return false; |
1821 | } | |
1822 | break; | |
1823 | case ATH9K_CIPHER_WEP: | |
e31a16d6 | 1824 | if (k->kv_len < WLAN_KEY_LEN_WEP40) { |
c46917bb LR |
1825 | ath_print(common, ATH_DBG_ANY, |
1826 | "WEP key length %u too small\n", k->kv_len); | |
f1dc5600 S |
1827 | return false; |
1828 | } | |
e31a16d6 | 1829 | if (k->kv_len <= WLAN_KEY_LEN_WEP40) |
f1dc5600 | 1830 | keyType = AR_KEYTABLE_TYPE_40; |
e31a16d6 | 1831 | else if (k->kv_len <= WLAN_KEY_LEN_WEP104) |
f1dc5600 S |
1832 | keyType = AR_KEYTABLE_TYPE_104; |
1833 | else | |
1834 | keyType = AR_KEYTABLE_TYPE_128; | |
1835 | break; | |
1836 | case ATH9K_CIPHER_CLR: | |
1837 | keyType = AR_KEYTABLE_TYPE_CLR; | |
1838 | break; | |
1839 | default: | |
c46917bb LR |
1840 | ath_print(common, ATH_DBG_FATAL, |
1841 | "cipher %u not supported\n", k->kv_type); | |
f1dc5600 | 1842 | return false; |
f078f209 LR |
1843 | } |
1844 | ||
e0caf9ea JM |
1845 | key0 = get_unaligned_le32(k->kv_val + 0); |
1846 | key1 = get_unaligned_le16(k->kv_val + 4); | |
1847 | key2 = get_unaligned_le32(k->kv_val + 6); | |
1848 | key3 = get_unaligned_le16(k->kv_val + 10); | |
1849 | key4 = get_unaligned_le32(k->kv_val + 12); | |
e31a16d6 | 1850 | if (k->kv_len <= WLAN_KEY_LEN_WEP104) |
f1dc5600 | 1851 | key4 &= 0xff; |
f078f209 | 1852 | |
672903b3 JM |
1853 | /* |
1854 | * Note: Key cache registers access special memory area that requires | |
1855 | * two 32-bit writes to actually update the values in the internal | |
1856 | * memory. Consequently, the exact order and pairs used here must be | |
1857 | * maintained. | |
1858 | */ | |
1859 | ||
f1dc5600 S |
1860 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
1861 | u16 micentry = entry + 64; | |
f078f209 | 1862 | |
672903b3 JM |
1863 | /* |
1864 | * Write inverted key[47:0] first to avoid Michael MIC errors | |
1865 | * on frames that could be sent or received at the same time. | |
1866 | * The correct key will be written in the end once everything | |
1867 | * else is ready. | |
1868 | */ | |
f1dc5600 S |
1869 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); |
1870 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); | |
672903b3 JM |
1871 | |
1872 | /* Write key[95:48] */ | |
f1dc5600 S |
1873 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
1874 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); | |
672903b3 JM |
1875 | |
1876 | /* Write key[127:96] and key type */ | |
f1dc5600 S |
1877 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
1878 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); | |
672903b3 JM |
1879 | |
1880 | /* Write MAC address for the entry */ | |
f1dc5600 | 1881 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
f078f209 | 1882 | |
2660b81a | 1883 | if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { |
672903b3 JM |
1884 | /* |
1885 | * TKIP uses two key cache entries: | |
1886 | * Michael MIC TX/RX keys in the same key cache entry | |
1887 | * (idx = main index + 64): | |
1888 | * key0 [31:0] = RX key [31:0] | |
1889 | * key1 [15:0] = TX key [31:16] | |
1890 | * key1 [31:16] = reserved | |
1891 | * key2 [31:0] = RX key [63:32] | |
1892 | * key3 [15:0] = TX key [15:0] | |
1893 | * key3 [31:16] = reserved | |
1894 | * key4 [31:0] = TX key [63:32] | |
1895 | */ | |
f1dc5600 | 1896 | u32 mic0, mic1, mic2, mic3, mic4; |
f078f209 | 1897 | |
f1dc5600 S |
1898 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
1899 | mic2 = get_unaligned_le32(k->kv_mic + 4); | |
1900 | mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; | |
1901 | mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; | |
1902 | mic4 = get_unaligned_le32(k->kv_txmic + 4); | |
672903b3 JM |
1903 | |
1904 | /* Write RX[31:0] and TX[31:16] */ | |
f1dc5600 S |
1905 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
1906 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); | |
672903b3 JM |
1907 | |
1908 | /* Write RX[63:32] and TX[15:0] */ | |
f1dc5600 S |
1909 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
1910 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); | |
672903b3 JM |
1911 | |
1912 | /* Write TX[63:32] and keyType(reserved) */ | |
f1dc5600 S |
1913 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); |
1914 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), | |
1915 | AR_KEYTABLE_TYPE_CLR); | |
f078f209 | 1916 | |
f1dc5600 | 1917 | } else { |
672903b3 JM |
1918 | /* |
1919 | * TKIP uses four key cache entries (two for group | |
1920 | * keys): | |
1921 | * Michael MIC TX/RX keys are in different key cache | |
1922 | * entries (idx = main index + 64 for TX and | |
1923 | * main index + 32 + 96 for RX): | |
1924 | * key0 [31:0] = TX/RX MIC key [31:0] | |
1925 | * key1 [31:0] = reserved | |
1926 | * key2 [31:0] = TX/RX MIC key [63:32] | |
1927 | * key3 [31:0] = reserved | |
1928 | * key4 [31:0] = reserved | |
1929 | * | |
1930 | * Upper layer code will call this function separately | |
1931 | * for TX and RX keys when these registers offsets are | |
1932 | * used. | |
1933 | */ | |
f1dc5600 | 1934 | u32 mic0, mic2; |
f078f209 | 1935 | |
f1dc5600 S |
1936 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
1937 | mic2 = get_unaligned_le32(k->kv_mic + 4); | |
672903b3 JM |
1938 | |
1939 | /* Write MIC key[31:0] */ | |
f1dc5600 S |
1940 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
1941 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); | |
672903b3 JM |
1942 | |
1943 | /* Write MIC key[63:32] */ | |
f1dc5600 S |
1944 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
1945 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); | |
672903b3 JM |
1946 | |
1947 | /* Write TX[63:32] and keyType(reserved) */ | |
f1dc5600 S |
1948 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); |
1949 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), | |
1950 | AR_KEYTABLE_TYPE_CLR); | |
1951 | } | |
672903b3 JM |
1952 | |
1953 | /* MAC address registers are reserved for the MIC entry */ | |
f1dc5600 S |
1954 | REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); |
1955 | REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); | |
672903b3 JM |
1956 | |
1957 | /* | |
1958 | * Write the correct (un-inverted) key[47:0] last to enable | |
1959 | * TKIP now that all other registers are set with correct | |
1960 | * values. | |
1961 | */ | |
f1dc5600 S |
1962 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
1963 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); | |
1964 | } else { | |
672903b3 | 1965 | /* Write key[47:0] */ |
f1dc5600 S |
1966 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
1967 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); | |
672903b3 JM |
1968 | |
1969 | /* Write key[95:48] */ | |
f1dc5600 S |
1970 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
1971 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); | |
672903b3 JM |
1972 | |
1973 | /* Write key[127:96] and key type */ | |
f1dc5600 S |
1974 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
1975 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); | |
f078f209 | 1976 | |
672903b3 | 1977 | /* Write MAC address for the entry */ |
f1dc5600 S |
1978 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
1979 | } | |
f078f209 | 1980 | |
f078f209 LR |
1981 | return true; |
1982 | } | |
7322fd19 | 1983 | EXPORT_SYMBOL(ath9k_hw_set_keycache_entry); |
f078f209 | 1984 | |
cbe61d8a | 1985 | bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) |
f078f209 | 1986 | { |
2660b81a | 1987 | if (entry < ah->caps.keycache_size) { |
f1dc5600 S |
1988 | u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); |
1989 | if (val & AR_KEYTABLE_VALID) | |
1990 | return true; | |
1991 | } | |
1992 | return false; | |
f078f209 | 1993 | } |
7322fd19 | 1994 | EXPORT_SYMBOL(ath9k_hw_keyisvalid); |
f078f209 | 1995 | |
f1dc5600 S |
1996 | /******************************/ |
1997 | /* Power Management (Chipset) */ | |
1998 | /******************************/ | |
1999 | ||
42d5bc3f LR |
2000 | /* |
2001 | * Notify Power Mgt is disabled in self-generated frames. | |
2002 | * If requested, force chip to sleep. | |
2003 | */ | |
cbe61d8a | 2004 | static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 2005 | { |
f1dc5600 S |
2006 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
2007 | if (setChip) { | |
42d5bc3f LR |
2008 | /* |
2009 | * Clear the RTC force wake bit to allow the | |
2010 | * mac to go to sleep. | |
2011 | */ | |
f1dc5600 S |
2012 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
2013 | AR_RTC_FORCE_WAKE_EN); | |
42d5bc3f | 2014 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
f1dc5600 | 2015 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
f078f209 | 2016 | |
42d5bc3f | 2017 | /* Shutdown chip. Active low */ |
14b3af38 | 2018 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) |
4921be80 S |
2019 | REG_CLR_BIT(ah, (AR_RTC_RESET), |
2020 | AR_RTC_RESET_EN); | |
f1dc5600 | 2021 | } |
f078f209 LR |
2022 | } |
2023 | ||
bbd79af5 LR |
2024 | /* |
2025 | * Notify Power Management is enabled in self-generating | |
2026 | * frames. If request, set power mode of chip to | |
2027 | * auto/normal. Duration in units of 128us (1/8 TU). | |
2028 | */ | |
cbe61d8a | 2029 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 2030 | { |
f1dc5600 S |
2031 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
2032 | if (setChip) { | |
2660b81a | 2033 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 2034 | |
f1dc5600 | 2035 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
bbd79af5 | 2036 | /* Set WakeOnInterrupt bit; clear ForceWake bit */ |
f1dc5600 S |
2037 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
2038 | AR_RTC_FORCE_WAKE_ON_INT); | |
2039 | } else { | |
bbd79af5 LR |
2040 | /* |
2041 | * Clear the RTC force wake bit to allow the | |
2042 | * mac to go to sleep. | |
2043 | */ | |
f1dc5600 S |
2044 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
2045 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 2046 | } |
f078f209 | 2047 | } |
f078f209 LR |
2048 | } |
2049 | ||
cbe61d8a | 2050 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) |
f078f209 | 2051 | { |
f1dc5600 S |
2052 | u32 val; |
2053 | int i; | |
f078f209 | 2054 | |
f1dc5600 S |
2055 | if (setChip) { |
2056 | if ((REG_READ(ah, AR_RTC_STATUS) & | |
2057 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { | |
2058 | if (ath9k_hw_set_reset_reg(ah, | |
2059 | ATH9K_RESET_POWER_ON) != true) { | |
2060 | return false; | |
2061 | } | |
e041228f LR |
2062 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
2063 | ath9k_hw_init_pll(ah, NULL); | |
f1dc5600 S |
2064 | } |
2065 | if (AR_SREV_9100(ah)) | |
2066 | REG_SET_BIT(ah, AR_RTC_RESET, | |
2067 | AR_RTC_RESET_EN); | |
f078f209 | 2068 | |
f1dc5600 S |
2069 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
2070 | AR_RTC_FORCE_WAKE_EN); | |
2071 | udelay(50); | |
f078f209 | 2072 | |
f1dc5600 S |
2073 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
2074 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; | |
2075 | if (val == AR_RTC_STATUS_ON) | |
2076 | break; | |
2077 | udelay(50); | |
2078 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, | |
2079 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 2080 | } |
f1dc5600 | 2081 | if (i == 0) { |
c46917bb LR |
2082 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
2083 | "Failed to wakeup in %uus\n", | |
2084 | POWER_UP_TIME / 20); | |
f1dc5600 | 2085 | return false; |
f078f209 | 2086 | } |
f078f209 LR |
2087 | } |
2088 | ||
f1dc5600 | 2089 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
f078f209 | 2090 | |
f1dc5600 | 2091 | return true; |
f078f209 LR |
2092 | } |
2093 | ||
9ecdef4b | 2094 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
f078f209 | 2095 | { |
c46917bb | 2096 | struct ath_common *common = ath9k_hw_common(ah); |
cbe61d8a | 2097 | int status = true, setChip = true; |
f1dc5600 S |
2098 | static const char *modes[] = { |
2099 | "AWAKE", | |
2100 | "FULL-SLEEP", | |
2101 | "NETWORK SLEEP", | |
2102 | "UNDEFINED" | |
2103 | }; | |
f1dc5600 | 2104 | |
cbdec975 GJ |
2105 | if (ah->power_mode == mode) |
2106 | return status; | |
2107 | ||
c46917bb LR |
2108 | ath_print(common, ATH_DBG_RESET, "%s -> %s\n", |
2109 | modes[ah->power_mode], modes[mode]); | |
f1dc5600 S |
2110 | |
2111 | switch (mode) { | |
2112 | case ATH9K_PM_AWAKE: | |
2113 | status = ath9k_hw_set_power_awake(ah, setChip); | |
2114 | break; | |
2115 | case ATH9K_PM_FULL_SLEEP: | |
2116 | ath9k_set_power_sleep(ah, setChip); | |
2660b81a | 2117 | ah->chip_fullsleep = true; |
f1dc5600 S |
2118 | break; |
2119 | case ATH9K_PM_NETWORK_SLEEP: | |
2120 | ath9k_set_power_network_sleep(ah, setChip); | |
2121 | break; | |
f078f209 | 2122 | default: |
c46917bb LR |
2123 | ath_print(common, ATH_DBG_FATAL, |
2124 | "Unknown power mode %u\n", mode); | |
f078f209 LR |
2125 | return false; |
2126 | } | |
2660b81a | 2127 | ah->power_mode = mode; |
f1dc5600 S |
2128 | |
2129 | return status; | |
f078f209 | 2130 | } |
7322fd19 | 2131 | EXPORT_SYMBOL(ath9k_hw_setpower); |
f078f209 | 2132 | |
24c1a280 LR |
2133 | /* |
2134 | * Helper for ASPM support. | |
2135 | * | |
2136 | * Disable PLL when in L0s as well as receiver clock when in L1. | |
2137 | * This power saving option must be enabled through the SerDes. | |
2138 | * | |
2139 | * Programming the SerDes must go through the same 288 bit serial shift | |
2140 | * register as the other analog registers. Hence the 9 writes. | |
2141 | */ | |
d70357d5 LR |
2142 | static void ar9002_hw_configpcipowersave(struct ath_hw *ah, |
2143 | int restore, | |
2144 | int power_off) | |
f078f209 | 2145 | { |
f1dc5600 | 2146 | u8 i; |
93b1b37f | 2147 | u32 val; |
f078f209 | 2148 | |
2660b81a | 2149 | if (ah->is_pciexpress != true) |
f1dc5600 | 2150 | return; |
f078f209 | 2151 | |
24c1a280 | 2152 | /* Do not touch SerDes registers */ |
2660b81a | 2153 | if (ah->config.pcie_powersave_enable == 2) |
f1dc5600 S |
2154 | return; |
2155 | ||
24c1a280 | 2156 | /* Nothing to do on restore for 11N */ |
93b1b37f VN |
2157 | if (!restore) { |
2158 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
2159 | /* | |
2160 | * AR9280 2.0 or later chips use SerDes values from the | |
2161 | * initvals.h initialized depending on chipset during | |
d70357d5 | 2162 | * __ath9k_hw_init() |
93b1b37f VN |
2163 | */ |
2164 | for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { | |
2165 | REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), | |
2166 | INI_RA(&ah->iniPcieSerdes, i, 1)); | |
2167 | } | |
2168 | } else if (AR_SREV_9280(ah) && | |
2169 | (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) { | |
2170 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00); | |
2171 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
2172 | ||
2173 | /* RX shut off when elecidle is asserted */ | |
2174 | REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019); | |
2175 | REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820); | |
2176 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560); | |
2177 | ||
2178 | /* Shut off CLKREQ active in L1 */ | |
2179 | if (ah->config.pcie_clock_req) | |
2180 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc); | |
2181 | else | |
2182 | REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd); | |
f1dc5600 | 2183 | |
93b1b37f VN |
2184 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
2185 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
2186 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007); | |
f1dc5600 | 2187 | |
93b1b37f VN |
2188 | /* Load the new settings */ |
2189 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); | |
f1dc5600 | 2190 | |
93b1b37f VN |
2191 | } else { |
2192 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); | |
2193 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
f1dc5600 | 2194 | |
93b1b37f VN |
2195 | /* RX shut off when elecidle is asserted */ |
2196 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); | |
2197 | REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); | |
2198 | REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); | |
f1dc5600 | 2199 | |
93b1b37f VN |
2200 | /* |
2201 | * Ignore ah->ah_config.pcie_clock_req setting for | |
2202 | * pre-AR9280 11n | |
2203 | */ | |
2204 | REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); | |
24c1a280 | 2205 | |
93b1b37f VN |
2206 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
2207 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
2208 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); | |
24c1a280 | 2209 | |
93b1b37f VN |
2210 | /* Load the new settings */ |
2211 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); | |
2212 | } | |
24c1a280 | 2213 | |
93b1b37f | 2214 | udelay(1000); |
24c1a280 | 2215 | |
93b1b37f VN |
2216 | /* set bit 19 to allow forcing of pcie core into L1 state */ |
2217 | REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); | |
f078f209 | 2218 | |
93b1b37f VN |
2219 | /* Several PCIe massages to ensure proper behaviour */ |
2220 | if (ah->config.pcie_waen) { | |
2221 | val = ah->config.pcie_waen; | |
2222 | if (!power_off) | |
2223 | val &= (~AR_WA_D3_L1_DISABLE); | |
2224 | } else { | |
2225 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || | |
2226 | AR_SREV_9287(ah)) { | |
2227 | val = AR9285_WA_DEFAULT; | |
2228 | if (!power_off) | |
2229 | val &= (~AR_WA_D3_L1_DISABLE); | |
2230 | } else if (AR_SREV_9280(ah)) { | |
2231 | /* | |
2232 | * On AR9280 chips bit 22 of 0x4004 needs to be | |
2233 | * set otherwise card may disappear. | |
2234 | */ | |
2235 | val = AR9280_WA_DEFAULT; | |
2236 | if (!power_off) | |
2237 | val &= (~AR_WA_D3_L1_DISABLE); | |
2238 | } else | |
2239 | val = AR_WA_DEFAULT; | |
2240 | } | |
6d08b9b9 | 2241 | |
93b1b37f VN |
2242 | REG_WRITE(ah, AR_WA, val); |
2243 | } | |
f1dc5600 | 2244 | |
93b1b37f | 2245 | if (power_off) { |
24c1a280 | 2246 | /* |
93b1b37f VN |
2247 | * Set PCIe workaround bits |
2248 | * bit 14 in WA register (disable L1) should only | |
2249 | * be set when device enters D3 and be cleared | |
2250 | * when device comes back to D0. | |
24c1a280 | 2251 | */ |
93b1b37f VN |
2252 | if (ah->config.pcie_waen) { |
2253 | if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) | |
2254 | REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); | |
2255 | } else { | |
2256 | if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) || | |
2257 | AR_SREV_9287(ah)) && | |
2258 | (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) || | |
2259 | (AR_SREV_9280(ah) && | |
2260 | (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) { | |
2261 | REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE); | |
2262 | } | |
2263 | } | |
f1dc5600 | 2264 | } |
f078f209 LR |
2265 | } |
2266 | ||
f1dc5600 S |
2267 | /**********************/ |
2268 | /* Interrupt Handling */ | |
2269 | /**********************/ | |
2270 | ||
cbe61d8a | 2271 | bool ath9k_hw_intrpend(struct ath_hw *ah) |
f078f209 LR |
2272 | { |
2273 | u32 host_isr; | |
2274 | ||
2275 | if (AR_SREV_9100(ah)) | |
2276 | return true; | |
2277 | ||
2278 | host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); | |
2279 | if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS)) | |
2280 | return true; | |
2281 | ||
2282 | host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
2283 | if ((host_isr & AR_INTR_SYNC_DEFAULT) | |
2284 | && (host_isr != AR_INTR_SPURIOUS)) | |
2285 | return true; | |
2286 | ||
2287 | return false; | |
2288 | } | |
7322fd19 | 2289 | EXPORT_SYMBOL(ath9k_hw_intrpend); |
f078f209 | 2290 | |
cbe61d8a | 2291 | bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked) |
f078f209 LR |
2292 | { |
2293 | u32 isr = 0; | |
2294 | u32 mask2 = 0; | |
2660b81a | 2295 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 LR |
2296 | u32 sync_cause = 0; |
2297 | bool fatal_int = false; | |
c46917bb | 2298 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
2299 | |
2300 | if (!AR_SREV_9100(ah)) { | |
2301 | if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { | |
2302 | if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) | |
2303 | == AR_RTC_STATUS_ON) { | |
2304 | isr = REG_READ(ah, AR_ISR); | |
2305 | } | |
2306 | } | |
2307 | ||
f1dc5600 S |
2308 | sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & |
2309 | AR_INTR_SYNC_DEFAULT; | |
f078f209 LR |
2310 | |
2311 | *masked = 0; | |
2312 | ||
2313 | if (!isr && !sync_cause) | |
2314 | return false; | |
2315 | } else { | |
2316 | *masked = 0; | |
2317 | isr = REG_READ(ah, AR_ISR); | |
2318 | } | |
2319 | ||
2320 | if (isr) { | |
f078f209 LR |
2321 | if (isr & AR_ISR_BCNMISC) { |
2322 | u32 isr2; | |
2323 | isr2 = REG_READ(ah, AR_ISR_S2); | |
2324 | if (isr2 & AR_ISR_S2_TIM) | |
2325 | mask2 |= ATH9K_INT_TIM; | |
2326 | if (isr2 & AR_ISR_S2_DTIM) | |
2327 | mask2 |= ATH9K_INT_DTIM; | |
2328 | if (isr2 & AR_ISR_S2_DTIMSYNC) | |
2329 | mask2 |= ATH9K_INT_DTIMSYNC; | |
2330 | if (isr2 & (AR_ISR_S2_CABEND)) | |
2331 | mask2 |= ATH9K_INT_CABEND; | |
2332 | if (isr2 & AR_ISR_S2_GTT) | |
2333 | mask2 |= ATH9K_INT_GTT; | |
2334 | if (isr2 & AR_ISR_S2_CST) | |
2335 | mask2 |= ATH9K_INT_CST; | |
4af9cf4f S |
2336 | if (isr2 & AR_ISR_S2_TSFOOR) |
2337 | mask2 |= ATH9K_INT_TSFOOR; | |
f078f209 LR |
2338 | } |
2339 | ||
2340 | isr = REG_READ(ah, AR_ISR_RAC); | |
2341 | if (isr == 0xffffffff) { | |
2342 | *masked = 0; | |
2343 | return false; | |
2344 | } | |
2345 | ||
2346 | *masked = isr & ATH9K_INT_COMMON; | |
2347 | ||
0ce024cb | 2348 | if (ah->config.rx_intr_mitigation) { |
f078f209 LR |
2349 | if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) |
2350 | *masked |= ATH9K_INT_RX; | |
2351 | } | |
2352 | ||
2353 | if (isr & (AR_ISR_RXOK | AR_ISR_RXERR)) | |
2354 | *masked |= ATH9K_INT_RX; | |
2355 | if (isr & | |
2356 | (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR | | |
2357 | AR_ISR_TXEOL)) { | |
2358 | u32 s0_s, s1_s; | |
2359 | ||
2360 | *masked |= ATH9K_INT_TX; | |
2361 | ||
2362 | s0_s = REG_READ(ah, AR_ISR_S0_S); | |
2660b81a S |
2363 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK); |
2364 | ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); | |
f078f209 LR |
2365 | |
2366 | s1_s = REG_READ(ah, AR_ISR_S1_S); | |
2660b81a S |
2367 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); |
2368 | ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); | |
f078f209 LR |
2369 | } |
2370 | ||
2371 | if (isr & AR_ISR_RXORN) { | |
c46917bb LR |
2372 | ath_print(common, ATH_DBG_INTERRUPT, |
2373 | "receive FIFO overrun interrupt\n"); | |
f078f209 LR |
2374 | } |
2375 | ||
2376 | if (!AR_SREV_9100(ah)) { | |
60b67f51 | 2377 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
f078f209 LR |
2378 | u32 isr5 = REG_READ(ah, AR_ISR_S5_S); |
2379 | if (isr5 & AR_ISR_S5_TIM_TIMER) | |
2380 | *masked |= ATH9K_INT_TIM_TIMER; | |
2381 | } | |
2382 | } | |
2383 | ||
2384 | *masked |= mask2; | |
2385 | } | |
f1dc5600 | 2386 | |
f078f209 LR |
2387 | if (AR_SREV_9100(ah)) |
2388 | return true; | |
f1dc5600 | 2389 | |
ff155a45 VT |
2390 | if (isr & AR_ISR_GENTMR) { |
2391 | u32 s5_s; | |
2392 | ||
2393 | s5_s = REG_READ(ah, AR_ISR_S5_S); | |
2394 | if (isr & AR_ISR_GENTMR) { | |
2395 | ah->intr_gen_timer_trigger = | |
2396 | MS(s5_s, AR_ISR_S5_GENTIMER_TRIG); | |
2397 | ||
2398 | ah->intr_gen_timer_thresh = | |
2399 | MS(s5_s, AR_ISR_S5_GENTIMER_THRESH); | |
2400 | ||
2401 | if (ah->intr_gen_timer_trigger) | |
2402 | *masked |= ATH9K_INT_GENTIMER; | |
2403 | ||
2404 | } | |
2405 | } | |
2406 | ||
f078f209 LR |
2407 | if (sync_cause) { |
2408 | fatal_int = | |
2409 | (sync_cause & | |
2410 | (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR)) | |
2411 | ? true : false; | |
2412 | ||
2413 | if (fatal_int) { | |
2414 | if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { | |
c46917bb LR |
2415 | ath_print(common, ATH_DBG_ANY, |
2416 | "received PCI FATAL interrupt\n"); | |
f078f209 LR |
2417 | } |
2418 | if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { | |
c46917bb LR |
2419 | ath_print(common, ATH_DBG_ANY, |
2420 | "received PCI PERR interrupt\n"); | |
f078f209 | 2421 | } |
a89bff9a | 2422 | *masked |= ATH9K_INT_FATAL; |
f078f209 LR |
2423 | } |
2424 | if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { | |
c46917bb LR |
2425 | ath_print(common, ATH_DBG_INTERRUPT, |
2426 | "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); | |
f078f209 LR |
2427 | REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); |
2428 | REG_WRITE(ah, AR_RC, 0); | |
2429 | *masked |= ATH9K_INT_FATAL; | |
2430 | } | |
2431 | if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { | |
c46917bb LR |
2432 | ath_print(common, ATH_DBG_INTERRUPT, |
2433 | "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); | |
f078f209 LR |
2434 | } |
2435 | ||
2436 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause); | |
2437 | (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); | |
2438 | } | |
f1dc5600 | 2439 | |
f078f209 LR |
2440 | return true; |
2441 | } | |
7322fd19 | 2442 | EXPORT_SYMBOL(ath9k_hw_getisr); |
f078f209 | 2443 | |
cbe61d8a | 2444 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints) |
f078f209 | 2445 | { |
152d530d | 2446 | enum ath9k_int omask = ah->imask; |
f078f209 | 2447 | u32 mask, mask2; |
2660b81a | 2448 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
c46917bb | 2449 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 2450 | |
c46917bb | 2451 | ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); |
f078f209 LR |
2452 | |
2453 | if (omask & ATH9K_INT_GLOBAL) { | |
c46917bb | 2454 | ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n"); |
f078f209 LR |
2455 | REG_WRITE(ah, AR_IER, AR_IER_DISABLE); |
2456 | (void) REG_READ(ah, AR_IER); | |
2457 | if (!AR_SREV_9100(ah)) { | |
2458 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0); | |
2459 | (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); | |
2460 | ||
2461 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); | |
2462 | (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); | |
2463 | } | |
2464 | } | |
2465 | ||
2466 | mask = ints & ATH9K_INT_COMMON; | |
2467 | mask2 = 0; | |
2468 | ||
2469 | if (ints & ATH9K_INT_TX) { | |
2660b81a | 2470 | if (ah->txok_interrupt_mask) |
f078f209 | 2471 | mask |= AR_IMR_TXOK; |
2660b81a | 2472 | if (ah->txdesc_interrupt_mask) |
f078f209 | 2473 | mask |= AR_IMR_TXDESC; |
2660b81a | 2474 | if (ah->txerr_interrupt_mask) |
f078f209 | 2475 | mask |= AR_IMR_TXERR; |
2660b81a | 2476 | if (ah->txeol_interrupt_mask) |
f078f209 LR |
2477 | mask |= AR_IMR_TXEOL; |
2478 | } | |
2479 | if (ints & ATH9K_INT_RX) { | |
2480 | mask |= AR_IMR_RXERR; | |
0ce024cb | 2481 | if (ah->config.rx_intr_mitigation) |
f078f209 LR |
2482 | mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM; |
2483 | else | |
2484 | mask |= AR_IMR_RXOK | AR_IMR_RXDESC; | |
60b67f51 | 2485 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
f078f209 LR |
2486 | mask |= AR_IMR_GENTMR; |
2487 | } | |
2488 | ||
2489 | if (ints & (ATH9K_INT_BMISC)) { | |
2490 | mask |= AR_IMR_BCNMISC; | |
2491 | if (ints & ATH9K_INT_TIM) | |
2492 | mask2 |= AR_IMR_S2_TIM; | |
2493 | if (ints & ATH9K_INT_DTIM) | |
2494 | mask2 |= AR_IMR_S2_DTIM; | |
2495 | if (ints & ATH9K_INT_DTIMSYNC) | |
2496 | mask2 |= AR_IMR_S2_DTIMSYNC; | |
2497 | if (ints & ATH9K_INT_CABEND) | |
4af9cf4f S |
2498 | mask2 |= AR_IMR_S2_CABEND; |
2499 | if (ints & ATH9K_INT_TSFOOR) | |
2500 | mask2 |= AR_IMR_S2_TSFOOR; | |
f078f209 LR |
2501 | } |
2502 | ||
2503 | if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) { | |
2504 | mask |= AR_IMR_BCNMISC; | |
2505 | if (ints & ATH9K_INT_GTT) | |
2506 | mask2 |= AR_IMR_S2_GTT; | |
2507 | if (ints & ATH9K_INT_CST) | |
2508 | mask2 |= AR_IMR_S2_CST; | |
2509 | } | |
2510 | ||
c46917bb | 2511 | ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); |
f078f209 | 2512 | REG_WRITE(ah, AR_IMR, mask); |
74bad5cb PR |
2513 | ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | |
2514 | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | | |
2515 | AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST); | |
2516 | ah->imrs2_reg |= mask2; | |
2517 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); | |
f078f209 | 2518 | |
60b67f51 | 2519 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
f078f209 LR |
2520 | if (ints & ATH9K_INT_TIM_TIMER) |
2521 | REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); | |
2522 | else | |
2523 | REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER); | |
2524 | } | |
2525 | ||
2526 | if (ints & ATH9K_INT_GLOBAL) { | |
c46917bb | 2527 | ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n"); |
f078f209 LR |
2528 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); |
2529 | if (!AR_SREV_9100(ah)) { | |
2530 | REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, | |
2531 | AR_INTR_MAC_IRQ); | |
2532 | REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); | |
2533 | ||
2534 | ||
2535 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, | |
2536 | AR_INTR_SYNC_DEFAULT); | |
2537 | REG_WRITE(ah, AR_INTR_SYNC_MASK, | |
2538 | AR_INTR_SYNC_DEFAULT); | |
2539 | } | |
c46917bb LR |
2540 | ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", |
2541 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); | |
f078f209 LR |
2542 | } |
2543 | ||
2544 | return omask; | |
2545 | } | |
7322fd19 | 2546 | EXPORT_SYMBOL(ath9k_hw_set_interrupts); |
f078f209 | 2547 | |
f1dc5600 S |
2548 | /*******************/ |
2549 | /* Beacon Handling */ | |
2550 | /*******************/ | |
2551 | ||
cbe61d8a | 2552 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
f078f209 | 2553 | { |
f078f209 LR |
2554 | int flags = 0; |
2555 | ||
2660b81a | 2556 | ah->beacon_interval = beacon_period; |
f078f209 | 2557 | |
2660b81a | 2558 | switch (ah->opmode) { |
d97809db CM |
2559 | case NL80211_IFTYPE_STATION: |
2560 | case NL80211_IFTYPE_MONITOR: | |
f078f209 LR |
2561 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
2562 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); | |
2563 | REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); | |
2564 | flags |= AR_TBTT_TIMER_EN; | |
2565 | break; | |
d97809db | 2566 | case NL80211_IFTYPE_ADHOC: |
9cb5412b | 2567 | case NL80211_IFTYPE_MESH_POINT: |
f078f209 LR |
2568 | REG_SET_BIT(ah, AR_TXCFG, |
2569 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); | |
2570 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, | |
2571 | TU_TO_USEC(next_beacon + | |
2660b81a S |
2572 | (ah->atim_window ? ah-> |
2573 | atim_window : 1))); | |
f078f209 | 2574 | flags |= AR_NDP_TIMER_EN; |
d97809db | 2575 | case NL80211_IFTYPE_AP: |
f078f209 LR |
2576 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
2577 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, | |
2578 | TU_TO_USEC(next_beacon - | |
2660b81a | 2579 | ah->config. |
60b67f51 | 2580 | dma_beacon_response_time)); |
f078f209 LR |
2581 | REG_WRITE(ah, AR_NEXT_SWBA, |
2582 | TU_TO_USEC(next_beacon - | |
2660b81a | 2583 | ah->config. |
60b67f51 | 2584 | sw_beacon_response_time)); |
f078f209 LR |
2585 | flags |= |
2586 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; | |
2587 | break; | |
d97809db | 2588 | default: |
c46917bb LR |
2589 | ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, |
2590 | "%s: unsupported opmode: %d\n", | |
2591 | __func__, ah->opmode); | |
d97809db CM |
2592 | return; |
2593 | break; | |
f078f209 LR |
2594 | } |
2595 | ||
2596 | REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
2597 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
2598 | REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); | |
2599 | REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); | |
2600 | ||
2601 | beacon_period &= ~ATH9K_BEACON_ENA; | |
2602 | if (beacon_period & ATH9K_BEACON_RESET_TSF) { | |
f078f209 LR |
2603 | ath9k_hw_reset_tsf(ah); |
2604 | } | |
2605 | ||
2606 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); | |
2607 | } | |
7322fd19 | 2608 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
f078f209 | 2609 | |
cbe61d8a | 2610 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
f1dc5600 | 2611 | const struct ath9k_beacon_state *bs) |
f078f209 LR |
2612 | { |
2613 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; | |
2660b81a | 2614 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
c46917bb | 2615 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
2616 | |
2617 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); | |
2618 | ||
2619 | REG_WRITE(ah, AR_BEACON_PERIOD, | |
2620 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
2621 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, | |
2622 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
2623 | ||
2624 | REG_RMW_FIELD(ah, AR_RSSI_THR, | |
2625 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); | |
2626 | ||
2627 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; | |
2628 | ||
2629 | if (bs->bs_sleepduration > beaconintval) | |
2630 | beaconintval = bs->bs_sleepduration; | |
2631 | ||
2632 | dtimperiod = bs->bs_dtimperiod; | |
2633 | if (bs->bs_sleepduration > dtimperiod) | |
2634 | dtimperiod = bs->bs_sleepduration; | |
2635 | ||
2636 | if (beaconintval == dtimperiod) | |
2637 | nextTbtt = bs->bs_nextdtim; | |
2638 | else | |
2639 | nextTbtt = bs->bs_nexttbtt; | |
2640 | ||
c46917bb LR |
2641 | ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
2642 | ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); | |
2643 | ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); | |
2644 | ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); | |
f078f209 | 2645 | |
f1dc5600 S |
2646 | REG_WRITE(ah, AR_NEXT_DTIM, |
2647 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); | |
2648 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); | |
f078f209 | 2649 | |
f1dc5600 S |
2650 | REG_WRITE(ah, AR_SLEEP1, |
2651 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) | |
2652 | | AR_SLEEP1_ASSUME_DTIM); | |
f078f209 | 2653 | |
f1dc5600 S |
2654 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
2655 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); | |
2656 | else | |
2657 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; | |
f078f209 | 2658 | |
f1dc5600 S |
2659 | REG_WRITE(ah, AR_SLEEP2, |
2660 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); | |
f078f209 | 2661 | |
f1dc5600 S |
2662 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
2663 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); | |
f078f209 | 2664 | |
f1dc5600 S |
2665 | REG_SET_BIT(ah, AR_TIMER_MODE, |
2666 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | | |
2667 | AR_DTIM_TIMER_EN); | |
f078f209 | 2668 | |
4af9cf4f S |
2669 | /* TSF Out of Range Threshold */ |
2670 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); | |
f078f209 | 2671 | } |
7322fd19 | 2672 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
f078f209 | 2673 | |
f1dc5600 S |
2674 | /*******************/ |
2675 | /* HW Capabilities */ | |
2676 | /*******************/ | |
2677 | ||
a9a29ce6 | 2678 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
f078f209 | 2679 | { |
2660b81a | 2680 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
608b88cb | 2681 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
c46917bb | 2682 | struct ath_common *common = ath9k_hw_common(ah); |
766ec4a9 | 2683 | struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; |
608b88cb | 2684 | |
f1dc5600 | 2685 | u16 capField = 0, eeval; |
f078f209 | 2686 | |
f74df6fb | 2687 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
608b88cb | 2688 | regulatory->current_rd = eeval; |
f078f209 | 2689 | |
f74df6fb | 2690 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); |
fec0de11 S |
2691 | if (AR_SREV_9285_10_OR_LATER(ah)) |
2692 | eeval |= AR9285_RDEXT_DEFAULT; | |
608b88cb | 2693 | regulatory->current_rd_ext = eeval; |
f078f209 | 2694 | |
f74df6fb | 2695 | capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); |
f1dc5600 | 2696 | |
2660b81a | 2697 | if (ah->opmode != NL80211_IFTYPE_AP && |
d535a42a | 2698 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
608b88cb LR |
2699 | if (regulatory->current_rd == 0x64 || |
2700 | regulatory->current_rd == 0x65) | |
2701 | regulatory->current_rd += 5; | |
2702 | else if (regulatory->current_rd == 0x41) | |
2703 | regulatory->current_rd = 0x43; | |
c46917bb LR |
2704 | ath_print(common, ATH_DBG_REGULATORY, |
2705 | "regdomain mapped to 0x%x\n", regulatory->current_rd); | |
f1dc5600 | 2706 | } |
f078f209 | 2707 | |
f74df6fb | 2708 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
a9a29ce6 GJ |
2709 | if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { |
2710 | ath_print(common, ATH_DBG_FATAL, | |
2711 | "no band has been marked as supported in EEPROM.\n"); | |
2712 | return -EINVAL; | |
2713 | } | |
2714 | ||
f1dc5600 | 2715 | bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); |
f078f209 | 2716 | |
f1dc5600 S |
2717 | if (eeval & AR5416_OPFLAGS_11A) { |
2718 | set_bit(ATH9K_MODE_11A, pCap->wireless_modes); | |
2660b81a | 2719 | if (ah->config.ht_enable) { |
f1dc5600 S |
2720 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) |
2721 | set_bit(ATH9K_MODE_11NA_HT20, | |
2722 | pCap->wireless_modes); | |
2723 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { | |
2724 | set_bit(ATH9K_MODE_11NA_HT40PLUS, | |
2725 | pCap->wireless_modes); | |
2726 | set_bit(ATH9K_MODE_11NA_HT40MINUS, | |
2727 | pCap->wireless_modes); | |
2728 | } | |
f078f209 | 2729 | } |
f078f209 LR |
2730 | } |
2731 | ||
f1dc5600 | 2732 | if (eeval & AR5416_OPFLAGS_11G) { |
f1dc5600 | 2733 | set_bit(ATH9K_MODE_11G, pCap->wireless_modes); |
2660b81a | 2734 | if (ah->config.ht_enable) { |
f1dc5600 S |
2735 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) |
2736 | set_bit(ATH9K_MODE_11NG_HT20, | |
2737 | pCap->wireless_modes); | |
2738 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { | |
2739 | set_bit(ATH9K_MODE_11NG_HT40PLUS, | |
2740 | pCap->wireless_modes); | |
2741 | set_bit(ATH9K_MODE_11NG_HT40MINUS, | |
2742 | pCap->wireless_modes); | |
2743 | } | |
2744 | } | |
f078f209 | 2745 | } |
f1dc5600 | 2746 | |
f74df6fb | 2747 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
d7e7d229 LR |
2748 | /* |
2749 | * For AR9271 we will temporarilly uses the rx chainmax as read from | |
2750 | * the EEPROM. | |
2751 | */ | |
8147f5de | 2752 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
d7e7d229 LR |
2753 | !(eeval & AR5416_OPFLAGS_11A) && |
2754 | !(AR_SREV_9271(ah))) | |
2755 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ | |
8147f5de S |
2756 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
2757 | else | |
d7e7d229 | 2758 | /* Use rx_chainmask from EEPROM. */ |
8147f5de | 2759 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
f078f209 | 2760 | |
d535a42a | 2761 | if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) |
2660b81a | 2762 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
f078f209 | 2763 | |
f1dc5600 S |
2764 | pCap->low_2ghz_chan = 2312; |
2765 | pCap->high_2ghz_chan = 2732; | |
f078f209 | 2766 | |
f1dc5600 S |
2767 | pCap->low_5ghz_chan = 4920; |
2768 | pCap->high_5ghz_chan = 6100; | |
f078f209 | 2769 | |
f1dc5600 S |
2770 | pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; |
2771 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; | |
2772 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; | |
f078f209 | 2773 | |
f1dc5600 S |
2774 | pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; |
2775 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; | |
2776 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; | |
f078f209 | 2777 | |
2660b81a | 2778 | if (ah->config.ht_enable) |
f1dc5600 S |
2779 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
2780 | else | |
2781 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; | |
f078f209 | 2782 | |
f1dc5600 S |
2783 | pCap->hw_caps |= ATH9K_HW_CAP_GTT; |
2784 | pCap->hw_caps |= ATH9K_HW_CAP_VEOL; | |
2785 | pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; | |
2786 | pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; | |
f078f209 | 2787 | |
f1dc5600 S |
2788 | if (capField & AR_EEPROM_EEPCAP_MAXQCU) |
2789 | pCap->total_queues = | |
2790 | MS(capField, AR_EEPROM_EEPCAP_MAXQCU); | |
2791 | else | |
2792 | pCap->total_queues = ATH9K_NUM_TX_QUEUES; | |
f078f209 | 2793 | |
f1dc5600 S |
2794 | if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) |
2795 | pCap->keycache_size = | |
2796 | 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); | |
2797 | else | |
2798 | pCap->keycache_size = AR_KEYTABLE_SIZE; | |
f078f209 | 2799 | |
f1dc5600 | 2800 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; |
f4709fdf LR |
2801 | |
2802 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) | |
2803 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; | |
2804 | else | |
2805 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; | |
f078f209 | 2806 | |
5b5fa355 S |
2807 | if (AR_SREV_9271(ah)) |
2808 | pCap->num_gpio_pins = AR9271_NUM_GPIO; | |
2809 | else if (AR_SREV_9285_10_OR_LATER(ah)) | |
cb33c412 SB |
2810 | pCap->num_gpio_pins = AR9285_NUM_GPIO; |
2811 | else if (AR_SREV_9280_10_OR_LATER(ah)) | |
f1dc5600 S |
2812 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
2813 | else | |
2814 | pCap->num_gpio_pins = AR_NUM_GPIO; | |
f078f209 | 2815 | |
f1dc5600 S |
2816 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
2817 | pCap->hw_caps |= ATH9K_HW_CAP_CST; | |
2818 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; | |
2819 | } else { | |
2820 | pCap->rts_aggr_limit = (8 * 1024); | |
f078f209 LR |
2821 | } |
2822 | ||
f1dc5600 S |
2823 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; |
2824 | ||
e97275cb | 2825 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
2660b81a S |
2826 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
2827 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { | |
2828 | ah->rfkill_gpio = | |
2829 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); | |
2830 | ah->rfkill_polarity = | |
2831 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); | |
f1dc5600 S |
2832 | |
2833 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; | |
f078f209 | 2834 | } |
f1dc5600 | 2835 | #endif |
bde748a4 VN |
2836 | if (AR_SREV_9271(ah)) |
2837 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; | |
2838 | else | |
2839 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; | |
f078f209 | 2840 | |
e7594072 | 2841 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
f1dc5600 S |
2842 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
2843 | else | |
2844 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; | |
f078f209 | 2845 | |
608b88cb | 2846 | if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { |
f1dc5600 S |
2847 | pCap->reg_cap = |
2848 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
2849 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | | |
2850 | AR_EEPROM_EEREGCAP_EN_KK_U2 | | |
2851 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; | |
f078f209 | 2852 | } else { |
f1dc5600 S |
2853 | pCap->reg_cap = |
2854 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
2855 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; | |
f078f209 | 2856 | } |
f078f209 | 2857 | |
ebb90cfc SB |
2858 | /* Advertise midband for AR5416 with FCC midband set in eeprom */ |
2859 | if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && | |
2860 | AR_SREV_5416(ah)) | |
2861 | pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; | |
f1dc5600 S |
2862 | |
2863 | pCap->num_antcfg_5ghz = | |
f74df6fb | 2864 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); |
f1dc5600 | 2865 | pCap->num_antcfg_2ghz = |
f74df6fb | 2866 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); |
f078f209 | 2867 | |
fe12946e | 2868 | if (AR_SREV_9280_10_OR_LATER(ah) && |
a36cfbca | 2869 | ath9k_hw_btcoex_supported(ah)) { |
766ec4a9 LR |
2870 | btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; |
2871 | btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; | |
22f25d0d | 2872 | |
8c8f9ba7 | 2873 | if (AR_SREV_9285(ah)) { |
766ec4a9 LR |
2874 | btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; |
2875 | btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; | |
8c8f9ba7 | 2876 | } else { |
766ec4a9 | 2877 | btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; |
8c8f9ba7 | 2878 | } |
22f25d0d | 2879 | } else { |
766ec4a9 | 2880 | btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; |
c97c92d9 | 2881 | } |
a9a29ce6 | 2882 | |
ceb26445 | 2883 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1adf02ff | 2884 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA; |
ceb26445 VT |
2885 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; |
2886 | pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; | |
2887 | pCap->rx_status_len = sizeof(struct ar9003_rxs); | |
2888 | } | |
1adf02ff | 2889 | |
a9a29ce6 | 2890 | return 0; |
f078f209 LR |
2891 | } |
2892 | ||
cbe61d8a | 2893 | bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
f1dc5600 | 2894 | u32 capability, u32 *result) |
f078f209 | 2895 | { |
608b88cb | 2896 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
f1dc5600 S |
2897 | switch (type) { |
2898 | case ATH9K_CAP_CIPHER: | |
2899 | switch (capability) { | |
2900 | case ATH9K_CIPHER_AES_CCM: | |
2901 | case ATH9K_CIPHER_AES_OCB: | |
2902 | case ATH9K_CIPHER_TKIP: | |
2903 | case ATH9K_CIPHER_WEP: | |
2904 | case ATH9K_CIPHER_MIC: | |
2905 | case ATH9K_CIPHER_CLR: | |
2906 | return true; | |
2907 | default: | |
2908 | return false; | |
2909 | } | |
2910 | case ATH9K_CAP_TKIP_MIC: | |
2911 | switch (capability) { | |
2912 | case 0: | |
2913 | return true; | |
2914 | case 1: | |
2660b81a | 2915 | return (ah->sta_id1_defaults & |
f1dc5600 S |
2916 | AR_STA_ID1_CRPT_MIC_ENABLE) ? true : |
2917 | false; | |
2918 | } | |
2919 | case ATH9K_CAP_TKIP_SPLIT: | |
2660b81a | 2920 | return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? |
f1dc5600 | 2921 | false : true; |
f1dc5600 S |
2922 | case ATH9K_CAP_MCAST_KEYSRCH: |
2923 | switch (capability) { | |
2924 | case 0: | |
2925 | return true; | |
2926 | case 1: | |
2927 | if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { | |
2928 | return false; | |
2929 | } else { | |
2660b81a | 2930 | return (ah->sta_id1_defaults & |
f1dc5600 S |
2931 | AR_STA_ID1_MCAST_KSRCH) ? true : |
2932 | false; | |
2933 | } | |
2934 | } | |
2935 | return false; | |
f1dc5600 S |
2936 | case ATH9K_CAP_TXPOW: |
2937 | switch (capability) { | |
2938 | case 0: | |
2939 | return 0; | |
2940 | case 1: | |
608b88cb | 2941 | *result = regulatory->power_limit; |
f1dc5600 S |
2942 | return 0; |
2943 | case 2: | |
608b88cb | 2944 | *result = regulatory->max_power_level; |
f1dc5600 S |
2945 | return 0; |
2946 | case 3: | |
608b88cb | 2947 | *result = regulatory->tp_scale; |
f1dc5600 S |
2948 | return 0; |
2949 | } | |
2950 | return false; | |
8bd1d07f SB |
2951 | case ATH9K_CAP_DS: |
2952 | return (AR_SREV_9280_20_OR_LATER(ah) && | |
2953 | (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) | |
2954 | ? false : true; | |
f1dc5600 S |
2955 | default: |
2956 | return false; | |
f078f209 | 2957 | } |
f078f209 | 2958 | } |
7322fd19 | 2959 | EXPORT_SYMBOL(ath9k_hw_getcapability); |
f078f209 | 2960 | |
cbe61d8a | 2961 | bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
f1dc5600 | 2962 | u32 capability, u32 setting, int *status) |
f078f209 | 2963 | { |
f1dc5600 S |
2964 | switch (type) { |
2965 | case ATH9K_CAP_TKIP_MIC: | |
2966 | if (setting) | |
2660b81a | 2967 | ah->sta_id1_defaults |= |
f1dc5600 S |
2968 | AR_STA_ID1_CRPT_MIC_ENABLE; |
2969 | else | |
2660b81a | 2970 | ah->sta_id1_defaults &= |
f1dc5600 S |
2971 | ~AR_STA_ID1_CRPT_MIC_ENABLE; |
2972 | return true; | |
f1dc5600 S |
2973 | case ATH9K_CAP_MCAST_KEYSRCH: |
2974 | if (setting) | |
2660b81a | 2975 | ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; |
f1dc5600 | 2976 | else |
2660b81a | 2977 | ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; |
f1dc5600 | 2978 | return true; |
f1dc5600 S |
2979 | default: |
2980 | return false; | |
f078f209 LR |
2981 | } |
2982 | } | |
7322fd19 | 2983 | EXPORT_SYMBOL(ath9k_hw_setcapability); |
f078f209 | 2984 | |
f1dc5600 S |
2985 | /****************************/ |
2986 | /* GPIO / RFKILL / Antennae */ | |
2987 | /****************************/ | |
f078f209 | 2988 | |
cbe61d8a | 2989 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
f1dc5600 S |
2990 | u32 gpio, u32 type) |
2991 | { | |
2992 | int addr; | |
2993 | u32 gpio_shift, tmp; | |
f078f209 | 2994 | |
f1dc5600 S |
2995 | if (gpio > 11) |
2996 | addr = AR_GPIO_OUTPUT_MUX3; | |
2997 | else if (gpio > 5) | |
2998 | addr = AR_GPIO_OUTPUT_MUX2; | |
2999 | else | |
3000 | addr = AR_GPIO_OUTPUT_MUX1; | |
f078f209 | 3001 | |
f1dc5600 | 3002 | gpio_shift = (gpio % 6) * 5; |
f078f209 | 3003 | |
f1dc5600 S |
3004 | if (AR_SREV_9280_20_OR_LATER(ah) |
3005 | || (addr != AR_GPIO_OUTPUT_MUX1)) { | |
3006 | REG_RMW(ah, addr, (type << gpio_shift), | |
3007 | (0x1f << gpio_shift)); | |
f078f209 | 3008 | } else { |
f1dc5600 S |
3009 | tmp = REG_READ(ah, addr); |
3010 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); | |
3011 | tmp &= ~(0x1f << gpio_shift); | |
3012 | tmp |= (type << gpio_shift); | |
3013 | REG_WRITE(ah, addr, tmp); | |
f078f209 | 3014 | } |
f078f209 LR |
3015 | } |
3016 | ||
cbe61d8a | 3017 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
f078f209 | 3018 | { |
f1dc5600 | 3019 | u32 gpio_shift; |
f078f209 | 3020 | |
9680e8a3 | 3021 | BUG_ON(gpio >= ah->caps.num_gpio_pins); |
f078f209 | 3022 | |
f1dc5600 | 3023 | gpio_shift = gpio << 1; |
f078f209 | 3024 | |
f1dc5600 S |
3025 | REG_RMW(ah, |
3026 | AR_GPIO_OE_OUT, | |
3027 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), | |
3028 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 3029 | } |
7322fd19 | 3030 | EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); |
f078f209 | 3031 | |
cbe61d8a | 3032 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
f078f209 | 3033 | { |
cb33c412 SB |
3034 | #define MS_REG_READ(x, y) \ |
3035 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) | |
3036 | ||
2660b81a | 3037 | if (gpio >= ah->caps.num_gpio_pins) |
f1dc5600 | 3038 | return 0xffffffff; |
f078f209 | 3039 | |
783dfca1 FF |
3040 | if (AR_SREV_9300_20_OR_LATER(ah)) |
3041 | return MS_REG_READ(AR9300, gpio) != 0; | |
3042 | else if (AR_SREV_9271(ah)) | |
5b5fa355 S |
3043 | return MS_REG_READ(AR9271, gpio) != 0; |
3044 | else if (AR_SREV_9287_10_OR_LATER(ah)) | |
ac88b6ec VN |
3045 | return MS_REG_READ(AR9287, gpio) != 0; |
3046 | else if (AR_SREV_9285_10_OR_LATER(ah)) | |
cb33c412 SB |
3047 | return MS_REG_READ(AR9285, gpio) != 0; |
3048 | else if (AR_SREV_9280_10_OR_LATER(ah)) | |
3049 | return MS_REG_READ(AR928X, gpio) != 0; | |
3050 | else | |
3051 | return MS_REG_READ(AR, gpio) != 0; | |
f078f209 | 3052 | } |
7322fd19 | 3053 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
f078f209 | 3054 | |
cbe61d8a | 3055 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
f1dc5600 | 3056 | u32 ah_signal_type) |
f078f209 | 3057 | { |
f1dc5600 | 3058 | u32 gpio_shift; |
f078f209 | 3059 | |
f1dc5600 | 3060 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
f078f209 | 3061 | |
f1dc5600 | 3062 | gpio_shift = 2 * gpio; |
f078f209 | 3063 | |
f1dc5600 S |
3064 | REG_RMW(ah, |
3065 | AR_GPIO_OE_OUT, | |
3066 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), | |
3067 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 3068 | } |
7322fd19 | 3069 | EXPORT_SYMBOL(ath9k_hw_cfg_output); |
f078f209 | 3070 | |
cbe61d8a | 3071 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
f078f209 | 3072 | { |
5b5fa355 S |
3073 | if (AR_SREV_9271(ah)) |
3074 | val = ~val; | |
3075 | ||
f1dc5600 S |
3076 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
3077 | AR_GPIO_BIT(gpio)); | |
f078f209 | 3078 | } |
7322fd19 | 3079 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
f078f209 | 3080 | |
cbe61d8a | 3081 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah) |
f078f209 | 3082 | { |
f1dc5600 | 3083 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
f078f209 | 3084 | } |
7322fd19 | 3085 | EXPORT_SYMBOL(ath9k_hw_getdefantenna); |
f078f209 | 3086 | |
cbe61d8a | 3087 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
f078f209 | 3088 | { |
f1dc5600 | 3089 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
f078f209 | 3090 | } |
7322fd19 | 3091 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
f078f209 | 3092 | |
f1dc5600 S |
3093 | /*********************/ |
3094 | /* General Operation */ | |
3095 | /*********************/ | |
3096 | ||
cbe61d8a | 3097 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
f078f209 | 3098 | { |
f1dc5600 S |
3099 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
3100 | u32 phybits = REG_READ(ah, AR_PHY_ERR); | |
f078f209 | 3101 | |
f1dc5600 S |
3102 | if (phybits & AR_PHY_ERR_RADAR) |
3103 | bits |= ATH9K_RX_FILTER_PHYRADAR; | |
3104 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) | |
3105 | bits |= ATH9K_RX_FILTER_PHYERR; | |
dc2222a8 | 3106 | |
f1dc5600 | 3107 | return bits; |
f078f209 | 3108 | } |
7322fd19 | 3109 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
f078f209 | 3110 | |
cbe61d8a | 3111 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
f078f209 | 3112 | { |
f1dc5600 | 3113 | u32 phybits; |
f078f209 | 3114 | |
7ea310be S |
3115 | REG_WRITE(ah, AR_RX_FILTER, bits); |
3116 | ||
f1dc5600 S |
3117 | phybits = 0; |
3118 | if (bits & ATH9K_RX_FILTER_PHYRADAR) | |
3119 | phybits |= AR_PHY_ERR_RADAR; | |
3120 | if (bits & ATH9K_RX_FILTER_PHYERR) | |
3121 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; | |
3122 | REG_WRITE(ah, AR_PHY_ERR, phybits); | |
f078f209 | 3123 | |
f1dc5600 S |
3124 | if (phybits) |
3125 | REG_WRITE(ah, AR_RXCFG, | |
3126 | REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); | |
3127 | else | |
3128 | REG_WRITE(ah, AR_RXCFG, | |
3129 | REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); | |
3130 | } | |
7322fd19 | 3131 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
f078f209 | 3132 | |
cbe61d8a | 3133 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
f1dc5600 | 3134 | { |
63a75b91 SB |
3135 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
3136 | return false; | |
3137 | ||
3138 | ath9k_hw_init_pll(ah, NULL); | |
3139 | return true; | |
f1dc5600 | 3140 | } |
7322fd19 | 3141 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
f078f209 | 3142 | |
cbe61d8a | 3143 | bool ath9k_hw_disable(struct ath_hw *ah) |
f1dc5600 | 3144 | { |
9ecdef4b | 3145 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 3146 | return false; |
f078f209 | 3147 | |
63a75b91 SB |
3148 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
3149 | return false; | |
3150 | ||
3151 | ath9k_hw_init_pll(ah, NULL); | |
3152 | return true; | |
f078f209 | 3153 | } |
7322fd19 | 3154 | EXPORT_SYMBOL(ath9k_hw_disable); |
f078f209 | 3155 | |
8fbff4b8 | 3156 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) |
f078f209 | 3157 | { |
608b88cb | 3158 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
2660b81a | 3159 | struct ath9k_channel *chan = ah->curchan; |
5f8e077c | 3160 | struct ieee80211_channel *channel = chan->chan; |
f078f209 | 3161 | |
608b88cb | 3162 | regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); |
6f255425 | 3163 | |
8fbff4b8 | 3164 | ah->eep_ops->set_txpower(ah, chan, |
608b88cb | 3165 | ath9k_regd_get_ctl(regulatory, chan), |
8fbff4b8 VT |
3166 | channel->max_antenna_gain * 2, |
3167 | channel->max_power * 2, | |
3168 | min((u32) MAX_RATE_POWER, | |
608b88cb | 3169 | (u32) regulatory->power_limit)); |
6f255425 | 3170 | } |
7322fd19 | 3171 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
6f255425 | 3172 | |
cbe61d8a | 3173 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) |
f078f209 | 3174 | { |
1510718d | 3175 | memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN); |
f078f209 | 3176 | } |
7322fd19 | 3177 | EXPORT_SYMBOL(ath9k_hw_setmac); |
f078f209 | 3178 | |
cbe61d8a | 3179 | void ath9k_hw_setopmode(struct ath_hw *ah) |
f078f209 | 3180 | { |
2660b81a | 3181 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
f078f209 | 3182 | } |
7322fd19 | 3183 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
f078f209 | 3184 | |
cbe61d8a | 3185 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
f078f209 | 3186 | { |
f1dc5600 S |
3187 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
3188 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); | |
f078f209 | 3189 | } |
7322fd19 | 3190 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
f078f209 | 3191 | |
f2b2143e | 3192 | void ath9k_hw_write_associd(struct ath_hw *ah) |
f078f209 | 3193 | { |
1510718d LR |
3194 | struct ath_common *common = ath9k_hw_common(ah); |
3195 | ||
3196 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); | |
3197 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | | |
3198 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); | |
f078f209 | 3199 | } |
7322fd19 | 3200 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
f078f209 | 3201 | |
cbe61d8a | 3202 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
f078f209 | 3203 | { |
f1dc5600 | 3204 | u64 tsf; |
f078f209 | 3205 | |
f1dc5600 S |
3206 | tsf = REG_READ(ah, AR_TSF_U32); |
3207 | tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); | |
f078f209 | 3208 | |
f1dc5600 S |
3209 | return tsf; |
3210 | } | |
7322fd19 | 3211 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
f078f209 | 3212 | |
cbe61d8a | 3213 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
27abe060 | 3214 | { |
27abe060 | 3215 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
b9a16197 | 3216 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
27abe060 | 3217 | } |
7322fd19 | 3218 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
27abe060 | 3219 | |
cbe61d8a | 3220 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
f1dc5600 | 3221 | { |
f9b604f6 GJ |
3222 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
3223 | AH_TSF_WRITE_TIMEOUT)) | |
c46917bb LR |
3224 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
3225 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); | |
f9b604f6 | 3226 | |
f1dc5600 S |
3227 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
3228 | } | |
7322fd19 | 3229 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
f078f209 | 3230 | |
54e4cec6 | 3231 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) |
f1dc5600 | 3232 | { |
f1dc5600 | 3233 | if (setting) |
2660b81a | 3234 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
f1dc5600 | 3235 | else |
2660b81a | 3236 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
f1dc5600 | 3237 | } |
7322fd19 | 3238 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
f078f209 | 3239 | |
30cbd422 LR |
3240 | /* |
3241 | * Extend 15-bit time stamp from rx descriptor to | |
3242 | * a full 64-bit TSF using the current h/w TSF. | |
3243 | */ | |
3244 | u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp) | |
3245 | { | |
3246 | u64 tsf; | |
3247 | ||
3248 | tsf = ath9k_hw_gettsf64(ah); | |
3249 | if ((tsf & 0x7fff) < rstamp) | |
3250 | tsf -= 0x8000; | |
3251 | return (tsf & ~0x7fff) | rstamp; | |
3252 | } | |
3253 | EXPORT_SYMBOL(ath9k_hw_extend_tsf); | |
3254 | ||
25c56eec | 3255 | void ath9k_hw_set11nmac2040(struct ath_hw *ah) |
f1dc5600 | 3256 | { |
25c56eec | 3257 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
f1dc5600 S |
3258 | u32 macmode; |
3259 | ||
25c56eec | 3260 | if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) |
f1dc5600 S |
3261 | macmode = AR_2040_JOINED_RX_CLEAR; |
3262 | else | |
3263 | macmode = 0; | |
f078f209 | 3264 | |
f1dc5600 | 3265 | REG_WRITE(ah, AR_2040_MODE, macmode); |
f078f209 | 3266 | } |
ff155a45 VT |
3267 | |
3268 | /* HW Generic timers configuration */ | |
3269 | ||
3270 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = | |
3271 | { | |
3272 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3273 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3274 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3275 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3276 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3277 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3278 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3279 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3280 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, | |
3281 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, | |
3282 | AR_NDP2_TIMER_MODE, 0x0002}, | |
3283 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, | |
3284 | AR_NDP2_TIMER_MODE, 0x0004}, | |
3285 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, | |
3286 | AR_NDP2_TIMER_MODE, 0x0008}, | |
3287 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, | |
3288 | AR_NDP2_TIMER_MODE, 0x0010}, | |
3289 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, | |
3290 | AR_NDP2_TIMER_MODE, 0x0020}, | |
3291 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, | |
3292 | AR_NDP2_TIMER_MODE, 0x0040}, | |
3293 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, | |
3294 | AR_NDP2_TIMER_MODE, 0x0080} | |
3295 | }; | |
3296 | ||
3297 | /* HW generic timer primitives */ | |
3298 | ||
3299 | /* compute and clear index of rightmost 1 */ | |
3300 | static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) | |
3301 | { | |
3302 | u32 b; | |
3303 | ||
3304 | b = *mask; | |
3305 | b &= (0-b); | |
3306 | *mask &= ~b; | |
3307 | b *= debruijn32; | |
3308 | b >>= 27; | |
3309 | ||
3310 | return timer_table->gen_timer_index[b]; | |
3311 | } | |
3312 | ||
1773912b | 3313 | u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
ff155a45 VT |
3314 | { |
3315 | return REG_READ(ah, AR_TSF_L32); | |
3316 | } | |
7322fd19 | 3317 | EXPORT_SYMBOL(ath9k_hw_gettsf32); |
ff155a45 VT |
3318 | |
3319 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
3320 | void (*trigger)(void *), | |
3321 | void (*overflow)(void *), | |
3322 | void *arg, | |
3323 | u8 timer_index) | |
3324 | { | |
3325 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3326 | struct ath_gen_timer *timer; | |
3327 | ||
3328 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); | |
3329 | ||
3330 | if (timer == NULL) { | |
c46917bb LR |
3331 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
3332 | "Failed to allocate memory" | |
3333 | "for hw timer[%d]\n", timer_index); | |
ff155a45 VT |
3334 | return NULL; |
3335 | } | |
3336 | ||
3337 | /* allocate a hardware generic timer slot */ | |
3338 | timer_table->timers[timer_index] = timer; | |
3339 | timer->index = timer_index; | |
3340 | timer->trigger = trigger; | |
3341 | timer->overflow = overflow; | |
3342 | timer->arg = arg; | |
3343 | ||
3344 | return timer; | |
3345 | } | |
7322fd19 | 3346 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
ff155a45 | 3347 | |
cd9bf689 LR |
3348 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
3349 | struct ath_gen_timer *timer, | |
3350 | u32 timer_next, | |
3351 | u32 timer_period) | |
ff155a45 VT |
3352 | { |
3353 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3354 | u32 tsf; | |
3355 | ||
3356 | BUG_ON(!timer_period); | |
3357 | ||
3358 | set_bit(timer->index, &timer_table->timer_mask.timer_bits); | |
3359 | ||
3360 | tsf = ath9k_hw_gettsf32(ah); | |
3361 | ||
c46917bb LR |
3362 | ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, |
3363 | "curent tsf %x period %x" | |
3364 | "timer_next %x\n", tsf, timer_period, timer_next); | |
ff155a45 VT |
3365 | |
3366 | /* | |
3367 | * Pull timer_next forward if the current TSF already passed it | |
3368 | * because of software latency | |
3369 | */ | |
3370 | if (timer_next < tsf) | |
3371 | timer_next = tsf + timer_period; | |
3372 | ||
3373 | /* | |
3374 | * Program generic timer registers | |
3375 | */ | |
3376 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, | |
3377 | timer_next); | |
3378 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, | |
3379 | timer_period); | |
3380 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
3381 | gen_tmr_configuration[timer->index].mode_mask); | |
3382 | ||
3383 | /* Enable both trigger and thresh interrupt masks */ | |
3384 | REG_SET_BIT(ah, AR_IMR_S5, | |
3385 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
3386 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
ff155a45 | 3387 | } |
7322fd19 | 3388 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
ff155a45 | 3389 | |
cd9bf689 | 3390 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
ff155a45 VT |
3391 | { |
3392 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3393 | ||
3394 | if ((timer->index < AR_FIRST_NDP_TIMER) || | |
3395 | (timer->index >= ATH_MAX_GEN_TIMER)) { | |
3396 | return; | |
3397 | } | |
3398 | ||
3399 | /* Clear generic timer enable bits. */ | |
3400 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
3401 | gen_tmr_configuration[timer->index].mode_mask); | |
3402 | ||
3403 | /* Disable both trigger and thresh interrupt masks */ | |
3404 | REG_CLR_BIT(ah, AR_IMR_S5, | |
3405 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
3406 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
3407 | ||
3408 | clear_bit(timer->index, &timer_table->timer_mask.timer_bits); | |
ff155a45 | 3409 | } |
7322fd19 | 3410 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
ff155a45 VT |
3411 | |
3412 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) | |
3413 | { | |
3414 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3415 | ||
3416 | /* free the hardware generic timer slot */ | |
3417 | timer_table->timers[timer->index] = NULL; | |
3418 | kfree(timer); | |
3419 | } | |
7322fd19 | 3420 | EXPORT_SYMBOL(ath_gen_timer_free); |
ff155a45 VT |
3421 | |
3422 | /* | |
3423 | * Generic Timer Interrupts handling | |
3424 | */ | |
3425 | void ath_gen_timer_isr(struct ath_hw *ah) | |
3426 | { | |
3427 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3428 | struct ath_gen_timer *timer; | |
c46917bb | 3429 | struct ath_common *common = ath9k_hw_common(ah); |
ff155a45 VT |
3430 | u32 trigger_mask, thresh_mask, index; |
3431 | ||
3432 | /* get hardware generic timer interrupt status */ | |
3433 | trigger_mask = ah->intr_gen_timer_trigger; | |
3434 | thresh_mask = ah->intr_gen_timer_thresh; | |
3435 | trigger_mask &= timer_table->timer_mask.val; | |
3436 | thresh_mask &= timer_table->timer_mask.val; | |
3437 | ||
3438 | trigger_mask &= ~thresh_mask; | |
3439 | ||
3440 | while (thresh_mask) { | |
3441 | index = rightmost_index(timer_table, &thresh_mask); | |
3442 | timer = timer_table->timers[index]; | |
3443 | BUG_ON(!timer); | |
c46917bb LR |
3444 | ath_print(common, ATH_DBG_HWTIMER, |
3445 | "TSF overflow for Gen timer %d\n", index); | |
ff155a45 VT |
3446 | timer->overflow(timer->arg); |
3447 | } | |
3448 | ||
3449 | while (trigger_mask) { | |
3450 | index = rightmost_index(timer_table, &trigger_mask); | |
3451 | timer = timer_table->timers[index]; | |
3452 | BUG_ON(!timer); | |
c46917bb LR |
3453 | ath_print(common, ATH_DBG_HWTIMER, |
3454 | "Gen timer[%d] trigger\n", index); | |
ff155a45 VT |
3455 | timer->trigger(timer->arg); |
3456 | } | |
3457 | } | |
7322fd19 | 3458 | EXPORT_SYMBOL(ath_gen_timer_isr); |
2da4f01a | 3459 | |
05020d23 S |
3460 | /********/ |
3461 | /* HTC */ | |
3462 | /********/ | |
3463 | ||
3464 | void ath9k_hw_htc_resetinit(struct ath_hw *ah) | |
3465 | { | |
3466 | ah->htc_reset_init = true; | |
3467 | } | |
3468 | EXPORT_SYMBOL(ath9k_hw_htc_resetinit); | |
3469 | ||
2da4f01a LR |
3470 | static struct { |
3471 | u32 version; | |
3472 | const char * name; | |
3473 | } ath_mac_bb_names[] = { | |
3474 | /* Devices with external radios */ | |
3475 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
3476 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
3477 | { AR_SREV_VERSION_9100, "9100" }, | |
3478 | { AR_SREV_VERSION_9160, "9160" }, | |
3479 | /* Single-chip solutions */ | |
3480 | { AR_SREV_VERSION_9280, "9280" }, | |
3481 | { AR_SREV_VERSION_9285, "9285" }, | |
11158472 LR |
3482 | { AR_SREV_VERSION_9287, "9287" }, |
3483 | { AR_SREV_VERSION_9271, "9271" }, | |
2da4f01a LR |
3484 | }; |
3485 | ||
3486 | /* For devices with external radios */ | |
3487 | static struct { | |
3488 | u16 version; | |
3489 | const char * name; | |
3490 | } ath_rf_names[] = { | |
3491 | { 0, "5133" }, | |
3492 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
3493 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
3494 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
3495 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
3496 | }; | |
3497 | ||
3498 | /* | |
3499 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
3500 | */ | |
f934c4d9 | 3501 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
2da4f01a LR |
3502 | { |
3503 | int i; | |
3504 | ||
3505 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
3506 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
3507 | return ath_mac_bb_names[i].name; | |
3508 | } | |
3509 | } | |
3510 | ||
3511 | return "????"; | |
3512 | } | |
2da4f01a LR |
3513 | |
3514 | /* | |
3515 | * Return the RF name. "????" is returned if the RF is unknown. | |
3516 | * Used for devices with external radios. | |
3517 | */ | |
f934c4d9 | 3518 | static const char *ath9k_hw_rf_name(u16 rf_version) |
2da4f01a LR |
3519 | { |
3520 | int i; | |
3521 | ||
3522 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
3523 | if (ath_rf_names[i].version == rf_version) { | |
3524 | return ath_rf_names[i].name; | |
3525 | } | |
3526 | } | |
3527 | ||
3528 | return "????"; | |
3529 | } | |
f934c4d9 LR |
3530 | |
3531 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) | |
3532 | { | |
3533 | int used; | |
3534 | ||
3535 | /* chipsets >= AR9280 are single-chip */ | |
3536 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
3537 | used = snprintf(hw_name, len, | |
3538 | "Atheros AR%s Rev:%x", | |
3539 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
3540 | ah->hw_version.macRev); | |
3541 | } | |
3542 | else { | |
3543 | used = snprintf(hw_name, len, | |
3544 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", | |
3545 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
3546 | ah->hw_version.macRev, | |
3547 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & | |
3548 | AR_RADIO_SREV_MAJOR)), | |
3549 | ah->hw_version.phyRev); | |
3550 | } | |
3551 | ||
3552 | hw_name[used] = '\0'; | |
3553 | } | |
3554 | EXPORT_SYMBOL(ath9k_hw_name); | |
d70357d5 LR |
3555 | |
3556 | /* Sets up the AR5008/AR9001/AR9002 hardware familiy callbacks */ | |
3557 | static void ar9002_hw_attach_ops(struct ath_hw *ah) | |
3558 | { | |
3559 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
3560 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); | |
3561 | ||
3562 | priv_ops->init_cal_settings = ar9002_hw_init_cal_settings; | |
3563 | priv_ops->init_mode_regs = ar9002_hw_init_mode_regs; | |
3564 | priv_ops->macversion_supported = ar9002_hw_macversion_supported; | |
3565 | ||
3566 | ops->config_pci_powersave = ar9002_hw_configpcipowersave; | |
8fe65368 | 3567 | |
8525f280 | 3568 | ar5008_hw_attach_phy_ops(ah); |
8fe65368 LR |
3569 | if (AR_SREV_9280_10_OR_LATER(ah)) |
3570 | ar9002_hw_attach_phy_ops(ah); | |
ae3bb6d4 VT |
3571 | |
3572 | ar9002_hw_attach_mac_ops(ah); | |
8525f280 LR |
3573 | } |
3574 | ||
3575 | /* Sets up the AR9003 hardware familiy callbacks */ | |
3576 | static void ar9003_hw_attach_ops(struct ath_hw *ah) | |
3577 | { | |
61accab9 LR |
3578 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
3579 | ||
3580 | priv_ops->macversion_supported = ar9003_hw_macversion_supported; | |
3581 | ||
8525f280 | 3582 | ar9003_hw_attach_phy_ops(ah); |
ae3bb6d4 VT |
3583 | |
3584 | ar9003_hw_attach_mac_ops(ah); | |
d70357d5 | 3585 | } |