]>
Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
b3950e6a | 2 | * Copyright (c) 2008-2010 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
f078f209 LR |
19 | #include <asm/unaligned.h> |
20 | ||
af03abec | 21 | #include "hw.h" |
d70357d5 | 22 | #include "hw-ops.h" |
cfe8cba9 | 23 | #include "rc.h" |
b622a720 | 24 | #include "ar9003_mac.h" |
f078f209 | 25 | |
cbe61d8a | 26 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
f078f209 | 27 | |
7322fd19 LR |
28 | MODULE_AUTHOR("Atheros Communications"); |
29 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
30 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
31 | MODULE_LICENSE("Dual BSD/GPL"); | |
32 | ||
33 | static int __init ath9k_init(void) | |
34 | { | |
35 | return 0; | |
36 | } | |
37 | module_init(ath9k_init); | |
38 | ||
39 | static void __exit ath9k_exit(void) | |
40 | { | |
41 | return; | |
42 | } | |
43 | module_exit(ath9k_exit); | |
44 | ||
d70357d5 LR |
45 | /* Private hardware callbacks */ |
46 | ||
47 | static void ath9k_hw_init_cal_settings(struct ath_hw *ah) | |
48 | { | |
49 | ath9k_hw_private_ops(ah)->init_cal_settings(ah); | |
50 | } | |
51 | ||
52 | static void ath9k_hw_init_mode_regs(struct ath_hw *ah) | |
53 | { | |
54 | ath9k_hw_private_ops(ah)->init_mode_regs(ah); | |
55 | } | |
56 | ||
57 | static bool ath9k_hw_macversion_supported(struct ath_hw *ah) | |
58 | { | |
59 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
60 | ||
61 | return priv_ops->macversion_supported(ah->hw_version.macVersion); | |
62 | } | |
63 | ||
64773964 LR |
64 | static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, |
65 | struct ath9k_channel *chan) | |
66 | { | |
67 | return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); | |
68 | } | |
69 | ||
991312d8 LR |
70 | static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) |
71 | { | |
72 | if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) | |
73 | return; | |
74 | ||
75 | ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); | |
76 | } | |
77 | ||
e36b27af LR |
78 | static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) |
79 | { | |
80 | /* You will not have this callback if using the old ANI */ | |
81 | if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) | |
82 | return; | |
83 | ||
84 | ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); | |
85 | } | |
86 | ||
f1dc5600 S |
87 | /********************/ |
88 | /* Helper Functions */ | |
89 | /********************/ | |
f078f209 | 90 | |
dfdac8ac | 91 | static void ath9k_hw_set_clockrate(struct ath_hw *ah) |
f1dc5600 | 92 | { |
b002a4a9 | 93 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
dfdac8ac FF |
94 | struct ath_common *common = ath9k_hw_common(ah); |
95 | unsigned int clockrate; | |
cbe61d8a | 96 | |
2660b81a | 97 | if (!ah->curchan) /* should really check for CCK instead */ |
dfdac8ac FF |
98 | clockrate = ATH9K_CLOCK_RATE_CCK; |
99 | else if (conf->channel->band == IEEE80211_BAND_2GHZ) | |
100 | clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; | |
101 | else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) | |
102 | clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; | |
e5553724 | 103 | else |
dfdac8ac FF |
104 | clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; |
105 | ||
106 | if (conf_is_ht40(conf)) | |
107 | clockrate *= 2; | |
108 | ||
109 | common->clockrate = clockrate; | |
f1dc5600 S |
110 | } |
111 | ||
cbe61d8a | 112 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
f1dc5600 | 113 | { |
dfdac8ac | 114 | struct ath_common *common = ath9k_hw_common(ah); |
cbe61d8a | 115 | |
dfdac8ac | 116 | return usecs * common->clockrate; |
f1dc5600 | 117 | } |
f078f209 | 118 | |
0caa7b14 | 119 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
f078f209 LR |
120 | { |
121 | int i; | |
122 | ||
0caa7b14 S |
123 | BUG_ON(timeout < AH_TIME_QUANTUM); |
124 | ||
125 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { | |
f078f209 LR |
126 | if ((REG_READ(ah, reg) & mask) == val) |
127 | return true; | |
128 | ||
129 | udelay(AH_TIME_QUANTUM); | |
130 | } | |
04bd4638 | 131 | |
c46917bb LR |
132 | ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, |
133 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", | |
134 | timeout, reg, REG_READ(ah, reg), mask, val); | |
f078f209 | 135 | |
f1dc5600 | 136 | return false; |
f078f209 | 137 | } |
7322fd19 | 138 | EXPORT_SYMBOL(ath9k_hw_wait); |
f078f209 LR |
139 | |
140 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) | |
141 | { | |
142 | u32 retval; | |
143 | int i; | |
144 | ||
145 | for (i = 0, retval = 0; i < n; i++) { | |
146 | retval = (retval << 1) | (val & 1); | |
147 | val >>= 1; | |
148 | } | |
149 | return retval; | |
150 | } | |
151 | ||
cbe61d8a | 152 | bool ath9k_get_channel_edges(struct ath_hw *ah, |
f1dc5600 S |
153 | u16 flags, u16 *low, |
154 | u16 *high) | |
f078f209 | 155 | { |
2660b81a | 156 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 157 | |
f1dc5600 S |
158 | if (flags & CHANNEL_5GHZ) { |
159 | *low = pCap->low_5ghz_chan; | |
160 | *high = pCap->high_5ghz_chan; | |
161 | return true; | |
f078f209 | 162 | } |
f1dc5600 S |
163 | if ((flags & CHANNEL_2GHZ)) { |
164 | *low = pCap->low_2ghz_chan; | |
165 | *high = pCap->high_2ghz_chan; | |
166 | return true; | |
167 | } | |
168 | return false; | |
f078f209 LR |
169 | } |
170 | ||
cbe61d8a | 171 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 172 | u8 phy, int kbps, |
f1dc5600 S |
173 | u32 frameLen, u16 rateix, |
174 | bool shortPreamble) | |
f078f209 | 175 | { |
f1dc5600 | 176 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
f078f209 | 177 | |
f1dc5600 S |
178 | if (kbps == 0) |
179 | return 0; | |
f078f209 | 180 | |
545750d3 | 181 | switch (phy) { |
46d14a58 | 182 | case WLAN_RC_PHY_CCK: |
f1dc5600 | 183 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
545750d3 | 184 | if (shortPreamble) |
f1dc5600 S |
185 | phyTime >>= 1; |
186 | numBits = frameLen << 3; | |
187 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); | |
188 | break; | |
46d14a58 | 189 | case WLAN_RC_PHY_OFDM: |
2660b81a | 190 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
f1dc5600 S |
191 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
192 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
193 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
194 | txTime = OFDM_SIFS_TIME_QUARTER | |
195 | + OFDM_PREAMBLE_TIME_QUARTER | |
196 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); | |
2660b81a S |
197 | } else if (ah->curchan && |
198 | IS_CHAN_HALF_RATE(ah->curchan)) { | |
f1dc5600 S |
199 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
200 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
201 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
202 | txTime = OFDM_SIFS_TIME_HALF + | |
203 | OFDM_PREAMBLE_TIME_HALF | |
204 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); | |
205 | } else { | |
206 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; | |
207 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
208 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
209 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME | |
210 | + (numSymbols * OFDM_SYMBOL_TIME); | |
211 | } | |
212 | break; | |
213 | default: | |
c46917bb | 214 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
545750d3 | 215 | "Unknown phy %u (rate ix %u)\n", phy, rateix); |
f1dc5600 S |
216 | txTime = 0; |
217 | break; | |
218 | } | |
f078f209 | 219 | |
f1dc5600 S |
220 | return txTime; |
221 | } | |
7322fd19 | 222 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
f078f209 | 223 | |
cbe61d8a | 224 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
f1dc5600 S |
225 | struct ath9k_channel *chan, |
226 | struct chan_centers *centers) | |
f078f209 | 227 | { |
f1dc5600 | 228 | int8_t extoff; |
f078f209 | 229 | |
f1dc5600 S |
230 | if (!IS_CHAN_HT40(chan)) { |
231 | centers->ctl_center = centers->ext_center = | |
232 | centers->synth_center = chan->channel; | |
233 | return; | |
f078f209 | 234 | } |
f078f209 | 235 | |
f1dc5600 S |
236 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
237 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { | |
238 | centers->synth_center = | |
239 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; | |
240 | extoff = 1; | |
241 | } else { | |
242 | centers->synth_center = | |
243 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; | |
244 | extoff = -1; | |
245 | } | |
f078f209 | 246 | |
f1dc5600 S |
247 | centers->ctl_center = |
248 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); | |
6420014c | 249 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
f1dc5600 | 250 | centers->ext_center = |
6420014c | 251 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
f078f209 LR |
252 | } |
253 | ||
f1dc5600 S |
254 | /******************/ |
255 | /* Chip Revisions */ | |
256 | /******************/ | |
257 | ||
cbe61d8a | 258 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
f078f209 | 259 | { |
f1dc5600 | 260 | u32 val; |
f078f209 | 261 | |
f1dc5600 | 262 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
f078f209 | 263 | |
f1dc5600 S |
264 | if (val == 0xFF) { |
265 | val = REG_READ(ah, AR_SREV); | |
d535a42a S |
266 | ah->hw_version.macVersion = |
267 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; | |
268 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
2660b81a | 269 | ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; |
f1dc5600 S |
270 | } else { |
271 | if (!AR_SREV_9100(ah)) | |
d535a42a | 272 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
f078f209 | 273 | |
d535a42a | 274 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
f078f209 | 275 | |
d535a42a | 276 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
2660b81a | 277 | ah->is_pciexpress = true; |
f1dc5600 | 278 | } |
f078f209 LR |
279 | } |
280 | ||
f1dc5600 S |
281 | /************************************/ |
282 | /* HW Attach, Detach, Init Routines */ | |
283 | /************************************/ | |
284 | ||
cbe61d8a | 285 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
f078f209 | 286 | { |
feed029c | 287 | if (AR_SREV_9100(ah)) |
f1dc5600 | 288 | return; |
f078f209 | 289 | |
7d0d0df0 S |
290 | ENABLE_REGWRITE_BUFFER(ah); |
291 | ||
f1dc5600 S |
292 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
293 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
294 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); | |
295 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); | |
296 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); | |
297 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); | |
298 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
299 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
300 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); | |
f078f209 | 301 | |
f1dc5600 | 302 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
7d0d0df0 S |
303 | |
304 | REGWRITE_BUFFER_FLUSH(ah); | |
f078f209 LR |
305 | } |
306 | ||
1f3f0618 | 307 | /* This should work for all families including legacy */ |
cbe61d8a | 308 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
f078f209 | 309 | { |
c46917bb | 310 | struct ath_common *common = ath9k_hw_common(ah); |
1f3f0618 | 311 | u32 regAddr[2] = { AR_STA_ID0 }; |
f1dc5600 S |
312 | u32 regHold[2]; |
313 | u32 patternData[4] = { 0x55555555, | |
314 | 0xaaaaaaaa, | |
315 | 0x66666666, | |
316 | 0x99999999 }; | |
1f3f0618 | 317 | int i, j, loop_max; |
f078f209 | 318 | |
1f3f0618 SB |
319 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
320 | loop_max = 2; | |
321 | regAddr[1] = AR_PHY_BASE + (8 << 2); | |
322 | } else | |
323 | loop_max = 1; | |
324 | ||
325 | for (i = 0; i < loop_max; i++) { | |
f1dc5600 S |
326 | u32 addr = regAddr[i]; |
327 | u32 wrData, rdData; | |
f078f209 | 328 | |
f1dc5600 S |
329 | regHold[i] = REG_READ(ah, addr); |
330 | for (j = 0; j < 0x100; j++) { | |
331 | wrData = (j << 16) | j; | |
332 | REG_WRITE(ah, addr, wrData); | |
333 | rdData = REG_READ(ah, addr); | |
334 | if (rdData != wrData) { | |
c46917bb LR |
335 | ath_print(common, ATH_DBG_FATAL, |
336 | "address test failed " | |
337 | "addr: 0x%08x - wr:0x%08x != " | |
338 | "rd:0x%08x\n", | |
339 | addr, wrData, rdData); | |
f1dc5600 S |
340 | return false; |
341 | } | |
342 | } | |
343 | for (j = 0; j < 4; j++) { | |
344 | wrData = patternData[j]; | |
345 | REG_WRITE(ah, addr, wrData); | |
346 | rdData = REG_READ(ah, addr); | |
347 | if (wrData != rdData) { | |
c46917bb LR |
348 | ath_print(common, ATH_DBG_FATAL, |
349 | "address test failed " | |
350 | "addr: 0x%08x - wr:0x%08x != " | |
351 | "rd:0x%08x\n", | |
352 | addr, wrData, rdData); | |
f1dc5600 S |
353 | return false; |
354 | } | |
f078f209 | 355 | } |
f1dc5600 | 356 | REG_WRITE(ah, regAddr[i], regHold[i]); |
f078f209 | 357 | } |
f1dc5600 | 358 | udelay(100); |
cbe61d8a | 359 | |
f078f209 LR |
360 | return true; |
361 | } | |
362 | ||
b8b0f377 | 363 | static void ath9k_hw_init_config(struct ath_hw *ah) |
f1dc5600 S |
364 | { |
365 | int i; | |
f078f209 | 366 | |
2660b81a S |
367 | ah->config.dma_beacon_response_time = 2; |
368 | ah->config.sw_beacon_response_time = 10; | |
369 | ah->config.additional_swba_backoff = 0; | |
370 | ah->config.ack_6mb = 0x0; | |
371 | ah->config.cwm_ignore_extcca = 0; | |
372 | ah->config.pcie_powersave_enable = 0; | |
2660b81a | 373 | ah->config.pcie_clock_req = 0; |
2660b81a S |
374 | ah->config.pcie_waen = 0; |
375 | ah->config.analog_shiftreg = 1; | |
03c72518 | 376 | ah->config.enable_ani = true; |
f078f209 | 377 | |
f1dc5600 | 378 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
2660b81a S |
379 | ah->config.spurchans[i][0] = AR_NO_SPUR; |
380 | ah->config.spurchans[i][1] = AR_NO_SPUR; | |
f078f209 LR |
381 | } |
382 | ||
5ffaf8a3 LR |
383 | if (ah->hw_version.devid != AR2427_DEVID_PCIE) |
384 | ah->config.ht_enable = 1; | |
385 | else | |
386 | ah->config.ht_enable = 0; | |
387 | ||
0ce024cb | 388 | ah->config.rx_intr_mitigation = true; |
6a0ec30a | 389 | ah->config.pcieSerDesWrite = true; |
6158425b LR |
390 | |
391 | /* | |
392 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) | |
393 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). | |
394 | * This means we use it for all AR5416 devices, and the few | |
395 | * minor PCI AR9280 devices out there. | |
396 | * | |
397 | * Serialization is required because these devices do not handle | |
398 | * well the case of two concurrent reads/writes due to the latency | |
399 | * involved. During one read/write another read/write can be issued | |
400 | * on another CPU while the previous read/write may still be working | |
401 | * on our hardware, if we hit this case the hardware poops in a loop. | |
402 | * We prevent this by serializing reads and writes. | |
403 | * | |
404 | * This issue is not present on PCI-Express devices or pre-AR5416 | |
405 | * devices (legacy, 802.11abg). | |
406 | */ | |
407 | if (num_possible_cpus() > 1) | |
2d6a5e95 | 408 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
f078f209 LR |
409 | } |
410 | ||
50aca25b | 411 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
f078f209 | 412 | { |
608b88cb LR |
413 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
414 | ||
415 | regulatory->country_code = CTRY_DEFAULT; | |
416 | regulatory->power_limit = MAX_RATE_POWER; | |
417 | regulatory->tp_scale = ATH9K_TP_SCALE_MAX; | |
418 | ||
d535a42a | 419 | ah->hw_version.magic = AR5416_MAGIC; |
d535a42a | 420 | ah->hw_version.subvendorid = 0; |
f078f209 LR |
421 | |
422 | ah->ah_flags = 0; | |
f078f209 LR |
423 | if (!AR_SREV_9100(ah)) |
424 | ah->ah_flags = AH_USE_EEPROM; | |
425 | ||
2660b81a | 426 | ah->atim_window = 0; |
16f2411f FF |
427 | ah->sta_id1_defaults = |
428 | AR_STA_ID1_CRPT_MIC_ENABLE | | |
429 | AR_STA_ID1_MCAST_KSRCH; | |
2660b81a S |
430 | ah->beacon_interval = 100; |
431 | ah->enable_32kHz_clock = DONT_USE_32KHZ; | |
432 | ah->slottime = (u32) -1; | |
2660b81a | 433 | ah->globaltxtimeout = (u32) -1; |
cbdec975 | 434 | ah->power_mode = ATH9K_PM_UNDEFINED; |
f078f209 LR |
435 | } |
436 | ||
cbe61d8a | 437 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
f078f209 | 438 | { |
1510718d | 439 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
440 | u32 sum; |
441 | int i; | |
442 | u16 eeval; | |
49101676 | 443 | u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; |
f078f209 LR |
444 | |
445 | sum = 0; | |
446 | for (i = 0; i < 3; i++) { | |
49101676 | 447 | eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); |
f078f209 | 448 | sum += eeval; |
1510718d LR |
449 | common->macaddr[2 * i] = eeval >> 8; |
450 | common->macaddr[2 * i + 1] = eeval & 0xff; | |
f078f209 | 451 | } |
d8baa939 | 452 | if (sum == 0 || sum == 0xffff * 3) |
f078f209 | 453 | return -EADDRNOTAVAIL; |
f078f209 LR |
454 | |
455 | return 0; | |
456 | } | |
457 | ||
f637cfd6 | 458 | static int ath9k_hw_post_init(struct ath_hw *ah) |
f078f209 | 459 | { |
f1dc5600 | 460 | int ecode; |
f078f209 | 461 | |
527d485f S |
462 | if (!AR_SREV_9271(ah)) { |
463 | if (!ath9k_hw_chip_test(ah)) | |
464 | return -ENODEV; | |
465 | } | |
f078f209 | 466 | |
ebd5a14a LR |
467 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
468 | ecode = ar9002_hw_rf_claim(ah); | |
469 | if (ecode != 0) | |
470 | return ecode; | |
471 | } | |
f078f209 | 472 | |
f637cfd6 | 473 | ecode = ath9k_hw_eeprom_init(ah); |
f1dc5600 S |
474 | if (ecode != 0) |
475 | return ecode; | |
7d01b221 | 476 | |
c46917bb LR |
477 | ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, |
478 | "Eeprom VER: %d, REV: %d\n", | |
479 | ah->eep_ops->get_eeprom_ver(ah), | |
480 | ah->eep_ops->get_eeprom_rev(ah)); | |
7d01b221 | 481 | |
8fe65368 LR |
482 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); |
483 | if (ecode) { | |
484 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, | |
485 | "Failed allocating banks for " | |
486 | "external radio\n"); | |
487 | return ecode; | |
574d6b12 | 488 | } |
f078f209 | 489 | |
f1dc5600 S |
490 | if (!AR_SREV_9100(ah)) { |
491 | ath9k_hw_ani_setup(ah); | |
f637cfd6 | 492 | ath9k_hw_ani_init(ah); |
f078f209 LR |
493 | } |
494 | ||
f078f209 LR |
495 | return 0; |
496 | } | |
497 | ||
8525f280 | 498 | static void ath9k_hw_attach_ops(struct ath_hw *ah) |
ee2bb460 | 499 | { |
8525f280 LR |
500 | if (AR_SREV_9300_20_OR_LATER(ah)) |
501 | ar9003_hw_attach_ops(ah); | |
502 | else | |
503 | ar9002_hw_attach_ops(ah); | |
aa4058ae LR |
504 | } |
505 | ||
d70357d5 LR |
506 | /* Called for all hardware families */ |
507 | static int __ath9k_hw_init(struct ath_hw *ah) | |
aa4058ae | 508 | { |
c46917bb | 509 | struct ath_common *common = ath9k_hw_common(ah); |
95fafca2 | 510 | int r = 0; |
aa4058ae | 511 | |
bab1f62e LR |
512 | if (ah->hw_version.devid == AR5416_AR9100_DEVID) |
513 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; | |
aa4058ae LR |
514 | |
515 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { | |
c46917bb LR |
516 | ath_print(common, ATH_DBG_FATAL, |
517 | "Couldn't reset chip\n"); | |
95fafca2 | 518 | return -EIO; |
aa4058ae LR |
519 | } |
520 | ||
bab1f62e LR |
521 | ath9k_hw_init_defaults(ah); |
522 | ath9k_hw_init_config(ah); | |
523 | ||
8525f280 | 524 | ath9k_hw_attach_ops(ah); |
d70357d5 | 525 | |
9ecdef4b | 526 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
c46917bb | 527 | ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); |
95fafca2 | 528 | return -EIO; |
aa4058ae LR |
529 | } |
530 | ||
531 | if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { | |
532 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || | |
4c85ab11 JL |
533 | ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && |
534 | !ah->is_pciexpress)) { | |
aa4058ae LR |
535 | ah->config.serialize_regmode = |
536 | SER_REG_MODE_ON; | |
537 | } else { | |
538 | ah->config.serialize_regmode = | |
539 | SER_REG_MODE_OFF; | |
540 | } | |
541 | } | |
542 | ||
c46917bb | 543 | ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", |
aa4058ae LR |
544 | ah->config.serialize_regmode); |
545 | ||
f4709fdf LR |
546 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
547 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; | |
548 | else | |
549 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; | |
550 | ||
d70357d5 | 551 | if (!ath9k_hw_macversion_supported(ah)) { |
c46917bb LR |
552 | ath_print(common, ATH_DBG_FATAL, |
553 | "Mac Chip Rev 0x%02x.%x is not supported by " | |
554 | "this driver\n", ah->hw_version.macVersion, | |
555 | ah->hw_version.macRev); | |
95fafca2 | 556 | return -EOPNOTSUPP; |
aa4058ae LR |
557 | } |
558 | ||
0df13da4 | 559 | if (AR_SREV_9271(ah) || AR_SREV_9100(ah)) |
d7e7d229 LR |
560 | ah->is_pciexpress = false; |
561 | ||
aa4058ae | 562 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
aa4058ae LR |
563 | ath9k_hw_init_cal_settings(ah); |
564 | ||
565 | ah->ani_function = ATH9K_ANI_ALL; | |
7a37081e | 566 | if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
aa4058ae | 567 | ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; |
e36b27af LR |
568 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
569 | ah->ani_function &= ~ATH9K_ANI_MRC_CCK; | |
aa4058ae LR |
570 | |
571 | ath9k_hw_init_mode_regs(ah); | |
572 | ||
9a658d2b LR |
573 | /* |
574 | * Read back AR_WA into a permanent copy and set bits 14 and 17. | |
575 | * We need to do this to avoid RMW of this register. We cannot | |
576 | * read the reg when chip is asleep. | |
577 | */ | |
578 | ah->WARegVal = REG_READ(ah, AR_WA); | |
579 | ah->WARegVal |= (AR_WA_D3_L1_DISABLE | | |
580 | AR_WA_ASPM_TIMER_BASED_DISABLE); | |
581 | ||
aa4058ae | 582 | if (ah->is_pciexpress) |
93b1b37f | 583 | ath9k_hw_configpcipowersave(ah, 0, 0); |
aa4058ae LR |
584 | else |
585 | ath9k_hw_disablepcie(ah); | |
586 | ||
d8f492b7 LR |
587 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
588 | ar9002_hw_cck_chan14_spread(ah); | |
193cd458 | 589 | |
f637cfd6 | 590 | r = ath9k_hw_post_init(ah); |
aa4058ae | 591 | if (r) |
95fafca2 | 592 | return r; |
aa4058ae LR |
593 | |
594 | ath9k_hw_init_mode_gain_regs(ah); | |
a9a29ce6 GJ |
595 | r = ath9k_hw_fill_cap_info(ah); |
596 | if (r) | |
597 | return r; | |
598 | ||
4f3acf81 LR |
599 | r = ath9k_hw_init_macaddr(ah); |
600 | if (r) { | |
c46917bb LR |
601 | ath_print(common, ATH_DBG_FATAL, |
602 | "Failed to initialize MAC address\n"); | |
95fafca2 | 603 | return r; |
f078f209 LR |
604 | } |
605 | ||
d7e7d229 | 606 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
2660b81a | 607 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); |
f1dc5600 | 608 | else |
2660b81a | 609 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); |
f078f209 | 610 | |
aea702b7 | 611 | ah->bb_watchdog_timeout_ms = 25; |
f078f209 | 612 | |
211f5859 LR |
613 | common->state = ATH_HW_INITIALIZED; |
614 | ||
4f3acf81 | 615 | return 0; |
f078f209 LR |
616 | } |
617 | ||
d70357d5 | 618 | int ath9k_hw_init(struct ath_hw *ah) |
f078f209 | 619 | { |
d70357d5 LR |
620 | int ret; |
621 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 622 | |
d70357d5 LR |
623 | /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ |
624 | switch (ah->hw_version.devid) { | |
625 | case AR5416_DEVID_PCI: | |
626 | case AR5416_DEVID_PCIE: | |
627 | case AR5416_AR9100_DEVID: | |
628 | case AR9160_DEVID_PCI: | |
629 | case AR9280_DEVID_PCI: | |
630 | case AR9280_DEVID_PCIE: | |
631 | case AR9285_DEVID_PCIE: | |
db3cc53a SB |
632 | case AR9287_DEVID_PCI: |
633 | case AR9287_DEVID_PCIE: | |
d70357d5 | 634 | case AR2427_DEVID_PCIE: |
db3cc53a | 635 | case AR9300_DEVID_PCIE: |
d70357d5 LR |
636 | break; |
637 | default: | |
638 | if (common->bus_ops->ath_bus_type == ATH_USB) | |
639 | break; | |
640 | ath_print(common, ATH_DBG_FATAL, | |
641 | "Hardware device ID 0x%04x not supported\n", | |
642 | ah->hw_version.devid); | |
643 | return -EOPNOTSUPP; | |
644 | } | |
f078f209 | 645 | |
d70357d5 LR |
646 | ret = __ath9k_hw_init(ah); |
647 | if (ret) { | |
648 | ath_print(common, ATH_DBG_FATAL, | |
649 | "Unable to initialize hardware; " | |
650 | "initialization status: %d\n", ret); | |
651 | return ret; | |
652 | } | |
f078f209 | 653 | |
d70357d5 | 654 | return 0; |
f078f209 | 655 | } |
d70357d5 | 656 | EXPORT_SYMBOL(ath9k_hw_init); |
f078f209 | 657 | |
cbe61d8a | 658 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
f078f209 | 659 | { |
7d0d0df0 S |
660 | ENABLE_REGWRITE_BUFFER(ah); |
661 | ||
f1dc5600 S |
662 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
663 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); | |
f078f209 | 664 | |
f1dc5600 S |
665 | REG_WRITE(ah, AR_QOS_NO_ACK, |
666 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | | |
667 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | | |
668 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); | |
669 | ||
670 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); | |
671 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); | |
672 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); | |
673 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); | |
674 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); | |
7d0d0df0 S |
675 | |
676 | REGWRITE_BUFFER_FLUSH(ah); | |
f078f209 LR |
677 | } |
678 | ||
cbe61d8a | 679 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
f1dc5600 | 680 | struct ath9k_channel *chan) |
f078f209 | 681 | { |
64773964 | 682 | u32 pll = ath9k_hw_compute_pll_control(ah, chan); |
f078f209 | 683 | |
d03a66c1 | 684 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
f078f209 | 685 | |
c75724d1 LR |
686 | /* Switch the core clock for ar9271 to 117Mhz */ |
687 | if (AR_SREV_9271(ah)) { | |
25e2ab17 S |
688 | udelay(500); |
689 | REG_WRITE(ah, 0x50040, 0x304); | |
c75724d1 LR |
690 | } |
691 | ||
f1dc5600 S |
692 | udelay(RTC_PLL_SETTLE_DELAY); |
693 | ||
694 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | |
f078f209 LR |
695 | } |
696 | ||
cbe61d8a | 697 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
d97809db | 698 | enum nl80211_iftype opmode) |
f078f209 | 699 | { |
152d530d | 700 | u32 imr_reg = AR_IMR_TXERR | |
f1dc5600 S |
701 | AR_IMR_TXURN | |
702 | AR_IMR_RXERR | | |
703 | AR_IMR_RXORN | | |
704 | AR_IMR_BCNMISC; | |
f078f209 | 705 | |
66860240 VT |
706 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
707 | imr_reg |= AR_IMR_RXOK_HP; | |
708 | if (ah->config.rx_intr_mitigation) | |
709 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
710 | else | |
711 | imr_reg |= AR_IMR_RXOK_LP; | |
f078f209 | 712 | |
66860240 VT |
713 | } else { |
714 | if (ah->config.rx_intr_mitigation) | |
715 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
716 | else | |
717 | imr_reg |= AR_IMR_RXOK; | |
718 | } | |
f078f209 | 719 | |
66860240 VT |
720 | if (ah->config.tx_intr_mitigation) |
721 | imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; | |
722 | else | |
723 | imr_reg |= AR_IMR_TXOK; | |
f078f209 | 724 | |
d97809db | 725 | if (opmode == NL80211_IFTYPE_AP) |
152d530d | 726 | imr_reg |= AR_IMR_MIB; |
f078f209 | 727 | |
7d0d0df0 S |
728 | ENABLE_REGWRITE_BUFFER(ah); |
729 | ||
152d530d | 730 | REG_WRITE(ah, AR_IMR, imr_reg); |
74bad5cb PR |
731 | ah->imrs2_reg |= AR_IMR_S2_GTT; |
732 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); | |
f078f209 | 733 | |
f1dc5600 S |
734 | if (!AR_SREV_9100(ah)) { |
735 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); | |
736 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); | |
737 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); | |
738 | } | |
66860240 | 739 | |
7d0d0df0 | 740 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 741 | |
66860240 VT |
742 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
743 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); | |
744 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); | |
745 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); | |
746 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); | |
747 | } | |
f078f209 LR |
748 | } |
749 | ||
0005baf4 | 750 | static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
f078f209 | 751 | { |
0005baf4 FF |
752 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
753 | val = min(val, (u32) 0xFFFF); | |
754 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); | |
f078f209 LR |
755 | } |
756 | ||
0005baf4 | 757 | static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
f078f209 | 758 | { |
0005baf4 FF |
759 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
760 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); | |
761 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); | |
762 | } | |
763 | ||
764 | static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) | |
765 | { | |
766 | u32 val = ath9k_hw_mac_to_clks(ah, us); | |
767 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); | |
768 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); | |
f078f209 | 769 | } |
f1dc5600 | 770 | |
cbe61d8a | 771 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
f078f209 | 772 | { |
f078f209 | 773 | if (tu > 0xFFFF) { |
c46917bb LR |
774 | ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, |
775 | "bad global tx timeout %u\n", tu); | |
2660b81a | 776 | ah->globaltxtimeout = (u32) -1; |
f078f209 LR |
777 | return false; |
778 | } else { | |
779 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); | |
2660b81a | 780 | ah->globaltxtimeout = tu; |
f078f209 LR |
781 | return true; |
782 | } | |
783 | } | |
784 | ||
0005baf4 | 785 | void ath9k_hw_init_global_settings(struct ath_hw *ah) |
f078f209 | 786 | { |
0005baf4 FF |
787 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
788 | int acktimeout; | |
e239d859 | 789 | int slottime; |
0005baf4 FF |
790 | int sifstime; |
791 | ||
c46917bb LR |
792 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", |
793 | ah->misc_mode); | |
f078f209 | 794 | |
2660b81a | 795 | if (ah->misc_mode != 0) |
f1dc5600 | 796 | REG_WRITE(ah, AR_PCU_MISC, |
2660b81a | 797 | REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); |
0005baf4 FF |
798 | |
799 | if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) | |
800 | sifstime = 16; | |
801 | else | |
802 | sifstime = 10; | |
803 | ||
e239d859 FF |
804 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
805 | slottime = ah->slottime + 3 * ah->coverage_class; | |
806 | acktimeout = slottime + sifstime; | |
42c4568a FF |
807 | |
808 | /* | |
809 | * Workaround for early ACK timeouts, add an offset to match the | |
810 | * initval's 64us ack timeout value. | |
811 | * This was initially only meant to work around an issue with delayed | |
812 | * BA frames in some implementations, but it has been found to fix ACK | |
813 | * timeout issues in other cases as well. | |
814 | */ | |
815 | if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) | |
816 | acktimeout += 64 - sifstime - ah->slottime; | |
817 | ||
e239d859 | 818 | ath9k_hw_setslottime(ah, slottime); |
0005baf4 FF |
819 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
820 | ath9k_hw_set_cts_timeout(ah, acktimeout); | |
2660b81a S |
821 | if (ah->globaltxtimeout != (u32) -1) |
822 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); | |
f1dc5600 | 823 | } |
0005baf4 | 824 | EXPORT_SYMBOL(ath9k_hw_init_global_settings); |
f1dc5600 | 825 | |
285f2dda | 826 | void ath9k_hw_deinit(struct ath_hw *ah) |
f1dc5600 | 827 | { |
211f5859 LR |
828 | struct ath_common *common = ath9k_hw_common(ah); |
829 | ||
736b3a27 | 830 | if (common->state < ATH_HW_INITIALIZED) |
211f5859 LR |
831 | goto free_hw; |
832 | ||
9ecdef4b | 833 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
211f5859 LR |
834 | |
835 | free_hw: | |
8fe65368 | 836 | ath9k_hw_rf_free_ext_banks(ah); |
f1dc5600 | 837 | } |
285f2dda | 838 | EXPORT_SYMBOL(ath9k_hw_deinit); |
f1dc5600 | 839 | |
f1dc5600 S |
840 | /*******/ |
841 | /* INI */ | |
842 | /*******/ | |
843 | ||
8fe65368 | 844 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) |
3a702e49 BC |
845 | { |
846 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); | |
847 | ||
848 | if (IS_CHAN_B(chan)) | |
849 | ctl |= CTL_11B; | |
850 | else if (IS_CHAN_G(chan)) | |
851 | ctl |= CTL_11G; | |
852 | else | |
853 | ctl |= CTL_11A; | |
854 | ||
855 | return ctl; | |
856 | } | |
857 | ||
f1dc5600 S |
858 | /****************************************/ |
859 | /* Reset and Channel Switching Routines */ | |
860 | /****************************************/ | |
f1dc5600 | 861 | |
cbe61d8a | 862 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
f1dc5600 | 863 | { |
57b32227 | 864 | struct ath_common *common = ath9k_hw_common(ah); |
f1dc5600 S |
865 | u32 regval; |
866 | ||
7d0d0df0 S |
867 | ENABLE_REGWRITE_BUFFER(ah); |
868 | ||
d7e7d229 LR |
869 | /* |
870 | * set AHB_MODE not to do cacheline prefetches | |
871 | */ | |
57b32227 FF |
872 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
873 | regval = REG_READ(ah, AR_AHB_MODE); | |
874 | REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); | |
875 | } | |
f1dc5600 | 876 | |
d7e7d229 LR |
877 | /* |
878 | * let mac dma reads be in 128 byte chunks | |
879 | */ | |
f1dc5600 S |
880 | regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; |
881 | REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); | |
882 | ||
7d0d0df0 | 883 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 884 | |
d7e7d229 LR |
885 | /* |
886 | * Restore TX Trigger Level to its pre-reset value. | |
887 | * The initial value depends on whether aggregation is enabled, and is | |
888 | * adjusted whenever underruns are detected. | |
889 | */ | |
57b32227 FF |
890 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
891 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); | |
f1dc5600 | 892 | |
7d0d0df0 | 893 | ENABLE_REGWRITE_BUFFER(ah); |
f1dc5600 | 894 | |
d7e7d229 LR |
895 | /* |
896 | * let mac dma writes be in 128 byte chunks | |
897 | */ | |
f1dc5600 S |
898 | regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; |
899 | REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); | |
900 | ||
d7e7d229 LR |
901 | /* |
902 | * Setup receive FIFO threshold to hold off TX activities | |
903 | */ | |
f1dc5600 S |
904 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
905 | ||
57b32227 FF |
906 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
907 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); | |
908 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); | |
909 | ||
910 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - | |
911 | ah->caps.rx_status_len); | |
912 | } | |
913 | ||
d7e7d229 LR |
914 | /* |
915 | * reduce the number of usable entries in PCU TXBUF to avoid | |
916 | * wrap around issues. | |
917 | */ | |
f1dc5600 | 918 | if (AR_SREV_9285(ah)) { |
d7e7d229 LR |
919 | /* For AR9285 the number of Fifos are reduced to half. |
920 | * So set the usable tx buf size also to half to | |
921 | * avoid data/delimiter underruns | |
922 | */ | |
f1dc5600 S |
923 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
924 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); | |
d7e7d229 | 925 | } else if (!AR_SREV_9271(ah)) { |
f1dc5600 S |
926 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
927 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); | |
928 | } | |
744d4025 | 929 | |
7d0d0df0 | 930 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 931 | |
744d4025 VT |
932 | if (AR_SREV_9300_20_OR_LATER(ah)) |
933 | ath9k_hw_reset_txstatus_ring(ah); | |
f1dc5600 S |
934 | } |
935 | ||
cbe61d8a | 936 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
f1dc5600 S |
937 | { |
938 | u32 val; | |
939 | ||
940 | val = REG_READ(ah, AR_STA_ID1); | |
941 | val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); | |
942 | switch (opmode) { | |
d97809db | 943 | case NL80211_IFTYPE_AP: |
f1dc5600 S |
944 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
945 | | AR_STA_ID1_KSRCH_MODE); | |
946 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 947 | break; |
d97809db | 948 | case NL80211_IFTYPE_ADHOC: |
9cb5412b | 949 | case NL80211_IFTYPE_MESH_POINT: |
f1dc5600 S |
950 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
951 | | AR_STA_ID1_KSRCH_MODE); | |
952 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 953 | break; |
d97809db CM |
954 | case NL80211_IFTYPE_STATION: |
955 | case NL80211_IFTYPE_MONITOR: | |
f1dc5600 | 956 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); |
f078f209 | 957 | break; |
f1dc5600 S |
958 | } |
959 | } | |
960 | ||
8fe65368 LR |
961 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
962 | u32 *coef_mantissa, u32 *coef_exponent) | |
f1dc5600 S |
963 | { |
964 | u32 coef_exp, coef_man; | |
965 | ||
966 | for (coef_exp = 31; coef_exp > 0; coef_exp--) | |
967 | if ((coef_scaled >> coef_exp) & 0x1) | |
968 | break; | |
969 | ||
970 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); | |
971 | ||
972 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); | |
973 | ||
974 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); | |
975 | *coef_exponent = coef_exp - 16; | |
976 | } | |
977 | ||
cbe61d8a | 978 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
f1dc5600 S |
979 | { |
980 | u32 rst_flags; | |
981 | u32 tmpReg; | |
982 | ||
70768496 S |
983 | if (AR_SREV_9100(ah)) { |
984 | u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); | |
985 | val &= ~AR_RTC_DERIVED_CLK_PERIOD; | |
986 | val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); | |
987 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); | |
988 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); | |
989 | } | |
990 | ||
7d0d0df0 S |
991 | ENABLE_REGWRITE_BUFFER(ah); |
992 | ||
9a658d2b LR |
993 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
994 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
995 | udelay(10); | |
996 | } | |
997 | ||
f1dc5600 S |
998 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
999 | AR_RTC_FORCE_WAKE_ON_INT); | |
1000 | ||
1001 | if (AR_SREV_9100(ah)) { | |
1002 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | | |
1003 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; | |
1004 | } else { | |
1005 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
1006 | if (tmpReg & | |
1007 | (AR_INTR_SYNC_LOCAL_TIMEOUT | | |
1008 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { | |
42d5bc3f | 1009 | u32 val; |
f1dc5600 | 1010 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
42d5bc3f LR |
1011 | |
1012 | val = AR_RC_HOSTIF; | |
1013 | if (!AR_SREV_9300_20_OR_LATER(ah)) | |
1014 | val |= AR_RC_AHB; | |
1015 | REG_WRITE(ah, AR_RC, val); | |
1016 | ||
1017 | } else if (!AR_SREV_9300_20_OR_LATER(ah)) | |
f1dc5600 | 1018 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
f1dc5600 S |
1019 | |
1020 | rst_flags = AR_RTC_RC_MAC_WARM; | |
1021 | if (type == ATH9K_RESET_COLD) | |
1022 | rst_flags |= AR_RTC_RC_MAC_COLD; | |
1023 | } | |
1024 | ||
d03a66c1 | 1025 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
7d0d0df0 S |
1026 | |
1027 | REGWRITE_BUFFER_FLUSH(ah); | |
7d0d0df0 | 1028 | |
f1dc5600 S |
1029 | udelay(50); |
1030 | ||
d03a66c1 | 1031 | REG_WRITE(ah, AR_RTC_RC, 0); |
0caa7b14 | 1032 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
c46917bb LR |
1033 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
1034 | "RTC stuck in MAC reset\n"); | |
f1dc5600 S |
1035 | return false; |
1036 | } | |
1037 | ||
1038 | if (!AR_SREV_9100(ah)) | |
1039 | REG_WRITE(ah, AR_RC, 0); | |
1040 | ||
f1dc5600 S |
1041 | if (AR_SREV_9100(ah)) |
1042 | udelay(50); | |
1043 | ||
1044 | return true; | |
1045 | } | |
1046 | ||
cbe61d8a | 1047 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
f1dc5600 | 1048 | { |
7d0d0df0 S |
1049 | ENABLE_REGWRITE_BUFFER(ah); |
1050 | ||
9a658d2b LR |
1051 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1052 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1053 | udelay(10); | |
1054 | } | |
1055 | ||
f1dc5600 S |
1056 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
1057 | AR_RTC_FORCE_WAKE_ON_INT); | |
1058 | ||
42d5bc3f | 1059 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
1c29ce67 VT |
1060 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
1061 | ||
d03a66c1 | 1062 | REG_WRITE(ah, AR_RTC_RESET, 0); |
ee031112 | 1063 | udelay(2); |
1c29ce67 | 1064 | |
7d0d0df0 | 1065 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1066 | |
84e2169b SB |
1067 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1068 | udelay(2); | |
1069 | ||
1070 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) | |
1c29ce67 VT |
1071 | REG_WRITE(ah, AR_RC, 0); |
1072 | ||
d03a66c1 | 1073 | REG_WRITE(ah, AR_RTC_RESET, 1); |
f1dc5600 S |
1074 | |
1075 | if (!ath9k_hw_wait(ah, | |
1076 | AR_RTC_STATUS, | |
1077 | AR_RTC_STATUS_M, | |
0caa7b14 S |
1078 | AR_RTC_STATUS_ON, |
1079 | AH_WAIT_TIMEOUT)) { | |
c46917bb LR |
1080 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
1081 | "RTC not waking up\n"); | |
f1dc5600 | 1082 | return false; |
f078f209 LR |
1083 | } |
1084 | ||
f1dc5600 S |
1085 | ath9k_hw_read_revisions(ah); |
1086 | ||
1087 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); | |
1088 | } | |
1089 | ||
cbe61d8a | 1090 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
f1dc5600 | 1091 | { |
9a658d2b LR |
1092 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1093 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1094 | udelay(10); | |
1095 | } | |
1096 | ||
f1dc5600 S |
1097 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
1098 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); | |
1099 | ||
1100 | switch (type) { | |
1101 | case ATH9K_RESET_POWER_ON: | |
1102 | return ath9k_hw_set_reset_power_on(ah); | |
f1dc5600 S |
1103 | case ATH9K_RESET_WARM: |
1104 | case ATH9K_RESET_COLD: | |
1105 | return ath9k_hw_set_reset(ah, type); | |
f1dc5600 S |
1106 | default: |
1107 | return false; | |
1108 | } | |
f078f209 LR |
1109 | } |
1110 | ||
cbe61d8a | 1111 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
f1dc5600 | 1112 | struct ath9k_channel *chan) |
f078f209 | 1113 | { |
42abfbee | 1114 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { |
8bd1d07f SB |
1115 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) |
1116 | return false; | |
1117 | } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) | |
f1dc5600 | 1118 | return false; |
f078f209 | 1119 | |
9ecdef4b | 1120 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 1121 | return false; |
f078f209 | 1122 | |
2660b81a | 1123 | ah->chip_fullsleep = false; |
f1dc5600 | 1124 | ath9k_hw_init_pll(ah, chan); |
f1dc5600 | 1125 | ath9k_hw_set_rfmode(ah, chan); |
f078f209 | 1126 | |
f1dc5600 | 1127 | return true; |
f078f209 LR |
1128 | } |
1129 | ||
cbe61d8a | 1130 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
25c56eec | 1131 | struct ath9k_channel *chan) |
f078f209 | 1132 | { |
608b88cb | 1133 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
c46917bb | 1134 | struct ath_common *common = ath9k_hw_common(ah); |
5f8e077c | 1135 | struct ieee80211_channel *channel = chan->chan; |
8fe65368 | 1136 | u32 qnum; |
0a3b7bac | 1137 | int r; |
f078f209 LR |
1138 | |
1139 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | |
1140 | if (ath9k_hw_numtxpending(ah, qnum)) { | |
c46917bb LR |
1141 | ath_print(common, ATH_DBG_QUEUE, |
1142 | "Transmit frames pending on " | |
1143 | "queue %d\n", qnum); | |
f078f209 LR |
1144 | return false; |
1145 | } | |
1146 | } | |
1147 | ||
8fe65368 | 1148 | if (!ath9k_hw_rfbus_req(ah)) { |
c46917bb LR |
1149 | ath_print(common, ATH_DBG_FATAL, |
1150 | "Could not kill baseband RX\n"); | |
f078f209 LR |
1151 | return false; |
1152 | } | |
1153 | ||
8fe65368 | 1154 | ath9k_hw_set_channel_regs(ah, chan); |
f078f209 | 1155 | |
8fe65368 | 1156 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac LR |
1157 | if (r) { |
1158 | ath_print(common, ATH_DBG_FATAL, | |
1159 | "Failed to set channel\n"); | |
1160 | return false; | |
f078f209 | 1161 | } |
dfdac8ac | 1162 | ath9k_hw_set_clockrate(ah); |
f078f209 | 1163 | |
8fbff4b8 | 1164 | ah->eep_ops->set_txpower(ah, chan, |
608b88cb | 1165 | ath9k_regd_get_ctl(regulatory, chan), |
f74df6fb S |
1166 | channel->max_antenna_gain * 2, |
1167 | channel->max_power * 2, | |
1168 | min((u32) MAX_RATE_POWER, | |
608b88cb | 1169 | (u32) regulatory->power_limit)); |
f078f209 | 1170 | |
8fe65368 | 1171 | ath9k_hw_rfbus_done(ah); |
f078f209 | 1172 | |
f1dc5600 S |
1173 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1174 | ath9k_hw_set_delta_slope(ah, chan); | |
1175 | ||
8fe65368 | 1176 | ath9k_hw_spur_mitigate_freq(ah, chan); |
f1dc5600 | 1177 | |
f1dc5600 S |
1178 | return true; |
1179 | } | |
1180 | ||
c9c99e5e | 1181 | bool ath9k_hw_check_alive(struct ath_hw *ah) |
3b319aae | 1182 | { |
c9c99e5e FF |
1183 | int count = 50; |
1184 | u32 reg; | |
1185 | ||
e17f83ea | 1186 | if (AR_SREV_9285_12_OR_LATER(ah)) |
c9c99e5e FF |
1187 | return true; |
1188 | ||
1189 | do { | |
1190 | reg = REG_READ(ah, AR_OBS_BUS_1); | |
3b319aae | 1191 | |
c9c99e5e FF |
1192 | if ((reg & 0x7E7FFFEF) == 0x00702400) |
1193 | continue; | |
1194 | ||
1195 | switch (reg & 0x7E000B00) { | |
1196 | case 0x1E000000: | |
1197 | case 0x52000B00: | |
1198 | case 0x18000B00: | |
1199 | continue; | |
1200 | default: | |
1201 | return true; | |
1202 | } | |
1203 | } while (count-- > 0); | |
3b319aae | 1204 | |
c9c99e5e | 1205 | return false; |
3b319aae | 1206 | } |
c9c99e5e | 1207 | EXPORT_SYMBOL(ath9k_hw_check_alive); |
3b319aae | 1208 | |
cbe61d8a | 1209 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
20bd2a09 | 1210 | struct ath9k_hw_cal_data *caldata, bool bChannelChange) |
f078f209 | 1211 | { |
1510718d | 1212 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1213 | u32 saveLedState; |
2660b81a | 1214 | struct ath9k_channel *curchan = ah->curchan; |
f078f209 LR |
1215 | u32 saveDefAntenna; |
1216 | u32 macStaId1; | |
46fe782c | 1217 | u64 tsf = 0; |
8fe65368 | 1218 | int i, r; |
f078f209 | 1219 | |
43c27613 LR |
1220 | ah->txchainmask = common->tx_chainmask; |
1221 | ah->rxchainmask = common->rx_chainmask; | |
f078f209 | 1222 | |
9b9cc61c VT |
1223 | if (!ah->chip_fullsleep) { |
1224 | ath9k_hw_abortpcurecv(ah); | |
9cc2f3e8 | 1225 | if (!ath9k_hw_stopdmarecv(ah)) { |
9b9cc61c VT |
1226 | ath_print(common, ATH_DBG_XMIT, |
1227 | "Failed to stop receive dma\n"); | |
9cc2f3e8 FF |
1228 | bChannelChange = false; |
1229 | } | |
9b9cc61c VT |
1230 | } |
1231 | ||
9ecdef4b | 1232 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
ae8d2858 | 1233 | return -EIO; |
f078f209 | 1234 | |
d9891c78 | 1235 | if (curchan && !ah->chip_fullsleep) |
f078f209 LR |
1236 | ath9k_hw_getnf(ah, curchan); |
1237 | ||
20bd2a09 FF |
1238 | ah->caldata = caldata; |
1239 | if (caldata && | |
1240 | (chan->channel != caldata->channel || | |
1241 | (chan->channelFlags & ~CHANNEL_CW_INT) != | |
1242 | (caldata->channelFlags & ~CHANNEL_CW_INT))) { | |
1243 | /* Operating channel changed, reset channel calibration data */ | |
1244 | memset(caldata, 0, sizeof(*caldata)); | |
1245 | ath9k_init_nfcal_hist_buffer(ah, chan); | |
1246 | } | |
1247 | ||
f078f209 | 1248 | if (bChannelChange && |
2660b81a S |
1249 | (ah->chip_fullsleep != true) && |
1250 | (ah->curchan != NULL) && | |
1251 | (chan->channel != ah->curchan->channel) && | |
f078f209 | 1252 | ((chan->channelFlags & CHANNEL_ALL) == |
2660b81a | 1253 | (ah->curchan->channelFlags & CHANNEL_ALL)) && |
58d7e0f3 | 1254 | (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { |
f078f209 | 1255 | |
25c56eec | 1256 | if (ath9k_hw_channel_change(ah, chan)) { |
2660b81a | 1257 | ath9k_hw_loadnf(ah, ah->curchan); |
00c86590 | 1258 | ath9k_hw_start_nfcal(ah, true); |
c2ba3342 RM |
1259 | if (AR_SREV_9271(ah)) |
1260 | ar9002_hw_load_ani_reg(ah, chan); | |
ae8d2858 | 1261 | return 0; |
f078f209 LR |
1262 | } |
1263 | } | |
1264 | ||
1265 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); | |
1266 | if (saveDefAntenna == 0) | |
1267 | saveDefAntenna = 1; | |
1268 | ||
1269 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; | |
1270 | ||
46fe782c | 1271 | /* For chips on which RTC reset is done, save TSF before it gets cleared */ |
f860d526 FF |
1272 | if (AR_SREV_9100(ah) || |
1273 | (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) | |
46fe782c S |
1274 | tsf = ath9k_hw_gettsf64(ah); |
1275 | ||
f078f209 LR |
1276 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
1277 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | | |
1278 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); | |
1279 | ||
1280 | ath9k_hw_mark_phy_inactive(ah); | |
1281 | ||
05020d23 | 1282 | /* Only required on the first reset */ |
d7e7d229 LR |
1283 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1284 | REG_WRITE(ah, | |
1285 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1286 | AR9271_RADIO_RF_RST); | |
1287 | udelay(50); | |
1288 | } | |
1289 | ||
f078f209 | 1290 | if (!ath9k_hw_chip_reset(ah, chan)) { |
c46917bb | 1291 | ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); |
ae8d2858 | 1292 | return -EINVAL; |
f078f209 LR |
1293 | } |
1294 | ||
05020d23 | 1295 | /* Only required on the first reset */ |
d7e7d229 LR |
1296 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1297 | ah->htc_reset_init = false; | |
1298 | REG_WRITE(ah, | |
1299 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1300 | AR9271_GATE_MAC_CTL); | |
1301 | udelay(50); | |
1302 | } | |
1303 | ||
46fe782c | 1304 | /* Restore TSF */ |
f860d526 | 1305 | if (tsf) |
46fe782c S |
1306 | ath9k_hw_settsf64(ah, tsf); |
1307 | ||
7a37081e | 1308 | if (AR_SREV_9280_20_OR_LATER(ah)) |
369391db | 1309 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
f078f209 | 1310 | |
e9141f71 S |
1311 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1312 | ar9002_hw_enable_async_fifo(ah); | |
1313 | ||
25c56eec | 1314 | r = ath9k_hw_process_ini(ah, chan); |
ae8d2858 LR |
1315 | if (r) |
1316 | return r; | |
f078f209 | 1317 | |
f860d526 FF |
1318 | /* |
1319 | * Some AR91xx SoC devices frequently fail to accept TSF writes | |
1320 | * right after the chip reset. When that happens, write a new | |
1321 | * value after the initvals have been applied, with an offset | |
1322 | * based on measured time difference | |
1323 | */ | |
1324 | if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { | |
1325 | tsf += 1500; | |
1326 | ath9k_hw_settsf64(ah, tsf); | |
1327 | } | |
1328 | ||
0ced0e17 JM |
1329 | /* Setup MFP options for CCMP */ |
1330 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
1331 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt | |
1332 | * frames when constructing CCMP AAD. */ | |
1333 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, | |
1334 | 0xc7ff); | |
1335 | ah->sw_mgmt_crypto = false; | |
1336 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | |
1337 | /* Disable hardware crypto for management frames */ | |
1338 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, | |
1339 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); | |
1340 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | |
1341 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); | |
1342 | ah->sw_mgmt_crypto = true; | |
1343 | } else | |
1344 | ah->sw_mgmt_crypto = true; | |
1345 | ||
f078f209 LR |
1346 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1347 | ath9k_hw_set_delta_slope(ah, chan); | |
1348 | ||
8fe65368 | 1349 | ath9k_hw_spur_mitigate_freq(ah, chan); |
d6509151 | 1350 | ah->eep_ops->set_board_values(ah, chan); |
a7765828 | 1351 | |
6819d57f S |
1352 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
1353 | ||
7d0d0df0 S |
1354 | ENABLE_REGWRITE_BUFFER(ah); |
1355 | ||
1510718d LR |
1356 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); |
1357 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) | |
f078f209 LR |
1358 | | macStaId1 |
1359 | | AR_STA_ID1_RTS_USE_DEF | |
2660b81a | 1360 | | (ah->config. |
60b67f51 | 1361 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
2660b81a | 1362 | | ah->sta_id1_defaults); |
13b81559 | 1363 | ath_hw_setbssidmask(common); |
f078f209 | 1364 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); |
3453ad88 | 1365 | ath9k_hw_write_associd(ah); |
f078f209 | 1366 | REG_WRITE(ah, AR_ISR, ~0); |
f078f209 LR |
1367 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); |
1368 | ||
7d0d0df0 | 1369 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1370 | |
8fe65368 | 1371 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac LR |
1372 | if (r) |
1373 | return r; | |
f078f209 | 1374 | |
dfdac8ac FF |
1375 | ath9k_hw_set_clockrate(ah); |
1376 | ||
7d0d0df0 S |
1377 | ENABLE_REGWRITE_BUFFER(ah); |
1378 | ||
f078f209 LR |
1379 | for (i = 0; i < AR_NUM_DCU; i++) |
1380 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); | |
1381 | ||
7d0d0df0 | 1382 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1383 | |
2660b81a S |
1384 | ah->intr_txqs = 0; |
1385 | for (i = 0; i < ah->caps.total_queues; i++) | |
f078f209 LR |
1386 | ath9k_hw_resettxqueue(ah, i); |
1387 | ||
2660b81a | 1388 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
e36b27af | 1389 | ath9k_hw_ani_cache_ini_regs(ah); |
f078f209 LR |
1390 | ath9k_hw_init_qos(ah); |
1391 | ||
2660b81a | 1392 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
500c064d | 1393 | ath9k_enable_rfkill(ah); |
3b319aae | 1394 | |
0005baf4 | 1395 | ath9k_hw_init_global_settings(ah); |
f078f209 | 1396 | |
6c94fdc9 | 1397 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
e9141f71 | 1398 | ar9002_hw_update_async_fifo(ah); |
6c94fdc9 | 1399 | ar9002_hw_enable_wep_aggregation(ah); |
ac88b6ec VN |
1400 | } |
1401 | ||
f078f209 LR |
1402 | REG_WRITE(ah, AR_STA_ID1, |
1403 | REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); | |
1404 | ||
1405 | ath9k_hw_set_dma(ah); | |
1406 | ||
1407 | REG_WRITE(ah, AR_OBS, 8); | |
1408 | ||
0ce024cb | 1409 | if (ah->config.rx_intr_mitigation) { |
f078f209 LR |
1410 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); |
1411 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); | |
1412 | } | |
1413 | ||
7f62a136 VT |
1414 | if (ah->config.tx_intr_mitigation) { |
1415 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); | |
1416 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); | |
1417 | } | |
1418 | ||
f078f209 LR |
1419 | ath9k_hw_init_bb(ah, chan); |
1420 | ||
ae8d2858 | 1421 | if (!ath9k_hw_init_cal(ah, chan)) |
6badaaf7 | 1422 | return -EIO; |
f078f209 | 1423 | |
7d0d0df0 | 1424 | ENABLE_REGWRITE_BUFFER(ah); |
f078f209 | 1425 | |
8fe65368 | 1426 | ath9k_hw_restore_chainmask(ah); |
f078f209 LR |
1427 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
1428 | ||
7d0d0df0 | 1429 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1430 | |
d7e7d229 LR |
1431 | /* |
1432 | * For big endian systems turn on swapping for descriptors | |
1433 | */ | |
f078f209 LR |
1434 | if (AR_SREV_9100(ah)) { |
1435 | u32 mask; | |
1436 | mask = REG_READ(ah, AR_CFG); | |
1437 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | |
c46917bb | 1438 | ath_print(common, ATH_DBG_RESET, |
04bd4638 | 1439 | "CFG Byte Swap Set 0x%x\n", mask); |
f078f209 LR |
1440 | } else { |
1441 | mask = | |
1442 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | |
1443 | REG_WRITE(ah, AR_CFG, mask); | |
c46917bb | 1444 | ath_print(common, ATH_DBG_RESET, |
04bd4638 | 1445 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); |
f078f209 LR |
1446 | } |
1447 | } else { | |
cbba8cd1 S |
1448 | if (common->bus_ops->ath_bus_type == ATH_USB) { |
1449 | /* Configure AR9271 target WLAN */ | |
1450 | if (AR_SREV_9271(ah)) | |
1451 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); | |
1452 | else | |
1453 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
1454 | } | |
f078f209 | 1455 | #ifdef __BIG_ENDIAN |
d7e7d229 LR |
1456 | else |
1457 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
f078f209 LR |
1458 | #endif |
1459 | } | |
1460 | ||
766ec4a9 | 1461 | if (ah->btcoex_hw.enabled) |
42cc41ed VT |
1462 | ath9k_hw_btcoex_enable(ah); |
1463 | ||
00c86590 | 1464 | if (AR_SREV_9300_20_OR_LATER(ah)) |
aea702b7 | 1465 | ar9003_hw_bb_watchdog_config(ah); |
d8903a53 | 1466 | |
ae8d2858 | 1467 | return 0; |
f078f209 | 1468 | } |
7322fd19 | 1469 | EXPORT_SYMBOL(ath9k_hw_reset); |
f078f209 | 1470 | |
f1dc5600 S |
1471 | /******************************/ |
1472 | /* Power Management (Chipset) */ | |
1473 | /******************************/ | |
1474 | ||
42d5bc3f LR |
1475 | /* |
1476 | * Notify Power Mgt is disabled in self-generated frames. | |
1477 | * If requested, force chip to sleep. | |
1478 | */ | |
cbe61d8a | 1479 | static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 1480 | { |
f1dc5600 S |
1481 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
1482 | if (setChip) { | |
42d5bc3f LR |
1483 | /* |
1484 | * Clear the RTC force wake bit to allow the | |
1485 | * mac to go to sleep. | |
1486 | */ | |
f1dc5600 S |
1487 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
1488 | AR_RTC_FORCE_WAKE_EN); | |
42d5bc3f | 1489 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
f1dc5600 | 1490 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
f078f209 | 1491 | |
42d5bc3f | 1492 | /* Shutdown chip. Active low */ |
14b3af38 | 1493 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) |
4921be80 S |
1494 | REG_CLR_BIT(ah, (AR_RTC_RESET), |
1495 | AR_RTC_RESET_EN); | |
f1dc5600 | 1496 | } |
9a658d2b LR |
1497 | |
1498 | /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ | |
1499 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
1500 | REG_WRITE(ah, AR_WA, | |
1501 | ah->WARegVal & ~AR_WA_D3_L1_DISABLE); | |
f078f209 LR |
1502 | } |
1503 | ||
bbd79af5 LR |
1504 | /* |
1505 | * Notify Power Management is enabled in self-generating | |
1506 | * frames. If request, set power mode of chip to | |
1507 | * auto/normal. Duration in units of 128us (1/8 TU). | |
1508 | */ | |
cbe61d8a | 1509 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 1510 | { |
f1dc5600 S |
1511 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
1512 | if (setChip) { | |
2660b81a | 1513 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 1514 | |
f1dc5600 | 1515 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
bbd79af5 | 1516 | /* Set WakeOnInterrupt bit; clear ForceWake bit */ |
f1dc5600 S |
1517 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
1518 | AR_RTC_FORCE_WAKE_ON_INT); | |
1519 | } else { | |
bbd79af5 LR |
1520 | /* |
1521 | * Clear the RTC force wake bit to allow the | |
1522 | * mac to go to sleep. | |
1523 | */ | |
f1dc5600 S |
1524 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
1525 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 1526 | } |
f078f209 | 1527 | } |
9a658d2b LR |
1528 | |
1529 | /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ | |
1530 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
1531 | REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); | |
f078f209 LR |
1532 | } |
1533 | ||
cbe61d8a | 1534 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) |
f078f209 | 1535 | { |
f1dc5600 S |
1536 | u32 val; |
1537 | int i; | |
f078f209 | 1538 | |
9a658d2b LR |
1539 | /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ |
1540 | if (AR_SREV_9300_20_OR_LATER(ah)) { | |
1541 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1542 | udelay(10); | |
1543 | } | |
1544 | ||
f1dc5600 S |
1545 | if (setChip) { |
1546 | if ((REG_READ(ah, AR_RTC_STATUS) & | |
1547 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { | |
1548 | if (ath9k_hw_set_reset_reg(ah, | |
1549 | ATH9K_RESET_POWER_ON) != true) { | |
1550 | return false; | |
1551 | } | |
e041228f LR |
1552 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1553 | ath9k_hw_init_pll(ah, NULL); | |
f1dc5600 S |
1554 | } |
1555 | if (AR_SREV_9100(ah)) | |
1556 | REG_SET_BIT(ah, AR_RTC_RESET, | |
1557 | AR_RTC_RESET_EN); | |
f078f209 | 1558 | |
f1dc5600 S |
1559 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
1560 | AR_RTC_FORCE_WAKE_EN); | |
1561 | udelay(50); | |
f078f209 | 1562 | |
f1dc5600 S |
1563 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
1564 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; | |
1565 | if (val == AR_RTC_STATUS_ON) | |
1566 | break; | |
1567 | udelay(50); | |
1568 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, | |
1569 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 1570 | } |
f1dc5600 | 1571 | if (i == 0) { |
c46917bb LR |
1572 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
1573 | "Failed to wakeup in %uus\n", | |
1574 | POWER_UP_TIME / 20); | |
f1dc5600 | 1575 | return false; |
f078f209 | 1576 | } |
f078f209 LR |
1577 | } |
1578 | ||
f1dc5600 | 1579 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
f078f209 | 1580 | |
f1dc5600 | 1581 | return true; |
f078f209 LR |
1582 | } |
1583 | ||
9ecdef4b | 1584 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
f078f209 | 1585 | { |
c46917bb | 1586 | struct ath_common *common = ath9k_hw_common(ah); |
cbe61d8a | 1587 | int status = true, setChip = true; |
f1dc5600 S |
1588 | static const char *modes[] = { |
1589 | "AWAKE", | |
1590 | "FULL-SLEEP", | |
1591 | "NETWORK SLEEP", | |
1592 | "UNDEFINED" | |
1593 | }; | |
f1dc5600 | 1594 | |
cbdec975 GJ |
1595 | if (ah->power_mode == mode) |
1596 | return status; | |
1597 | ||
c46917bb LR |
1598 | ath_print(common, ATH_DBG_RESET, "%s -> %s\n", |
1599 | modes[ah->power_mode], modes[mode]); | |
f1dc5600 S |
1600 | |
1601 | switch (mode) { | |
1602 | case ATH9K_PM_AWAKE: | |
1603 | status = ath9k_hw_set_power_awake(ah, setChip); | |
1604 | break; | |
1605 | case ATH9K_PM_FULL_SLEEP: | |
1606 | ath9k_set_power_sleep(ah, setChip); | |
2660b81a | 1607 | ah->chip_fullsleep = true; |
f1dc5600 S |
1608 | break; |
1609 | case ATH9K_PM_NETWORK_SLEEP: | |
1610 | ath9k_set_power_network_sleep(ah, setChip); | |
1611 | break; | |
f078f209 | 1612 | default: |
c46917bb LR |
1613 | ath_print(common, ATH_DBG_FATAL, |
1614 | "Unknown power mode %u\n", mode); | |
f078f209 LR |
1615 | return false; |
1616 | } | |
2660b81a | 1617 | ah->power_mode = mode; |
f1dc5600 S |
1618 | |
1619 | return status; | |
f078f209 | 1620 | } |
7322fd19 | 1621 | EXPORT_SYMBOL(ath9k_hw_setpower); |
f078f209 | 1622 | |
f1dc5600 S |
1623 | /*******************/ |
1624 | /* Beacon Handling */ | |
1625 | /*******************/ | |
1626 | ||
cbe61d8a | 1627 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
f078f209 | 1628 | { |
f078f209 LR |
1629 | int flags = 0; |
1630 | ||
2660b81a | 1631 | ah->beacon_interval = beacon_period; |
f078f209 | 1632 | |
7d0d0df0 S |
1633 | ENABLE_REGWRITE_BUFFER(ah); |
1634 | ||
2660b81a | 1635 | switch (ah->opmode) { |
d97809db CM |
1636 | case NL80211_IFTYPE_STATION: |
1637 | case NL80211_IFTYPE_MONITOR: | |
f078f209 LR |
1638 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
1639 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); | |
1640 | REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); | |
1641 | flags |= AR_TBTT_TIMER_EN; | |
1642 | break; | |
d97809db | 1643 | case NL80211_IFTYPE_ADHOC: |
9cb5412b | 1644 | case NL80211_IFTYPE_MESH_POINT: |
f078f209 LR |
1645 | REG_SET_BIT(ah, AR_TXCFG, |
1646 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); | |
1647 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, | |
1648 | TU_TO_USEC(next_beacon + | |
2660b81a S |
1649 | (ah->atim_window ? ah-> |
1650 | atim_window : 1))); | |
f078f209 | 1651 | flags |= AR_NDP_TIMER_EN; |
d97809db | 1652 | case NL80211_IFTYPE_AP: |
f078f209 LR |
1653 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
1654 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, | |
1655 | TU_TO_USEC(next_beacon - | |
2660b81a | 1656 | ah->config. |
60b67f51 | 1657 | dma_beacon_response_time)); |
f078f209 LR |
1658 | REG_WRITE(ah, AR_NEXT_SWBA, |
1659 | TU_TO_USEC(next_beacon - | |
2660b81a | 1660 | ah->config. |
60b67f51 | 1661 | sw_beacon_response_time)); |
f078f209 LR |
1662 | flags |= |
1663 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; | |
1664 | break; | |
d97809db | 1665 | default: |
c46917bb LR |
1666 | ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, |
1667 | "%s: unsupported opmode: %d\n", | |
1668 | __func__, ah->opmode); | |
d97809db CM |
1669 | return; |
1670 | break; | |
f078f209 LR |
1671 | } |
1672 | ||
1673 | REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
1674 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
1675 | REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); | |
1676 | REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); | |
1677 | ||
7d0d0df0 | 1678 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1679 | |
f078f209 LR |
1680 | beacon_period &= ~ATH9K_BEACON_ENA; |
1681 | if (beacon_period & ATH9K_BEACON_RESET_TSF) { | |
f078f209 LR |
1682 | ath9k_hw_reset_tsf(ah); |
1683 | } | |
1684 | ||
1685 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); | |
1686 | } | |
7322fd19 | 1687 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
f078f209 | 1688 | |
cbe61d8a | 1689 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
f1dc5600 | 1690 | const struct ath9k_beacon_state *bs) |
f078f209 LR |
1691 | { |
1692 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; | |
2660b81a | 1693 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
c46917bb | 1694 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1695 | |
7d0d0df0 S |
1696 | ENABLE_REGWRITE_BUFFER(ah); |
1697 | ||
f078f209 LR |
1698 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); |
1699 | ||
1700 | REG_WRITE(ah, AR_BEACON_PERIOD, | |
1701 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
1702 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, | |
1703 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
1704 | ||
7d0d0df0 | 1705 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1706 | |
f078f209 LR |
1707 | REG_RMW_FIELD(ah, AR_RSSI_THR, |
1708 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); | |
1709 | ||
1710 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; | |
1711 | ||
1712 | if (bs->bs_sleepduration > beaconintval) | |
1713 | beaconintval = bs->bs_sleepduration; | |
1714 | ||
1715 | dtimperiod = bs->bs_dtimperiod; | |
1716 | if (bs->bs_sleepduration > dtimperiod) | |
1717 | dtimperiod = bs->bs_sleepduration; | |
1718 | ||
1719 | if (beaconintval == dtimperiod) | |
1720 | nextTbtt = bs->bs_nextdtim; | |
1721 | else | |
1722 | nextTbtt = bs->bs_nexttbtt; | |
1723 | ||
c46917bb LR |
1724 | ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
1725 | ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); | |
1726 | ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); | |
1727 | ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); | |
f078f209 | 1728 | |
7d0d0df0 S |
1729 | ENABLE_REGWRITE_BUFFER(ah); |
1730 | ||
f1dc5600 S |
1731 | REG_WRITE(ah, AR_NEXT_DTIM, |
1732 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); | |
1733 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); | |
f078f209 | 1734 | |
f1dc5600 S |
1735 | REG_WRITE(ah, AR_SLEEP1, |
1736 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) | |
1737 | | AR_SLEEP1_ASSUME_DTIM); | |
f078f209 | 1738 | |
f1dc5600 S |
1739 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
1740 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); | |
1741 | else | |
1742 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; | |
f078f209 | 1743 | |
f1dc5600 S |
1744 | REG_WRITE(ah, AR_SLEEP2, |
1745 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); | |
f078f209 | 1746 | |
f1dc5600 S |
1747 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
1748 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); | |
f078f209 | 1749 | |
7d0d0df0 | 1750 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1751 | |
f1dc5600 S |
1752 | REG_SET_BIT(ah, AR_TIMER_MODE, |
1753 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | | |
1754 | AR_DTIM_TIMER_EN); | |
f078f209 | 1755 | |
4af9cf4f S |
1756 | /* TSF Out of Range Threshold */ |
1757 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); | |
f078f209 | 1758 | } |
7322fd19 | 1759 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
f078f209 | 1760 | |
f1dc5600 S |
1761 | /*******************/ |
1762 | /* HW Capabilities */ | |
1763 | /*******************/ | |
1764 | ||
a9a29ce6 | 1765 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
f078f209 | 1766 | { |
2660b81a | 1767 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
608b88cb | 1768 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
c46917bb | 1769 | struct ath_common *common = ath9k_hw_common(ah); |
766ec4a9 | 1770 | struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; |
608b88cb | 1771 | |
f1dc5600 | 1772 | u16 capField = 0, eeval; |
754dc536 | 1773 | u8 ant_div_ctl1; |
f078f209 | 1774 | |
f74df6fb | 1775 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
608b88cb | 1776 | regulatory->current_rd = eeval; |
f078f209 | 1777 | |
f74df6fb | 1778 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); |
e17f83ea | 1779 | if (AR_SREV_9285_12_OR_LATER(ah)) |
fec0de11 | 1780 | eeval |= AR9285_RDEXT_DEFAULT; |
608b88cb | 1781 | regulatory->current_rd_ext = eeval; |
f078f209 | 1782 | |
f74df6fb | 1783 | capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); |
f1dc5600 | 1784 | |
2660b81a | 1785 | if (ah->opmode != NL80211_IFTYPE_AP && |
d535a42a | 1786 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
608b88cb LR |
1787 | if (regulatory->current_rd == 0x64 || |
1788 | regulatory->current_rd == 0x65) | |
1789 | regulatory->current_rd += 5; | |
1790 | else if (regulatory->current_rd == 0x41) | |
1791 | regulatory->current_rd = 0x43; | |
c46917bb LR |
1792 | ath_print(common, ATH_DBG_REGULATORY, |
1793 | "regdomain mapped to 0x%x\n", regulatory->current_rd); | |
f1dc5600 | 1794 | } |
f078f209 | 1795 | |
f74df6fb | 1796 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
a9a29ce6 GJ |
1797 | if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { |
1798 | ath_print(common, ATH_DBG_FATAL, | |
1799 | "no band has been marked as supported in EEPROM.\n"); | |
1800 | return -EINVAL; | |
1801 | } | |
1802 | ||
d4659912 FF |
1803 | if (eeval & AR5416_OPFLAGS_11A) |
1804 | pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; | |
f078f209 | 1805 | |
d4659912 FF |
1806 | if (eeval & AR5416_OPFLAGS_11G) |
1807 | pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; | |
f1dc5600 | 1808 | |
f74df6fb | 1809 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
d7e7d229 LR |
1810 | /* |
1811 | * For AR9271 we will temporarilly uses the rx chainmax as read from | |
1812 | * the EEPROM. | |
1813 | */ | |
8147f5de | 1814 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
d7e7d229 LR |
1815 | !(eeval & AR5416_OPFLAGS_11A) && |
1816 | !(AR_SREV_9271(ah))) | |
1817 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ | |
8147f5de S |
1818 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
1819 | else | |
d7e7d229 | 1820 | /* Use rx_chainmask from EEPROM. */ |
8147f5de | 1821 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
f078f209 | 1822 | |
7a37081e | 1823 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
f078f209 | 1824 | |
f1dc5600 S |
1825 | pCap->low_2ghz_chan = 2312; |
1826 | pCap->high_2ghz_chan = 2732; | |
f078f209 | 1827 | |
f1dc5600 S |
1828 | pCap->low_5ghz_chan = 4920; |
1829 | pCap->high_5ghz_chan = 6100; | |
f078f209 | 1830 | |
ce2220d1 BR |
1831 | common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; |
1832 | ||
2660b81a | 1833 | if (ah->config.ht_enable) |
f1dc5600 S |
1834 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
1835 | else | |
1836 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; | |
f078f209 | 1837 | |
f1dc5600 S |
1838 | if (capField & AR_EEPROM_EEPCAP_MAXQCU) |
1839 | pCap->total_queues = | |
1840 | MS(capField, AR_EEPROM_EEPCAP_MAXQCU); | |
1841 | else | |
1842 | pCap->total_queues = ATH9K_NUM_TX_QUEUES; | |
f078f209 | 1843 | |
f1dc5600 S |
1844 | if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) |
1845 | pCap->keycache_size = | |
1846 | 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); | |
1847 | else | |
1848 | pCap->keycache_size = AR_KEYTABLE_SIZE; | |
f078f209 | 1849 | |
f4709fdf LR |
1850 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
1851 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; | |
1852 | else | |
1853 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; | |
f078f209 | 1854 | |
5b5fa355 S |
1855 | if (AR_SREV_9271(ah)) |
1856 | pCap->num_gpio_pins = AR9271_NUM_GPIO; | |
88c1f4f6 S |
1857 | else if (AR_DEVID_7010(ah)) |
1858 | pCap->num_gpio_pins = AR7010_NUM_GPIO; | |
e17f83ea | 1859 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
cb33c412 | 1860 | pCap->num_gpio_pins = AR9285_NUM_GPIO; |
7a37081e | 1861 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
f1dc5600 S |
1862 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
1863 | else | |
1864 | pCap->num_gpio_pins = AR_NUM_GPIO; | |
f078f209 | 1865 | |
f1dc5600 S |
1866 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
1867 | pCap->hw_caps |= ATH9K_HW_CAP_CST; | |
1868 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; | |
1869 | } else { | |
1870 | pCap->rts_aggr_limit = (8 * 1024); | |
f078f209 LR |
1871 | } |
1872 | ||
f1dc5600 S |
1873 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; |
1874 | ||
e97275cb | 1875 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
2660b81a S |
1876 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
1877 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { | |
1878 | ah->rfkill_gpio = | |
1879 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); | |
1880 | ah->rfkill_polarity = | |
1881 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); | |
f1dc5600 S |
1882 | |
1883 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; | |
f078f209 | 1884 | } |
f1dc5600 | 1885 | #endif |
d5d1154f | 1886 | if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) |
bde748a4 VN |
1887 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; |
1888 | else | |
1889 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; | |
f078f209 | 1890 | |
e7594072 | 1891 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
f1dc5600 S |
1892 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
1893 | else | |
1894 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; | |
f078f209 | 1895 | |
608b88cb | 1896 | if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { |
f1dc5600 S |
1897 | pCap->reg_cap = |
1898 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
1899 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | | |
1900 | AR_EEPROM_EEREGCAP_EN_KK_U2 | | |
1901 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; | |
f078f209 | 1902 | } else { |
f1dc5600 S |
1903 | pCap->reg_cap = |
1904 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
1905 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; | |
f078f209 | 1906 | } |
f078f209 | 1907 | |
ebb90cfc SB |
1908 | /* Advertise midband for AR5416 with FCC midband set in eeprom */ |
1909 | if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && | |
1910 | AR_SREV_5416(ah)) | |
1911 | pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; | |
f1dc5600 S |
1912 | |
1913 | pCap->num_antcfg_5ghz = | |
f74df6fb | 1914 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); |
f1dc5600 | 1915 | pCap->num_antcfg_2ghz = |
f74df6fb | 1916 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); |
f078f209 | 1917 | |
7a37081e | 1918 | if (AR_SREV_9280_20_OR_LATER(ah) && |
a36cfbca | 1919 | ath9k_hw_btcoex_supported(ah)) { |
766ec4a9 LR |
1920 | btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; |
1921 | btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; | |
22f25d0d | 1922 | |
8c8f9ba7 | 1923 | if (AR_SREV_9285(ah)) { |
766ec4a9 LR |
1924 | btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; |
1925 | btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; | |
8c8f9ba7 | 1926 | } else { |
766ec4a9 | 1927 | btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; |
8c8f9ba7 | 1928 | } |
22f25d0d | 1929 | } else { |
766ec4a9 | 1930 | btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; |
c97c92d9 | 1931 | } |
a9a29ce6 | 1932 | |
ceb26445 | 1933 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
e5553724 VT |
1934 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC | |
1935 | ATH9K_HW_CAP_FASTCLOCK; | |
ceb26445 VT |
1936 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; |
1937 | pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; | |
1938 | pCap->rx_status_len = sizeof(struct ar9003_rxs); | |
162c3be3 | 1939 | pCap->tx_desc_len = sizeof(struct ar9003_txc); |
5088c2f1 | 1940 | pCap->txs_len = sizeof(struct ar9003_txs); |
4935250a FF |
1941 | if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) |
1942 | pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; | |
162c3be3 VT |
1943 | } else { |
1944 | pCap->tx_desc_len = sizeof(struct ath_desc); | |
6b42e8d0 FF |
1945 | if (AR_SREV_9280_20(ah) && |
1946 | ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= | |
1947 | AR5416_EEP_MINOR_VER_16) || | |
1948 | ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) | |
1949 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; | |
ceb26445 | 1950 | } |
1adf02ff | 1951 | |
6c84ce08 VT |
1952 | if (AR_SREV_9300_20_OR_LATER(ah)) |
1953 | pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; | |
1954 | ||
a42acef0 | 1955 | if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) |
6473d24d VT |
1956 | pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; |
1957 | ||
754dc536 VT |
1958 | if (AR_SREV_9285(ah)) |
1959 | if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { | |
1960 | ant_div_ctl1 = | |
1961 | ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); | |
1962 | if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) | |
1963 | pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; | |
1964 | } | |
1965 | ||
a9a29ce6 | 1966 | return 0; |
f078f209 LR |
1967 | } |
1968 | ||
f1dc5600 S |
1969 | /****************************/ |
1970 | /* GPIO / RFKILL / Antennae */ | |
1971 | /****************************/ | |
f078f209 | 1972 | |
cbe61d8a | 1973 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
f1dc5600 S |
1974 | u32 gpio, u32 type) |
1975 | { | |
1976 | int addr; | |
1977 | u32 gpio_shift, tmp; | |
f078f209 | 1978 | |
f1dc5600 S |
1979 | if (gpio > 11) |
1980 | addr = AR_GPIO_OUTPUT_MUX3; | |
1981 | else if (gpio > 5) | |
1982 | addr = AR_GPIO_OUTPUT_MUX2; | |
1983 | else | |
1984 | addr = AR_GPIO_OUTPUT_MUX1; | |
f078f209 | 1985 | |
f1dc5600 | 1986 | gpio_shift = (gpio % 6) * 5; |
f078f209 | 1987 | |
f1dc5600 S |
1988 | if (AR_SREV_9280_20_OR_LATER(ah) |
1989 | || (addr != AR_GPIO_OUTPUT_MUX1)) { | |
1990 | REG_RMW(ah, addr, (type << gpio_shift), | |
1991 | (0x1f << gpio_shift)); | |
f078f209 | 1992 | } else { |
f1dc5600 S |
1993 | tmp = REG_READ(ah, addr); |
1994 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); | |
1995 | tmp &= ~(0x1f << gpio_shift); | |
1996 | tmp |= (type << gpio_shift); | |
1997 | REG_WRITE(ah, addr, tmp); | |
f078f209 | 1998 | } |
f078f209 LR |
1999 | } |
2000 | ||
cbe61d8a | 2001 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
f078f209 | 2002 | { |
f1dc5600 | 2003 | u32 gpio_shift; |
f078f209 | 2004 | |
9680e8a3 | 2005 | BUG_ON(gpio >= ah->caps.num_gpio_pins); |
f078f209 | 2006 | |
88c1f4f6 S |
2007 | if (AR_DEVID_7010(ah)) { |
2008 | gpio_shift = gpio; | |
2009 | REG_RMW(ah, AR7010_GPIO_OE, | |
2010 | (AR7010_GPIO_OE_AS_INPUT << gpio_shift), | |
2011 | (AR7010_GPIO_OE_MASK << gpio_shift)); | |
2012 | return; | |
2013 | } | |
f078f209 | 2014 | |
88c1f4f6 | 2015 | gpio_shift = gpio << 1; |
f1dc5600 S |
2016 | REG_RMW(ah, |
2017 | AR_GPIO_OE_OUT, | |
2018 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), | |
2019 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 2020 | } |
7322fd19 | 2021 | EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); |
f078f209 | 2022 | |
cbe61d8a | 2023 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
f078f209 | 2024 | { |
cb33c412 SB |
2025 | #define MS_REG_READ(x, y) \ |
2026 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) | |
2027 | ||
2660b81a | 2028 | if (gpio >= ah->caps.num_gpio_pins) |
f1dc5600 | 2029 | return 0xffffffff; |
f078f209 | 2030 | |
88c1f4f6 S |
2031 | if (AR_DEVID_7010(ah)) { |
2032 | u32 val; | |
2033 | val = REG_READ(ah, AR7010_GPIO_IN); | |
2034 | return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; | |
2035 | } else if (AR_SREV_9300_20_OR_LATER(ah)) | |
783dfca1 FF |
2036 | return MS_REG_READ(AR9300, gpio) != 0; |
2037 | else if (AR_SREV_9271(ah)) | |
5b5fa355 | 2038 | return MS_REG_READ(AR9271, gpio) != 0; |
a42acef0 | 2039 | else if (AR_SREV_9287_11_OR_LATER(ah)) |
ac88b6ec | 2040 | return MS_REG_READ(AR9287, gpio) != 0; |
e17f83ea | 2041 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
cb33c412 | 2042 | return MS_REG_READ(AR9285, gpio) != 0; |
7a37081e | 2043 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
cb33c412 SB |
2044 | return MS_REG_READ(AR928X, gpio) != 0; |
2045 | else | |
2046 | return MS_REG_READ(AR, gpio) != 0; | |
f078f209 | 2047 | } |
7322fd19 | 2048 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
f078f209 | 2049 | |
cbe61d8a | 2050 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
f1dc5600 | 2051 | u32 ah_signal_type) |
f078f209 | 2052 | { |
f1dc5600 | 2053 | u32 gpio_shift; |
f078f209 | 2054 | |
88c1f4f6 S |
2055 | if (AR_DEVID_7010(ah)) { |
2056 | gpio_shift = gpio; | |
2057 | REG_RMW(ah, AR7010_GPIO_OE, | |
2058 | (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), | |
2059 | (AR7010_GPIO_OE_MASK << gpio_shift)); | |
2060 | return; | |
2061 | } | |
f078f209 | 2062 | |
88c1f4f6 | 2063 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
f1dc5600 | 2064 | gpio_shift = 2 * gpio; |
f1dc5600 S |
2065 | REG_RMW(ah, |
2066 | AR_GPIO_OE_OUT, | |
2067 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), | |
2068 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 2069 | } |
7322fd19 | 2070 | EXPORT_SYMBOL(ath9k_hw_cfg_output); |
f078f209 | 2071 | |
cbe61d8a | 2072 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
f078f209 | 2073 | { |
88c1f4f6 S |
2074 | if (AR_DEVID_7010(ah)) { |
2075 | val = val ? 0 : 1; | |
2076 | REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), | |
2077 | AR_GPIO_BIT(gpio)); | |
2078 | return; | |
2079 | } | |
2080 | ||
5b5fa355 S |
2081 | if (AR_SREV_9271(ah)) |
2082 | val = ~val; | |
2083 | ||
f1dc5600 S |
2084 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
2085 | AR_GPIO_BIT(gpio)); | |
f078f209 | 2086 | } |
7322fd19 | 2087 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
f078f209 | 2088 | |
cbe61d8a | 2089 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah) |
f078f209 | 2090 | { |
f1dc5600 | 2091 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
f078f209 | 2092 | } |
7322fd19 | 2093 | EXPORT_SYMBOL(ath9k_hw_getdefantenna); |
f078f209 | 2094 | |
cbe61d8a | 2095 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
f078f209 | 2096 | { |
f1dc5600 | 2097 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
f078f209 | 2098 | } |
7322fd19 | 2099 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
f078f209 | 2100 | |
f1dc5600 S |
2101 | /*********************/ |
2102 | /* General Operation */ | |
2103 | /*********************/ | |
2104 | ||
cbe61d8a | 2105 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
f078f209 | 2106 | { |
f1dc5600 S |
2107 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
2108 | u32 phybits = REG_READ(ah, AR_PHY_ERR); | |
f078f209 | 2109 | |
f1dc5600 S |
2110 | if (phybits & AR_PHY_ERR_RADAR) |
2111 | bits |= ATH9K_RX_FILTER_PHYRADAR; | |
2112 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) | |
2113 | bits |= ATH9K_RX_FILTER_PHYERR; | |
dc2222a8 | 2114 | |
f1dc5600 | 2115 | return bits; |
f078f209 | 2116 | } |
7322fd19 | 2117 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
f078f209 | 2118 | |
cbe61d8a | 2119 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
f078f209 | 2120 | { |
f1dc5600 | 2121 | u32 phybits; |
f078f209 | 2122 | |
7d0d0df0 S |
2123 | ENABLE_REGWRITE_BUFFER(ah); |
2124 | ||
7ea310be S |
2125 | REG_WRITE(ah, AR_RX_FILTER, bits); |
2126 | ||
f1dc5600 S |
2127 | phybits = 0; |
2128 | if (bits & ATH9K_RX_FILTER_PHYRADAR) | |
2129 | phybits |= AR_PHY_ERR_RADAR; | |
2130 | if (bits & ATH9K_RX_FILTER_PHYERR) | |
2131 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; | |
2132 | REG_WRITE(ah, AR_PHY_ERR, phybits); | |
f078f209 | 2133 | |
f1dc5600 S |
2134 | if (phybits) |
2135 | REG_WRITE(ah, AR_RXCFG, | |
2136 | REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); | |
2137 | else | |
2138 | REG_WRITE(ah, AR_RXCFG, | |
2139 | REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); | |
7d0d0df0 S |
2140 | |
2141 | REGWRITE_BUFFER_FLUSH(ah); | |
f1dc5600 | 2142 | } |
7322fd19 | 2143 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
f078f209 | 2144 | |
cbe61d8a | 2145 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
f1dc5600 | 2146 | { |
63a75b91 SB |
2147 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
2148 | return false; | |
2149 | ||
2150 | ath9k_hw_init_pll(ah, NULL); | |
2151 | return true; | |
f1dc5600 | 2152 | } |
7322fd19 | 2153 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
f078f209 | 2154 | |
cbe61d8a | 2155 | bool ath9k_hw_disable(struct ath_hw *ah) |
f1dc5600 | 2156 | { |
9ecdef4b | 2157 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 2158 | return false; |
f078f209 | 2159 | |
63a75b91 SB |
2160 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
2161 | return false; | |
2162 | ||
2163 | ath9k_hw_init_pll(ah, NULL); | |
2164 | return true; | |
f078f209 | 2165 | } |
7322fd19 | 2166 | EXPORT_SYMBOL(ath9k_hw_disable); |
f078f209 | 2167 | |
8fbff4b8 | 2168 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) |
f078f209 | 2169 | { |
608b88cb | 2170 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
2660b81a | 2171 | struct ath9k_channel *chan = ah->curchan; |
5f8e077c | 2172 | struct ieee80211_channel *channel = chan->chan; |
f078f209 | 2173 | |
608b88cb | 2174 | regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); |
6f255425 | 2175 | |
8fbff4b8 | 2176 | ah->eep_ops->set_txpower(ah, chan, |
608b88cb | 2177 | ath9k_regd_get_ctl(regulatory, chan), |
8fbff4b8 VT |
2178 | channel->max_antenna_gain * 2, |
2179 | channel->max_power * 2, | |
2180 | min((u32) MAX_RATE_POWER, | |
608b88cb | 2181 | (u32) regulatory->power_limit)); |
6f255425 | 2182 | } |
7322fd19 | 2183 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
6f255425 | 2184 | |
cbe61d8a | 2185 | void ath9k_hw_setopmode(struct ath_hw *ah) |
f078f209 | 2186 | { |
2660b81a | 2187 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
f078f209 | 2188 | } |
7322fd19 | 2189 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
f078f209 | 2190 | |
cbe61d8a | 2191 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
f078f209 | 2192 | { |
f1dc5600 S |
2193 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
2194 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); | |
f078f209 | 2195 | } |
7322fd19 | 2196 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
f078f209 | 2197 | |
f2b2143e | 2198 | void ath9k_hw_write_associd(struct ath_hw *ah) |
f078f209 | 2199 | { |
1510718d LR |
2200 | struct ath_common *common = ath9k_hw_common(ah); |
2201 | ||
2202 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); | |
2203 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | | |
2204 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); | |
f078f209 | 2205 | } |
7322fd19 | 2206 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
f078f209 | 2207 | |
1c0fc65e BP |
2208 | #define ATH9K_MAX_TSF_READ 10 |
2209 | ||
cbe61d8a | 2210 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
f078f209 | 2211 | { |
1c0fc65e BP |
2212 | u32 tsf_lower, tsf_upper1, tsf_upper2; |
2213 | int i; | |
2214 | ||
2215 | tsf_upper1 = REG_READ(ah, AR_TSF_U32); | |
2216 | for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { | |
2217 | tsf_lower = REG_READ(ah, AR_TSF_L32); | |
2218 | tsf_upper2 = REG_READ(ah, AR_TSF_U32); | |
2219 | if (tsf_upper2 == tsf_upper1) | |
2220 | break; | |
2221 | tsf_upper1 = tsf_upper2; | |
2222 | } | |
f078f209 | 2223 | |
1c0fc65e | 2224 | WARN_ON( i == ATH9K_MAX_TSF_READ ); |
f078f209 | 2225 | |
1c0fc65e | 2226 | return (((u64)tsf_upper1 << 32) | tsf_lower); |
f1dc5600 | 2227 | } |
7322fd19 | 2228 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
f078f209 | 2229 | |
cbe61d8a | 2230 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
27abe060 | 2231 | { |
27abe060 | 2232 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
b9a16197 | 2233 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
27abe060 | 2234 | } |
7322fd19 | 2235 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
27abe060 | 2236 | |
cbe61d8a | 2237 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
f1dc5600 | 2238 | { |
f9b604f6 GJ |
2239 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
2240 | AH_TSF_WRITE_TIMEOUT)) | |
c46917bb LR |
2241 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
2242 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); | |
f9b604f6 | 2243 | |
f1dc5600 S |
2244 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
2245 | } | |
7322fd19 | 2246 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
f078f209 | 2247 | |
54e4cec6 | 2248 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) |
f1dc5600 | 2249 | { |
f1dc5600 | 2250 | if (setting) |
2660b81a | 2251 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
f1dc5600 | 2252 | else |
2660b81a | 2253 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
f1dc5600 | 2254 | } |
7322fd19 | 2255 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
f078f209 | 2256 | |
25c56eec | 2257 | void ath9k_hw_set11nmac2040(struct ath_hw *ah) |
f1dc5600 | 2258 | { |
25c56eec | 2259 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
f1dc5600 S |
2260 | u32 macmode; |
2261 | ||
25c56eec | 2262 | if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) |
f1dc5600 S |
2263 | macmode = AR_2040_JOINED_RX_CLEAR; |
2264 | else | |
2265 | macmode = 0; | |
f078f209 | 2266 | |
f1dc5600 | 2267 | REG_WRITE(ah, AR_2040_MODE, macmode); |
f078f209 | 2268 | } |
ff155a45 VT |
2269 | |
2270 | /* HW Generic timers configuration */ | |
2271 | ||
2272 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = | |
2273 | { | |
2274 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2275 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2276 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2277 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2278 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2279 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2280 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2281 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2282 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, | |
2283 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, | |
2284 | AR_NDP2_TIMER_MODE, 0x0002}, | |
2285 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, | |
2286 | AR_NDP2_TIMER_MODE, 0x0004}, | |
2287 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, | |
2288 | AR_NDP2_TIMER_MODE, 0x0008}, | |
2289 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, | |
2290 | AR_NDP2_TIMER_MODE, 0x0010}, | |
2291 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, | |
2292 | AR_NDP2_TIMER_MODE, 0x0020}, | |
2293 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, | |
2294 | AR_NDP2_TIMER_MODE, 0x0040}, | |
2295 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, | |
2296 | AR_NDP2_TIMER_MODE, 0x0080} | |
2297 | }; | |
2298 | ||
2299 | /* HW generic timer primitives */ | |
2300 | ||
2301 | /* compute and clear index of rightmost 1 */ | |
2302 | static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) | |
2303 | { | |
2304 | u32 b; | |
2305 | ||
2306 | b = *mask; | |
2307 | b &= (0-b); | |
2308 | *mask &= ~b; | |
2309 | b *= debruijn32; | |
2310 | b >>= 27; | |
2311 | ||
2312 | return timer_table->gen_timer_index[b]; | |
2313 | } | |
2314 | ||
1773912b | 2315 | u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
ff155a45 VT |
2316 | { |
2317 | return REG_READ(ah, AR_TSF_L32); | |
2318 | } | |
7322fd19 | 2319 | EXPORT_SYMBOL(ath9k_hw_gettsf32); |
ff155a45 VT |
2320 | |
2321 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
2322 | void (*trigger)(void *), | |
2323 | void (*overflow)(void *), | |
2324 | void *arg, | |
2325 | u8 timer_index) | |
2326 | { | |
2327 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2328 | struct ath_gen_timer *timer; | |
2329 | ||
2330 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); | |
2331 | ||
2332 | if (timer == NULL) { | |
c46917bb LR |
2333 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
2334 | "Failed to allocate memory" | |
2335 | "for hw timer[%d]\n", timer_index); | |
ff155a45 VT |
2336 | return NULL; |
2337 | } | |
2338 | ||
2339 | /* allocate a hardware generic timer slot */ | |
2340 | timer_table->timers[timer_index] = timer; | |
2341 | timer->index = timer_index; | |
2342 | timer->trigger = trigger; | |
2343 | timer->overflow = overflow; | |
2344 | timer->arg = arg; | |
2345 | ||
2346 | return timer; | |
2347 | } | |
7322fd19 | 2348 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
ff155a45 | 2349 | |
cd9bf689 LR |
2350 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
2351 | struct ath_gen_timer *timer, | |
2352 | u32 timer_next, | |
2353 | u32 timer_period) | |
ff155a45 VT |
2354 | { |
2355 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2356 | u32 tsf; | |
2357 | ||
2358 | BUG_ON(!timer_period); | |
2359 | ||
2360 | set_bit(timer->index, &timer_table->timer_mask.timer_bits); | |
2361 | ||
2362 | tsf = ath9k_hw_gettsf32(ah); | |
2363 | ||
c46917bb LR |
2364 | ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, |
2365 | "curent tsf %x period %x" | |
2366 | "timer_next %x\n", tsf, timer_period, timer_next); | |
ff155a45 VT |
2367 | |
2368 | /* | |
2369 | * Pull timer_next forward if the current TSF already passed it | |
2370 | * because of software latency | |
2371 | */ | |
2372 | if (timer_next < tsf) | |
2373 | timer_next = tsf + timer_period; | |
2374 | ||
2375 | /* | |
2376 | * Program generic timer registers | |
2377 | */ | |
2378 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, | |
2379 | timer_next); | |
2380 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, | |
2381 | timer_period); | |
2382 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
2383 | gen_tmr_configuration[timer->index].mode_mask); | |
2384 | ||
2385 | /* Enable both trigger and thresh interrupt masks */ | |
2386 | REG_SET_BIT(ah, AR_IMR_S5, | |
2387 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
2388 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
ff155a45 | 2389 | } |
7322fd19 | 2390 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
ff155a45 | 2391 | |
cd9bf689 | 2392 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
ff155a45 VT |
2393 | { |
2394 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2395 | ||
2396 | if ((timer->index < AR_FIRST_NDP_TIMER) || | |
2397 | (timer->index >= ATH_MAX_GEN_TIMER)) { | |
2398 | return; | |
2399 | } | |
2400 | ||
2401 | /* Clear generic timer enable bits. */ | |
2402 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
2403 | gen_tmr_configuration[timer->index].mode_mask); | |
2404 | ||
2405 | /* Disable both trigger and thresh interrupt masks */ | |
2406 | REG_CLR_BIT(ah, AR_IMR_S5, | |
2407 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
2408 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
2409 | ||
2410 | clear_bit(timer->index, &timer_table->timer_mask.timer_bits); | |
ff155a45 | 2411 | } |
7322fd19 | 2412 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
ff155a45 VT |
2413 | |
2414 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) | |
2415 | { | |
2416 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2417 | ||
2418 | /* free the hardware generic timer slot */ | |
2419 | timer_table->timers[timer->index] = NULL; | |
2420 | kfree(timer); | |
2421 | } | |
7322fd19 | 2422 | EXPORT_SYMBOL(ath_gen_timer_free); |
ff155a45 VT |
2423 | |
2424 | /* | |
2425 | * Generic Timer Interrupts handling | |
2426 | */ | |
2427 | void ath_gen_timer_isr(struct ath_hw *ah) | |
2428 | { | |
2429 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2430 | struct ath_gen_timer *timer; | |
c46917bb | 2431 | struct ath_common *common = ath9k_hw_common(ah); |
ff155a45 VT |
2432 | u32 trigger_mask, thresh_mask, index; |
2433 | ||
2434 | /* get hardware generic timer interrupt status */ | |
2435 | trigger_mask = ah->intr_gen_timer_trigger; | |
2436 | thresh_mask = ah->intr_gen_timer_thresh; | |
2437 | trigger_mask &= timer_table->timer_mask.val; | |
2438 | thresh_mask &= timer_table->timer_mask.val; | |
2439 | ||
2440 | trigger_mask &= ~thresh_mask; | |
2441 | ||
2442 | while (thresh_mask) { | |
2443 | index = rightmost_index(timer_table, &thresh_mask); | |
2444 | timer = timer_table->timers[index]; | |
2445 | BUG_ON(!timer); | |
c46917bb LR |
2446 | ath_print(common, ATH_DBG_HWTIMER, |
2447 | "TSF overflow for Gen timer %d\n", index); | |
ff155a45 VT |
2448 | timer->overflow(timer->arg); |
2449 | } | |
2450 | ||
2451 | while (trigger_mask) { | |
2452 | index = rightmost_index(timer_table, &trigger_mask); | |
2453 | timer = timer_table->timers[index]; | |
2454 | BUG_ON(!timer); | |
c46917bb LR |
2455 | ath_print(common, ATH_DBG_HWTIMER, |
2456 | "Gen timer[%d] trigger\n", index); | |
ff155a45 VT |
2457 | timer->trigger(timer->arg); |
2458 | } | |
2459 | } | |
7322fd19 | 2460 | EXPORT_SYMBOL(ath_gen_timer_isr); |
2da4f01a | 2461 | |
05020d23 S |
2462 | /********/ |
2463 | /* HTC */ | |
2464 | /********/ | |
2465 | ||
2466 | void ath9k_hw_htc_resetinit(struct ath_hw *ah) | |
2467 | { | |
2468 | ah->htc_reset_init = true; | |
2469 | } | |
2470 | EXPORT_SYMBOL(ath9k_hw_htc_resetinit); | |
2471 | ||
2da4f01a LR |
2472 | static struct { |
2473 | u32 version; | |
2474 | const char * name; | |
2475 | } ath_mac_bb_names[] = { | |
2476 | /* Devices with external radios */ | |
2477 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
2478 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
2479 | { AR_SREV_VERSION_9100, "9100" }, | |
2480 | { AR_SREV_VERSION_9160, "9160" }, | |
2481 | /* Single-chip solutions */ | |
2482 | { AR_SREV_VERSION_9280, "9280" }, | |
2483 | { AR_SREV_VERSION_9285, "9285" }, | |
11158472 LR |
2484 | { AR_SREV_VERSION_9287, "9287" }, |
2485 | { AR_SREV_VERSION_9271, "9271" }, | |
ec83903e | 2486 | { AR_SREV_VERSION_9300, "9300" }, |
2da4f01a LR |
2487 | }; |
2488 | ||
2489 | /* For devices with external radios */ | |
2490 | static struct { | |
2491 | u16 version; | |
2492 | const char * name; | |
2493 | } ath_rf_names[] = { | |
2494 | { 0, "5133" }, | |
2495 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
2496 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
2497 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
2498 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
2499 | }; | |
2500 | ||
2501 | /* | |
2502 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
2503 | */ | |
f934c4d9 | 2504 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
2da4f01a LR |
2505 | { |
2506 | int i; | |
2507 | ||
2508 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
2509 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
2510 | return ath_mac_bb_names[i].name; | |
2511 | } | |
2512 | } | |
2513 | ||
2514 | return "????"; | |
2515 | } | |
2da4f01a LR |
2516 | |
2517 | /* | |
2518 | * Return the RF name. "????" is returned if the RF is unknown. | |
2519 | * Used for devices with external radios. | |
2520 | */ | |
f934c4d9 | 2521 | static const char *ath9k_hw_rf_name(u16 rf_version) |
2da4f01a LR |
2522 | { |
2523 | int i; | |
2524 | ||
2525 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
2526 | if (ath_rf_names[i].version == rf_version) { | |
2527 | return ath_rf_names[i].name; | |
2528 | } | |
2529 | } | |
2530 | ||
2531 | return "????"; | |
2532 | } | |
f934c4d9 LR |
2533 | |
2534 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) | |
2535 | { | |
2536 | int used; | |
2537 | ||
2538 | /* chipsets >= AR9280 are single-chip */ | |
7a37081e | 2539 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
f934c4d9 LR |
2540 | used = snprintf(hw_name, len, |
2541 | "Atheros AR%s Rev:%x", | |
2542 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
2543 | ah->hw_version.macRev); | |
2544 | } | |
2545 | else { | |
2546 | used = snprintf(hw_name, len, | |
2547 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", | |
2548 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
2549 | ah->hw_version.macRev, | |
2550 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & | |
2551 | AR_RADIO_SREV_MAJOR)), | |
2552 | ah->hw_version.phyRev); | |
2553 | } | |
2554 | ||
2555 | hw_name[used] = '\0'; | |
2556 | } | |
2557 | EXPORT_SYMBOL(ath9k_hw_name); |