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ath9k: use common read/write ops on pci and debug code
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
cfe8cba9 21#include "rc.h"
f078f209
LR		 22#include "initvals.h"
23
4febf7b8
LR		 24#define ATH9K_CLOCK_RATE_CCK 22
25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 27
cbe61d8a 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
25c56eec 29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
cbe61d8a 30static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072 31 struct ar5416_eeprom_def *pEepData,
f1dc5600 32 u32 reg, u32 value);
cbe61d8a
S		 33static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
34static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
f078f209 35
f1dc5600
S		 36/********************/
37/* Helper Functions */
38/********************/
f078f209 39
cbe61d8a 40static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
f1dc5600 41{
b002a4a9 42 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 43
2660b81a 44 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 45 return clks / ATH9K_CLOCK_RATE_CCK;
46 if (conf->channel->band == IEEE80211_BAND_2GHZ)
47 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
cbe61d8a 48
4febf7b8 49 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 50}
f078f209 51
cbe61d8a 52static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
f1dc5600 53{
b002a4a9 54 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 55
4febf7b8 56 if (conf_is_ht40(conf))
f1dc5600
S		 57 return ath9k_hw_mac_usec(ah, clks) / 2;
58 else
59 return ath9k_hw_mac_usec(ah, clks);
60}
f078f209 61
cbe61d8a 62static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 63{
b002a4a9 64 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 65
2660b81a 66 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 67 return usecs *ATH9K_CLOCK_RATE_CCK;
68 if (conf->channel->band == IEEE80211_BAND_2GHZ)
69 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
70 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 71}
72
cbe61d8a 73static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 74{
b002a4a9 75 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 76
4febf7b8 77 if (conf_is_ht40(conf))
f1dc5600
S		 78 return ath9k_hw_mac_clks(ah, usecs) * 2;
79 else
80 return ath9k_hw_mac_clks(ah, usecs);
81}
f078f209 82
0caa7b14 83bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 84{
85 int i;
86
0caa7b14
S		 87 BUG_ON(timeout < AH_TIME_QUANTUM);
88
89 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 90 if ((REG_READ(ah, reg) & mask) == val)
91 return true;
92
93 udelay(AH_TIME_QUANTUM);
94 }
04bd4638 95
c46917bb
LR		 96 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
97 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
98 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 99
f1dc5600 100 return false;
f078f209
LR		 101}
102
103u32 ath9k_hw_reverse_bits(u32 val, u32 n)
104{
105 u32 retval;
106 int i;
107
108 for (i = 0, retval = 0; i < n; i++) {
109 retval = (retval << 1) | (val & 1);
110 val >>= 1;
111 }
112 return retval;
113}
114
cbe61d8a 115bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 116 u16 flags, u16 *low,
117 u16 *high)
f078f209 118{
2660b81a 119 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 120
f1dc5600
S		 121 if (flags & CHANNEL_5GHZ) {
122 *low = pCap->low_5ghz_chan;
123 *high = pCap->high_5ghz_chan;
124 return true;
f078f209 125 }
f1dc5600
S		 126 if ((flags & CHANNEL_2GHZ)) {
127 *low = pCap->low_2ghz_chan;
128 *high = pCap->high_2ghz_chan;
129 return true;
130 }
131 return false;
f078f209
LR		 132}
133
cbe61d8a 134u16 ath9k_hw_computetxtime(struct ath_hw *ah,
4f0fc7c3 135 const struct ath_rate_table *rates,
f1dc5600
S		 136 u32 frameLen, u16 rateix,
137 bool shortPreamble)
f078f209 138{
f1dc5600
S		 139 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
140 u32 kbps;
f078f209 141
e63835b0 142 kbps = rates->info[rateix].ratekbps;
f078f209 143
f1dc5600
S		 144 if (kbps == 0)
145 return 0;
f078f209 146
f1dc5600 147 switch (rates->info[rateix].phy) {
46d14a58 148 case WLAN_RC_PHY_CCK:
f1dc5600 149 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
e63835b0 150 if (shortPreamble && rates->info[rateix].short_preamble)
f1dc5600
S		 151 phyTime >>= 1;
152 numBits = frameLen << 3;
153 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
154 break;
46d14a58 155 case WLAN_RC_PHY_OFDM:
2660b81a 156 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 157 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
158 numBits = OFDM_PLCP_BITS + (frameLen << 3);
159 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
160 txTime = OFDM_SIFS_TIME_QUARTER
161 + OFDM_PREAMBLE_TIME_QUARTER
162 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 163 } else if (ah->curchan &&
164 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 165 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
166 numBits = OFDM_PLCP_BITS + (frameLen << 3);
167 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
168 txTime = OFDM_SIFS_TIME_HALF +
169 OFDM_PREAMBLE_TIME_HALF
170 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
171 } else {
172 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
173 numBits = OFDM_PLCP_BITS + (frameLen << 3);
174 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
175 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
176 + (numSymbols * OFDM_SYMBOL_TIME);
177 }
178 break;
179 default:
c46917bb
LR		 180 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
181 "Unknown phy %u (rate ix %u)\n",
182 rates->info[rateix].phy, rateix);
f1dc5600
S		 183 txTime = 0;
184 break;
185 }
f078f209 186
f1dc5600
S		 187 return txTime;
188}
f078f209 189
cbe61d8a 190void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 191 struct ath9k_channel *chan,
192 struct chan_centers *centers)
f078f209 193{
f1dc5600 194 int8_t extoff;
f078f209 195
f1dc5600
S		 196 if (!IS_CHAN_HT40(chan)) {
197 centers->ctl_center = centers->ext_center =
198 centers->synth_center = chan->channel;
199 return;
f078f209 200 }
f078f209 201
f1dc5600
S		 202 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
203 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
204 centers->synth_center =
205 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
206 extoff = 1;
207 } else {
208 centers->synth_center =
209 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
210 extoff = -1;
211 }
f078f209 212
f1dc5600
S		 213 centers->ctl_center =
214 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 215 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 216 centers->ext_center =
6420014c 217 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 218}
219
f1dc5600
S		 220/******************/
221/* Chip Revisions */
222/******************/
223
cbe61d8a 224static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 225{
f1dc5600 226 u32 val;
f078f209 227
f1dc5600 228 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 229
f1dc5600
S		 230 if (val == 0xFF) {
231 val = REG_READ(ah, AR_SREV);
d535a42a
S		 232 ah->hw_version.macVersion =
233 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
234 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 235 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 236 } else {
237 if (!AR_SREV_9100(ah))
d535a42a 238 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 239
d535a42a 240 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 241
d535a42a 242 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 243 ah->is_pciexpress = true;
f1dc5600 244 }
f078f209
LR		 245}
246
cbe61d8a 247static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 248{
f1dc5600
S		 249 u32 val;
250 int i;
f078f209 251
f1dc5600 252 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 253
f1dc5600
S		 254 for (i = 0; i < 8; i++)
255 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
256 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
257 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 258
f1dc5600 259 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 260}
261
f1dc5600
S		 262/************************************/
263/* HW Attach, Detach, Init Routines */
264/************************************/
265
cbe61d8a 266static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 267{
feed029c 268 if (AR_SREV_9100(ah))
f1dc5600 269 return;
f078f209 270
f1dc5600
S		 271 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
272 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
273 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
274 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
275 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 280
f1dc5600 281 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 282}
283
cbe61d8a 284static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 285{
c46917bb 286 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 287 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
288 u32 regHold[2];
289 u32 patternData[4] = { 0x55555555,
290 0xaaaaaaaa,
291 0x66666666,
292 0x99999999 };
293 int i, j;
f078f209 294
f1dc5600
S		 295 for (i = 0; i < 2; i++) {
296 u32 addr = regAddr[i];
297 u32 wrData, rdData;
f078f209 298
f1dc5600
S		 299 regHold[i] = REG_READ(ah, addr);
300 for (j = 0; j < 0x100; j++) {
301 wrData = (j << 16) | j;
302 REG_WRITE(ah, addr, wrData);
303 rdData = REG_READ(ah, addr);
304 if (rdData != wrData) {
c46917bb
LR		 305 ath_print(common, ATH_DBG_FATAL,
306 "address test failed "
307 "addr: 0x%08x - wr:0x%08x != "
308 "rd:0x%08x\n",
309 addr, wrData, rdData);
f1dc5600
S		 310 return false;
311 }
312 }
313 for (j = 0; j < 4; j++) {
314 wrData = patternData[j];
315 REG_WRITE(ah, addr, wrData);
316 rdData = REG_READ(ah, addr);
317 if (wrData != rdData) {
c46917bb
LR		 318 ath_print(common, ATH_DBG_FATAL,
319 "address test failed "
320 "addr: 0x%08x - wr:0x%08x != "
321 "rd:0x%08x\n",
322 addr, wrData, rdData);
f1dc5600
S		 323 return false;
324 }
f078f209 325 }
f1dc5600 326 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 327 }
f1dc5600 328 udelay(100);
cbe61d8a 329
f078f209
LR		 330 return true;
331}
332
f1dc5600 333static const char *ath9k_hw_devname(u16 devid)
f078f209 334{
f1dc5600
S		 335 switch (devid) {
336 case AR5416_DEVID_PCI:
f1dc5600 337 return "Atheros 5416";
392dff83
BP		 338 case AR5416_DEVID_PCIE:
339 return "Atheros 5418";
f1dc5600
S		 340 case AR9160_DEVID_PCI:
341 return "Atheros 9160";
0c1aa495
GJ		 342 case AR5416_AR9100_DEVID:
343 return "Atheros 9100";
f1dc5600
S		 344 case AR9280_DEVID_PCI:
345 case AR9280_DEVID_PCIE:
346 return "Atheros 9280";
e7594072
SB		 347 case AR9285_DEVID_PCIE:
348 return "Atheros 9285";
ac88b6ec
VN		 349 case AR5416_DEVID_AR9287_PCI:
350 case AR5416_DEVID_AR9287_PCIE:
351 return "Atheros 9287";
f078f209
LR		 352 }
353
f1dc5600
S		 354 return NULL;
355}
f078f209 356
b8b0f377 357static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 358{
359 int i;
f078f209 360
2660b81a
S		 361 ah->config.dma_beacon_response_time = 2;
362 ah->config.sw_beacon_response_time = 10;
363 ah->config.additional_swba_backoff = 0;
364 ah->config.ack_6mb = 0x0;
365 ah->config.cwm_ignore_extcca = 0;
366 ah->config.pcie_powersave_enable = 0;
2660b81a 367 ah->config.pcie_clock_req = 0;
2660b81a
S		 368 ah->config.pcie_waen = 0;
369 ah->config.analog_shiftreg = 1;
370 ah->config.ht_enable = 1;
371 ah->config.ofdm_trig_low = 200;
372 ah->config.ofdm_trig_high = 500;
373 ah->config.cck_trig_high = 200;
374 ah->config.cck_trig_low = 100;
375 ah->config.enable_ani = 1;
1cf6873a 376 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
2660b81a 377 ah->config.antenna_switch_swap = 0;
f078f209 378
f1dc5600 379 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 380 ah->config.spurchans[i][0] = AR_NO_SPUR;
381 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 382 }
383
0ef1f168 384 ah->config.intr_mitigation = true;
6158425b
LR		 385
386 /*
387 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
388 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
389 * This means we use it for all AR5416 devices, and the few
390 * minor PCI AR9280 devices out there.
391 *
392 * Serialization is required because these devices do not handle
393 * well the case of two concurrent reads/writes due to the latency
394 * involved. During one read/write another read/write can be issued
395 * on another CPU while the previous read/write may still be working
396 * on our hardware, if we hit this case the hardware poops in a loop.
397 * We prevent this by serializing reads and writes.
398 *
399 * This issue is not present on PCI-Express devices or pre-AR5416
400 * devices (legacy, 802.11abg).
401 */
402 if (num_possible_cpus() > 1)
2d6a5e95 403 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 404}
405
50aca25b 406static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 407{
608b88cb
LR		 408 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
409
410 regulatory->country_code = CTRY_DEFAULT;
411 regulatory->power_limit = MAX_RATE_POWER;
412 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
413
d535a42a 414 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 415 ah->hw_version.subvendorid = 0;
f078f209
LR		 416
417 ah->ah_flags = 0;
8df5d1b7 418 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
d535a42a 419 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
f078f209
LR		 420 if (!AR_SREV_9100(ah))
421 ah->ah_flags = AH_USE_EEPROM;
422
2660b81a 423 ah->atim_window = 0;
2660b81a
S		 424 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
425 ah->beacon_interval = 100;
426 ah->enable_32kHz_clock = DONT_USE_32KHZ;
427 ah->slottime = (u32) -1;
428 ah->acktimeout = (u32) -1;
429 ah->ctstimeout = (u32) -1;
430 ah->globaltxtimeout = (u32) -1;
431
432 ah->gbeacon_rate = 0;
f078f209 433
cbdec975 434 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 435}
436
cbe61d8a 437static int ath9k_hw_rfattach(struct ath_hw *ah)
f078f209 438{
f1dc5600
S		 439 bool rfStatus = false;
440 int ecode = 0;
f078f209 441
f1dc5600
S		 442 rfStatus = ath9k_hw_init_rf(ah, &ecode);
443 if (!rfStatus) {
c46917bb
LR		 444 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
445 "RF setup failed, status: %u\n", ecode);
f1dc5600
S		 446 return ecode;
447 }
f078f209 448
f1dc5600 449 return 0;
f078f209
LR		 450}
451
cbe61d8a 452static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 453{
f1dc5600
S		 454 u32 val;
455
456 REG_WRITE(ah, AR_PHY(0), 0x00000007);
457
458 val = ath9k_hw_get_radiorev(ah);
459 switch (val & AR_RADIO_SREV_MAJOR) {
460 case 0:
461 val = AR_RAD5133_SREV_MAJOR;
462 break;
463 case AR_RAD5133_SREV_MAJOR:
464 case AR_RAD5122_SREV_MAJOR:
465 case AR_RAD2133_SREV_MAJOR:
466 case AR_RAD2122_SREV_MAJOR:
467 break;
f078f209 468 default:
c46917bb
LR		 469 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
470 "Radio Chip Rev 0x%02X not supported\n",
471 val & AR_RADIO_SREV_MAJOR);
f1dc5600 472 return -EOPNOTSUPP;
f078f209 473 }
f078f209 474
d535a42a 475 ah->hw_version.analog5GhzRev = val;
f078f209 476
f1dc5600 477 return 0;
f078f209
LR		 478}
479
cbe61d8a 480static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 481{
1510718d 482 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 483 u32 sum;
484 int i;
485 u16 eeval;
f078f209
LR		 486
487 sum = 0;
488 for (i = 0; i < 3; i++) {
f74df6fb 489 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 490 sum += eeval;
1510718d
LR		 491 common->macaddr[2 * i] = eeval >> 8;
492 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 493 }
d8baa939 494 if (sum == 0 || sum == 0xffff * 3)
f078f209 495 return -EADDRNOTAVAIL;
f078f209
LR		 496
497 return 0;
498}
499
cbe61d8a 500static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 501{
502 u32 rxgain_type;
9f804202 503
f74df6fb
S		 504 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
505 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 506
507 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 508 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 509 ar9280Modes_backoff_13db_rxgain_9280_2,
510 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
511 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 512 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 513 ar9280Modes_backoff_23db_rxgain_9280_2,
514 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
515 else
2660b81a 516 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 517 ar9280Modes_original_rxgain_9280_2,
518 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 519 } else {
2660b81a 520 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 521 ar9280Modes_original_rxgain_9280_2,
522 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 523 }
9f804202
SB		 524}
525
cbe61d8a 526static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 527{
528 u32 txgain_type;
9f804202 529
f74df6fb
S		 530 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
531 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 532
533 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 534 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 535 ar9280Modes_high_power_tx_gain_9280_2,
536 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
537 else
2660b81a 538 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 539 ar9280Modes_original_tx_gain_9280_2,
540 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 541 } else {
2660b81a 542 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 543 ar9280Modes_original_tx_gain_9280_2,
544 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 545 }
9f804202
SB		 546}
547
f637cfd6 548static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 549{
f1dc5600 550 int ecode;
f078f209 551
d8baa939 552 if (!ath9k_hw_chip_test(ah))
f1dc5600 553 return -ENODEV;
f078f209 554
f1dc5600
S		 555 ecode = ath9k_hw_rf_claim(ah);
556 if (ecode != 0)
f078f209 557 return ecode;
f078f209 558
f637cfd6 559 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 560 if (ecode != 0)
561 return ecode;
7d01b221 562
c46917bb
LR		 563 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
564 "Eeprom VER: %d, REV: %d\n",
565 ah->eep_ops->get_eeprom_ver(ah),
566 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 567
f1dc5600
S		 568 ecode = ath9k_hw_rfattach(ah);
569 if (ecode != 0)
570 return ecode;
f078f209 571
f1dc5600
S		 572 if (!AR_SREV_9100(ah)) {
573 ath9k_hw_ani_setup(ah);
f637cfd6 574 ath9k_hw_ani_init(ah);
f078f209
LR		 575 }
576
f078f209
LR		 577 return 0;
578}
579
ee2bb460
LR		 580static bool ath9k_hw_devid_supported(u16 devid)
581{
582 switch (devid) {
583 case AR5416_DEVID_PCI:
584 case AR5416_DEVID_PCIE:
585 case AR5416_AR9100_DEVID:
586 case AR9160_DEVID_PCI:
587 case AR9280_DEVID_PCI:
588 case AR9280_DEVID_PCIE:
589 case AR9285_DEVID_PCIE:
590 case AR5416_DEVID_AR9287_PCI:
591 case AR5416_DEVID_AR9287_PCIE:
592 return true;
593 default:
594 break;
595 }
596 return false;
597}
598
f9d4a668
LR		 599static bool ath9k_hw_macversion_supported(u32 macversion)
600{
601 switch (macversion) {
602 case AR_SREV_VERSION_5416_PCI:
603 case AR_SREV_VERSION_5416_PCIE:
604 case AR_SREV_VERSION_9160:
605 case AR_SREV_VERSION_9100:
606 case AR_SREV_VERSION_9280:
607 case AR_SREV_VERSION_9285:
608 case AR_SREV_VERSION_9287:
609 return true;
d7e7d229
LR		 610 /* Not yet */
611 case AR_SREV_VERSION_9271:
f9d4a668
LR		 612 default:
613 break;
614 }
615 return false;
616}
617
aa4058ae 618static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
f078f209 619{
f1dc5600
S		 620 if (AR_SREV_9160_10_OR_LATER(ah)) {
621 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a
S		 622 ah->iq_caldata.calData = &iq_cal_single_sample;
623 ah->adcgain_caldata.calData =
f1dc5600 624 &adc_gain_cal_single_sample;
2660b81a 625 ah->adcdc_caldata.calData =
f1dc5600 626 &adc_dc_cal_single_sample;
2660b81a 627 ah->adcdc_calinitdata.calData =
f1dc5600
S		 628 &adc_init_dc_cal;
629 } else {
2660b81a
S		 630 ah->iq_caldata.calData = &iq_cal_multi_sample;
631 ah->adcgain_caldata.calData =
f1dc5600 632 &adc_gain_cal_multi_sample;
2660b81a 633 ah->adcdc_caldata.calData =
f1dc5600 634 &adc_dc_cal_multi_sample;
2660b81a 635 ah->adcdc_calinitdata.calData =
f1dc5600
S		 636 &adc_init_dc_cal;
637 }
2660b81a 638 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
f1dc5600 639 }
aa4058ae 640}
f078f209 641
aa4058ae
LR		 642static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
643{
d7e7d229
LR		 644 if (AR_SREV_9271(ah)) {
645 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
646 ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
647 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
648 ARRAY_SIZE(ar9271Common_9271_1_0), 2);
649 return;
650 }
651
ac88b6ec
VN		 652 if (AR_SREV_9287_11_OR_LATER(ah)) {
653 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
654 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
655 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
656 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
657 if (ah->config.pcie_clock_req)
658 INIT_INI_ARRAY(&ah->iniPcieSerdes,
659 ar9287PciePhy_clkreq_off_L1_9287_1_1,
660 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
661 else
662 INIT_INI_ARRAY(&ah->iniPcieSerdes,
663 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
664 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
665 2);
666 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
667 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
668 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
669 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
670 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
671
672 if (ah->config.pcie_clock_req)
673 INIT_INI_ARRAY(&ah->iniPcieSerdes,
674 ar9287PciePhy_clkreq_off_L1_9287_1_0,
675 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
676 else
677 INIT_INI_ARRAY(&ah->iniPcieSerdes,
678 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
679 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
680 2);
681 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
f078f209 682
4e845168 683
2660b81a 684 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
e7594072 685 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
2660b81a 686 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
e7594072
SB		 687 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
688
2660b81a
S		 689 if (ah->config.pcie_clock_req) {
690 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 691 ar9285PciePhy_clkreq_off_L1_9285_1_2,
692 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
693 } else {
2660b81a 694 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 695 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
696 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
697 2);
698 }
699 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
2660b81a 700 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
e7594072 701 ARRAY_SIZE(ar9285Modes_9285), 6);
2660b81a 702 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
e7594072
SB		 703 ARRAY_SIZE(ar9285Common_9285), 2);
704
2660b81a
S		 705 if (ah->config.pcie_clock_req) {
706 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 707 ar9285PciePhy_clkreq_off_L1_9285,
708 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
709 } else {
2660b81a 710 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 711 ar9285PciePhy_clkreq_always_on_L1_9285,
712 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
713 }
714 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a 715 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
f1dc5600 716 ARRAY_SIZE(ar9280Modes_9280_2), 6);
2660b81a 717 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
f1dc5600 718 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 719
2660b81a
S		 720 if (ah->config.pcie_clock_req) {
721 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 722 ar9280PciePhy_clkreq_off_L1_9280,
723 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
724 } else {
2660b81a 725 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 726 ar9280PciePhy_clkreq_always_on_L1_9280,
727 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
728 }
2660b81a 729 INIT_INI_ARRAY(&ah->iniModesAdditional,
f1dc5600
S		 730 ar9280Modes_fast_clock_9280_2,
731 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
732 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 733 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
f1dc5600 734 ARRAY_SIZE(ar9280Modes_9280), 6);
2660b81a 735 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
f1dc5600
S		 736 ARRAY_SIZE(ar9280Common_9280), 2);
737 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2660b81a 738 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
f1dc5600 739 ARRAY_SIZE(ar5416Modes_9160), 6);
2660b81a 740 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
f1dc5600 741 ARRAY_SIZE(ar5416Common_9160), 2);
2660b81a 742 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
f1dc5600 743 ARRAY_SIZE(ar5416Bank0_9160), 2);
2660b81a 744 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
f1dc5600 745 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
2660b81a 746 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
f1dc5600 747 ARRAY_SIZE(ar5416Bank1_9160), 2);
2660b81a 748 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
f1dc5600 749 ARRAY_SIZE(ar5416Bank2_9160), 2);
2660b81a 750 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
f1dc5600 751 ARRAY_SIZE(ar5416Bank3_9160), 3);
2660b81a 752 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
f1dc5600 753 ARRAY_SIZE(ar5416Bank6_9160), 3);
2660b81a 754 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
f1dc5600 755 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
2660b81a 756 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
f1dc5600
S		 757 ARRAY_SIZE(ar5416Bank7_9160), 2);
758 if (AR_SREV_9160_11(ah)) {
2660b81a 759 INIT_INI_ARRAY(&ah->iniAddac,
f1dc5600
S		 760 ar5416Addac_91601_1,
761 ARRAY_SIZE(ar5416Addac_91601_1), 2);
762 } else {
2660b81a 763 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
f1dc5600
S		 764 ARRAY_SIZE(ar5416Addac_9160), 2);
765 }
766 } else if (AR_SREV_9100_OR_LATER(ah)) {
2660b81a 767 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
f1dc5600 768 ARRAY_SIZE(ar5416Modes_9100), 6);
2660b81a 769 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
f1dc5600 770 ARRAY_SIZE(ar5416Common_9100), 2);
2660b81a 771 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
f1dc5600 772 ARRAY_SIZE(ar5416Bank0_9100), 2);
2660b81a 773 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
f1dc5600 774 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
2660b81a 775 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
f1dc5600 776 ARRAY_SIZE(ar5416Bank1_9100), 2);
2660b81a 777 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
f1dc5600 778 ARRAY_SIZE(ar5416Bank2_9100), 2);
2660b81a 779 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
f1dc5600 780 ARRAY_SIZE(ar5416Bank3_9100), 3);
2660b81a 781 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
f1dc5600 782 ARRAY_SIZE(ar5416Bank6_9100), 3);
2660b81a 783 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
f1dc5600 784 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
2660b81a 785 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
f1dc5600 786 ARRAY_SIZE(ar5416Bank7_9100), 2);
2660b81a 787 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
f1dc5600
S		 788 ARRAY_SIZE(ar5416Addac_9100), 2);
789 } else {
2660b81a 790 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
f1dc5600 791 ARRAY_SIZE(ar5416Modes), 6);
2660b81a 792 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
f1dc5600 793 ARRAY_SIZE(ar5416Common), 2);
2660b81a 794 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
f1dc5600 795 ARRAY_SIZE(ar5416Bank0), 2);
2660b81a 796 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
f1dc5600 797 ARRAY_SIZE(ar5416BB_RfGain), 3);
2660b81a 798 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
f1dc5600 799 ARRAY_SIZE(ar5416Bank1), 2);
2660b81a 800 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
f1dc5600 801 ARRAY_SIZE(ar5416Bank2), 2);
2660b81a 802 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
f1dc5600 803 ARRAY_SIZE(ar5416Bank3), 3);
2660b81a 804 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
f1dc5600 805 ARRAY_SIZE(ar5416Bank6), 3);
2660b81a 806 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
f1dc5600 807 ARRAY_SIZE(ar5416Bank6TPC), 3);
2660b81a 808 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
f1dc5600 809 ARRAY_SIZE(ar5416Bank7), 2);
2660b81a 810 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
f1dc5600 811 ARRAY_SIZE(ar5416Addac), 2);
f078f209 812 }
aa4058ae 813}
f078f209 814
aa4058ae
LR		 815static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
816{
b37fa870 817 if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec
VN		 818 INIT_INI_ARRAY(&ah->iniModesRxGain,
819 ar9287Modes_rx_gain_9287_1_1,
820 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
821 else if (AR_SREV_9287_10(ah))
822 INIT_INI_ARRAY(&ah->iniModesRxGain,
823 ar9287Modes_rx_gain_9287_1_0,
824 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
825 else if (AR_SREV_9280_20(ah))
826 ath9k_hw_init_rxgain_ini(ah);
827
b37fa870 828 if (AR_SREV_9287_11_OR_LATER(ah)) {
ac88b6ec
VN		 829 INIT_INI_ARRAY(&ah->iniModesTxGain,
830 ar9287Modes_tx_gain_9287_1_1,
831 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
832 } else if (AR_SREV_9287_10(ah)) {
833 INIT_INI_ARRAY(&ah->iniModesTxGain,
834 ar9287Modes_tx_gain_9287_1_0,
835 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
836 } else if (AR_SREV_9280_20(ah)) {
837 ath9k_hw_init_txgain_ini(ah);
838 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4e845168
SB		 839 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
840
841 /* txgain table */
842 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
843 INIT_INI_ARRAY(&ah->iniModesTxGain,
844 ar9285Modes_high_power_tx_gain_9285_1_2,
845 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
846 } else {
847 INIT_INI_ARRAY(&ah->iniModesTxGain,
848 ar9285Modes_original_tx_gain_9285_1_2,
849 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
850 }
851
852 }
aa4058ae 853}
4e845168 854
aa4058ae
LR		 855static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
856{
857 u32 i, j;
06d0f066
S		 858
859 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
860 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
861
862 /* EEPROM Fixup */
2660b81a
S		 863 for (i = 0; i < ah->iniModes.ia_rows; i++) {
864 u32 reg = INI_RA(&ah->iniModes, i, 0);
f078f209 865
2660b81a
S		 866 for (j = 1; j < ah->iniModes.ia_columns; j++) {
867 u32 val = INI_RA(&ah->iniModes, i, j);
f078f209 868
2660b81a 869 INI_RA(&ah->iniModes, i, j) =
e7594072 870 ath9k_hw_ini_fixup(ah,
2660b81a 871 &ah->eeprom.def,
f1dc5600
S		 872 reg, val);
873 }
f078f209 874 }
f1dc5600 875 }
aa4058ae
LR		 876}
877
f637cfd6 878int ath9k_hw_init(struct ath_hw *ah)
aa4058ae 879{
c46917bb 880 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 881 int r = 0;
aa4058ae 882
95fafca2
LR		 883 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
884 return -EOPNOTSUPP;
aa4058ae
LR		 885
886 ath9k_hw_init_defaults(ah);
887 ath9k_hw_init_config(ah);
888
889 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 890 ath_print(common, ATH_DBG_FATAL,
891 "Couldn't reset chip\n");
95fafca2 892 return -EIO;
aa4058ae
LR		 893 }
894
9ecdef4b 895 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 896 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 897 return -EIO;
aa4058ae
LR		 898 }
899
900 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
901 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
902 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
903 ah->config.serialize_regmode =
904 SER_REG_MODE_ON;
905 } else {
906 ah->config.serialize_regmode =
907 SER_REG_MODE_OFF;
908 }
909 }
910
c46917bb 911 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 912 ah->config.serialize_regmode);
913
914 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
c46917bb
LR		 915 ath_print(common, ATH_DBG_FATAL,
916 "Mac Chip Rev 0x%02x.%x is not supported by "
917 "this driver\n", ah->hw_version.macVersion,
918 ah->hw_version.macRev);
95fafca2 919 return -EOPNOTSUPP;
aa4058ae
LR		 920 }
921
922 if (AR_SREV_9100(ah)) {
923 ah->iq_caldata.calData = &iq_cal_multi_sample;
924 ah->supp_cals = IQ_MISMATCH_CAL;
925 ah->is_pciexpress = false;
926 }
d7e7d229
LR		 927
928 if (AR_SREV_9271(ah))
929 ah->is_pciexpress = false;
930
aa4058ae
LR		 931 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
932
933 ath9k_hw_init_cal_settings(ah);
934
935 ah->ani_function = ATH9K_ANI_ALL;
936 if (AR_SREV_9280_10_OR_LATER(ah))
937 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
938
939 ath9k_hw_init_mode_regs(ah);
940
941 if (ah->is_pciexpress)
93b1b37f 942 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 943 else
944 ath9k_hw_disablepcie(ah);
945
193cd458
S		 946 /* Support for Japan ch.14 (2484) spread */
947 if (AR_SREV_9287_11_OR_LATER(ah)) {
948 INIT_INI_ARRAY(&ah->iniCckfirNormal,
949 ar9287Common_normal_cck_fir_coeff_92871_1,
950 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
951 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
952 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
953 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
954 }
955
f637cfd6 956 r = ath9k_hw_post_init(ah);
aa4058ae 957 if (r)
95fafca2 958 return r;
aa4058ae
LR		 959
960 ath9k_hw_init_mode_gain_regs(ah);
961 ath9k_hw_fill_cap_info(ah);
962 ath9k_hw_init_11a_eeprom_fix(ah);
f6688cd8 963
4f3acf81
LR		 964 r = ath9k_hw_init_macaddr(ah);
965 if (r) {
c46917bb
LR		 966 ath_print(common, ATH_DBG_FATAL,
967 "Failed to initialize MAC address\n");
95fafca2 968 return r;
f078f209
LR		 969 }
970
d7e7d229 971 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 972 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 973 else
2660b81a 974 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 975
f1dc5600 976 ath9k_init_nfcal_hist_buffer(ah);
f078f209 977
4f3acf81 978 return 0;
f078f209
LR		 979}
980
cbe61d8a 981static void ath9k_hw_init_bb(struct ath_hw *ah,
f1dc5600 982 struct ath9k_channel *chan)
f078f209 983{
f1dc5600 984 u32 synthDelay;
f078f209 985
f1dc5600 986 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 987 if (IS_CHAN_B(chan))
f1dc5600
S		 988 synthDelay = (4 * synthDelay) / 22;
989 else
990 synthDelay /= 10;
f078f209 991
f1dc5600 992 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 993
f1dc5600 994 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 995}
996
cbe61d8a 997static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 998{
f1dc5600
S		 999 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1000 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 1001
f1dc5600
S		 1002 REG_WRITE(ah, AR_QOS_NO_ACK,
1003 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1004 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1005 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1006
1007 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1008 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1009 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1010 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1011 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 1012}
1013
cbe61d8a 1014static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 1015 struct ath9k_channel *chan)
f078f209 1016{
f1dc5600 1017 u32 pll;
f078f209 1018
f1dc5600
S		 1019 if (AR_SREV_9100(ah)) {
1020 if (chan && IS_CHAN_5GHZ(chan))
1021 pll = 0x1450;
f078f209 1022 else
f1dc5600
S		 1023 pll = 0x1458;
1024 } else {
1025 if (AR_SREV_9280_10_OR_LATER(ah)) {
1026 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1027
f1dc5600
S		 1028 if (chan && IS_CHAN_HALF_RATE(chan))
1029 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1030 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1031 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1032
f1dc5600
S		 1033 if (chan && IS_CHAN_5GHZ(chan)) {
1034 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 1035
f078f209 1036
f1dc5600
S		 1037 if (AR_SREV_9280_20(ah)) {
1038 if (((chan->channel % 20) == 0)
1039 || ((chan->channel % 10) == 0))
1040 pll = 0x2850;
1041 else
1042 pll = 0x142c;
1043 }
1044 } else {
1045 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1046 }
f078f209 1047
f1dc5600 1048 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 1049
f1dc5600 1050 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1051
f1dc5600
S		 1052 if (chan && IS_CHAN_HALF_RATE(chan))
1053 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1054 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1055 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1056
f1dc5600
S		 1057 if (chan && IS_CHAN_5GHZ(chan))
1058 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1059 else
1060 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1061 } else {
1062 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 1063
f1dc5600
S		 1064 if (chan && IS_CHAN_HALF_RATE(chan))
1065 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1066 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1067 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 1068
f1dc5600
S		 1069 if (chan && IS_CHAN_5GHZ(chan))
1070 pll |= SM(0xa, AR_RTC_PLL_DIV);
1071 else
1072 pll |= SM(0xb, AR_RTC_PLL_DIV);
1073 }
1074 }
d03a66c1 1075 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 1076
f1dc5600
S		 1077 udelay(RTC_PLL_SETTLE_DELAY);
1078
1079 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1080}
1081
cbe61d8a 1082static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
f078f209 1083{
f078f209
LR		 1084 int rx_chainmask, tx_chainmask;
1085
2660b81a
S		 1086 rx_chainmask = ah->rxchainmask;
1087 tx_chainmask = ah->txchainmask;
f078f209
LR		 1088
1089 switch (rx_chainmask) {
1090 case 0x5:
1091 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1092 AR_PHY_SWAP_ALT_CHAIN);
1093 case 0x3:
d535a42a 1094 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
f078f209
LR		 1095 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1096 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1097 break;
1098 }
1099 case 0x1:
1100 case 0x2:
f078f209
LR		 1101 case 0x7:
1102 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1103 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1104 break;
1105 default:
1106 break;
1107 }
1108
1109 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1110 if (tx_chainmask == 0x5) {
1111 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1112 AR_PHY_SWAP_ALT_CHAIN);
1113 }
1114 if (AR_SREV_9100(ah))
1115 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1116 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1117}
1118
cbe61d8a 1119static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 1120 enum nl80211_iftype opmode)
f078f209 1121{
2660b81a 1122 ah->mask_reg = AR_IMR_TXERR |
f1dc5600
S		 1123 AR_IMR_TXURN |
1124 AR_IMR_RXERR |
1125 AR_IMR_RXORN |
1126 AR_IMR_BCNMISC;
f078f209 1127
0ef1f168 1128 if (ah->config.intr_mitigation)
2660b81a 1129 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1130 else
2660b81a 1131 ah->mask_reg |= AR_IMR_RXOK;
f078f209 1132
2660b81a 1133 ah->mask_reg |= AR_IMR_TXOK;
f078f209 1134
d97809db 1135 if (opmode == NL80211_IFTYPE_AP)
2660b81a 1136 ah->mask_reg |= AR_IMR_MIB;
f078f209 1137
2660b81a 1138 REG_WRITE(ah, AR_IMR, ah->mask_reg);
f1dc5600 1139 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1140
f1dc5600
S		 1141 if (!AR_SREV_9100(ah)) {
1142 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1143 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1144 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1145 }
f078f209
LR		 1146}
1147
cbe61d8a 1148static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1149{
f078f209 1150 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
c46917bb
LR		 1151 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1152 "bad ack timeout %u\n", us);
2660b81a 1153 ah->acktimeout = (u32) -1;
f078f209
LR		 1154 return false;
1155 } else {
1156 REG_RMW_FIELD(ah, AR_TIME_OUT,
1157 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1158 ah->acktimeout = us;
f078f209
LR		 1159 return true;
1160 }
1161}
1162
cbe61d8a 1163static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
f078f209 1164{
f078f209 1165 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
c46917bb
LR		 1166 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1167 "bad cts timeout %u\n", us);
2660b81a 1168 ah->ctstimeout = (u32) -1;
f078f209
LR		 1169 return false;
1170 } else {
1171 REG_RMW_FIELD(ah, AR_TIME_OUT,
1172 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1173 ah->ctstimeout = us;
f078f209
LR		 1174 return true;
1175 }
1176}
f1dc5600 1177
cbe61d8a 1178static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1179{
f078f209 1180 if (tu > 0xFFFF) {
c46917bb
LR		 1181 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1182 "bad global tx timeout %u\n", tu);
2660b81a 1183 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1184 return false;
1185 } else {
1186 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1187 ah->globaltxtimeout = tu;
f078f209
LR		 1188 return true;
1189 }
1190}
1191
cbe61d8a 1192static void ath9k_hw_init_user_settings(struct ath_hw *ah)
f078f209 1193{
c46917bb
LR		 1194 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1195 ah->misc_mode);
f078f209 1196
2660b81a 1197 if (ah->misc_mode != 0)
f1dc5600 1198 REG_WRITE(ah, AR_PCU_MISC,
2660b81a
S		 1199 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1200 if (ah->slottime != (u32) -1)
1201 ath9k_hw_setslottime(ah, ah->slottime);
1202 if (ah->acktimeout != (u32) -1)
1203 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1204 if (ah->ctstimeout != (u32) -1)
1205 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1206 if (ah->globaltxtimeout != (u32) -1)
1207 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600
S		 1208}
1209
1210const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1211{
1212 return vendorid == ATHEROS_VENDOR_ID ?
1213 ath9k_hw_devname(devid) : NULL;
1214}
1215
cbe61d8a 1216void ath9k_hw_detach(struct ath_hw *ah)
f1dc5600
S		 1217{
1218 if (!AR_SREV_9100(ah))
e70c0cfd 1219 ath9k_hw_ani_disable(ah);
f1dc5600 1220
081b35ab 1221 ath9k_hw_rf_free(ah);
9ecdef4b 1222 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1223 kfree(ah);
9db6b6a2 1224 ah = NULL;
f1dc5600
S		 1225}
1226
f1dc5600
S		 1227/*******/
1228/* INI */
1229/*******/
1230
cbe61d8a 1231static void ath9k_hw_override_ini(struct ath_hw *ah,
f1dc5600
S		 1232 struct ath9k_channel *chan)
1233{
d7e7d229
LR		 1234 u32 val;
1235
1236 if (AR_SREV_9271(ah)) {
1237 /*
1238 * Enable spectral scan to solution for issues with stuck
1239 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1240 * AR9271 1.1
1241 */
1242 if (AR_SREV_9271_10(ah)) {
1243 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1244 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1245 }
1246 else if (AR_SREV_9271_11(ah))
1247 /*
1248 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1249 * present on AR9271 1.1
1250 */
1251 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1252 return;
1253 }
1254
8aa15e15
SB		 1255 /*
1256 * Set the RX_ABORT and RX_DIS and clear if off only after
1257 * RXE is set for MAC. This prevents frames with corrupted
1258 * descriptor status.
1259 */
1260 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1261
204d7940
VT		 1262 if (AR_SREV_9280_10_OR_LATER(ah)) {
1263 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1264 (~AR_PCU_MISC_MODE2_HWWAR1);
1265
1266 if (AR_SREV_9287_10_OR_LATER(ah))
1267 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1268
1269 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1270 }
8aa15e15 1271
a8c96d3b 1272 if (!AR_SREV_5416_20_OR_LATER(ah) ||
f1dc5600
S		 1273 AR_SREV_9280_10_OR_LATER(ah))
1274 return;
d7e7d229
LR		 1275 /*
1276 * Disable BB clock gating
1277 * Necessary to avoid issues on AR5416 2.0
1278 */
f1dc5600 1279 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1280}
1281
cbe61d8a 1282static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
e7594072 1283 struct ar5416_eeprom_def *pEepData,
f1dc5600 1284 u32 reg, u32 value)
f078f209 1285{
f1dc5600 1286 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
c46917bb 1287 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1288
d535a42a 1289 switch (ah->hw_version.devid) {
f1dc5600
S		 1290 case AR9280_DEVID_PCI:
1291 if (reg == 0x7894) {
c46917bb 1292 ath_print(common, ATH_DBG_EEPROM,
f1dc5600
S		 1293 "ini VAL: %x EEPROM: %x\n", value,
1294 (pBase->version & 0xff));
1295
1296 if ((pBase->version & 0xff) > 0x0a) {
c46917bb
LR		 1297 ath_print(common, ATH_DBG_EEPROM,
1298 "PWDCLKIND: %d\n",
1299 pBase->pwdclkind);
f1dc5600
S		 1300 value &= ~AR_AN_TOP2_PWDCLKIND;
1301 value |= AR_AN_TOP2_PWDCLKIND &
1302 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1303 } else {
c46917bb
LR		 1304 ath_print(common, ATH_DBG_EEPROM,
1305 "PWDCLKIND Earlier Rev\n");
f1dc5600
S		 1306 }
1307
c46917bb
LR		 1308 ath_print(common, ATH_DBG_EEPROM,
1309 "final ini VAL: %x\n", value);
f1dc5600
S		 1310 }
1311 break;
1312 }
1313
1314 return value;
f078f209
LR		 1315}
1316
cbe61d8a 1317static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072
SB		 1318 struct ar5416_eeprom_def *pEepData,
1319 u32 reg, u32 value)
1320{
2660b81a 1321 if (ah->eep_map == EEP_MAP_4KBITS)
e7594072
SB		 1322 return value;
1323 else
1324 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1325}
1326
8bd1d07f
SB		 1327static void ath9k_olc_init(struct ath_hw *ah)
1328{
1329 u32 i;
1330
db91f2e4
VN		 1331 if (OLC_FOR_AR9287_10_LATER) {
1332 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1333 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1334 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1335 AR9287_AN_TXPC0_TXPCMODE,
1336 AR9287_AN_TXPC0_TXPCMODE_S,
1337 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1338 udelay(100);
1339 } else {
1340 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1341 ah->originalGain[i] =
1342 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1343 AR_PHY_TX_GAIN);
1344 ah->PDADCdelta = 0;
1345 }
8bd1d07f
SB		 1346}
1347
3a702e49
BC		 1348static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1349 struct ath9k_channel *chan)
1350{
1351 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1352
1353 if (IS_CHAN_B(chan))
1354 ctl |= CTL_11B;
1355 else if (IS_CHAN_G(chan))
1356 ctl |= CTL_11G;
1357 else
1358 ctl |= CTL_11A;
1359
1360 return ctl;
1361}
1362
cbe61d8a 1363static int ath9k_hw_process_ini(struct ath_hw *ah,
25c56eec 1364 struct ath9k_channel *chan)
f078f209 1365{
608b88cb 1366 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f078f209 1367 int i, regWrites = 0;
5f8e077c 1368 struct ieee80211_channel *channel = chan->chan;
f078f209 1369 u32 modesIndex, freqIndex;
f078f209
LR		 1370
1371 switch (chan->chanmode) {
1372 case CHANNEL_A:
1373 case CHANNEL_A_HT20:
1374 modesIndex = 1;
1375 freqIndex = 1;
1376 break;
1377 case CHANNEL_A_HT40PLUS:
1378 case CHANNEL_A_HT40MINUS:
1379 modesIndex = 2;
1380 freqIndex = 1;
1381 break;
1382 case CHANNEL_G:
1383 case CHANNEL_G_HT20:
1384 case CHANNEL_B:
1385 modesIndex = 4;
1386 freqIndex = 2;
1387 break;
1388 case CHANNEL_G_HT40PLUS:
1389 case CHANNEL_G_HT40MINUS:
1390 modesIndex = 3;
1391 freqIndex = 2;
1392 break;
1393
1394 default:
1395 return -EINVAL;
1396 }
1397
1398 REG_WRITE(ah, AR_PHY(0), 0x00000007);
f078f209 1399 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
f74df6fb 1400 ah->eep_ops->set_addac(ah, chan);
f078f209 1401
a8c96d3b 1402 if (AR_SREV_5416_22_OR_LATER(ah)) {
2660b81a 1403 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
f078f209
LR		 1404 } else {
1405 struct ar5416IniArray temp;
1406 u32 addacSize =
2660b81a
S		 1407 sizeof(u32) * ah->iniAddac.ia_rows *
1408 ah->iniAddac.ia_columns;
f078f209 1409
2660b81a
S		 1410 memcpy(ah->addac5416_21,
1411 ah->iniAddac.ia_array, addacSize);
f078f209 1412
2660b81a 1413 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
f078f209 1414
2660b81a
S		 1415 temp.ia_array = ah->addac5416_21;
1416 temp.ia_columns = ah->iniAddac.ia_columns;
1417 temp.ia_rows = ah->iniAddac.ia_rows;
f078f209
LR		 1418 REG_WRITE_ARRAY(&temp, 1, regWrites);
1419 }
f1dc5600 1420
f078f209
LR		 1421 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1422
2660b81a
S		 1423 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1424 u32 reg = INI_RA(&ah->iniModes, i, 0);
1425 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
f078f209 1426
f078f209
LR		 1427 REG_WRITE(ah, reg, val);
1428
1429 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1430 && ah->config.analog_shiftreg) {
f078f209
LR		 1431 udelay(100);
1432 }
1433
1434 DO_DELAY(regWrites);
1435 }
1436
ac88b6ec 1437 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1438 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
9f804202 1439
ac88b6ec
VN		 1440 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1441 AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1442 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
9f804202 1443
2660b81a
S		 1444 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1445 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1446 u32 val = INI_RA(&ah->iniCommon, i, 1);
f078f209
LR		 1447
1448 REG_WRITE(ah, reg, val);
1449
1450 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1451 && ah->config.analog_shiftreg) {
f078f209
LR		 1452 udelay(100);
1453 }
1454
1455 DO_DELAY(regWrites);
1456 }
1457
1458 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1459
1460 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
2660b81a 1461 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
f078f209
LR		 1462 regWrites);
1463 }
1464
1465 ath9k_hw_override_ini(ah, chan);
25c56eec 1466 ath9k_hw_set_regs(ah, chan);
f078f209
LR		 1467 ath9k_hw_init_chain_masks(ah);
1468
8bd1d07f
SB		 1469 if (OLC_FOR_AR9280_20_LATER)
1470 ath9k_olc_init(ah);
1471
8fbff4b8 1472 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1473 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 1474 channel->max_antenna_gain * 2,
1475 channel->max_power * 2,
1476 min((u32) MAX_RATE_POWER,
608b88cb 1477 (u32) regulatory->power_limit));
f078f209
LR		 1478
1479 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
c46917bb
LR		 1480 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1481 "ar5416SetRfRegs failed\n");
f078f209
LR		 1482 return -EIO;
1483 }
1484
1485 return 0;
1486}
1487
f1dc5600
S		 1488/****************************************/
1489/* Reset and Channel Switching Routines */
1490/****************************************/
1491
cbe61d8a 1492static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1493{
f1dc5600
S		 1494 u32 rfMode = 0;
1495
1496 if (chan == NULL)
1497 return;
1498
1499 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1500 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1501
1502 if (!AR_SREV_9280_10_OR_LATER(ah))
1503 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1504 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1505
1506 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1507 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1508
1509 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1510}
1511
cbe61d8a 1512static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
f1dc5600
S		 1513{
1514 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1515}
1516
cbe61d8a 1517static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 1518{
1519 u32 regval;
1520
d7e7d229
LR		 1521 /*
1522 * set AHB_MODE not to do cacheline prefetches
1523 */
f1dc5600
S		 1524 regval = REG_READ(ah, AR_AHB_MODE);
1525 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1526
d7e7d229
LR		 1527 /*
1528 * let mac dma reads be in 128 byte chunks
1529 */
f1dc5600
S		 1530 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1531 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1532
d7e7d229
LR		 1533 /*
1534 * Restore TX Trigger Level to its pre-reset value.
1535 * The initial value depends on whether aggregation is enabled, and is
1536 * adjusted whenever underruns are detected.
1537 */
2660b81a 1538 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1539
d7e7d229
LR		 1540 /*
1541 * let mac dma writes be in 128 byte chunks
1542 */
f1dc5600
S		 1543 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1544 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1545
d7e7d229
LR		 1546 /*
1547 * Setup receive FIFO threshold to hold off TX activities
1548 */
f1dc5600
S		 1549 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1550
d7e7d229
LR		 1551 /*
1552 * reduce the number of usable entries in PCU TXBUF to avoid
1553 * wrap around issues.
1554 */
f1dc5600 1555 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1556 /* For AR9285 the number of Fifos are reduced to half.
1557 * So set the usable tx buf size also to half to
1558 * avoid data/delimiter underruns
1559 */
f1dc5600
S		 1560 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1561 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1562 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1563 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1564 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1565 }
1566}
1567
cbe61d8a 1568static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1569{
1570 u32 val;
1571
1572 val = REG_READ(ah, AR_STA_ID1);
1573 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1574 switch (opmode) {
d97809db 1575 case NL80211_IFTYPE_AP:
f1dc5600
S		 1576 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1577 | AR_STA_ID1_KSRCH_MODE);
1578 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1579 break;
d97809db 1580 case NL80211_IFTYPE_ADHOC:
9cb5412b 1581 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 1582 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1583 | AR_STA_ID1_KSRCH_MODE);
1584 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1585 break;
d97809db
CM		 1586 case NL80211_IFTYPE_STATION:
1587 case NL80211_IFTYPE_MONITOR:
f1dc5600 1588 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1589 break;
f1dc5600
S		 1590 }
1591}
1592
cbe61d8a 1593static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
f1dc5600
S		 1594 u32 coef_scaled,
1595 u32 *coef_mantissa,
1596 u32 *coef_exponent)
1597{
1598 u32 coef_exp, coef_man;
1599
1600 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1601 if ((coef_scaled >> coef_exp) & 0x1)
1602 break;
1603
1604 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1605
1606 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1607
1608 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1609 *coef_exponent = coef_exp - 16;
1610}
1611
cbe61d8a 1612static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
f1dc5600
S		 1613 struct ath9k_channel *chan)
1614{
1615 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1616 u32 clockMhzScaled = 0x64000000;
1617 struct chan_centers centers;
1618
1619 if (IS_CHAN_HALF_RATE(chan))
1620 clockMhzScaled = clockMhzScaled >> 1;
1621 else if (IS_CHAN_QUARTER_RATE(chan))
1622 clockMhzScaled = clockMhzScaled >> 2;
1623
1624 ath9k_hw_get_channel_centers(ah, chan, &centers);
1625 coef_scaled = clockMhzScaled / centers.synth_center;
1626
1627 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1628 &ds_coef_exp);
1629
1630 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1631 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1632 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1633 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1634
1635 coef_scaled = (9 * coef_scaled) / 10;
1636
1637 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1638 &ds_coef_exp);
1639
1640 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1641 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1642 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1643 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1644}
1645
cbe61d8a 1646static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1647{
1648 u32 rst_flags;
1649 u32 tmpReg;
1650
70768496
S		 1651 if (AR_SREV_9100(ah)) {
1652 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1653 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1654 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1655 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1656 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1657 }
1658
f1dc5600
S		 1659 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1660 AR_RTC_FORCE_WAKE_ON_INT);
1661
1662 if (AR_SREV_9100(ah)) {
1663 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1664 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1665 } else {
1666 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1667 if (tmpReg &
1668 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1669 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1670 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1671 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1672 } else {
1673 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1674 }
1675
1676 rst_flags = AR_RTC_RC_MAC_WARM;
1677 if (type == ATH9K_RESET_COLD)
1678 rst_flags |= AR_RTC_RC_MAC_COLD;
1679 }
1680
d03a66c1 1681 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1682 udelay(50);
1683
d03a66c1 1684 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1685 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1686 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1687 "RTC stuck in MAC reset\n");
f1dc5600
S		 1688 return false;
1689 }
1690
1691 if (!AR_SREV_9100(ah))
1692 REG_WRITE(ah, AR_RC, 0);
1693
f1dc5600
S		 1694 if (AR_SREV_9100(ah))
1695 udelay(50);
1696
1697 return true;
1698}
1699
cbe61d8a 1700static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1701{
1702 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1703 AR_RTC_FORCE_WAKE_ON_INT);
1704
1c29ce67
VT		 1705 if (!AR_SREV_9100(ah))
1706 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1707
d03a66c1 1708 REG_WRITE(ah, AR_RTC_RESET, 0);
8bd1d07f 1709 udelay(2);
1c29ce67
VT		 1710
1711 if (!AR_SREV_9100(ah))
1712 REG_WRITE(ah, AR_RC, 0);
1713
d03a66c1 1714 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1715
1716 if (!ath9k_hw_wait(ah,
1717 AR_RTC_STATUS,
1718 AR_RTC_STATUS_M,
0caa7b14
S		 1719 AR_RTC_STATUS_ON,
1720 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1721 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1722 "RTC not waking up\n");
f1dc5600 1723 return false;
f078f209
LR		 1724 }
1725
f1dc5600
S		 1726 ath9k_hw_read_revisions(ah);
1727
1728 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1729}
1730
cbe61d8a 1731static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1732{
1733 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1734 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1735
1736 switch (type) {
1737 case ATH9K_RESET_POWER_ON:
1738 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1739 case ATH9K_RESET_WARM:
1740 case ATH9K_RESET_COLD:
1741 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1742 default:
1743 return false;
1744 }
f078f209
LR		 1745}
1746
25c56eec 1747static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1748{
f1dc5600 1749 u32 phymode;
e7594072 1750 u32 enableDacFifo = 0;
f078f209 1751
e7594072
SB		 1752 if (AR_SREV_9285_10_OR_LATER(ah))
1753 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1754 AR_PHY_FC_ENABLE_DAC_FIFO);
1755
f1dc5600 1756 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1757 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1758
1759 if (IS_CHAN_HT40(chan)) {
1760 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1761
f1dc5600
S		 1762 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1763 (chan->chanmode == CHANNEL_G_HT40PLUS))
1764 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1765
f078f209 1766 }
f1dc5600
S		 1767 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1768
25c56eec 1769 ath9k_hw_set11nmac2040(ah);
f078f209 1770
f1dc5600
S		 1771 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1772 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1773}
1774
cbe61d8a 1775static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1776 struct ath9k_channel *chan)
f078f209 1777{
42abfbee 1778 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1779 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1780 return false;
1781 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1782 return false;
f078f209 1783
9ecdef4b 1784 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1785 return false;
f078f209 1786
2660b81a 1787 ah->chip_fullsleep = false;
f1dc5600 1788 ath9k_hw_init_pll(ah, chan);
f1dc5600 1789 ath9k_hw_set_rfmode(ah, chan);
f078f209 1790
f1dc5600 1791 return true;
f078f209
LR		 1792}
1793
cbe61d8a 1794static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1795 struct ath9k_channel *chan)
f078f209 1796{
608b88cb 1797 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1798 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1799 struct ieee80211_channel *channel = chan->chan;
f078f209 1800 u32 synthDelay, qnum;
f078f209
LR		 1801
1802 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1803 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1804 ath_print(common, ATH_DBG_QUEUE,
1805 "Transmit frames pending on "
1806 "queue %d\n", qnum);
f078f209
LR		 1807 return false;
1808 }
1809 }
1810
1811 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1812 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
0caa7b14 1813 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1814 ath_print(common, ATH_DBG_FATAL,
1815 "Could not kill baseband RX\n");
f078f209
LR		 1816 return false;
1817 }
1818
25c56eec 1819 ath9k_hw_set_regs(ah, chan);
f078f209
LR		 1820
1821 if (AR_SREV_9280_10_OR_LATER(ah)) {
8fbff4b8 1822 ath9k_hw_ar9280_set_channel(ah, chan);
f078f209
LR		 1823 } else {
1824 if (!(ath9k_hw_set_channel(ah, chan))) {
c46917bb
LR		 1825 ath_print(common, ATH_DBG_FATAL,
1826 "Failed to set channel\n");
f078f209
LR		 1827 return false;
1828 }
1829 }
1830
8fbff4b8 1831 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1832 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1833 channel->max_antenna_gain * 2,
1834 channel->max_power * 2,
1835 min((u32) MAX_RATE_POWER,
608b88cb 1836 (u32) regulatory->power_limit));
f078f209
LR		 1837
1838 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1839 if (IS_CHAN_B(chan))
f078f209
LR		 1840 synthDelay = (4 * synthDelay) / 22;
1841 else
1842 synthDelay /= 10;
1843
1844 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1845
1846 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1847
f1dc5600
S		 1848 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1849 ath9k_hw_set_delta_slope(ah, chan);
1850
1851 if (AR_SREV_9280_10_OR_LATER(ah))
1852 ath9k_hw_9280_spur_mitigate(ah, chan);
1853 else
1854 ath9k_hw_spur_mitigate(ah, chan);
1855
1856 if (!chan->oneTimeCalsDone)
1857 chan->oneTimeCalsDone = true;
1858
1859 return true;
1860}
1861
cbe61d8a 1862static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 1863{
1864 int bb_spur = AR_NO_SPUR;
1865 int freq;
1866 int bin, cur_bin;
1867 int bb_spur_off, spur_subchannel_sd;
1868 int spur_freq_sd;
1869 int spur_delta_phase;
1870 int denominator;
1871 int upper, lower, cur_vit_mask;
1872 int tmp, newVal;
1873 int i;
1874 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1875 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1876 };
1877 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1878 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1879 };
1880 int inc[4] = { 0, 100, 0, 0 };
1881 struct chan_centers centers;
1882
1883 int8_t mask_m[123];
1884 int8_t mask_p[123];
1885 int8_t mask_amt;
1886 int tmp_mask;
1887 int cur_bb_spur;
1888 bool is2GHz = IS_CHAN_2GHZ(chan);
1889
1890 memset(&mask_m, 0, sizeof(int8_t) * 123);
1891 memset(&mask_p, 0, sizeof(int8_t) * 123);
1892
1893 ath9k_hw_get_channel_centers(ah, chan, &centers);
1894 freq = centers.synth_center;
1895
2660b81a 1896 ah->config.spurmode = SPUR_ENABLE_EEPROM;
f1dc5600 1897 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 1898 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 1899
1900 if (is2GHz)
1901 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1902 else
1903 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1904
1905 if (AR_NO_SPUR == cur_bb_spur)
1906 break;
1907 cur_bb_spur = cur_bb_spur - freq;
1908
1909 if (IS_CHAN_HT40(chan)) {
1910 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1911 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1912 bb_spur = cur_bb_spur;
1913 break;
1914 }
1915 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1916 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1917 bb_spur = cur_bb_spur;
1918 break;
1919 }
1920 }
1921
1922 if (AR_NO_SPUR == bb_spur) {
1923 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1924 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1925 return;
1926 } else {
1927 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1928 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1929 }
1930
1931 bin = bb_spur * 320;
1932
1933 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1934
1935 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1936 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1937 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1938 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1939 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1940
1941 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1942 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1943 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1944 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1945 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1946 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1947
1948 if (IS_CHAN_HT40(chan)) {
1949 if (bb_spur < 0) {
1950 spur_subchannel_sd = 1;
1951 bb_spur_off = bb_spur + 10;
1952 } else {
1953 spur_subchannel_sd = 0;
1954 bb_spur_off = bb_spur - 10;
1955 }
1956 } else {
1957 spur_subchannel_sd = 0;
1958 bb_spur_off = bb_spur;
1959 }
1960
1961 if (IS_CHAN_HT40(chan))
1962 spur_delta_phase =
1963 ((bb_spur * 262144) /
1964 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1965 else
1966 spur_delta_phase =
1967 ((bb_spur * 524288) /
1968 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1969
1970 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1971 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1972
1973 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1974 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1975 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1976 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1977
1978 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1979 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1980
1981 cur_bin = -6000;
1982 upper = bin + 100;
1983 lower = bin - 100;
1984
1985 for (i = 0; i < 4; i++) {
1986 int pilot_mask = 0;
1987 int chan_mask = 0;
1988 int bp = 0;
1989 for (bp = 0; bp < 30; bp++) {
1990 if ((cur_bin > lower) && (cur_bin < upper)) {
1991 pilot_mask = pilot_mask | 0x1 << bp;
1992 chan_mask = chan_mask | 0x1 << bp;
1993 }
1994 cur_bin += 100;
1995 }
1996 cur_bin += inc[i];
1997 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1998 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1999 }
2000
2001 cur_vit_mask = 6100;
2002 upper = bin + 120;
2003 lower = bin - 120;
2004
2005 for (i = 0; i < 123; i++) {
2006 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2007
2008 /* workaround for gcc bug #37014 */
a085ff71 2009 volatile int tmp_v = abs(cur_vit_mask - bin);
f1dc5600 2010
a085ff71 2011 if (tmp_v < 75)
f1dc5600
S		 2012 mask_amt = 1;
2013 else
2014 mask_amt = 0;
2015 if (cur_vit_mask < 0)
2016 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2017 else
2018 mask_p[cur_vit_mask / 100] = mask_amt;
2019 }
2020 cur_vit_mask -= 100;
2021 }
2022
2023 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2024 | (mask_m[48] << 26) | (mask_m[49] << 24)
2025 | (mask_m[50] << 22) | (mask_m[51] << 20)
2026 | (mask_m[52] << 18) | (mask_m[53] << 16)
2027 | (mask_m[54] << 14) | (mask_m[55] << 12)
2028 | (mask_m[56] << 10) | (mask_m[57] << 8)
2029 | (mask_m[58] << 6) | (mask_m[59] << 4)
2030 | (mask_m[60] << 2) | (mask_m[61] << 0);
2031 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2032 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2033
2034 tmp_mask = (mask_m[31] << 28)
2035 | (mask_m[32] << 26) | (mask_m[33] << 24)
2036 | (mask_m[34] << 22) | (mask_m[35] << 20)
2037 | (mask_m[36] << 18) | (mask_m[37] << 16)
2038 | (mask_m[48] << 14) | (mask_m[39] << 12)
2039 | (mask_m[40] << 10) | (mask_m[41] << 8)
2040 | (mask_m[42] << 6) | (mask_m[43] << 4)
2041 | (mask_m[44] << 2) | (mask_m[45] << 0);
2042 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2043 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2044
2045 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2046 | (mask_m[18] << 26) | (mask_m[18] << 24)
2047 | (mask_m[20] << 22) | (mask_m[20] << 20)
2048 | (mask_m[22] << 18) | (mask_m[22] << 16)
2049 | (mask_m[24] << 14) | (mask_m[24] << 12)
2050 | (mask_m[25] << 10) | (mask_m[26] << 8)
2051 | (mask_m[27] << 6) | (mask_m[28] << 4)
2052 | (mask_m[29] << 2) | (mask_m[30] << 0);
2053 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2054 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2055
2056 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2057 | (mask_m[2] << 26) | (mask_m[3] << 24)
2058 | (mask_m[4] << 22) | (mask_m[5] << 20)
2059 | (mask_m[6] << 18) | (mask_m[7] << 16)
2060 | (mask_m[8] << 14) | (mask_m[9] << 12)
2061 | (mask_m[10] << 10) | (mask_m[11] << 8)
2062 | (mask_m[12] << 6) | (mask_m[13] << 4)
2063 | (mask_m[14] << 2) | (mask_m[15] << 0);
2064 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2065 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2066
2067 tmp_mask = (mask_p[15] << 28)
2068 | (mask_p[14] << 26) | (mask_p[13] << 24)
2069 | (mask_p[12] << 22) | (mask_p[11] << 20)
2070 | (mask_p[10] << 18) | (mask_p[9] << 16)
2071 | (mask_p[8] << 14) | (mask_p[7] << 12)
2072 | (mask_p[6] << 10) | (mask_p[5] << 8)
2073 | (mask_p[4] << 6) | (mask_p[3] << 4)
2074 | (mask_p[2] << 2) | (mask_p[1] << 0);
2075 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2076 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2077
f1dc5600
S		 2078 tmp_mask = (mask_p[30] << 28)
2079 | (mask_p[29] << 26) | (mask_p[28] << 24)
2080 | (mask_p[27] << 22) | (mask_p[26] << 20)
2081 | (mask_p[25] << 18) | (mask_p[24] << 16)
2082 | (mask_p[23] << 14) | (mask_p[22] << 12)
2083 | (mask_p[21] << 10) | (mask_p[20] << 8)
2084 | (mask_p[19] << 6) | (mask_p[18] << 4)
2085 | (mask_p[17] << 2) | (mask_p[16] << 0);
2086 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2087 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2088
f1dc5600
S		 2089 tmp_mask = (mask_p[45] << 28)
2090 | (mask_p[44] << 26) | (mask_p[43] << 24)
2091 | (mask_p[42] << 22) | (mask_p[41] << 20)
2092 | (mask_p[40] << 18) | (mask_p[39] << 16)
2093 | (mask_p[38] << 14) | (mask_p[37] << 12)
2094 | (mask_p[36] << 10) | (mask_p[35] << 8)
2095 | (mask_p[34] << 6) | (mask_p[33] << 4)
2096 | (mask_p[32] << 2) | (mask_p[31] << 0);
2097 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2098 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2099
f1dc5600
S		 2100 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2101 | (mask_p[59] << 26) | (mask_p[58] << 24)
2102 | (mask_p[57] << 22) | (mask_p[56] << 20)
2103 | (mask_p[55] << 18) | (mask_p[54] << 16)
2104 | (mask_p[53] << 14) | (mask_p[52] << 12)
2105 | (mask_p[51] << 10) | (mask_p[50] << 8)
2106 | (mask_p[49] << 6) | (mask_p[48] << 4)
2107 | (mask_p[47] << 2) | (mask_p[46] << 0);
2108 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2109 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2110}
2111
cbe61d8a 2112static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 2113{
f1dc5600
S		 2114 int bb_spur = AR_NO_SPUR;
2115 int bin, cur_bin;
2116 int spur_freq_sd;
2117 int spur_delta_phase;
2118 int denominator;
2119 int upper, lower, cur_vit_mask;
2120 int tmp, new;
2121 int i;
2122 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2123 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2124 };
2125 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2126 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2127 };
2128 int inc[4] = { 0, 100, 0, 0 };
f078f209 2129
f1dc5600
S		 2130 int8_t mask_m[123];
2131 int8_t mask_p[123];
2132 int8_t mask_amt;
2133 int tmp_mask;
2134 int cur_bb_spur;
2135 bool is2GHz = IS_CHAN_2GHZ(chan);
f078f209 2136
f1dc5600
S		 2137 memset(&mask_m, 0, sizeof(int8_t) * 123);
2138 memset(&mask_p, 0, sizeof(int8_t) * 123);
f078f209 2139
f1dc5600 2140 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 2141 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 2142 if (AR_NO_SPUR == cur_bb_spur)
2143 break;
2144 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2145 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2146 bb_spur = cur_bb_spur;
2147 break;
2148 }
2149 }
f078f209 2150
f1dc5600
S		 2151 if (AR_NO_SPUR == bb_spur)
2152 return;
f078f209 2153
f1dc5600 2154 bin = bb_spur * 32;
f078f209 2155
f1dc5600
S		 2156 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2157 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2158 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2159 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2160 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
f078f209 2161
f1dc5600 2162 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
f078f209 2163
f1dc5600
S		 2164 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2165 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2166 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2167 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2168 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2169 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
f078f209 2170
f1dc5600
S		 2171 spur_delta_phase = ((bb_spur * 524288) / 100) &
2172 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
f078f209 2173
f1dc5600
S		 2174 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2175 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
f078f209 2176
f1dc5600
S		 2177 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2178 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2179 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2180 REG_WRITE(ah, AR_PHY_TIMING11, new);
f078f209 2181
f1dc5600
S		 2182 cur_bin = -6000;
2183 upper = bin + 100;
2184 lower = bin - 100;
f078f209 2185
f1dc5600
S		 2186 for (i = 0; i < 4; i++) {
2187 int pilot_mask = 0;
2188 int chan_mask = 0;
2189 int bp = 0;
2190 for (bp = 0; bp < 30; bp++) {
2191 if ((cur_bin > lower) && (cur_bin < upper)) {
2192 pilot_mask = pilot_mask | 0x1 << bp;
2193 chan_mask = chan_mask | 0x1 << bp;
2194 }
2195 cur_bin += 100;
2196 }
2197 cur_bin += inc[i];
2198 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2199 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
f078f209 2200 }
f078f209 2201
f1dc5600
S		 2202 cur_vit_mask = 6100;
2203 upper = bin + 120;
2204 lower = bin - 120;
f078f209 2205
f1dc5600
S		 2206 for (i = 0; i < 123; i++) {
2207 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
f078f209 2208
f1dc5600 2209 /* workaround for gcc bug #37014 */
a085ff71 2210 volatile int tmp_v = abs(cur_vit_mask - bin);
f078f209 2211
a085ff71 2212 if (tmp_v < 75)
f1dc5600
S		 2213 mask_amt = 1;
2214 else
2215 mask_amt = 0;
2216 if (cur_vit_mask < 0)
2217 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2218 else
2219 mask_p[cur_vit_mask / 100] = mask_amt;
2220 }
2221 cur_vit_mask -= 100;
f078f209
LR		 2222 }
2223
f1dc5600
S		 2224 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2225 | (mask_m[48] << 26) | (mask_m[49] << 24)
2226 | (mask_m[50] << 22) | (mask_m[51] << 20)
2227 | (mask_m[52] << 18) | (mask_m[53] << 16)
2228 | (mask_m[54] << 14) | (mask_m[55] << 12)
2229 | (mask_m[56] << 10) | (mask_m[57] << 8)
2230 | (mask_m[58] << 6) | (mask_m[59] << 4)
2231 | (mask_m[60] << 2) | (mask_m[61] << 0);
2232 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2233 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
f078f209 2234
f1dc5600
S		 2235 tmp_mask = (mask_m[31] << 28)
2236 | (mask_m[32] << 26) | (mask_m[33] << 24)
2237 | (mask_m[34] << 22) | (mask_m[35] << 20)
2238 | (mask_m[36] << 18) | (mask_m[37] << 16)
2239 | (mask_m[48] << 14) | (mask_m[39] << 12)
2240 | (mask_m[40] << 10) | (mask_m[41] << 8)
2241 | (mask_m[42] << 6) | (mask_m[43] << 4)
2242 | (mask_m[44] << 2) | (mask_m[45] << 0);
2243 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2244 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
f078f209 2245
f1dc5600
S		 2246 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2247 | (mask_m[18] << 26) | (mask_m[18] << 24)
2248 | (mask_m[20] << 22) | (mask_m[20] << 20)
2249 | (mask_m[22] << 18) | (mask_m[22] << 16)
2250 | (mask_m[24] << 14) | (mask_m[24] << 12)
2251 | (mask_m[25] << 10) | (mask_m[26] << 8)
2252 | (mask_m[27] << 6) | (mask_m[28] << 4)
2253 | (mask_m[29] << 2) | (mask_m[30] << 0);
2254 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2255 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
f078f209 2256
f1dc5600
S		 2257 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2258 | (mask_m[2] << 26) | (mask_m[3] << 24)
2259 | (mask_m[4] << 22) | (mask_m[5] << 20)
2260 | (mask_m[6] << 18) | (mask_m[7] << 16)
2261 | (mask_m[8] << 14) | (mask_m[9] << 12)
2262 | (mask_m[10] << 10) | (mask_m[11] << 8)
2263 | (mask_m[12] << 6) | (mask_m[13] << 4)
2264 | (mask_m[14] << 2) | (mask_m[15] << 0);
2265 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2266 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
f078f209 2267
f1dc5600
S		 2268 tmp_mask = (mask_p[15] << 28)
2269 | (mask_p[14] << 26) | (mask_p[13] << 24)
2270 | (mask_p[12] << 22) | (mask_p[11] << 20)
2271 | (mask_p[10] << 18) | (mask_p[9] << 16)
2272 | (mask_p[8] << 14) | (mask_p[7] << 12)
2273 | (mask_p[6] << 10) | (mask_p[5] << 8)
2274 | (mask_p[4] << 6) | (mask_p[3] << 4)
2275 | (mask_p[2] << 2) | (mask_p[1] << 0);
2276 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2277 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2278
f1dc5600
S		 2279 tmp_mask = (mask_p[30] << 28)
2280 | (mask_p[29] << 26) | (mask_p[28] << 24)
2281 | (mask_p[27] << 22) | (mask_p[26] << 20)
2282 | (mask_p[25] << 18) | (mask_p[24] << 16)
2283 | (mask_p[23] << 14) | (mask_p[22] << 12)
2284 | (mask_p[21] << 10) | (mask_p[20] << 8)
2285 | (mask_p[19] << 6) | (mask_p[18] << 4)
2286 | (mask_p[17] << 2) | (mask_p[16] << 0);
2287 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2288 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2289
f1dc5600
S		 2290 tmp_mask = (mask_p[45] << 28)
2291 | (mask_p[44] << 26) | (mask_p[43] << 24)
2292 | (mask_p[42] << 22) | (mask_p[41] << 20)
2293 | (mask_p[40] << 18) | (mask_p[39] << 16)
2294 | (mask_p[38] << 14) | (mask_p[37] << 12)
2295 | (mask_p[36] << 10) | (mask_p[35] << 8)
2296 | (mask_p[34] << 6) | (mask_p[33] << 4)
2297 | (mask_p[32] << 2) | (mask_p[31] << 0);
2298 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2299 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2300
f1dc5600
S		 2301 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2302 | (mask_p[59] << 26) | (mask_p[58] << 24)
2303 | (mask_p[57] << 22) | (mask_p[56] << 20)
2304 | (mask_p[55] << 18) | (mask_p[54] << 16)
2305 | (mask_p[53] << 14) | (mask_p[52] << 12)
2306 | (mask_p[51] << 10) | (mask_p[50] << 8)
2307 | (mask_p[49] << 6) | (mask_p[48] << 4)
2308 | (mask_p[47] << 2) | (mask_p[46] << 0);
2309 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2310 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2311}
2312
3b319aae
JB		 2313static void ath9k_enable_rfkill(struct ath_hw *ah)
2314{
2315 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2316 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2317
2318 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2319 AR_GPIO_INPUT_MUX2_RFSILENT);
2320
2321 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2322 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2323}
2324
cbe61d8a 2325int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 2326 bool bChannelChange)
f078f209 2327{
1510718d 2328 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2329 u32 saveLedState;
2660b81a 2330 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 2331 u32 saveDefAntenna;
2332 u32 macStaId1;
46fe782c 2333 u64 tsf = 0;
ae8d2858 2334 int i, rx_chainmask, r;
f078f209 2335
43c27613
LR		 2336 ah->txchainmask = common->tx_chainmask;
2337 ah->rxchainmask = common->rx_chainmask;
f078f209 2338
9ecdef4b 2339 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 2340 return -EIO;
f078f209 2341
9ebef799 2342 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 2343 ath9k_hw_getnf(ah, curchan);
2344
2345 if (bChannelChange &&
2660b81a
S		 2346 (ah->chip_fullsleep != true) &&
2347 (ah->curchan != NULL) &&
2348 (chan->channel != ah->curchan->channel) &&
f078f209 2349 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 2350 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 2351 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2352 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 2353
25c56eec 2354 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 2355 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 2356 ath9k_hw_start_nfcal(ah);
ae8d2858 2357 return 0;
f078f209
LR		 2358 }
2359 }
2360
2361 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2362 if (saveDefAntenna == 0)
2363 saveDefAntenna = 1;
2364
2365 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2366
46fe782c
S		 2367 /* For chips on which RTC reset is done, save TSF before it gets cleared */
2368 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2369 tsf = ath9k_hw_gettsf64(ah);
2370
f078f209
LR		 2371 saveLedState = REG_READ(ah, AR_CFG_LED) &
2372 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2373 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2374
2375 ath9k_hw_mark_phy_inactive(ah);
2376
d7e7d229
LR		 2377 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2378 REG_WRITE(ah,
2379 AR9271_RESET_POWER_DOWN_CONTROL,
2380 AR9271_RADIO_RF_RST);
2381 udelay(50);
2382 }
2383
f078f209 2384 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 2385 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 2386 return -EINVAL;
f078f209
LR		 2387 }
2388
d7e7d229
LR		 2389 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2390 ah->htc_reset_init = false;
2391 REG_WRITE(ah,
2392 AR9271_RESET_POWER_DOWN_CONTROL,
2393 AR9271_GATE_MAC_CTL);
2394 udelay(50);
2395 }
2396
46fe782c
S		 2397 /* Restore TSF */
2398 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2399 ath9k_hw_settsf64(ah, tsf);
2400
369391db
VT		 2401 if (AR_SREV_9280_10_OR_LATER(ah))
2402 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 2403
326bebbc 2404 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2405 /* Enable ASYNC FIFO */
2406 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2407 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2408 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2409 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2410 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2411 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2412 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2413 }
25c56eec 2414 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 2415 if (r)
2416 return r;
f078f209 2417
0ced0e17
JM		 2418 /* Setup MFP options for CCMP */
2419 if (AR_SREV_9280_20_OR_LATER(ah)) {
2420 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2421 * frames when constructing CCMP AAD. */
2422 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2423 0xc7ff);
2424 ah->sw_mgmt_crypto = false;
2425 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2426 /* Disable hardware crypto for management frames */
2427 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2428 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2429 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2430 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2431 ah->sw_mgmt_crypto = true;
2432 } else
2433 ah->sw_mgmt_crypto = true;
2434
f078f209
LR		 2435 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2436 ath9k_hw_set_delta_slope(ah, chan);
2437
2438 if (AR_SREV_9280_10_OR_LATER(ah))
2439 ath9k_hw_9280_spur_mitigate(ah, chan);
2440 else
2441 ath9k_hw_spur_mitigate(ah, chan);
2442
d6509151 2443 ah->eep_ops->set_board_values(ah, chan);
f078f209
LR		 2444
2445 ath9k_hw_decrease_chain_power(ah, chan);
2446
1510718d
LR		 2447 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2448 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 2449 | macStaId1
2450 | AR_STA_ID1_RTS_USE_DEF
2660b81a 2451 | (ah->config.
60b67f51 2452 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 2453 | ah->sta_id1_defaults);
2454 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2455
13b81559 2456 ath_hw_setbssidmask(common);
f078f209
LR		 2457
2458 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2459
3453ad88 2460 ath9k_hw_write_associd(ah);
f078f209
LR		 2461
2462 REG_WRITE(ah, AR_ISR, ~0);
2463
2464 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2465
8fbff4b8
VT		 2466 if (AR_SREV_9280_10_OR_LATER(ah))
2467 ath9k_hw_ar9280_set_channel(ah, chan);
2468 else
ae8d2858
LR		 2469 if (!(ath9k_hw_set_channel(ah, chan)))
2470 return -EIO;
f078f209
LR		 2471
2472 for (i = 0; i < AR_NUM_DCU; i++)
2473 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2474
2660b81a
S		 2475 ah->intr_txqs = 0;
2476 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 2477 ath9k_hw_resettxqueue(ah, i);
2478
2660b81a 2479 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 2480 ath9k_hw_init_qos(ah);
2481
2660b81a 2482 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 2483 ath9k_enable_rfkill(ah);
3b319aae 2484
f078f209
LR		 2485 ath9k_hw_init_user_settings(ah);
2486
326bebbc 2487 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2488 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2489 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2490 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2491 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2492 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2493 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2494
2495 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2496 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2497
2498 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2499 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2500 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2501 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2502 }
326bebbc 2503 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2504 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2505 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2506 }
2507
f078f209
LR		 2508 REG_WRITE(ah, AR_STA_ID1,
2509 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2510
2511 ath9k_hw_set_dma(ah);
2512
2513 REG_WRITE(ah, AR_OBS, 8);
2514
0ef1f168 2515 if (ah->config.intr_mitigation) {
f078f209
LR		 2516 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2517 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2518 }
2519
2520 ath9k_hw_init_bb(ah, chan);
2521
ae8d2858 2522 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2523 return -EIO;
f078f209 2524
2660b81a 2525 rx_chainmask = ah->rxchainmask;
f078f209
LR		 2526 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2527 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2528 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2529 }
2530
2531 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2532
d7e7d229
LR		 2533 /*
2534 * For big endian systems turn on swapping for descriptors
2535 */
f078f209
LR		 2536 if (AR_SREV_9100(ah)) {
2537 u32 mask;
2538 mask = REG_READ(ah, AR_CFG);
2539 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 2540 ath_print(common, ATH_DBG_RESET,
04bd4638 2541 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2542 } else {
2543 mask =
2544 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2545 REG_WRITE(ah, AR_CFG, mask);
c46917bb 2546 ath_print(common, ATH_DBG_RESET,
04bd4638 2547 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2548 }
2549 } else {
d7e7d229
LR		 2550 /* Configure AR9271 target WLAN */
2551 if (AR_SREV_9271(ah))
2552 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 2553#ifdef __BIG_ENDIAN
d7e7d229
LR		 2554 else
2555 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 2556#endif
2557 }
2558
766ec4a9 2559 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 2560 ath9k_hw_btcoex_enable(ah);
2561
ae8d2858 2562 return 0;
f078f209
LR		 2563}
2564
f1dc5600
S		 2565/************************/
2566/* Key Cache Management */
2567/************************/
f078f209 2568
cbe61d8a 2569bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 2570{
f1dc5600 2571 u32 keyType;
f078f209 2572
2660b81a 2573 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 2574 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2575 "keychache entry %u out of range\n", entry);
f078f209
LR		 2576 return false;
2577 }
2578
f1dc5600 2579 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2580
f1dc5600
S		 2581 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2582 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2583 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2584 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2585 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2586 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2587 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2588 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2589
f1dc5600
S		 2590 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2591 u16 micentry = entry + 64;
f078f209 2592
f1dc5600
S		 2593 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2594 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2595 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2596 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2597
f078f209
LR		 2598 }
2599
f078f209
LR		 2600 return true;
2601}
2602
cbe61d8a 2603bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 2604{
f1dc5600 2605 u32 macHi, macLo;
f078f209 2606
2660b81a 2607 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 2608 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2609 "keychache entry %u out of range\n", entry);
f1dc5600 2610 return false;
f078f209
LR		 2611 }
2612
f1dc5600
S		 2613 if (mac != NULL) {
2614 macHi = (mac[5] << 8) | mac[4];
2615 macLo = (mac[3] << 24) |
2616 (mac[2] << 16) |
2617 (mac[1] << 8) |
2618 mac[0];
2619 macLo >>= 1;
2620 macLo |= (macHi & 1) << 31;
2621 macHi >>= 1;
f078f209 2622 } else {
f1dc5600 2623 macLo = macHi = 0;
f078f209 2624 }
f1dc5600
S		 2625 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2626 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2627
f1dc5600 2628 return true;
f078f209
LR		 2629}
2630
cbe61d8a 2631bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 2632 const struct ath9k_keyval *k,
e0caf9ea 2633 const u8 *mac)
f078f209 2634{
2660b81a 2635 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2636 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 2637 u32 key0, key1, key2, key3, key4;
2638 u32 keyType;
f078f209 2639
f1dc5600 2640 if (entry >= pCap->keycache_size) {
c46917bb
LR		 2641 ath_print(common, ATH_DBG_FATAL,
2642 "keycache entry %u out of range\n", entry);
f1dc5600 2643 return false;
f078f209
LR		 2644 }
2645
f1dc5600
S		 2646 switch (k->kv_type) {
2647 case ATH9K_CIPHER_AES_OCB:
2648 keyType = AR_KEYTABLE_TYPE_AES;
2649 break;
2650 case ATH9K_CIPHER_AES_CCM:
2651 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 2652 ath_print(common, ATH_DBG_ANY,
2653 "AES-CCM not supported by mac rev 0x%x\n",
2654 ah->hw_version.macRev);
f1dc5600
S		 2655 return false;
2656 }
2657 keyType = AR_KEYTABLE_TYPE_CCM;
2658 break;
2659 case ATH9K_CIPHER_TKIP:
2660 keyType = AR_KEYTABLE_TYPE_TKIP;
2661 if (ATH9K_IS_MIC_ENABLED(ah)
2662 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 2663 ath_print(common, ATH_DBG_ANY,
2664 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2665 return false;
2666 }
2667 break;
2668 case ATH9K_CIPHER_WEP:
e31a16d6 2669 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 2670 ath_print(common, ATH_DBG_ANY,
2671 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2672 return false;
2673 }
e31a16d6 2674 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 2675 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 2676 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 2677 keyType = AR_KEYTABLE_TYPE_104;
2678 else
2679 keyType = AR_KEYTABLE_TYPE_128;
2680 break;
2681 case ATH9K_CIPHER_CLR:
2682 keyType = AR_KEYTABLE_TYPE_CLR;
2683 break;
2684 default:
c46917bb
LR		 2685 ath_print(common, ATH_DBG_FATAL,
2686 "cipher %u not supported\n", k->kv_type);
f1dc5600 2687 return false;
f078f209
LR		 2688 }
2689
e0caf9ea
JM		 2690 key0 = get_unaligned_le32(k->kv_val + 0);
2691 key1 = get_unaligned_le16(k->kv_val + 4);
2692 key2 = get_unaligned_le32(k->kv_val + 6);
2693 key3 = get_unaligned_le16(k->kv_val + 10);
2694 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 2695 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 2696 key4 &= 0xff;
f078f209 2697
672903b3
JM		 2698 /*
2699 * Note: Key cache registers access special memory area that requires
2700 * two 32-bit writes to actually update the values in the internal
2701 * memory. Consequently, the exact order and pairs used here must be
2702 * maintained.
2703 */
2704
f1dc5600
S		 2705 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2706 u16 micentry = entry + 64;
f078f209 2707
672903b3
JM		 2708 /*
2709 * Write inverted key[47:0] first to avoid Michael MIC errors
2710 * on frames that could be sent or received at the same time.
2711 * The correct key will be written in the end once everything
2712 * else is ready.
2713 */
f1dc5600
S		 2714 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2715 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 2716
2717 /* Write key[95:48] */
f1dc5600
S		 2718 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2719 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2720
2721 /* Write key[127:96] and key type */
f1dc5600
S		 2722 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2723 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 2724
2725 /* Write MAC address for the entry */
f1dc5600 2726 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2727
2660b81a 2728 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 2729 /*
2730 * TKIP uses two key cache entries:
2731 * Michael MIC TX/RX keys in the same key cache entry
2732 * (idx = main index + 64):
2733 * key0 [31:0] = RX key [31:0]
2734 * key1 [15:0] = TX key [31:16]
2735 * key1 [31:16] = reserved
2736 * key2 [31:0] = RX key [63:32]
2737 * key3 [15:0] = TX key [15:0]
2738 * key3 [31:16] = reserved
2739 * key4 [31:0] = TX key [63:32]
2740 */
f1dc5600 2741 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2742
f1dc5600
S		 2743 mic0 = get_unaligned_le32(k->kv_mic + 0);
2744 mic2 = get_unaligned_le32(k->kv_mic + 4);
2745 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2746 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2747 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 2748
2749 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 2750 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2751 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 2752
2753 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 2754 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2755 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 2756
2757 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2758 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2759 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2760 AR_KEYTABLE_TYPE_CLR);
f078f209 2761
f1dc5600 2762 } else {
672903b3
JM		 2763 /*
2764 * TKIP uses four key cache entries (two for group
2765 * keys):
2766 * Michael MIC TX/RX keys are in different key cache
2767 * entries (idx = main index + 64 for TX and
2768 * main index + 32 + 96 for RX):
2769 * key0 [31:0] = TX/RX MIC key [31:0]
2770 * key1 [31:0] = reserved
2771 * key2 [31:0] = TX/RX MIC key [63:32]
2772 * key3 [31:0] = reserved
2773 * key4 [31:0] = reserved
2774 *
2775 * Upper layer code will call this function separately
2776 * for TX and RX keys when these registers offsets are
2777 * used.
2778 */
f1dc5600 2779 u32 mic0, mic2;
f078f209 2780
f1dc5600
S		 2781 mic0 = get_unaligned_le32(k->kv_mic + 0);
2782 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 2783
2784 /* Write MIC key[31:0] */
f1dc5600
S		 2785 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2786 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 2787
2788 /* Write MIC key[63:32] */
f1dc5600
S		 2789 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2790 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 2791
2792 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2793 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2794 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2795 AR_KEYTABLE_TYPE_CLR);
2796 }
672903b3
JM		 2797
2798 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 2799 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2800 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 2801
2802 /*
2803 * Write the correct (un-inverted) key[47:0] last to enable
2804 * TKIP now that all other registers are set with correct
2805 * values.
2806 */
f1dc5600
S		 2807 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2808 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2809 } else {
672903b3 2810 /* Write key[47:0] */
f1dc5600
S		 2811 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2812 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 2813
2814 /* Write key[95:48] */
f1dc5600
S		 2815 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2816 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2817
2818 /* Write key[127:96] and key type */
f1dc5600
S		 2819 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2820 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2821
672903b3 2822 /* Write MAC address for the entry */
f1dc5600
S		 2823 (void) ath9k_hw_keysetmac(ah, entry, mac);
2824 }
f078f209 2825
f078f209
LR		 2826 return true;
2827}
2828
cbe61d8a 2829bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 2830{
2660b81a 2831 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 2832 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2833 if (val & AR_KEYTABLE_VALID)
2834 return true;
2835 }
2836 return false;
f078f209
LR		 2837}
2838
f1dc5600
S		 2839/******************************/
2840/* Power Management (Chipset) */
2841/******************************/
2842
cbe61d8a 2843static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2844{
f1dc5600
S		 2845 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2846 if (setChip) {
2847 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2848 AR_RTC_FORCE_WAKE_EN);
2849 if (!AR_SREV_9100(ah))
2850 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2851
4921be80
S		 2852 if(!AR_SREV_5416(ah))
2853 REG_CLR_BIT(ah, (AR_RTC_RESET),
2854 AR_RTC_RESET_EN);
f1dc5600 2855 }
f078f209
LR		 2856}
2857
cbe61d8a 2858static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2859{
f1dc5600
S		 2860 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2861 if (setChip) {
2660b81a 2862 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2863
f1dc5600
S		 2864 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2865 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2866 AR_RTC_FORCE_WAKE_ON_INT);
2867 } else {
2868 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2869 AR_RTC_FORCE_WAKE_EN);
f078f209 2870 }
f078f209 2871 }
f078f209
LR		 2872}
2873
cbe61d8a 2874static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2875{
f1dc5600
S		 2876 u32 val;
2877 int i;
f078f209 2878
f1dc5600
S		 2879 if (setChip) {
2880 if ((REG_READ(ah, AR_RTC_STATUS) &
2881 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2882 if (ath9k_hw_set_reset_reg(ah,
2883 ATH9K_RESET_POWER_ON) != true) {
2884 return false;
2885 }
63a75b91 2886 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 2887 }
2888 if (AR_SREV_9100(ah))
2889 REG_SET_BIT(ah, AR_RTC_RESET,
2890 AR_RTC_RESET_EN);
f078f209 2891
f1dc5600
S		 2892 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2893 AR_RTC_FORCE_WAKE_EN);
2894 udelay(50);
f078f209 2895
f1dc5600
S		 2896 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2897 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2898 if (val == AR_RTC_STATUS_ON)
2899 break;
2900 udelay(50);
2901 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2902 AR_RTC_FORCE_WAKE_EN);
f078f209 2903 }
f1dc5600 2904 if (i == 0) {
c46917bb
LR		 2905 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2906 "Failed to wakeup in %uus\n",
2907 POWER_UP_TIME / 20);
f1dc5600 2908 return false;
f078f209 2909 }
f078f209
LR		 2910 }
2911
f1dc5600 2912 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2913
f1dc5600 2914 return true;
f078f209
LR		 2915}
2916
9ecdef4b 2917bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2918{
c46917bb 2919 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 2920 int status = true, setChip = true;
f1dc5600
S		 2921 static const char *modes[] = {
2922 "AWAKE",
2923 "FULL-SLEEP",
2924 "NETWORK SLEEP",
2925 "UNDEFINED"
2926 };
f1dc5600 2927
cbdec975
GJ		 2928 if (ah->power_mode == mode)
2929 return status;
2930
c46917bb
LR		 2931 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2932 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2933
2934 switch (mode) {
2935 case ATH9K_PM_AWAKE:
2936 status = ath9k_hw_set_power_awake(ah, setChip);
2937 break;
2938 case ATH9K_PM_FULL_SLEEP:
2939 ath9k_set_power_sleep(ah, setChip);
2660b81a 2940 ah->chip_fullsleep = true;
f1dc5600
S		 2941 break;
2942 case ATH9K_PM_NETWORK_SLEEP:
2943 ath9k_set_power_network_sleep(ah, setChip);
2944 break;
f078f209 2945 default:
c46917bb
LR		 2946 ath_print(common, ATH_DBG_FATAL,
2947 "Unknown power mode %u\n", mode);
f078f209
LR		 2948 return false;
2949 }
2660b81a 2950 ah->power_mode = mode;
f1dc5600
S		 2951
2952 return status;
f078f209
LR		 2953}
2954
24c1a280
LR		 2955/*
2956 * Helper for ASPM support.
2957 *
2958 * Disable PLL when in L0s as well as receiver clock when in L1.
2959 * This power saving option must be enabled through the SerDes.
2960 *
2961 * Programming the SerDes must go through the same 288 bit serial shift
2962 * register as the other analog registers. Hence the 9 writes.
2963 */
93b1b37f 2964void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
f078f209 2965{
f1dc5600 2966 u8 i;
93b1b37f 2967 u32 val;
f078f209 2968
2660b81a 2969 if (ah->is_pciexpress != true)
f1dc5600 2970 return;
f078f209 2971
24c1a280 2972 /* Do not touch SerDes registers */
2660b81a 2973 if (ah->config.pcie_powersave_enable == 2)
f1dc5600
S		 2974 return;
2975
24c1a280 2976 /* Nothing to do on restore for 11N */
93b1b37f
VN		 2977 if (!restore) {
2978 if (AR_SREV_9280_20_OR_LATER(ah)) {
2979 /*
2980 * AR9280 2.0 or later chips use SerDes values from the
2981 * initvals.h initialized depending on chipset during
2982 * ath9k_hw_init()
2983 */
2984 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2985 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2986 INI_RA(&ah->iniPcieSerdes, i, 1));
2987 }
2988 } else if (AR_SREV_9280(ah) &&
2989 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2990 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2991 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2992
2993 /* RX shut off when elecidle is asserted */
2994 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2995 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2996 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2997
2998 /* Shut off CLKREQ active in L1 */
2999 if (ah->config.pcie_clock_req)
3000 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3001 else
3002 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
f1dc5600 3003
93b1b37f
VN		 3004 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3005 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3006 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
f1dc5600 3007
93b1b37f
VN		 3008 /* Load the new settings */
3009 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f1dc5600 3010
93b1b37f
VN		 3011 } else {
3012 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3013 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
f1dc5600 3014
93b1b37f
VN		 3015 /* RX shut off when elecidle is asserted */
3016 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3017 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3018 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
f1dc5600 3019
93b1b37f
VN		 3020 /*
3021 * Ignore ah->ah_config.pcie_clock_req setting for
3022 * pre-AR9280 11n
3023 */
3024 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
24c1a280 3025
93b1b37f
VN		 3026 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3027 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3028 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
24c1a280 3029
93b1b37f
VN		 3030 /* Load the new settings */
3031 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3032 }
24c1a280 3033
93b1b37f 3034 udelay(1000);
24c1a280 3035
93b1b37f
VN		 3036 /* set bit 19 to allow forcing of pcie core into L1 state */
3037 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
f078f209 3038
93b1b37f
VN		 3039 /* Several PCIe massages to ensure proper behaviour */
3040 if (ah->config.pcie_waen) {
3041 val = ah->config.pcie_waen;
3042 if (!power_off)
3043 val &= (~AR_WA_D3_L1_DISABLE);
3044 } else {
3045 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3046 AR_SREV_9287(ah)) {
3047 val = AR9285_WA_DEFAULT;
3048 if (!power_off)
3049 val &= (~AR_WA_D3_L1_DISABLE);
3050 } else if (AR_SREV_9280(ah)) {
3051 /*
3052 * On AR9280 chips bit 22 of 0x4004 needs to be
3053 * set otherwise card may disappear.
3054 */
3055 val = AR9280_WA_DEFAULT;
3056 if (!power_off)
3057 val &= (~AR_WA_D3_L1_DISABLE);
3058 } else
3059 val = AR_WA_DEFAULT;
3060 }
6d08b9b9 3061
93b1b37f
VN		 3062 REG_WRITE(ah, AR_WA, val);
3063 }
f1dc5600 3064
93b1b37f 3065 if (power_off) {
24c1a280 3066 /*
93b1b37f
VN		 3067 * Set PCIe workaround bits
3068 * bit 14 in WA register (disable L1) should only
3069 * be set when device enters D3 and be cleared
3070 * when device comes back to D0.
24c1a280 3071 */
93b1b37f
VN		 3072 if (ah->config.pcie_waen) {
3073 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
3074 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3075 } else {
3076 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3077 AR_SREV_9287(ah)) &&
3078 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
3079 (AR_SREV_9280(ah) &&
3080 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
3081 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3082 }
3083 }
f1dc5600 3084 }
f078f209
LR		 3085}
3086
f1dc5600
S		 3087/**********************/
3088/* Interrupt Handling */
3089/**********************/
3090
cbe61d8a 3091bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 3092{
3093 u32 host_isr;
3094
3095 if (AR_SREV_9100(ah))
3096 return true;
3097
3098 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3099 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3100 return true;
3101
3102 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3103 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3104 && (host_isr != AR_INTR_SPURIOUS))
3105 return true;
3106
3107 return false;
3108}
3109
cbe61d8a 3110bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 3111{
3112 u32 isr = 0;
3113 u32 mask2 = 0;
2660b81a 3114 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3115 u32 sync_cause = 0;
3116 bool fatal_int = false;
c46917bb 3117 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 3118
3119 if (!AR_SREV_9100(ah)) {
3120 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3121 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3122 == AR_RTC_STATUS_ON) {
3123 isr = REG_READ(ah, AR_ISR);
3124 }
3125 }
3126
f1dc5600
S		 3127 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3128 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 3129
3130 *masked = 0;
3131
3132 if (!isr && !sync_cause)
3133 return false;
3134 } else {
3135 *masked = 0;
3136 isr = REG_READ(ah, AR_ISR);
3137 }
3138
3139 if (isr) {
f078f209
LR		 3140 if (isr & AR_ISR_BCNMISC) {
3141 u32 isr2;
3142 isr2 = REG_READ(ah, AR_ISR_S2);
3143 if (isr2 & AR_ISR_S2_TIM)
3144 mask2 |= ATH9K_INT_TIM;
3145 if (isr2 & AR_ISR_S2_DTIM)
3146 mask2 |= ATH9K_INT_DTIM;
3147 if (isr2 & AR_ISR_S2_DTIMSYNC)
3148 mask2 |= ATH9K_INT_DTIMSYNC;
3149 if (isr2 & (AR_ISR_S2_CABEND))
3150 mask2 |= ATH9K_INT_CABEND;
3151 if (isr2 & AR_ISR_S2_GTT)
3152 mask2 |= ATH9K_INT_GTT;
3153 if (isr2 & AR_ISR_S2_CST)
3154 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 3155 if (isr2 & AR_ISR_S2_TSFOOR)
3156 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 3157 }
3158
3159 isr = REG_READ(ah, AR_ISR_RAC);
3160 if (isr == 0xffffffff) {
3161 *masked = 0;
3162 return false;
3163 }
3164
3165 *masked = isr & ATH9K_INT_COMMON;
3166
0ef1f168 3167 if (ah->config.intr_mitigation) {
f078f209
LR		 3168 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3169 *masked |= ATH9K_INT_RX;
3170 }
3171
3172 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3173 *masked |= ATH9K_INT_RX;
3174 if (isr &
3175 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3176 AR_ISR_TXEOL)) {
3177 u32 s0_s, s1_s;
3178
3179 *masked |= ATH9K_INT_TX;
3180
3181 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 3182 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3183 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 3184
3185 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 3186 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3187 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 3188 }
3189
3190 if (isr & AR_ISR_RXORN) {
c46917bb
LR		 3191 ath_print(common, ATH_DBG_INTERRUPT,
3192 "receive FIFO overrun interrupt\n");
f078f209
LR		 3193 }
3194
3195 if (!AR_SREV_9100(ah)) {
60b67f51 3196 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3197 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3198 if (isr5 & AR_ISR_S5_TIM_TIMER)
3199 *masked |= ATH9K_INT_TIM_TIMER;
3200 }
3201 }
3202
3203 *masked |= mask2;
3204 }
f1dc5600 3205
f078f209
LR		 3206 if (AR_SREV_9100(ah))
3207 return true;
f1dc5600 3208
ff155a45
VT		 3209 if (isr & AR_ISR_GENTMR) {
3210 u32 s5_s;
3211
3212 s5_s = REG_READ(ah, AR_ISR_S5_S);
3213 if (isr & AR_ISR_GENTMR) {
3214 ah->intr_gen_timer_trigger =
3215 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3216
3217 ah->intr_gen_timer_thresh =
3218 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3219
3220 if (ah->intr_gen_timer_trigger)
3221 *masked |= ATH9K_INT_GENTIMER;
3222
3223 }
3224 }
3225
f078f209
LR		 3226 if (sync_cause) {
3227 fatal_int =
3228 (sync_cause &
3229 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3230 ? true : false;
3231
3232 if (fatal_int) {
3233 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
c46917bb
LR		 3234 ath_print(common, ATH_DBG_ANY,
3235 "received PCI FATAL interrupt\n");
f078f209
LR		 3236 }
3237 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
c46917bb
LR		 3238 ath_print(common, ATH_DBG_ANY,
3239 "received PCI PERR interrupt\n");
f078f209 3240 }
a89bff9a 3241 *masked |= ATH9K_INT_FATAL;
f078f209
LR		 3242 }
3243 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
c46917bb
LR		 3244 ath_print(common, ATH_DBG_INTERRUPT,
3245 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 3246 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3247 REG_WRITE(ah, AR_RC, 0);
3248 *masked |= ATH9K_INT_FATAL;
3249 }
3250 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
c46917bb
LR		 3251 ath_print(common, ATH_DBG_INTERRUPT,
3252 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 3253 }
3254
3255 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3256 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3257 }
f1dc5600 3258
f078f209
LR		 3259 return true;
3260}
3261
cbe61d8a 3262enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 3263{
2660b81a 3264 u32 omask = ah->mask_reg;
f078f209 3265 u32 mask, mask2;
2660b81a 3266 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 3267 struct ath_common *common = ath9k_hw_common(ah);
f078f209 3268
c46917bb 3269 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 3270
3271 if (omask & ATH9K_INT_GLOBAL) {
c46917bb 3272 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 3273 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3274 (void) REG_READ(ah, AR_IER);
3275 if (!AR_SREV_9100(ah)) {
3276 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3277 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3278
3279 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3280 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3281 }
3282 }
3283
3284 mask = ints & ATH9K_INT_COMMON;
3285 mask2 = 0;
3286
3287 if (ints & ATH9K_INT_TX) {
2660b81a 3288 if (ah->txok_interrupt_mask)
f078f209 3289 mask |= AR_IMR_TXOK;
2660b81a 3290 if (ah->txdesc_interrupt_mask)
f078f209 3291 mask |= AR_IMR_TXDESC;
2660b81a 3292 if (ah->txerr_interrupt_mask)
f078f209 3293 mask |= AR_IMR_TXERR;
2660b81a 3294 if (ah->txeol_interrupt_mask)
f078f209
LR		 3295 mask |= AR_IMR_TXEOL;
3296 }
3297 if (ints & ATH9K_INT_RX) {
3298 mask |= AR_IMR_RXERR;
0ef1f168 3299 if (ah->config.intr_mitigation)
f078f209
LR		 3300 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3301 else
3302 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 3303 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 3304 mask |= AR_IMR_GENTMR;
3305 }
3306
3307 if (ints & (ATH9K_INT_BMISC)) {
3308 mask |= AR_IMR_BCNMISC;
3309 if (ints & ATH9K_INT_TIM)
3310 mask2 |= AR_IMR_S2_TIM;
3311 if (ints & ATH9K_INT_DTIM)
3312 mask2 |= AR_IMR_S2_DTIM;
3313 if (ints & ATH9K_INT_DTIMSYNC)
3314 mask2 |= AR_IMR_S2_DTIMSYNC;
3315 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 3316 mask2 |= AR_IMR_S2_CABEND;
3317 if (ints & ATH9K_INT_TSFOOR)
3318 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 3319 }
3320
3321 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3322 mask |= AR_IMR_BCNMISC;
3323 if (ints & ATH9K_INT_GTT)
3324 mask2 |= AR_IMR_S2_GTT;
3325 if (ints & ATH9K_INT_CST)
3326 mask2 |= AR_IMR_S2_CST;
3327 }
3328
c46917bb 3329 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 3330 REG_WRITE(ah, AR_IMR, mask);
3331 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3332 AR_IMR_S2_DTIM |
3333 AR_IMR_S2_DTIMSYNC |
3334 AR_IMR_S2_CABEND |
3335 AR_IMR_S2_CABTO |
3336 AR_IMR_S2_TSFOOR |
3337 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3338 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2660b81a 3339 ah->mask_reg = ints;
f078f209 3340
60b67f51 3341 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3342 if (ints & ATH9K_INT_TIM_TIMER)
3343 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3344 else
3345 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3346 }
3347
3348 if (ints & ATH9K_INT_GLOBAL) {
c46917bb 3349 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 3350 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3351 if (!AR_SREV_9100(ah)) {
3352 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3353 AR_INTR_MAC_IRQ);
3354 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3355
3356
3357 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3358 AR_INTR_SYNC_DEFAULT);
3359 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3360 AR_INTR_SYNC_DEFAULT);
3361 }
c46917bb
LR		 3362 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3363 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
f078f209
LR		 3364 }
3365
3366 return omask;
3367}
3368
f1dc5600
S		 3369/*******************/
3370/* Beacon Handling */
3371/*******************/
3372
cbe61d8a 3373void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 3374{
f078f209
LR		 3375 int flags = 0;
3376
2660b81a 3377 ah->beacon_interval = beacon_period;
f078f209 3378
2660b81a 3379 switch (ah->opmode) {
d97809db
CM		 3380 case NL80211_IFTYPE_STATION:
3381 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 3382 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3383 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3384 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3385 flags |= AR_TBTT_TIMER_EN;
3386 break;
d97809db 3387 case NL80211_IFTYPE_ADHOC:
9cb5412b 3388 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 3389 REG_SET_BIT(ah, AR_TXCFG,
3390 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3391 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3392 TU_TO_USEC(next_beacon +
2660b81a
S		 3393 (ah->atim_window ? ah->
3394 atim_window : 1)));
f078f209 3395 flags |= AR_NDP_TIMER_EN;
d97809db 3396 case NL80211_IFTYPE_AP:
f078f209
LR		 3397 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3398 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3399 TU_TO_USEC(next_beacon -
2660b81a 3400 ah->config.
60b67f51 3401 dma_beacon_response_time));
f078f209
LR		 3402 REG_WRITE(ah, AR_NEXT_SWBA,
3403 TU_TO_USEC(next_beacon -
2660b81a 3404 ah->config.
60b67f51 3405 sw_beacon_response_time));
f078f209
LR		 3406 flags |=
3407 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3408 break;
d97809db 3409 default:
c46917bb
LR		 3410 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3411 "%s: unsupported opmode: %d\n",
3412 __func__, ah->opmode);
d97809db
CM		 3413 return;
3414 break;
f078f209
LR		 3415 }
3416
3417 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3418 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3419 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3420 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3421
3422 beacon_period &= ~ATH9K_BEACON_ENA;
3423 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 3424 ath9k_hw_reset_tsf(ah);
3425 }
3426
3427 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3428}
3429
cbe61d8a 3430void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 3431 const struct ath9k_beacon_state *bs)
f078f209
LR		 3432{
3433 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 3434 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 3435 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 3436
3437 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3438
3439 REG_WRITE(ah, AR_BEACON_PERIOD,
3440 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3441 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3442 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3443
3444 REG_RMW_FIELD(ah, AR_RSSI_THR,
3445 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3446
3447 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3448
3449 if (bs->bs_sleepduration > beaconintval)
3450 beaconintval = bs->bs_sleepduration;
3451
3452 dtimperiod = bs->bs_dtimperiod;
3453 if (bs->bs_sleepduration > dtimperiod)
3454 dtimperiod = bs->bs_sleepduration;
3455
3456 if (beaconintval == dtimperiod)
3457 nextTbtt = bs->bs_nextdtim;
3458 else
3459 nextTbtt = bs->bs_nexttbtt;
3460
c46917bb
LR		 3461 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3462 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3463 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3464 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3465
f1dc5600
S		 3466 REG_WRITE(ah, AR_NEXT_DTIM,
3467 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3468 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3469
f1dc5600
S		 3470 REG_WRITE(ah, AR_SLEEP1,
3471 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3472 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3473
f1dc5600
S		 3474 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3475 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3476 else
3477 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3478
f1dc5600
S		 3479 REG_WRITE(ah, AR_SLEEP2,
3480 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3481
f1dc5600
S		 3482 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3483 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3484
f1dc5600
S		 3485 REG_SET_BIT(ah, AR_TIMER_MODE,
3486 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3487 AR_DTIM_TIMER_EN);
f078f209 3488
4af9cf4f
S		 3489 /* TSF Out of Range Threshold */
3490 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209
LR		 3491}
3492
f1dc5600
S		 3493/*******************/
3494/* HW Capabilities */
3495/*******************/
3496
eef7a574 3497void ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 3498{
2660b81a 3499 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 3500 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 3501 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 3502 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 3503
f1dc5600 3504 u16 capField = 0, eeval;
f078f209 3505
f74df6fb 3506 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 3507 regulatory->current_rd = eeval;
f078f209 3508
f74df6fb 3509 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 3510 if (AR_SREV_9285_10_OR_LATER(ah))
3511 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 3512 regulatory->current_rd_ext = eeval;
f078f209 3513
f74df6fb 3514 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 3515
2660b81a 3516 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 3517 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 3518 if (regulatory->current_rd == 0x64 ||
3519 regulatory->current_rd == 0x65)
3520 regulatory->current_rd += 5;
3521 else if (regulatory->current_rd == 0x41)
3522 regulatory->current_rd = 0x43;
c46917bb
LR		 3523 ath_print(common, ATH_DBG_REGULATORY,
3524 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 3525 }
f078f209 3526
f74df6fb 3527 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
f1dc5600 3528 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3529
f1dc5600
S		 3530 if (eeval & AR5416_OPFLAGS_11A) {
3531 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 3532 if (ah->config.ht_enable) {
f1dc5600
S		 3533 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3534 set_bit(ATH9K_MODE_11NA_HT20,
3535 pCap->wireless_modes);
3536 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3537 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3538 pCap->wireless_modes);
3539 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3540 pCap->wireless_modes);
3541 }
f078f209 3542 }
f078f209
LR		 3543 }
3544
f1dc5600 3545 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 3546 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 3547 if (ah->config.ht_enable) {
f1dc5600
S		 3548 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3549 set_bit(ATH9K_MODE_11NG_HT20,
3550 pCap->wireless_modes);
3551 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3552 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3553 pCap->wireless_modes);
3554 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3555 pCap->wireless_modes);
3556 }
3557 }
f078f209 3558 }
f1dc5600 3559
f74df6fb 3560 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 3561 /*
3562 * For AR9271 we will temporarilly uses the rx chainmax as read from
3563 * the EEPROM.
3564 */
8147f5de 3565 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 3566 !(eeval & AR5416_OPFLAGS_11A) &&
3567 !(AR_SREV_9271(ah)))
3568 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 3569 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3570 else
d7e7d229 3571 /* Use rx_chainmask from EEPROM. */
8147f5de 3572 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 3573
d535a42a 3574 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 3575 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3576
f1dc5600
S		 3577 pCap->low_2ghz_chan = 2312;
3578 pCap->high_2ghz_chan = 2732;
f078f209 3579
f1dc5600
S		 3580 pCap->low_5ghz_chan = 4920;
3581 pCap->high_5ghz_chan = 6100;
f078f209 3582
f1dc5600
S		 3583 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3584 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3585 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3586
f1dc5600
S		 3587 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3588 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3589 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3590
2660b81a 3591 if (ah->config.ht_enable)
f1dc5600
S		 3592 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3593 else
3594 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3595
f1dc5600
S		 3596 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3597 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3598 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3599 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3600
f1dc5600
S		 3601 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3602 pCap->total_queues =
3603 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3604 else
3605 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3606
f1dc5600
S		 3607 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3608 pCap->keycache_size =
3609 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3610 else
3611 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3612
f1dc5600 3613 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f1dc5600 3614 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3615
cb33c412
SB		 3616 if (AR_SREV_9285_10_OR_LATER(ah))
3617 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3618 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3619 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3620 else
3621 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3622
f1dc5600
S		 3623 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3624 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3625 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3626 } else {
3627 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3628 }
3629
f1dc5600
S		 3630 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3631
e97275cb 3632#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 3633 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3634 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3635 ah->rfkill_gpio =
3636 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3637 ah->rfkill_polarity =
3638 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 3639
3640 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3641 }
f1dc5600 3642#endif
f078f209 3643
a3ca95fb 3644 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3645
e7594072 3646 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3647 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3648 else
3649 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3650
608b88cb 3651 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 3652 pCap->reg_cap =
3653 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3654 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3655 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3656 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3657 } else {
f1dc5600
S		 3658 pCap->reg_cap =
3659 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3660 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3661 }
f078f209 3662
ebb90cfc
SB		 3663 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3664 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3665 AR_SREV_5416(ah))
3666 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 3667
3668 pCap->num_antcfg_5ghz =
f74df6fb 3669 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3670 pCap->num_antcfg_2ghz =
f74df6fb 3671 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3672
fe12946e 3673 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 3674 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 3675 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3676 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 3677
8c8f9ba7 3678 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 3679 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3680 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 3681 } else {
766ec4a9 3682 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 3683 }
22f25d0d 3684 } else {
766ec4a9 3685 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 3686 }
f078f209
LR		 3687}
3688
cbe61d8a 3689bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3690 u32 capability, u32 *result)
f078f209 3691{
608b88cb 3692 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 3693 switch (type) {
3694 case ATH9K_CAP_CIPHER:
3695 switch (capability) {
3696 case ATH9K_CIPHER_AES_CCM:
3697 case ATH9K_CIPHER_AES_OCB:
3698 case ATH9K_CIPHER_TKIP:
3699 case ATH9K_CIPHER_WEP:
3700 case ATH9K_CIPHER_MIC:
3701 case ATH9K_CIPHER_CLR:
3702 return true;
3703 default:
3704 return false;
3705 }
3706 case ATH9K_CAP_TKIP_MIC:
3707 switch (capability) {
3708 case 0:
3709 return true;
3710 case 1:
2660b81a 3711 return (ah->sta_id1_defaults &
f1dc5600
S		 3712 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3713 false;
3714 }
3715 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 3716 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 3717 false : true;
f1dc5600
S		 3718 case ATH9K_CAP_DIVERSITY:
3719 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3720 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3721 true : false;
f1dc5600
S		 3722 case ATH9K_CAP_MCAST_KEYSRCH:
3723 switch (capability) {
3724 case 0:
3725 return true;
3726 case 1:
3727 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3728 return false;
3729 } else {
2660b81a 3730 return (ah->sta_id1_defaults &
f1dc5600
S		 3731 AR_STA_ID1_MCAST_KSRCH) ? true :
3732 false;
3733 }
3734 }
3735 return false;
f1dc5600
S		 3736 case ATH9K_CAP_TXPOW:
3737 switch (capability) {
3738 case 0:
3739 return 0;
3740 case 1:
608b88cb 3741 *result = regulatory->power_limit;
f1dc5600
S		 3742 return 0;
3743 case 2:
608b88cb 3744 *result = regulatory->max_power_level;
f1dc5600
S		 3745 return 0;
3746 case 3:
608b88cb 3747 *result = regulatory->tp_scale;
f1dc5600
S		 3748 return 0;
3749 }
3750 return false;
8bd1d07f
SB		 3751 case ATH9K_CAP_DS:
3752 return (AR_SREV_9280_20_OR_LATER(ah) &&
3753 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3754 ? false : true;
f1dc5600
S		 3755 default:
3756 return false;
f078f209 3757 }
f078f209
LR		 3758}
3759
cbe61d8a 3760bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3761 u32 capability, u32 setting, int *status)
f078f209 3762{
f1dc5600 3763 u32 v;
f078f209 3764
f1dc5600
S		 3765 switch (type) {
3766 case ATH9K_CAP_TKIP_MIC:
3767 if (setting)
2660b81a 3768 ah->sta_id1_defaults |=
f1dc5600
S		 3769 AR_STA_ID1_CRPT_MIC_ENABLE;
3770 else
2660b81a 3771 ah->sta_id1_defaults &=
f1dc5600
S		 3772 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3773 return true;
3774 case ATH9K_CAP_DIVERSITY:
3775 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3776 if (setting)
3777 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3778 else
3779 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3780 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3781 return true;
3782 case ATH9K_CAP_MCAST_KEYSRCH:
3783 if (setting)
2660b81a 3784 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3785 else
2660b81a 3786 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3787 return true;
f1dc5600
S		 3788 default:
3789 return false;
f078f209
LR		 3790 }
3791}
3792
f1dc5600
S		 3793/****************************/
3794/* GPIO / RFKILL / Antennae */
3795/****************************/
f078f209 3796
cbe61d8a 3797static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 3798 u32 gpio, u32 type)
3799{
3800 int addr;
3801 u32 gpio_shift, tmp;
f078f209 3802
f1dc5600
S		 3803 if (gpio > 11)
3804 addr = AR_GPIO_OUTPUT_MUX3;
3805 else if (gpio > 5)
3806 addr = AR_GPIO_OUTPUT_MUX2;
3807 else
3808 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3809
f1dc5600 3810 gpio_shift = (gpio % 6) * 5;
f078f209 3811
f1dc5600
S		 3812 if (AR_SREV_9280_20_OR_LATER(ah)
3813 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3814 REG_RMW(ah, addr, (type << gpio_shift),
3815 (0x1f << gpio_shift));
f078f209 3816 } else {
f1dc5600
S		 3817 tmp = REG_READ(ah, addr);
3818 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3819 tmp &= ~(0x1f << gpio_shift);
3820 tmp |= (type << gpio_shift);
3821 REG_WRITE(ah, addr, tmp);
f078f209 3822 }
f078f209
LR		 3823}
3824
cbe61d8a 3825void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 3826{
f1dc5600 3827 u32 gpio_shift;
f078f209 3828
9680e8a3 3829 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 3830
f1dc5600 3831 gpio_shift = gpio << 1;
f078f209 3832
f1dc5600
S		 3833 REG_RMW(ah,
3834 AR_GPIO_OE_OUT,
3835 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3836 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3837}
3838
cbe61d8a 3839u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 3840{
cb33c412
SB		 3841#define MS_REG_READ(x, y) \
3842 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3843
2660b81a 3844 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 3845 return 0xffffffff;
f078f209 3846
ac88b6ec
VN		 3847 if (AR_SREV_9287_10_OR_LATER(ah))
3848 return MS_REG_READ(AR9287, gpio) != 0;
3849 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 3850 return MS_REG_READ(AR9285, gpio) != 0;
3851 else if (AR_SREV_9280_10_OR_LATER(ah))
3852 return MS_REG_READ(AR928X, gpio) != 0;
3853 else
3854 return MS_REG_READ(AR, gpio) != 0;
f078f209
LR		 3855}
3856
cbe61d8a 3857void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 3858 u32 ah_signal_type)
f078f209 3859{
f1dc5600 3860 u32 gpio_shift;
f078f209 3861
f1dc5600 3862 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3863
f1dc5600 3864 gpio_shift = 2 * gpio;
f078f209 3865
f1dc5600
S		 3866 REG_RMW(ah,
3867 AR_GPIO_OE_OUT,
3868 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3869 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3870}
3871
cbe61d8a 3872void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 3873{
f1dc5600
S		 3874 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3875 AR_GPIO_BIT(gpio));
f078f209
LR		 3876}
3877
cbe61d8a 3878u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 3879{
f1dc5600 3880 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209
LR		 3881}
3882
cbe61d8a 3883void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 3884{
f1dc5600 3885 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209
LR		 3886}
3887
cbe61d8a 3888bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
f1dc5600
S		 3889 enum ath9k_ant_setting settings,
3890 struct ath9k_channel *chan,
3891 u8 *tx_chainmask,
3892 u8 *rx_chainmask,
3893 u8 *antenna_cfgd)
f078f209 3894{
f1dc5600 3895 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
f078f209 3896
f1dc5600
S		 3897 if (AR_SREV_9280(ah)) {
3898 if (!tx_chainmask_cfg) {
f078f209 3899
f1dc5600
S		 3900 tx_chainmask_cfg = *tx_chainmask;
3901 rx_chainmask_cfg = *rx_chainmask;
3902 }
f078f209 3903
f1dc5600
S		 3904 switch (settings) {
3905 case ATH9K_ANT_FIXED_A:
3906 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3907 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3908 *antenna_cfgd = true;
3909 break;
3910 case ATH9K_ANT_FIXED_B:
2660b81a 3911 if (ah->caps.tx_chainmask >
f1dc5600
S		 3912 ATH9K_ANTENNA1_CHAINMASK) {
3913 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3914 }
3915 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3916 *antenna_cfgd = true;
3917 break;
3918 case ATH9K_ANT_VARIABLE:
3919 *tx_chainmask = tx_chainmask_cfg;
3920 *rx_chainmask = rx_chainmask_cfg;
3921 *antenna_cfgd = true;
3922 break;
3923 default:
3924 break;
3925 }
3926 } else {
1cf6873a 3927 ah->config.diversity_control = settings;
f078f209 3928 }
f078f209 3929
f1dc5600 3930 return true;
f078f209
LR		 3931}
3932
f1dc5600
S		 3933/*********************/
3934/* General Operation */
3935/*********************/
3936
cbe61d8a 3937u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 3938{
f1dc5600
S		 3939 u32 bits = REG_READ(ah, AR_RX_FILTER);
3940 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3941
f1dc5600
S		 3942 if (phybits & AR_PHY_ERR_RADAR)
3943 bits |= ATH9K_RX_FILTER_PHYRADAR;
3944 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3945 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3946
f1dc5600 3947 return bits;
f078f209
LR		 3948}
3949
cbe61d8a 3950void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 3951{
f1dc5600 3952 u32 phybits;
f078f209 3953
7ea310be
S		 3954 REG_WRITE(ah, AR_RX_FILTER, bits);
3955
f1dc5600
S		 3956 phybits = 0;
3957 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3958 phybits |= AR_PHY_ERR_RADAR;
3959 if (bits & ATH9K_RX_FILTER_PHYERR)
3960 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3961 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3962
f1dc5600
S		 3963 if (phybits)
3964 REG_WRITE(ah, AR_RXCFG,
3965 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3966 else
3967 REG_WRITE(ah, AR_RXCFG,
3968 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3969}
f078f209 3970
cbe61d8a 3971bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 3972{
63a75b91
SB		 3973 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3974 return false;
3975
3976 ath9k_hw_init_pll(ah, NULL);
3977 return true;
f1dc5600 3978}
f078f209 3979
cbe61d8a 3980bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 3981{
9ecdef4b 3982 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 3983 return false;
f078f209 3984
63a75b91
SB		 3985 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3986 return false;
3987
3988 ath9k_hw_init_pll(ah, NULL);
3989 return true;
f078f209
LR		 3990}
3991
8fbff4b8 3992void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 3993{
608b88cb 3994 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 3995 struct ath9k_channel *chan = ah->curchan;
5f8e077c 3996 struct ieee80211_channel *channel = chan->chan;
f078f209 3997
608b88cb 3998 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 3999
8fbff4b8 4000 ah->eep_ops->set_txpower(ah, chan,
608b88cb 4001 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 4002 channel->max_antenna_gain * 2,
4003 channel->max_power * 2,
4004 min((u32) MAX_RATE_POWER,
608b88cb 4005 (u32) regulatory->power_limit));
6f255425
LR		 4006}
4007
cbe61d8a 4008void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 4009{
1510718d 4010 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209
LR		 4011}
4012
cbe61d8a 4013void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 4014{
2660b81a 4015 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209
LR		 4016}
4017
cbe61d8a 4018void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 4019{
f1dc5600
S		 4020 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4021 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209
LR		 4022}
4023
f2b2143e 4024void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 4025{
1510718d
LR		 4026 struct ath_common *common = ath9k_hw_common(ah);
4027
4028 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
4029 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
4030 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 4031}
4032
cbe61d8a 4033u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 4034{
f1dc5600 4035 u64 tsf;
f078f209 4036
f1dc5600
S		 4037 tsf = REG_READ(ah, AR_TSF_U32);
4038 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 4039
f1dc5600
S		 4040 return tsf;
4041}
f078f209 4042
cbe61d8a 4043void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 4044{
27abe060 4045 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 4046 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060
AF		 4047}
4048
cbe61d8a 4049void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 4050{
f9b604f6
GJ		 4051 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4052 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 4053 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4054 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 4055
f1dc5600
S		 4056 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4057}
f078f209 4058
54e4cec6 4059void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 4060{
f1dc5600 4061 if (setting)
2660b81a 4062 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 4063 else
2660b81a 4064 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 4065}
f078f209 4066
cbe61d8a 4067bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f1dc5600 4068{
f1dc5600 4069 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
c46917bb
LR		 4070 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4071 "bad slot time %u\n", us);
2660b81a 4072 ah->slottime = (u32) -1;
f1dc5600
S		 4073 return false;
4074 } else {
4075 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
2660b81a 4076 ah->slottime = us;
f1dc5600 4077 return true;
f078f209 4078 }
f1dc5600
S		 4079}
4080
25c56eec 4081void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 4082{
25c56eec 4083 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 4084 u32 macmode;
4085
25c56eec 4086 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 4087 macmode = AR_2040_JOINED_RX_CLEAR;
4088 else
4089 macmode = 0;
f078f209 4090
f1dc5600 4091 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 4092}
ff155a45
VT		 4093
4094/* HW Generic timers configuration */
4095
4096static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4097{
4098 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4099 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4100 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4101 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4102 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4103 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4104 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4105 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4106 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4107 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4108 AR_NDP2_TIMER_MODE, 0x0002},
4109 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4110 AR_NDP2_TIMER_MODE, 0x0004},
4111 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4112 AR_NDP2_TIMER_MODE, 0x0008},
4113 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4114 AR_NDP2_TIMER_MODE, 0x0010},
4115 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4116 AR_NDP2_TIMER_MODE, 0x0020},
4117 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4118 AR_NDP2_TIMER_MODE, 0x0040},
4119 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4120 AR_NDP2_TIMER_MODE, 0x0080}
4121};
4122
4123/* HW generic timer primitives */
4124
4125/* compute and clear index of rightmost 1 */
4126static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4127{
4128 u32 b;
4129
4130 b = *mask;
4131 b &= (0-b);
4132 *mask &= ~b;
4133 b *= debruijn32;
4134 b >>= 27;
4135
4136 return timer_table->gen_timer_index[b];
4137}
4138
1773912b 4139u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 4140{
4141 return REG_READ(ah, AR_TSF_L32);
4142}
4143
4144struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4145 void (*trigger)(void *),
4146 void (*overflow)(void *),
4147 void *arg,
4148 u8 timer_index)
4149{
4150 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4151 struct ath_gen_timer *timer;
4152
4153 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4154
4155 if (timer == NULL) {
c46917bb
LR		 4156 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
4157 "Failed to allocate memory"
4158 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 4159 return NULL;
4160 }
4161
4162 /* allocate a hardware generic timer slot */
4163 timer_table->timers[timer_index] = timer;
4164 timer->index = timer_index;
4165 timer->trigger = trigger;
4166 timer->overflow = overflow;
4167 timer->arg = arg;
4168
4169 return timer;
4170}
4171
cd9bf689
LR		 4172void ath9k_hw_gen_timer_start(struct ath_hw *ah,
4173 struct ath_gen_timer *timer,
4174 u32 timer_next,
4175 u32 timer_period)
ff155a45
VT		 4176{
4177 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4178 u32 tsf;
4179
4180 BUG_ON(!timer_period);
4181
4182 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4183
4184 tsf = ath9k_hw_gettsf32(ah);
4185
c46917bb
LR		 4186 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
4187 "curent tsf %x period %x"
4188 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 4189
4190 /*
4191 * Pull timer_next forward if the current TSF already passed it
4192 * because of software latency
4193 */
4194 if (timer_next < tsf)
4195 timer_next = tsf + timer_period;
4196
4197 /*
4198 * Program generic timer registers
4199 */
4200 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4201 timer_next);
4202 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4203 timer_period);
4204 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4205 gen_tmr_configuration[timer->index].mode_mask);
4206
4207 /* Enable both trigger and thresh interrupt masks */
4208 REG_SET_BIT(ah, AR_IMR_S5,
4209 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4210 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45
VT		 4211}
4212
cd9bf689 4213void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 4214{
4215 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4216
4217 if ((timer->index < AR_FIRST_NDP_TIMER) ||
4218 (timer->index >= ATH_MAX_GEN_TIMER)) {
4219 return;
4220 }
4221
4222 /* Clear generic timer enable bits. */
4223 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4224 gen_tmr_configuration[timer->index].mode_mask);
4225
4226 /* Disable both trigger and thresh interrupt masks */
4227 REG_CLR_BIT(ah, AR_IMR_S5,
4228 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4229 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4230
4231 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45
VT		 4232}
4233
4234void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4235{
4236 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4237
4238 /* free the hardware generic timer slot */
4239 timer_table->timers[timer->index] = NULL;
4240 kfree(timer);
4241}
4242
4243/*
4244 * Generic Timer Interrupts handling
4245 */
4246void ath_gen_timer_isr(struct ath_hw *ah)
4247{
4248 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4249 struct ath_gen_timer *timer;
c46917bb 4250 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 4251 u32 trigger_mask, thresh_mask, index;
4252
4253 /* get hardware generic timer interrupt status */
4254 trigger_mask = ah->intr_gen_timer_trigger;
4255 thresh_mask = ah->intr_gen_timer_thresh;
4256 trigger_mask &= timer_table->timer_mask.val;
4257 thresh_mask &= timer_table->timer_mask.val;
4258
4259 trigger_mask &= ~thresh_mask;
4260
4261 while (thresh_mask) {
4262 index = rightmost_index(timer_table, &thresh_mask);
4263 timer = timer_table->timers[index];
4264 BUG_ON(!timer);
c46917bb
LR		 4265 ath_print(common, ATH_DBG_HWTIMER,
4266 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 4267 timer->overflow(timer->arg);
4268 }
4269
4270 while (trigger_mask) {
4271 index = rightmost_index(timer_table, &trigger_mask);
4272 timer = timer_table->timers[index];
4273 BUG_ON(!timer);
c46917bb
LR		 4274 ath_print(common, ATH_DBG_HWTIMER,
4275 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 4276 timer->trigger(timer->arg);
4277 }
4278}
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