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ath9k: Set default noise floor value for AR9287
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
7b6840ab 19#include <linux/pci.h>
f078f209 20
394cf0a1 21#include "ath9k.h"
f078f209
LR		 22#include "initvals.h"
23
4febf7b8
LR		 24#define ATH9K_CLOCK_RATE_CCK 22
25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 27
cbe61d8a
S		 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 30 enum ath9k_ht_macmode macmode);
cbe61d8a 31static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072 32 struct ar5416_eeprom_def *pEepData,
f1dc5600 33 u32 reg, u32 value);
cbe61d8a
S		 34static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
f078f209 36
f1dc5600
S		 37/********************/
38/* Helper Functions */
39/********************/
f078f209 40
cbe61d8a 41static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
f1dc5600 42{
4febf7b8 43 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 44
2660b81a 45 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 46 return clks / ATH9K_CLOCK_RATE_CCK;
47 if (conf->channel->band == IEEE80211_BAND_2GHZ)
48 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
cbe61d8a 49
4febf7b8 50 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 51}
f078f209 52
cbe61d8a 53static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
f1dc5600 54{
4febf7b8 55 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 56
4febf7b8 57 if (conf_is_ht40(conf))
f1dc5600
S		 58 return ath9k_hw_mac_usec(ah, clks) / 2;
59 else
60 return ath9k_hw_mac_usec(ah, clks);
61}
f078f209 62
cbe61d8a 63static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 64{
4febf7b8 65 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 66
2660b81a 67 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 68 return usecs *ATH9K_CLOCK_RATE_CCK;
69 if (conf->channel->band == IEEE80211_BAND_2GHZ)
70 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
71 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 72}
73
cbe61d8a 74static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 75{
4febf7b8 76 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 77
4febf7b8 78 if (conf_is_ht40(conf))
f1dc5600
S		 79 return ath9k_hw_mac_clks(ah, usecs) * 2;
80 else
81 return ath9k_hw_mac_clks(ah, usecs);
82}
f078f209 83
fb4a3d35
GJ		 84/*
85 * Read and write, they both share the same lock. We do this to serialize
86 * reads and writes on Atheros 802.11n PCI devices only. This is required
87 * as the FIFO on these devices can only accept sanely 2 requests. After
88 * that the device goes bananas. Serializing the reads/writes prevents this
89 * from happening.
90 */
91
92void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
93{
94 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
95 unsigned long flags;
96 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
97 iowrite32(val, ah->ah_sc->mem + reg_offset);
98 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
99 } else
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101}
102
103unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
104{
105 u32 val;
106 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
107 unsigned long flags;
108 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
109 val = ioread32(ah->ah_sc->mem + reg_offset);
110 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
111 } else
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 return val;
114}
115
0caa7b14 116bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 117{
118 int i;
119
0caa7b14
S		 120 BUG_ON(timeout < AH_TIME_QUANTUM);
121
122 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 123 if ((REG_READ(ah, reg) & mask) == val)
124 return true;
125
126 udelay(AH_TIME_QUANTUM);
127 }
04bd4638 128
d8baa939 129 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
0caa7b14
S		 130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
131 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 132
f1dc5600 133 return false;
f078f209
LR		 134}
135
136u32 ath9k_hw_reverse_bits(u32 val, u32 n)
137{
138 u32 retval;
139 int i;
140
141 for (i = 0, retval = 0; i < n; i++) {
142 retval = (retval << 1) | (val & 1);
143 val >>= 1;
144 }
145 return retval;
146}
147
cbe61d8a 148bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 149 u16 flags, u16 *low,
150 u16 *high)
f078f209 151{
2660b81a 152 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 153
f1dc5600
S		 154 if (flags & CHANNEL_5GHZ) {
155 *low = pCap->low_5ghz_chan;
156 *high = pCap->high_5ghz_chan;
157 return true;
f078f209 158 }
f1dc5600
S		 159 if ((flags & CHANNEL_2GHZ)) {
160 *low = pCap->low_2ghz_chan;
161 *high = pCap->high_2ghz_chan;
162 return true;
163 }
164 return false;
f078f209
LR		 165}
166
cbe61d8a 167u16 ath9k_hw_computetxtime(struct ath_hw *ah,
4f0fc7c3 168 const struct ath_rate_table *rates,
f1dc5600
S		 169 u32 frameLen, u16 rateix,
170 bool shortPreamble)
f078f209 171{
f1dc5600
S		 172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
173 u32 kbps;
f078f209 174
e63835b0 175 kbps = rates->info[rateix].ratekbps;
f078f209 176
f1dc5600
S		 177 if (kbps == 0)
178 return 0;
f078f209 179
f1dc5600 180 switch (rates->info[rateix].phy) {
46d14a58 181 case WLAN_RC_PHY_CCK:
f1dc5600 182 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
e63835b0 183 if (shortPreamble && rates->info[rateix].short_preamble)
f1dc5600
S		 184 phyTime >>= 1;
185 numBits = frameLen << 3;
186 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
187 break;
46d14a58 188 case WLAN_RC_PHY_OFDM:
2660b81a 189 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 190 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
191 numBits = OFDM_PLCP_BITS + (frameLen << 3);
192 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
193 txTime = OFDM_SIFS_TIME_QUARTER
194 + OFDM_PREAMBLE_TIME_QUARTER
195 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 196 } else if (ah->curchan &&
197 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 198 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
199 numBits = OFDM_PLCP_BITS + (frameLen << 3);
200 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
201 txTime = OFDM_SIFS_TIME_HALF +
202 OFDM_PREAMBLE_TIME_HALF
203 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
204 } else {
205 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
206 numBits = OFDM_PLCP_BITS + (frameLen << 3);
207 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
208 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
209 + (numSymbols * OFDM_SYMBOL_TIME);
210 }
211 break;
212 default:
d8baa939 213 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 214 "Unknown phy %u (rate ix %u)\n",
f1dc5600
S		 215 rates->info[rateix].phy, rateix);
216 txTime = 0;
217 break;
218 }
f078f209 219
f1dc5600
S		 220 return txTime;
221}
f078f209 222
cbe61d8a 223void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 224 struct ath9k_channel *chan,
225 struct chan_centers *centers)
f078f209 226{
f1dc5600 227 int8_t extoff;
f078f209 228
f1dc5600
S		 229 if (!IS_CHAN_HT40(chan)) {
230 centers->ctl_center = centers->ext_center =
231 centers->synth_center = chan->channel;
232 return;
f078f209 233 }
f078f209 234
f1dc5600
S		 235 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
236 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
237 centers->synth_center =
238 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
239 extoff = 1;
240 } else {
241 centers->synth_center =
242 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
243 extoff = -1;
244 }
f078f209 245
f1dc5600
S		 246 centers->ctl_center =
247 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
248 centers->ext_center =
249 centers->synth_center + (extoff *
2660b81a 250 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
f1dc5600 251 HT40_CHANNEL_CENTER_SHIFT : 15));
f078f209
LR		 252}
253
f1dc5600
S		 254/******************/
255/* Chip Revisions */
256/******************/
257
cbe61d8a 258static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 259{
f1dc5600 260 u32 val;
f078f209 261
f1dc5600 262 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 263
f1dc5600
S		 264 if (val == 0xFF) {
265 val = REG_READ(ah, AR_SREV);
d535a42a
S		 266 ah->hw_version.macVersion =
267 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 269 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 270 } else {
271 if (!AR_SREV_9100(ah))
d535a42a 272 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 273
d535a42a 274 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 275
d535a42a 276 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 277 ah->is_pciexpress = true;
f1dc5600 278 }
f078f209
LR		 279}
280
cbe61d8a 281static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 282{
f1dc5600
S		 283 u32 val;
284 int i;
f078f209 285
f1dc5600 286 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 287
f1dc5600
S		 288 for (i = 0; i < 8; i++)
289 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
290 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
291 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 292
f1dc5600 293 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 294}
295
f1dc5600
S		 296/************************************/
297/* HW Attach, Detach, Init Routines */
298/************************************/
299
cbe61d8a 300static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 301{
feed029c 302 if (AR_SREV_9100(ah))
f1dc5600 303 return;
f078f209 304
f1dc5600
S		 305 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
306 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
307 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 314
f1dc5600 315 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 316}
317
cbe61d8a 318static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 319{
f1dc5600
S		 320 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
321 u32 regHold[2];
322 u32 patternData[4] = { 0x55555555,
323 0xaaaaaaaa,
324 0x66666666,
325 0x99999999 };
326 int i, j;
f078f209 327
f1dc5600
S		 328 for (i = 0; i < 2; i++) {
329 u32 addr = regAddr[i];
330 u32 wrData, rdData;
f078f209 331
f1dc5600
S		 332 regHold[i] = REG_READ(ah, addr);
333 for (j = 0; j < 0x100; j++) {
334 wrData = (j << 16) | j;
335 REG_WRITE(ah, addr, wrData);
336 rdData = REG_READ(ah, addr);
337 if (rdData != wrData) {
d8baa939 338 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 339 "address test failed "
f1dc5600 340 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 341 addr, wrData, rdData);
f1dc5600
S		 342 return false;
343 }
344 }
345 for (j = 0; j < 4; j++) {
346 wrData = patternData[j];
347 REG_WRITE(ah, addr, wrData);
348 rdData = REG_READ(ah, addr);
349 if (wrData != rdData) {
d8baa939 350 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 351 "address test failed "
f1dc5600 352 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 353 addr, wrData, rdData);
f1dc5600
S		 354 return false;
355 }
f078f209 356 }
f1dc5600 357 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 358 }
f1dc5600 359 udelay(100);
cbe61d8a 360
f078f209
LR		 361 return true;
362}
363
f1dc5600 364static const char *ath9k_hw_devname(u16 devid)
f078f209 365{
f1dc5600
S		 366 switch (devid) {
367 case AR5416_DEVID_PCI:
f1dc5600 368 return "Atheros 5416";
392dff83
BP		 369 case AR5416_DEVID_PCIE:
370 return "Atheros 5418";
f1dc5600
S		 371 case AR9160_DEVID_PCI:
372 return "Atheros 9160";
0c1aa495
GJ		 373 case AR5416_AR9100_DEVID:
374 return "Atheros 9100";
f1dc5600
S		 375 case AR9280_DEVID_PCI:
376 case AR9280_DEVID_PCIE:
377 return "Atheros 9280";
e7594072
SB		 378 case AR9285_DEVID_PCIE:
379 return "Atheros 9285";
ac88b6ec
VN		 380 case AR5416_DEVID_AR9287_PCI:
381 case AR5416_DEVID_AR9287_PCIE:
382 return "Atheros 9287";
f078f209
LR		 383 }
384
f1dc5600
S		 385 return NULL;
386}
f078f209 387
b8b0f377 388static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 389{
390 int i;
f078f209 391
2660b81a
S		 392 ah->config.dma_beacon_response_time = 2;
393 ah->config.sw_beacon_response_time = 10;
394 ah->config.additional_swba_backoff = 0;
395 ah->config.ack_6mb = 0x0;
396 ah->config.cwm_ignore_extcca = 0;
397 ah->config.pcie_powersave_enable = 0;
2660b81a 398 ah->config.pcie_clock_req = 0;
2660b81a
S		 399 ah->config.pcie_waen = 0;
400 ah->config.analog_shiftreg = 1;
401 ah->config.ht_enable = 1;
402 ah->config.ofdm_trig_low = 200;
403 ah->config.ofdm_trig_high = 500;
404 ah->config.cck_trig_high = 200;
405 ah->config.cck_trig_low = 100;
406 ah->config.enable_ani = 1;
1cf6873a 407 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
2660b81a 408 ah->config.antenna_switch_swap = 0;
f078f209 409
f1dc5600 410 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 411 ah->config.spurchans[i][0] = AR_NO_SPUR;
412 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 413 }
414
0ef1f168 415 ah->config.intr_mitigation = true;
6158425b
LR		 416
417 /*
418 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
419 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
420 * This means we use it for all AR5416 devices, and the few
421 * minor PCI AR9280 devices out there.
422 *
423 * Serialization is required because these devices do not handle
424 * well the case of two concurrent reads/writes due to the latency
425 * involved. During one read/write another read/write can be issued
426 * on another CPU while the previous read/write may still be working
427 * on our hardware, if we hit this case the hardware poops in a loop.
428 * We prevent this by serializing reads and writes.
429 *
430 * This issue is not present on PCI-Express devices or pre-AR5416
431 * devices (legacy, 802.11abg).
432 */
433 if (num_possible_cpus() > 1)
2d6a5e95 434 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 435}
436
50aca25b 437static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 438{
608b88cb
LR		 439 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
440
441 regulatory->country_code = CTRY_DEFAULT;
442 regulatory->power_limit = MAX_RATE_POWER;
443 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
444
d535a42a 445 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 446 ah->hw_version.subvendorid = 0;
f078f209
LR		 447
448 ah->ah_flags = 0;
8df5d1b7 449 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
d535a42a 450 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
f078f209
LR		 451 if (!AR_SREV_9100(ah))
452 ah->ah_flags = AH_USE_EEPROM;
453
2660b81a 454 ah->atim_window = 0;
2660b81a
S		 455 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
456 ah->beacon_interval = 100;
457 ah->enable_32kHz_clock = DONT_USE_32KHZ;
458 ah->slottime = (u32) -1;
459 ah->acktimeout = (u32) -1;
460 ah->ctstimeout = (u32) -1;
461 ah->globaltxtimeout = (u32) -1;
462
463 ah->gbeacon_rate = 0;
f078f209 464
cbdec975 465 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 466}
467
cbe61d8a 468static int ath9k_hw_rfattach(struct ath_hw *ah)
f078f209 469{
f1dc5600
S		 470 bool rfStatus = false;
471 int ecode = 0;
f078f209 472
f1dc5600
S		 473 rfStatus = ath9k_hw_init_rf(ah, &ecode);
474 if (!rfStatus) {
d8baa939
S		 475 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
476 "RF setup failed, status: %u\n", ecode);
f1dc5600
S		 477 return ecode;
478 }
f078f209 479
f1dc5600 480 return 0;
f078f209
LR		 481}
482
cbe61d8a 483static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 484{
f1dc5600
S		 485 u32 val;
486
487 REG_WRITE(ah, AR_PHY(0), 0x00000007);
488
489 val = ath9k_hw_get_radiorev(ah);
490 switch (val & AR_RADIO_SREV_MAJOR) {
491 case 0:
492 val = AR_RAD5133_SREV_MAJOR;
493 break;
494 case AR_RAD5133_SREV_MAJOR:
495 case AR_RAD5122_SREV_MAJOR:
496 case AR_RAD2133_SREV_MAJOR:
497 case AR_RAD2122_SREV_MAJOR:
498 break;
f078f209 499 default:
d8baa939
S		 500 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
501 "Radio Chip Rev 0x%02X not supported\n",
502 val & AR_RADIO_SREV_MAJOR);
f1dc5600 503 return -EOPNOTSUPP;
f078f209 504 }
f078f209 505
d535a42a 506 ah->hw_version.analog5GhzRev = val;
f078f209 507
f1dc5600 508 return 0;
f078f209
LR		 509}
510
cbe61d8a 511static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209
LR		 512{
513 u32 sum;
514 int i;
515 u16 eeval;
f078f209
LR		 516
517 sum = 0;
518 for (i = 0; i < 3; i++) {
f74df6fb 519 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 520 sum += eeval;
ba52da58
S		 521 ah->macaddr[2 * i] = eeval >> 8;
522 ah->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 523 }
d8baa939 524 if (sum == 0 || sum == 0xffff * 3)
f078f209 525 return -EADDRNOTAVAIL;
f078f209
LR		 526
527 return 0;
528}
529
cbe61d8a 530static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 531{
532 u32 rxgain_type;
9f804202 533
f74df6fb
S		 534 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
535 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 536
537 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 538 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 539 ar9280Modes_backoff_13db_rxgain_9280_2,
540 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
541 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 542 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 543 ar9280Modes_backoff_23db_rxgain_9280_2,
544 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
545 else
2660b81a 546 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 547 ar9280Modes_original_rxgain_9280_2,
548 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 549 } else {
2660b81a 550 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 551 ar9280Modes_original_rxgain_9280_2,
552 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 553 }
9f804202
SB		 554}
555
cbe61d8a 556static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 557{
558 u32 txgain_type;
9f804202 559
f74df6fb
S		 560 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
561 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 562
563 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 564 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 565 ar9280Modes_high_power_tx_gain_9280_2,
566 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
567 else
2660b81a 568 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 569 ar9280Modes_original_tx_gain_9280_2,
570 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 571 } else {
2660b81a 572 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 573 ar9280Modes_original_tx_gain_9280_2,
574 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 575 }
9f804202
SB		 576}
577
f637cfd6 578static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 579{
f1dc5600 580 int ecode;
f078f209 581
d8baa939 582 if (!ath9k_hw_chip_test(ah))
f1dc5600 583 return -ENODEV;
f078f209 584
f1dc5600
S		 585 ecode = ath9k_hw_rf_claim(ah);
586 if (ecode != 0)
f078f209 587 return ecode;
f078f209 588
f637cfd6 589 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 590 if (ecode != 0)
591 return ecode;
7d01b221
S		 592
593 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
594 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
595
f1dc5600
S		 596 ecode = ath9k_hw_rfattach(ah);
597 if (ecode != 0)
598 return ecode;
f078f209 599
f1dc5600
S		 600 if (!AR_SREV_9100(ah)) {
601 ath9k_hw_ani_setup(ah);
f637cfd6 602 ath9k_hw_ani_init(ah);
f078f209
LR		 603 }
604
f078f209
LR		 605 return 0;
606}
607
ee2bb460
LR		 608static bool ath9k_hw_devid_supported(u16 devid)
609{
610 switch (devid) {
611 case AR5416_DEVID_PCI:
612 case AR5416_DEVID_PCIE:
613 case AR5416_AR9100_DEVID:
614 case AR9160_DEVID_PCI:
615 case AR9280_DEVID_PCI:
616 case AR9280_DEVID_PCIE:
617 case AR9285_DEVID_PCIE:
618 case AR5416_DEVID_AR9287_PCI:
619 case AR5416_DEVID_AR9287_PCIE:
620 return true;
621 default:
622 break;
623 }
624 return false;
625}
626
f9d4a668
LR		 627static bool ath9k_hw_macversion_supported(u32 macversion)
628{
629 switch (macversion) {
630 case AR_SREV_VERSION_5416_PCI:
631 case AR_SREV_VERSION_5416_PCIE:
632 case AR_SREV_VERSION_9160:
633 case AR_SREV_VERSION_9100:
634 case AR_SREV_VERSION_9280:
635 case AR_SREV_VERSION_9285:
636 case AR_SREV_VERSION_9287:
637 return true;
d7e7d229
LR		 638 /* Not yet */
639 case AR_SREV_VERSION_9271:
f9d4a668
LR		 640 default:
641 break;
642 }
643 return false;
644}
645
aa4058ae 646static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
f078f209 647{
f1dc5600
S		 648 if (AR_SREV_9160_10_OR_LATER(ah)) {
649 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a
S		 650 ah->iq_caldata.calData = &iq_cal_single_sample;
651 ah->adcgain_caldata.calData =
f1dc5600 652 &adc_gain_cal_single_sample;
2660b81a 653 ah->adcdc_caldata.calData =
f1dc5600 654 &adc_dc_cal_single_sample;
2660b81a 655 ah->adcdc_calinitdata.calData =
f1dc5600
S		 656 &adc_init_dc_cal;
657 } else {
2660b81a
S		 658 ah->iq_caldata.calData = &iq_cal_multi_sample;
659 ah->adcgain_caldata.calData =
f1dc5600 660 &adc_gain_cal_multi_sample;
2660b81a 661 ah->adcdc_caldata.calData =
f1dc5600 662 &adc_dc_cal_multi_sample;
2660b81a 663 ah->adcdc_calinitdata.calData =
f1dc5600
S		 664 &adc_init_dc_cal;
665 }
2660b81a 666 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
f1dc5600 667 }
aa4058ae 668}
f078f209 669
aa4058ae
LR		 670static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
671{
d7e7d229
LR		 672 if (AR_SREV_9271(ah)) {
673 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
674 ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
675 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
676 ARRAY_SIZE(ar9271Common_9271_1_0), 2);
677 return;
678 }
679
ac88b6ec
VN		 680 if (AR_SREV_9287_11_OR_LATER(ah)) {
681 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
682 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
683 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
684 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
685 if (ah->config.pcie_clock_req)
686 INIT_INI_ARRAY(&ah->iniPcieSerdes,
687 ar9287PciePhy_clkreq_off_L1_9287_1_1,
688 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
689 else
690 INIT_INI_ARRAY(&ah->iniPcieSerdes,
691 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
692 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
693 2);
694 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
695 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
696 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
697 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
698 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
699
700 if (ah->config.pcie_clock_req)
701 INIT_INI_ARRAY(&ah->iniPcieSerdes,
702 ar9287PciePhy_clkreq_off_L1_9287_1_0,
703 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
704 else
705 INIT_INI_ARRAY(&ah->iniPcieSerdes,
706 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
707 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
708 2);
709 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
f078f209 710
4e845168 711
2660b81a 712 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
e7594072 713 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
2660b81a 714 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
e7594072
SB		 715 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
716
2660b81a
S		 717 if (ah->config.pcie_clock_req) {
718 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 719 ar9285PciePhy_clkreq_off_L1_9285_1_2,
720 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
721 } else {
2660b81a 722 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 723 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
724 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
725 2);
726 }
727 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
2660b81a 728 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
e7594072 729 ARRAY_SIZE(ar9285Modes_9285), 6);
2660b81a 730 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
e7594072
SB		 731 ARRAY_SIZE(ar9285Common_9285), 2);
732
2660b81a
S		 733 if (ah->config.pcie_clock_req) {
734 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 735 ar9285PciePhy_clkreq_off_L1_9285,
736 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
737 } else {
2660b81a 738 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 739 ar9285PciePhy_clkreq_always_on_L1_9285,
740 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
741 }
742 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a 743 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
f1dc5600 744 ARRAY_SIZE(ar9280Modes_9280_2), 6);
2660b81a 745 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
f1dc5600 746 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 747
2660b81a
S		 748 if (ah->config.pcie_clock_req) {
749 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 750 ar9280PciePhy_clkreq_off_L1_9280,
751 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
752 } else {
2660b81a 753 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 754 ar9280PciePhy_clkreq_always_on_L1_9280,
755 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
756 }
2660b81a 757 INIT_INI_ARRAY(&ah->iniModesAdditional,
f1dc5600
S		 758 ar9280Modes_fast_clock_9280_2,
759 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
760 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 761 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
f1dc5600 762 ARRAY_SIZE(ar9280Modes_9280), 6);
2660b81a 763 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
f1dc5600
S		 764 ARRAY_SIZE(ar9280Common_9280), 2);
765 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2660b81a 766 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
f1dc5600 767 ARRAY_SIZE(ar5416Modes_9160), 6);
2660b81a 768 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
f1dc5600 769 ARRAY_SIZE(ar5416Common_9160), 2);
2660b81a 770 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
f1dc5600 771 ARRAY_SIZE(ar5416Bank0_9160), 2);
2660b81a 772 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
f1dc5600 773 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
2660b81a 774 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
f1dc5600 775 ARRAY_SIZE(ar5416Bank1_9160), 2);
2660b81a 776 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
f1dc5600 777 ARRAY_SIZE(ar5416Bank2_9160), 2);
2660b81a 778 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
f1dc5600 779 ARRAY_SIZE(ar5416Bank3_9160), 3);
2660b81a 780 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
f1dc5600 781 ARRAY_SIZE(ar5416Bank6_9160), 3);
2660b81a 782 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
f1dc5600 783 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
2660b81a 784 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
f1dc5600
S		 785 ARRAY_SIZE(ar5416Bank7_9160), 2);
786 if (AR_SREV_9160_11(ah)) {
2660b81a 787 INIT_INI_ARRAY(&ah->iniAddac,
f1dc5600
S		 788 ar5416Addac_91601_1,
789 ARRAY_SIZE(ar5416Addac_91601_1), 2);
790 } else {
2660b81a 791 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
f1dc5600
S		 792 ARRAY_SIZE(ar5416Addac_9160), 2);
793 }
794 } else if (AR_SREV_9100_OR_LATER(ah)) {
2660b81a 795 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
f1dc5600 796 ARRAY_SIZE(ar5416Modes_9100), 6);
2660b81a 797 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
f1dc5600 798 ARRAY_SIZE(ar5416Common_9100), 2);
2660b81a 799 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
f1dc5600 800 ARRAY_SIZE(ar5416Bank0_9100), 2);
2660b81a 801 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
f1dc5600 802 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
2660b81a 803 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
f1dc5600 804 ARRAY_SIZE(ar5416Bank1_9100), 2);
2660b81a 805 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
f1dc5600 806 ARRAY_SIZE(ar5416Bank2_9100), 2);
2660b81a 807 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
f1dc5600 808 ARRAY_SIZE(ar5416Bank3_9100), 3);
2660b81a 809 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
f1dc5600 810 ARRAY_SIZE(ar5416Bank6_9100), 3);
2660b81a 811 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
f1dc5600 812 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
2660b81a 813 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
f1dc5600 814 ARRAY_SIZE(ar5416Bank7_9100), 2);
2660b81a 815 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
f1dc5600
S		 816 ARRAY_SIZE(ar5416Addac_9100), 2);
817 } else {
2660b81a 818 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
f1dc5600 819 ARRAY_SIZE(ar5416Modes), 6);
2660b81a 820 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
f1dc5600 821 ARRAY_SIZE(ar5416Common), 2);
2660b81a 822 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
f1dc5600 823 ARRAY_SIZE(ar5416Bank0), 2);
2660b81a 824 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
f1dc5600 825 ARRAY_SIZE(ar5416BB_RfGain), 3);
2660b81a 826 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
f1dc5600 827 ARRAY_SIZE(ar5416Bank1), 2);
2660b81a 828 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
f1dc5600 829 ARRAY_SIZE(ar5416Bank2), 2);
2660b81a 830 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
f1dc5600 831 ARRAY_SIZE(ar5416Bank3), 3);
2660b81a 832 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
f1dc5600 833 ARRAY_SIZE(ar5416Bank6), 3);
2660b81a 834 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
f1dc5600 835 ARRAY_SIZE(ar5416Bank6TPC), 3);
2660b81a 836 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
f1dc5600 837 ARRAY_SIZE(ar5416Bank7), 2);
2660b81a 838 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
f1dc5600 839 ARRAY_SIZE(ar5416Addac), 2);
f078f209 840 }
aa4058ae 841}
f078f209 842
aa4058ae
LR		 843static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
844{
ac88b6ec
VN		 845 if (AR_SREV_9287_11(ah))
846 INIT_INI_ARRAY(&ah->iniModesRxGain,
847 ar9287Modes_rx_gain_9287_1_1,
848 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
849 else if (AR_SREV_9287_10(ah))
850 INIT_INI_ARRAY(&ah->iniModesRxGain,
851 ar9287Modes_rx_gain_9287_1_0,
852 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
853 else if (AR_SREV_9280_20(ah))
854 ath9k_hw_init_rxgain_ini(ah);
855
856 if (AR_SREV_9287_11(ah)) {
857 INIT_INI_ARRAY(&ah->iniModesTxGain,
858 ar9287Modes_tx_gain_9287_1_1,
859 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
860 } else if (AR_SREV_9287_10(ah)) {
861 INIT_INI_ARRAY(&ah->iniModesTxGain,
862 ar9287Modes_tx_gain_9287_1_0,
863 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
864 } else if (AR_SREV_9280_20(ah)) {
865 ath9k_hw_init_txgain_ini(ah);
866 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4e845168
SB		 867 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
868
869 /* txgain table */
870 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
871 INIT_INI_ARRAY(&ah->iniModesTxGain,
872 ar9285Modes_high_power_tx_gain_9285_1_2,
873 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
874 } else {
875 INIT_INI_ARRAY(&ah->iniModesTxGain,
876 ar9285Modes_original_tx_gain_9285_1_2,
877 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
878 }
879
880 }
aa4058ae 881}
4e845168 882
aa4058ae
LR		 883static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
884{
885 u32 i, j;
06d0f066
S		 886
887 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
888 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
889
890 /* EEPROM Fixup */
2660b81a
S		 891 for (i = 0; i < ah->iniModes.ia_rows; i++) {
892 u32 reg = INI_RA(&ah->iniModes, i, 0);
f078f209 893
2660b81a
S		 894 for (j = 1; j < ah->iniModes.ia_columns; j++) {
895 u32 val = INI_RA(&ah->iniModes, i, j);
f078f209 896
2660b81a 897 INI_RA(&ah->iniModes, i, j) =
e7594072 898 ath9k_hw_ini_fixup(ah,
2660b81a 899 &ah->eeprom.def,
f1dc5600
S		 900 reg, val);
901 }
f078f209 902 }
f1dc5600 903 }
aa4058ae
LR		 904}
905
f637cfd6 906int ath9k_hw_init(struct ath_hw *ah)
aa4058ae 907{
95fafca2 908 int r = 0;
aa4058ae 909
95fafca2
LR		 910 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
911 return -EOPNOTSUPP;
aa4058ae
LR		 912
913 ath9k_hw_init_defaults(ah);
914 ath9k_hw_init_config(ah);
915
916 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
917 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
95fafca2 918 return -EIO;
aa4058ae
LR		 919 }
920
921 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
922 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 923 return -EIO;
aa4058ae
LR		 924 }
925
926 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
927 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
928 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
929 ah->config.serialize_regmode =
930 SER_REG_MODE_ON;
931 } else {
932 ah->config.serialize_regmode =
933 SER_REG_MODE_OFF;
934 }
935 }
936
937 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
938 ah->config.serialize_regmode);
939
940 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
941 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
942 "Mac Chip Rev 0x%02x.%x is not supported by "
943 "this driver\n", ah->hw_version.macVersion,
944 ah->hw_version.macRev);
95fafca2 945 return -EOPNOTSUPP;
aa4058ae
LR		 946 }
947
948 if (AR_SREV_9100(ah)) {
949 ah->iq_caldata.calData = &iq_cal_multi_sample;
950 ah->supp_cals = IQ_MISMATCH_CAL;
951 ah->is_pciexpress = false;
952 }
d7e7d229
LR		 953
954 if (AR_SREV_9271(ah))
955 ah->is_pciexpress = false;
956
aa4058ae
LR		 957 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
958
959 ath9k_hw_init_cal_settings(ah);
960
961 ah->ani_function = ATH9K_ANI_ALL;
962 if (AR_SREV_9280_10_OR_LATER(ah))
963 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
964
965 ath9k_hw_init_mode_regs(ah);
966
967 if (ah->is_pciexpress)
968 ath9k_hw_configpcipowersave(ah, 0);
969 else
970 ath9k_hw_disablepcie(ah);
971
f637cfd6 972 r = ath9k_hw_post_init(ah);
aa4058ae 973 if (r)
95fafca2 974 return r;
aa4058ae
LR		 975
976 ath9k_hw_init_mode_gain_regs(ah);
977 ath9k_hw_fill_cap_info(ah);
978 ath9k_hw_init_11a_eeprom_fix(ah);
f6688cd8 979
4f3acf81
LR		 980 r = ath9k_hw_init_macaddr(ah);
981 if (r) {
07c10c61 982 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
d8baa939 983 "Failed to initialize MAC address\n");
95fafca2 984 return r;
f078f209
LR		 985 }
986
d7e7d229 987 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 988 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 989 else
2660b81a 990 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 991
f1dc5600 992 ath9k_init_nfcal_hist_buffer(ah);
f078f209 993
4f3acf81 994 return 0;
f078f209
LR		 995}
996
cbe61d8a 997static void ath9k_hw_init_bb(struct ath_hw *ah,
f1dc5600 998 struct ath9k_channel *chan)
f078f209 999{
f1dc5600 1000 u32 synthDelay;
f078f209 1001
f1dc5600 1002 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1003 if (IS_CHAN_B(chan))
f1dc5600
S		 1004 synthDelay = (4 * synthDelay) / 22;
1005 else
1006 synthDelay /= 10;
f078f209 1007
f1dc5600 1008 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 1009
f1dc5600 1010 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 1011}
1012
cbe61d8a 1013static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 1014{
f1dc5600
S		 1015 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1016 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 1017
f1dc5600
S		 1018 REG_WRITE(ah, AR_QOS_NO_ACK,
1019 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1020 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1021 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1022
1023 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1024 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1025 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1026 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1027 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 1028}
1029
cbe61d8a 1030static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 1031 struct ath9k_channel *chan)
f078f209 1032{
f1dc5600 1033 u32 pll;
f078f209 1034
f1dc5600
S		 1035 if (AR_SREV_9100(ah)) {
1036 if (chan && IS_CHAN_5GHZ(chan))
1037 pll = 0x1450;
f078f209 1038 else
f1dc5600
S		 1039 pll = 0x1458;
1040 } else {
1041 if (AR_SREV_9280_10_OR_LATER(ah)) {
1042 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1043
f1dc5600
S		 1044 if (chan && IS_CHAN_HALF_RATE(chan))
1045 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1046 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1047 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1048
f1dc5600
S		 1049 if (chan && IS_CHAN_5GHZ(chan)) {
1050 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 1051
f078f209 1052
f1dc5600
S		 1053 if (AR_SREV_9280_20(ah)) {
1054 if (((chan->channel % 20) == 0)
1055 || ((chan->channel % 10) == 0))
1056 pll = 0x2850;
1057 else
1058 pll = 0x142c;
1059 }
1060 } else {
1061 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1062 }
f078f209 1063
f1dc5600 1064 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 1065
f1dc5600 1066 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1067
f1dc5600
S		 1068 if (chan && IS_CHAN_HALF_RATE(chan))
1069 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1070 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1071 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1072
f1dc5600
S		 1073 if (chan && IS_CHAN_5GHZ(chan))
1074 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1075 else
1076 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1077 } else {
1078 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 1079
f1dc5600
S		 1080 if (chan && IS_CHAN_HALF_RATE(chan))
1081 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1082 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1083 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 1084
f1dc5600
S		 1085 if (chan && IS_CHAN_5GHZ(chan))
1086 pll |= SM(0xa, AR_RTC_PLL_DIV);
1087 else
1088 pll |= SM(0xb, AR_RTC_PLL_DIV);
1089 }
1090 }
d03a66c1 1091 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 1092
f1dc5600
S		 1093 udelay(RTC_PLL_SETTLE_DELAY);
1094
1095 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1096}
1097
cbe61d8a 1098static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
f078f209 1099{
f078f209
LR		 1100 int rx_chainmask, tx_chainmask;
1101
2660b81a
S		 1102 rx_chainmask = ah->rxchainmask;
1103 tx_chainmask = ah->txchainmask;
f078f209
LR		 1104
1105 switch (rx_chainmask) {
1106 case 0x5:
1107 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1108 AR_PHY_SWAP_ALT_CHAIN);
1109 case 0x3:
d535a42a 1110 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
f078f209
LR		 1111 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1112 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1113 break;
1114 }
1115 case 0x1:
1116 case 0x2:
f078f209
LR		 1117 case 0x7:
1118 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1119 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1120 break;
1121 default:
1122 break;
1123 }
1124
1125 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1126 if (tx_chainmask == 0x5) {
1127 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1128 AR_PHY_SWAP_ALT_CHAIN);
1129 }
1130 if (AR_SREV_9100(ah))
1131 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1132 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1133}
1134
cbe61d8a 1135static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 1136 enum nl80211_iftype opmode)
f078f209 1137{
2660b81a 1138 ah->mask_reg = AR_IMR_TXERR |
f1dc5600
S		 1139 AR_IMR_TXURN |
1140 AR_IMR_RXERR |
1141 AR_IMR_RXORN |
1142 AR_IMR_BCNMISC;
f078f209 1143
0ef1f168 1144 if (ah->config.intr_mitigation)
2660b81a 1145 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1146 else
2660b81a 1147 ah->mask_reg |= AR_IMR_RXOK;
f078f209 1148
2660b81a 1149 ah->mask_reg |= AR_IMR_TXOK;
f078f209 1150
d97809db 1151 if (opmode == NL80211_IFTYPE_AP)
2660b81a 1152 ah->mask_reg |= AR_IMR_MIB;
f078f209 1153
2660b81a 1154 REG_WRITE(ah, AR_IMR, ah->mask_reg);
f1dc5600 1155 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1156
f1dc5600
S		 1157 if (!AR_SREV_9100(ah)) {
1158 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1159 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1160 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1161 }
f078f209
LR		 1162}
1163
cbe61d8a 1164static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1165{
f078f209 1166 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
04bd4638 1167 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
2660b81a 1168 ah->acktimeout = (u32) -1;
f078f209
LR		 1169 return false;
1170 } else {
1171 REG_RMW_FIELD(ah, AR_TIME_OUT,
1172 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1173 ah->acktimeout = us;
f078f209
LR		 1174 return true;
1175 }
1176}
1177
cbe61d8a 1178static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
f078f209 1179{
f078f209 1180 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
04bd4638 1181 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
2660b81a 1182 ah->ctstimeout = (u32) -1;
f078f209
LR		 1183 return false;
1184 } else {
1185 REG_RMW_FIELD(ah, AR_TIME_OUT,
1186 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1187 ah->ctstimeout = us;
f078f209
LR		 1188 return true;
1189 }
1190}
f1dc5600 1191
cbe61d8a 1192static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1193{
f078f209
LR		 1194 if (tu > 0xFFFF) {
1195 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
04bd4638 1196 "bad global tx timeout %u\n", tu);
2660b81a 1197 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1198 return false;
1199 } else {
1200 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1201 ah->globaltxtimeout = tu;
f078f209
LR		 1202 return true;
1203 }
1204}
1205
cbe61d8a 1206static void ath9k_hw_init_user_settings(struct ath_hw *ah)
f078f209 1207{
2660b81a
S		 1208 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1209 ah->misc_mode);
f078f209 1210
2660b81a 1211 if (ah->misc_mode != 0)
f1dc5600 1212 REG_WRITE(ah, AR_PCU_MISC,
2660b81a
S		 1213 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1214 if (ah->slottime != (u32) -1)
1215 ath9k_hw_setslottime(ah, ah->slottime);
1216 if (ah->acktimeout != (u32) -1)
1217 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1218 if (ah->ctstimeout != (u32) -1)
1219 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1220 if (ah->globaltxtimeout != (u32) -1)
1221 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600
S		 1222}
1223
1224const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1225{
1226 return vendorid == ATHEROS_VENDOR_ID ?
1227 ath9k_hw_devname(devid) : NULL;
1228}
1229
cbe61d8a 1230void ath9k_hw_detach(struct ath_hw *ah)
f1dc5600
S		 1231{
1232 if (!AR_SREV_9100(ah))
e70c0cfd 1233 ath9k_hw_ani_disable(ah);
f1dc5600 1234
081b35ab 1235 ath9k_hw_rf_free(ah);
f1dc5600
S		 1236 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1237 kfree(ah);
9db6b6a2 1238 ah = NULL;
f1dc5600
S		 1239}
1240
f1dc5600
S		 1241/*******/
1242/* INI */
1243/*******/
1244
cbe61d8a 1245static void ath9k_hw_override_ini(struct ath_hw *ah,
f1dc5600
S		 1246 struct ath9k_channel *chan)
1247{
d7e7d229
LR		 1248 u32 val;
1249
1250 if (AR_SREV_9271(ah)) {
1251 /*
1252 * Enable spectral scan to solution for issues with stuck
1253 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1254 * AR9271 1.1
1255 */
1256 if (AR_SREV_9271_10(ah)) {
1257 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1258 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1259 }
1260 else if (AR_SREV_9271_11(ah))
1261 /*
1262 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1263 * present on AR9271 1.1
1264 */
1265 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1266 return;
1267 }
1268
8aa15e15
SB		 1269 /*
1270 * Set the RX_ABORT and RX_DIS and clear if off only after
1271 * RXE is set for MAC. This prevents frames with corrupted
1272 * descriptor status.
1273 */
1274 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1275
1276
a8c96d3b 1277 if (!AR_SREV_5416_20_OR_LATER(ah) ||
f1dc5600
S		 1278 AR_SREV_9280_10_OR_LATER(ah))
1279 return;
d7e7d229
LR		 1280 /*
1281 * Disable BB clock gating
1282 * Necessary to avoid issues on AR5416 2.0
1283 */
f1dc5600 1284 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1285}
1286
cbe61d8a 1287static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
e7594072 1288 struct ar5416_eeprom_def *pEepData,
f1dc5600 1289 u32 reg, u32 value)
f078f209 1290{
f1dc5600 1291 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
f078f209 1292
d535a42a 1293 switch (ah->hw_version.devid) {
f1dc5600
S		 1294 case AR9280_DEVID_PCI:
1295 if (reg == 0x7894) {
d8baa939 1296 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
f1dc5600
S		 1297 "ini VAL: %x EEPROM: %x\n", value,
1298 (pBase->version & 0xff));
1299
1300 if ((pBase->version & 0xff) > 0x0a) {
d8baa939 1301 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
f1dc5600
S		 1302 "PWDCLKIND: %d\n",
1303 pBase->pwdclkind);
1304 value &= ~AR_AN_TOP2_PWDCLKIND;
1305 value |= AR_AN_TOP2_PWDCLKIND &
1306 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1307 } else {
d8baa939 1308 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
f1dc5600
S		 1309 "PWDCLKIND Earlier Rev\n");
1310 }
1311
d8baa939 1312 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
f1dc5600
S		 1313 "final ini VAL: %x\n", value);
1314 }
1315 break;
1316 }
1317
1318 return value;
f078f209
LR		 1319}
1320
cbe61d8a 1321static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072
SB		 1322 struct ar5416_eeprom_def *pEepData,
1323 u32 reg, u32 value)
1324{
2660b81a 1325 if (ah->eep_map == EEP_MAP_4KBITS)
e7594072
SB		 1326 return value;
1327 else
1328 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1329}
1330
8bd1d07f
SB		 1331static void ath9k_olc_init(struct ath_hw *ah)
1332{
1333 u32 i;
1334
db91f2e4
VN		 1335 if (OLC_FOR_AR9287_10_LATER) {
1336 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1337 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1338 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1339 AR9287_AN_TXPC0_TXPCMODE,
1340 AR9287_AN_TXPC0_TXPCMODE_S,
1341 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1342 udelay(100);
1343 } else {
1344 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1345 ah->originalGain[i] =
1346 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1347 AR_PHY_TX_GAIN);
1348 ah->PDADCdelta = 0;
1349 }
8bd1d07f
SB		 1350}
1351
3a702e49
BC		 1352static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1353 struct ath9k_channel *chan)
1354{
1355 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1356
1357 if (IS_CHAN_B(chan))
1358 ctl |= CTL_11B;
1359 else if (IS_CHAN_G(chan))
1360 ctl |= CTL_11G;
1361 else
1362 ctl |= CTL_11A;
1363
1364 return ctl;
1365}
1366
cbe61d8a 1367static int ath9k_hw_process_ini(struct ath_hw *ah,
f1dc5600
S		 1368 struct ath9k_channel *chan,
1369 enum ath9k_ht_macmode macmode)
f078f209 1370{
608b88cb 1371 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f078f209 1372 int i, regWrites = 0;
5f8e077c 1373 struct ieee80211_channel *channel = chan->chan;
f078f209 1374 u32 modesIndex, freqIndex;
f078f209
LR		 1375
1376 switch (chan->chanmode) {
1377 case CHANNEL_A:
1378 case CHANNEL_A_HT20:
1379 modesIndex = 1;
1380 freqIndex = 1;
1381 break;
1382 case CHANNEL_A_HT40PLUS:
1383 case CHANNEL_A_HT40MINUS:
1384 modesIndex = 2;
1385 freqIndex = 1;
1386 break;
1387 case CHANNEL_G:
1388 case CHANNEL_G_HT20:
1389 case CHANNEL_B:
1390 modesIndex = 4;
1391 freqIndex = 2;
1392 break;
1393 case CHANNEL_G_HT40PLUS:
1394 case CHANNEL_G_HT40MINUS:
1395 modesIndex = 3;
1396 freqIndex = 2;
1397 break;
1398
1399 default:
1400 return -EINVAL;
1401 }
1402
1403 REG_WRITE(ah, AR_PHY(0), 0x00000007);
f078f209 1404 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
f74df6fb 1405 ah->eep_ops->set_addac(ah, chan);
f078f209 1406
a8c96d3b 1407 if (AR_SREV_5416_22_OR_LATER(ah)) {
2660b81a 1408 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
f078f209
LR		 1409 } else {
1410 struct ar5416IniArray temp;
1411 u32 addacSize =
2660b81a
S		 1412 sizeof(u32) * ah->iniAddac.ia_rows *
1413 ah->iniAddac.ia_columns;
f078f209 1414
2660b81a
S		 1415 memcpy(ah->addac5416_21,
1416 ah->iniAddac.ia_array, addacSize);
f078f209 1417
2660b81a 1418 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
f078f209 1419
2660b81a
S		 1420 temp.ia_array = ah->addac5416_21;
1421 temp.ia_columns = ah->iniAddac.ia_columns;
1422 temp.ia_rows = ah->iniAddac.ia_rows;
f078f209
LR		 1423 REG_WRITE_ARRAY(&temp, 1, regWrites);
1424 }
f1dc5600 1425
f078f209
LR		 1426 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1427
2660b81a
S		 1428 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1429 u32 reg = INI_RA(&ah->iniModes, i, 0);
1430 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
f078f209 1431
f078f209
LR		 1432 REG_WRITE(ah, reg, val);
1433
1434 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1435 && ah->config.analog_shiftreg) {
f078f209
LR		 1436 udelay(100);
1437 }
1438
1439 DO_DELAY(regWrites);
1440 }
1441
ac88b6ec 1442 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1443 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
9f804202 1444
ac88b6ec
VN		 1445 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1446 AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1447 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
9f804202 1448
2660b81a
S		 1449 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1450 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1451 u32 val = INI_RA(&ah->iniCommon, i, 1);
f078f209
LR		 1452
1453 REG_WRITE(ah, reg, val);
1454
1455 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1456 && ah->config.analog_shiftreg) {
f078f209
LR		 1457 udelay(100);
1458 }
1459
1460 DO_DELAY(regWrites);
1461 }
1462
1463 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1464
1465 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
2660b81a 1466 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
f078f209
LR		 1467 regWrites);
1468 }
1469
1470 ath9k_hw_override_ini(ah, chan);
1471 ath9k_hw_set_regs(ah, chan, macmode);
1472 ath9k_hw_init_chain_masks(ah);
1473
8bd1d07f
SB		 1474 if (OLC_FOR_AR9280_20_LATER)
1475 ath9k_olc_init(ah);
1476
8fbff4b8 1477 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1478 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 1479 channel->max_antenna_gain * 2,
1480 channel->max_power * 2,
1481 min((u32) MAX_RATE_POWER,
608b88cb 1482 (u32) regulatory->power_limit));
f078f209
LR		 1483
1484 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
d8baa939 1485 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 1486 "ar5416SetRfRegs failed\n");
f078f209
LR		 1487 return -EIO;
1488 }
1489
1490 return 0;
1491}
1492
f1dc5600
S		 1493/****************************************/
1494/* Reset and Channel Switching Routines */
1495/****************************************/
1496
cbe61d8a 1497static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1498{
f1dc5600
S		 1499 u32 rfMode = 0;
1500
1501 if (chan == NULL)
1502 return;
1503
1504 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1505 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1506
1507 if (!AR_SREV_9280_10_OR_LATER(ah))
1508 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1509 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1510
1511 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1512 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1513
1514 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1515}
1516
cbe61d8a 1517static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
f1dc5600
S		 1518{
1519 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1520}
1521
cbe61d8a 1522static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 1523{
1524 u32 regval;
1525
d7e7d229
LR		 1526 /*
1527 * set AHB_MODE not to do cacheline prefetches
1528 */
f1dc5600
S		 1529 regval = REG_READ(ah, AR_AHB_MODE);
1530 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1531
d7e7d229
LR		 1532 /*
1533 * let mac dma reads be in 128 byte chunks
1534 */
f1dc5600
S		 1535 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1536 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1537
d7e7d229
LR		 1538 /*
1539 * Restore TX Trigger Level to its pre-reset value.
1540 * The initial value depends on whether aggregation is enabled, and is
1541 * adjusted whenever underruns are detected.
1542 */
2660b81a 1543 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1544
d7e7d229
LR		 1545 /*
1546 * let mac dma writes be in 128 byte chunks
1547 */
f1dc5600
S		 1548 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1549 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1550
d7e7d229
LR		 1551 /*
1552 * Setup receive FIFO threshold to hold off TX activities
1553 */
f1dc5600
S		 1554 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1555
d7e7d229
LR		 1556 /*
1557 * reduce the number of usable entries in PCU TXBUF to avoid
1558 * wrap around issues.
1559 */
f1dc5600 1560 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1561 /* For AR9285 the number of Fifos are reduced to half.
1562 * So set the usable tx buf size also to half to
1563 * avoid data/delimiter underruns
1564 */
f1dc5600
S		 1565 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1566 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1567 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1568 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1569 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1570 }
1571}
1572
cbe61d8a 1573static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1574{
1575 u32 val;
1576
1577 val = REG_READ(ah, AR_STA_ID1);
1578 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1579 switch (opmode) {
d97809db 1580 case NL80211_IFTYPE_AP:
f1dc5600
S		 1581 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1582 | AR_STA_ID1_KSRCH_MODE);
1583 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1584 break;
d97809db 1585 case NL80211_IFTYPE_ADHOC:
9cb5412b 1586 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 1587 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1588 | AR_STA_ID1_KSRCH_MODE);
1589 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1590 break;
d97809db
CM		 1591 case NL80211_IFTYPE_STATION:
1592 case NL80211_IFTYPE_MONITOR:
f1dc5600 1593 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1594 break;
f1dc5600
S		 1595 }
1596}
1597
cbe61d8a 1598static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
f1dc5600
S		 1599 u32 coef_scaled,
1600 u32 *coef_mantissa,
1601 u32 *coef_exponent)
1602{
1603 u32 coef_exp, coef_man;
1604
1605 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1606 if ((coef_scaled >> coef_exp) & 0x1)
1607 break;
1608
1609 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1610
1611 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1612
1613 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1614 *coef_exponent = coef_exp - 16;
1615}
1616
cbe61d8a 1617static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
f1dc5600
S		 1618 struct ath9k_channel *chan)
1619{
1620 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1621 u32 clockMhzScaled = 0x64000000;
1622 struct chan_centers centers;
1623
1624 if (IS_CHAN_HALF_RATE(chan))
1625 clockMhzScaled = clockMhzScaled >> 1;
1626 else if (IS_CHAN_QUARTER_RATE(chan))
1627 clockMhzScaled = clockMhzScaled >> 2;
1628
1629 ath9k_hw_get_channel_centers(ah, chan, &centers);
1630 coef_scaled = clockMhzScaled / centers.synth_center;
1631
1632 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1633 &ds_coef_exp);
1634
1635 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1636 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1637 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1638 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1639
1640 coef_scaled = (9 * coef_scaled) / 10;
1641
1642 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1643 &ds_coef_exp);
1644
1645 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1646 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1647 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1648 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1649}
1650
cbe61d8a 1651static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1652{
1653 u32 rst_flags;
1654 u32 tmpReg;
1655
70768496
S		 1656 if (AR_SREV_9100(ah)) {
1657 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1658 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1659 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1660 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1661 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1662 }
1663
f1dc5600
S		 1664 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1665 AR_RTC_FORCE_WAKE_ON_INT);
1666
1667 if (AR_SREV_9100(ah)) {
1668 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1669 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1670 } else {
1671 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1672 if (tmpReg &
1673 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1674 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1675 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1676 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1677 } else {
1678 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1679 }
1680
1681 rst_flags = AR_RTC_RC_MAC_WARM;
1682 if (type == ATH9K_RESET_COLD)
1683 rst_flags |= AR_RTC_RC_MAC_COLD;
1684 }
1685
d03a66c1 1686 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1687 udelay(50);
1688
d03a66c1 1689 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1690 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
f1dc5600 1691 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 1692 "RTC stuck in MAC reset\n");
f1dc5600
S		 1693 return false;
1694 }
1695
1696 if (!AR_SREV_9100(ah))
1697 REG_WRITE(ah, AR_RC, 0);
1698
1699 ath9k_hw_init_pll(ah, NULL);
1700
1701 if (AR_SREV_9100(ah))
1702 udelay(50);
1703
1704 return true;
1705}
1706
cbe61d8a 1707static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1708{
1709 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1710 AR_RTC_FORCE_WAKE_ON_INT);
1711
1c29ce67
VT		 1712 if (!AR_SREV_9100(ah))
1713 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1714
d03a66c1 1715 REG_WRITE(ah, AR_RTC_RESET, 0);
8bd1d07f 1716 udelay(2);
1c29ce67
VT		 1717
1718 if (!AR_SREV_9100(ah))
1719 REG_WRITE(ah, AR_RC, 0);
1720
d03a66c1 1721 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1722
1723 if (!ath9k_hw_wait(ah,
1724 AR_RTC_STATUS,
1725 AR_RTC_STATUS_M,
0caa7b14
S		 1726 AR_RTC_STATUS_ON,
1727 AH_WAIT_TIMEOUT)) {
04bd4638 1728 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
f1dc5600 1729 return false;
f078f209
LR		 1730 }
1731
f1dc5600
S		 1732 ath9k_hw_read_revisions(ah);
1733
1734 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1735}
1736
cbe61d8a 1737static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1738{
1739 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1740 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1741
1742 switch (type) {
1743 case ATH9K_RESET_POWER_ON:
1744 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1745 case ATH9K_RESET_WARM:
1746 case ATH9K_RESET_COLD:
1747 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1748 default:
1749 return false;
1750 }
f078f209
LR		 1751}
1752
cbe61d8a 1753static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 1754 enum ath9k_ht_macmode macmode)
f078f209 1755{
f1dc5600 1756 u32 phymode;
e7594072 1757 u32 enableDacFifo = 0;
f078f209 1758
e7594072
SB		 1759 if (AR_SREV_9285_10_OR_LATER(ah))
1760 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1761 AR_PHY_FC_ENABLE_DAC_FIFO);
1762
f1dc5600 1763 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1764 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1765
1766 if (IS_CHAN_HT40(chan)) {
1767 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1768
f1dc5600
S		 1769 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1770 (chan->chanmode == CHANNEL_G_HT40PLUS))
1771 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1772
2660b81a 1773 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
f1dc5600 1774 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
f078f209 1775 }
f1dc5600
S		 1776 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1777
1778 ath9k_hw_set11nmac2040(ah, macmode);
f078f209 1779
f1dc5600
S		 1780 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1781 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1782}
1783
cbe61d8a 1784static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1785 struct ath9k_channel *chan)
f078f209 1786{
8bd1d07f
SB		 1787 if (OLC_FOR_AR9280_20_LATER) {
1788 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1789 return false;
1790 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1791 return false;
f078f209 1792
f1dc5600
S		 1793 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1794 return false;
f078f209 1795
2660b81a 1796 ah->chip_fullsleep = false;
f1dc5600 1797 ath9k_hw_init_pll(ah, chan);
f1dc5600 1798 ath9k_hw_set_rfmode(ah, chan);
f078f209 1799
f1dc5600 1800 return true;
f078f209
LR		 1801}
1802
cbe61d8a 1803static bool ath9k_hw_channel_change(struct ath_hw *ah,
f1dc5600
S		 1804 struct ath9k_channel *chan,
1805 enum ath9k_ht_macmode macmode)
f078f209 1806{
608b88cb 1807 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
5f8e077c 1808 struct ieee80211_channel *channel = chan->chan;
f078f209 1809 u32 synthDelay, qnum;
f078f209
LR		 1810
1811 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1812 if (ath9k_hw_numtxpending(ah, qnum)) {
1813 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
04bd4638 1814 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1815 return false;
1816 }
1817 }
1818
1819 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1820 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
0caa7b14 1821 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
d8baa939 1822 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 1823 "Could not kill baseband RX\n");
f078f209
LR		 1824 return false;
1825 }
1826
1827 ath9k_hw_set_regs(ah, chan, macmode);
1828
1829 if (AR_SREV_9280_10_OR_LATER(ah)) {
8fbff4b8 1830 ath9k_hw_ar9280_set_channel(ah, chan);
f078f209
LR		 1831 } else {
1832 if (!(ath9k_hw_set_channel(ah, chan))) {
d8baa939
S		 1833 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1834 "Failed to set channel\n");
f078f209
LR		 1835 return false;
1836 }
1837 }
1838
8fbff4b8 1839 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1840 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1841 channel->max_antenna_gain * 2,
1842 channel->max_power * 2,
1843 min((u32) MAX_RATE_POWER,
608b88cb 1844 (u32) regulatory->power_limit));
f078f209
LR		 1845
1846 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1847 if (IS_CHAN_B(chan))
f078f209
LR		 1848 synthDelay = (4 * synthDelay) / 22;
1849 else
1850 synthDelay /= 10;
1851
1852 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1853
1854 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1855
f1dc5600
S		 1856 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1857 ath9k_hw_set_delta_slope(ah, chan);
1858
1859 if (AR_SREV_9280_10_OR_LATER(ah))
1860 ath9k_hw_9280_spur_mitigate(ah, chan);
1861 else
1862 ath9k_hw_spur_mitigate(ah, chan);
1863
1864 if (!chan->oneTimeCalsDone)
1865 chan->oneTimeCalsDone = true;
1866
1867 return true;
1868}
1869
cbe61d8a 1870static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 1871{
1872 int bb_spur = AR_NO_SPUR;
1873 int freq;
1874 int bin, cur_bin;
1875 int bb_spur_off, spur_subchannel_sd;
1876 int spur_freq_sd;
1877 int spur_delta_phase;
1878 int denominator;
1879 int upper, lower, cur_vit_mask;
1880 int tmp, newVal;
1881 int i;
1882 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1883 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1884 };
1885 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1886 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1887 };
1888 int inc[4] = { 0, 100, 0, 0 };
1889 struct chan_centers centers;
1890
1891 int8_t mask_m[123];
1892 int8_t mask_p[123];
1893 int8_t mask_amt;
1894 int tmp_mask;
1895 int cur_bb_spur;
1896 bool is2GHz = IS_CHAN_2GHZ(chan);
1897
1898 memset(&mask_m, 0, sizeof(int8_t) * 123);
1899 memset(&mask_p, 0, sizeof(int8_t) * 123);
1900
1901 ath9k_hw_get_channel_centers(ah, chan, &centers);
1902 freq = centers.synth_center;
1903
2660b81a 1904 ah->config.spurmode = SPUR_ENABLE_EEPROM;
f1dc5600 1905 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 1906 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 1907
1908 if (is2GHz)
1909 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1910 else
1911 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1912
1913 if (AR_NO_SPUR == cur_bb_spur)
1914 break;
1915 cur_bb_spur = cur_bb_spur - freq;
1916
1917 if (IS_CHAN_HT40(chan)) {
1918 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1919 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1920 bb_spur = cur_bb_spur;
1921 break;
1922 }
1923 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1924 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1925 bb_spur = cur_bb_spur;
1926 break;
1927 }
1928 }
1929
1930 if (AR_NO_SPUR == bb_spur) {
1931 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1932 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1933 return;
1934 } else {
1935 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1936 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1937 }
1938
1939 bin = bb_spur * 320;
1940
1941 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1942
1943 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1944 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1945 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1946 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1947 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1948
1949 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1950 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1951 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1952 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1953 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1954 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1955
1956 if (IS_CHAN_HT40(chan)) {
1957 if (bb_spur < 0) {
1958 spur_subchannel_sd = 1;
1959 bb_spur_off = bb_spur + 10;
1960 } else {
1961 spur_subchannel_sd = 0;
1962 bb_spur_off = bb_spur - 10;
1963 }
1964 } else {
1965 spur_subchannel_sd = 0;
1966 bb_spur_off = bb_spur;
1967 }
1968
1969 if (IS_CHAN_HT40(chan))
1970 spur_delta_phase =
1971 ((bb_spur * 262144) /
1972 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1973 else
1974 spur_delta_phase =
1975 ((bb_spur * 524288) /
1976 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1977
1978 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1979 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1980
1981 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1982 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1983 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1984 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1985
1986 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1987 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1988
1989 cur_bin = -6000;
1990 upper = bin + 100;
1991 lower = bin - 100;
1992
1993 for (i = 0; i < 4; i++) {
1994 int pilot_mask = 0;
1995 int chan_mask = 0;
1996 int bp = 0;
1997 for (bp = 0; bp < 30; bp++) {
1998 if ((cur_bin > lower) && (cur_bin < upper)) {
1999 pilot_mask = pilot_mask | 0x1 << bp;
2000 chan_mask = chan_mask | 0x1 << bp;
2001 }
2002 cur_bin += 100;
2003 }
2004 cur_bin += inc[i];
2005 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2006 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2007 }
2008
2009 cur_vit_mask = 6100;
2010 upper = bin + 120;
2011 lower = bin - 120;
2012
2013 for (i = 0; i < 123; i++) {
2014 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2015
2016 /* workaround for gcc bug #37014 */
a085ff71 2017 volatile int tmp_v = abs(cur_vit_mask - bin);
f1dc5600 2018
a085ff71 2019 if (tmp_v < 75)
f1dc5600
S		 2020 mask_amt = 1;
2021 else
2022 mask_amt = 0;
2023 if (cur_vit_mask < 0)
2024 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2025 else
2026 mask_p[cur_vit_mask / 100] = mask_amt;
2027 }
2028 cur_vit_mask -= 100;
2029 }
2030
2031 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2032 | (mask_m[48] << 26) | (mask_m[49] << 24)
2033 | (mask_m[50] << 22) | (mask_m[51] << 20)
2034 | (mask_m[52] << 18) | (mask_m[53] << 16)
2035 | (mask_m[54] << 14) | (mask_m[55] << 12)
2036 | (mask_m[56] << 10) | (mask_m[57] << 8)
2037 | (mask_m[58] << 6) | (mask_m[59] << 4)
2038 | (mask_m[60] << 2) | (mask_m[61] << 0);
2039 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2040 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2041
2042 tmp_mask = (mask_m[31] << 28)
2043 | (mask_m[32] << 26) | (mask_m[33] << 24)
2044 | (mask_m[34] << 22) | (mask_m[35] << 20)
2045 | (mask_m[36] << 18) | (mask_m[37] << 16)
2046 | (mask_m[48] << 14) | (mask_m[39] << 12)
2047 | (mask_m[40] << 10) | (mask_m[41] << 8)
2048 | (mask_m[42] << 6) | (mask_m[43] << 4)
2049 | (mask_m[44] << 2) | (mask_m[45] << 0);
2050 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2051 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2052
2053 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2054 | (mask_m[18] << 26) | (mask_m[18] << 24)
2055 | (mask_m[20] << 22) | (mask_m[20] << 20)
2056 | (mask_m[22] << 18) | (mask_m[22] << 16)
2057 | (mask_m[24] << 14) | (mask_m[24] << 12)
2058 | (mask_m[25] << 10) | (mask_m[26] << 8)
2059 | (mask_m[27] << 6) | (mask_m[28] << 4)
2060 | (mask_m[29] << 2) | (mask_m[30] << 0);
2061 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2062 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2063
2064 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2065 | (mask_m[2] << 26) | (mask_m[3] << 24)
2066 | (mask_m[4] << 22) | (mask_m[5] << 20)
2067 | (mask_m[6] << 18) | (mask_m[7] << 16)
2068 | (mask_m[8] << 14) | (mask_m[9] << 12)
2069 | (mask_m[10] << 10) | (mask_m[11] << 8)
2070 | (mask_m[12] << 6) | (mask_m[13] << 4)
2071 | (mask_m[14] << 2) | (mask_m[15] << 0);
2072 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2073 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2074
2075 tmp_mask = (mask_p[15] << 28)
2076 | (mask_p[14] << 26) | (mask_p[13] << 24)
2077 | (mask_p[12] << 22) | (mask_p[11] << 20)
2078 | (mask_p[10] << 18) | (mask_p[9] << 16)
2079 | (mask_p[8] << 14) | (mask_p[7] << 12)
2080 | (mask_p[6] << 10) | (mask_p[5] << 8)
2081 | (mask_p[4] << 6) | (mask_p[3] << 4)
2082 | (mask_p[2] << 2) | (mask_p[1] << 0);
2083 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2084 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2085
f1dc5600
S		 2086 tmp_mask = (mask_p[30] << 28)
2087 | (mask_p[29] << 26) | (mask_p[28] << 24)
2088 | (mask_p[27] << 22) | (mask_p[26] << 20)
2089 | (mask_p[25] << 18) | (mask_p[24] << 16)
2090 | (mask_p[23] << 14) | (mask_p[22] << 12)
2091 | (mask_p[21] << 10) | (mask_p[20] << 8)
2092 | (mask_p[19] << 6) | (mask_p[18] << 4)
2093 | (mask_p[17] << 2) | (mask_p[16] << 0);
2094 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2095 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2096
f1dc5600
S		 2097 tmp_mask = (mask_p[45] << 28)
2098 | (mask_p[44] << 26) | (mask_p[43] << 24)
2099 | (mask_p[42] << 22) | (mask_p[41] << 20)
2100 | (mask_p[40] << 18) | (mask_p[39] << 16)
2101 | (mask_p[38] << 14) | (mask_p[37] << 12)
2102 | (mask_p[36] << 10) | (mask_p[35] << 8)
2103 | (mask_p[34] << 6) | (mask_p[33] << 4)
2104 | (mask_p[32] << 2) | (mask_p[31] << 0);
2105 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2106 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2107
f1dc5600
S		 2108 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2109 | (mask_p[59] << 26) | (mask_p[58] << 24)
2110 | (mask_p[57] << 22) | (mask_p[56] << 20)
2111 | (mask_p[55] << 18) | (mask_p[54] << 16)
2112 | (mask_p[53] << 14) | (mask_p[52] << 12)
2113 | (mask_p[51] << 10) | (mask_p[50] << 8)
2114 | (mask_p[49] << 6) | (mask_p[48] << 4)
2115 | (mask_p[47] << 2) | (mask_p[46] << 0);
2116 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2117 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2118}
2119
cbe61d8a 2120static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 2121{
f1dc5600
S		 2122 int bb_spur = AR_NO_SPUR;
2123 int bin, cur_bin;
2124 int spur_freq_sd;
2125 int spur_delta_phase;
2126 int denominator;
2127 int upper, lower, cur_vit_mask;
2128 int tmp, new;
2129 int i;
2130 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2131 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2132 };
2133 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2134 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2135 };
2136 int inc[4] = { 0, 100, 0, 0 };
f078f209 2137
f1dc5600
S		 2138 int8_t mask_m[123];
2139 int8_t mask_p[123];
2140 int8_t mask_amt;
2141 int tmp_mask;
2142 int cur_bb_spur;
2143 bool is2GHz = IS_CHAN_2GHZ(chan);
f078f209 2144
f1dc5600
S		 2145 memset(&mask_m, 0, sizeof(int8_t) * 123);
2146 memset(&mask_p, 0, sizeof(int8_t) * 123);
f078f209 2147
f1dc5600 2148 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 2149 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 2150 if (AR_NO_SPUR == cur_bb_spur)
2151 break;
2152 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2153 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2154 bb_spur = cur_bb_spur;
2155 break;
2156 }
2157 }
f078f209 2158
f1dc5600
S		 2159 if (AR_NO_SPUR == bb_spur)
2160 return;
f078f209 2161
f1dc5600 2162 bin = bb_spur * 32;
f078f209 2163
f1dc5600
S		 2164 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2165 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2166 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2167 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2168 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
f078f209 2169
f1dc5600 2170 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
f078f209 2171
f1dc5600
S		 2172 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2173 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2174 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2175 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2176 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2177 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
f078f209 2178
f1dc5600
S		 2179 spur_delta_phase = ((bb_spur * 524288) / 100) &
2180 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
f078f209 2181
f1dc5600
S		 2182 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2183 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
f078f209 2184
f1dc5600
S		 2185 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2186 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2187 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2188 REG_WRITE(ah, AR_PHY_TIMING11, new);
f078f209 2189
f1dc5600
S		 2190 cur_bin = -6000;
2191 upper = bin + 100;
2192 lower = bin - 100;
f078f209 2193
f1dc5600
S		 2194 for (i = 0; i < 4; i++) {
2195 int pilot_mask = 0;
2196 int chan_mask = 0;
2197 int bp = 0;
2198 for (bp = 0; bp < 30; bp++) {
2199 if ((cur_bin > lower) && (cur_bin < upper)) {
2200 pilot_mask = pilot_mask | 0x1 << bp;
2201 chan_mask = chan_mask | 0x1 << bp;
2202 }
2203 cur_bin += 100;
2204 }
2205 cur_bin += inc[i];
2206 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2207 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
f078f209 2208 }
f078f209 2209
f1dc5600
S		 2210 cur_vit_mask = 6100;
2211 upper = bin + 120;
2212 lower = bin - 120;
f078f209 2213
f1dc5600
S		 2214 for (i = 0; i < 123; i++) {
2215 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
f078f209 2216
f1dc5600 2217 /* workaround for gcc bug #37014 */
a085ff71 2218 volatile int tmp_v = abs(cur_vit_mask - bin);
f078f209 2219
a085ff71 2220 if (tmp_v < 75)
f1dc5600
S		 2221 mask_amt = 1;
2222 else
2223 mask_amt = 0;
2224 if (cur_vit_mask < 0)
2225 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2226 else
2227 mask_p[cur_vit_mask / 100] = mask_amt;
2228 }
2229 cur_vit_mask -= 100;
f078f209
LR		 2230 }
2231
f1dc5600
S		 2232 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2233 | (mask_m[48] << 26) | (mask_m[49] << 24)
2234 | (mask_m[50] << 22) | (mask_m[51] << 20)
2235 | (mask_m[52] << 18) | (mask_m[53] << 16)
2236 | (mask_m[54] << 14) | (mask_m[55] << 12)
2237 | (mask_m[56] << 10) | (mask_m[57] << 8)
2238 | (mask_m[58] << 6) | (mask_m[59] << 4)
2239 | (mask_m[60] << 2) | (mask_m[61] << 0);
2240 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2241 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
f078f209 2242
f1dc5600
S		 2243 tmp_mask = (mask_m[31] << 28)
2244 | (mask_m[32] << 26) | (mask_m[33] << 24)
2245 | (mask_m[34] << 22) | (mask_m[35] << 20)
2246 | (mask_m[36] << 18) | (mask_m[37] << 16)
2247 | (mask_m[48] << 14) | (mask_m[39] << 12)
2248 | (mask_m[40] << 10) | (mask_m[41] << 8)
2249 | (mask_m[42] << 6) | (mask_m[43] << 4)
2250 | (mask_m[44] << 2) | (mask_m[45] << 0);
2251 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2252 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
f078f209 2253
f1dc5600
S		 2254 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2255 | (mask_m[18] << 26) | (mask_m[18] << 24)
2256 | (mask_m[20] << 22) | (mask_m[20] << 20)
2257 | (mask_m[22] << 18) | (mask_m[22] << 16)
2258 | (mask_m[24] << 14) | (mask_m[24] << 12)
2259 | (mask_m[25] << 10) | (mask_m[26] << 8)
2260 | (mask_m[27] << 6) | (mask_m[28] << 4)
2261 | (mask_m[29] << 2) | (mask_m[30] << 0);
2262 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2263 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
f078f209 2264
f1dc5600
S		 2265 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2266 | (mask_m[2] << 26) | (mask_m[3] << 24)
2267 | (mask_m[4] << 22) | (mask_m[5] << 20)
2268 | (mask_m[6] << 18) | (mask_m[7] << 16)
2269 | (mask_m[8] << 14) | (mask_m[9] << 12)
2270 | (mask_m[10] << 10) | (mask_m[11] << 8)
2271 | (mask_m[12] << 6) | (mask_m[13] << 4)
2272 | (mask_m[14] << 2) | (mask_m[15] << 0);
2273 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2274 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
f078f209 2275
f1dc5600
S		 2276 tmp_mask = (mask_p[15] << 28)
2277 | (mask_p[14] << 26) | (mask_p[13] << 24)
2278 | (mask_p[12] << 22) | (mask_p[11] << 20)
2279 | (mask_p[10] << 18) | (mask_p[9] << 16)
2280 | (mask_p[8] << 14) | (mask_p[7] << 12)
2281 | (mask_p[6] << 10) | (mask_p[5] << 8)
2282 | (mask_p[4] << 6) | (mask_p[3] << 4)
2283 | (mask_p[2] << 2) | (mask_p[1] << 0);
2284 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2285 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2286
f1dc5600
S		 2287 tmp_mask = (mask_p[30] << 28)
2288 | (mask_p[29] << 26) | (mask_p[28] << 24)
2289 | (mask_p[27] << 22) | (mask_p[26] << 20)
2290 | (mask_p[25] << 18) | (mask_p[24] << 16)
2291 | (mask_p[23] << 14) | (mask_p[22] << 12)
2292 | (mask_p[21] << 10) | (mask_p[20] << 8)
2293 | (mask_p[19] << 6) | (mask_p[18] << 4)
2294 | (mask_p[17] << 2) | (mask_p[16] << 0);
2295 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2296 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2297
f1dc5600
S		 2298 tmp_mask = (mask_p[45] << 28)
2299 | (mask_p[44] << 26) | (mask_p[43] << 24)
2300 | (mask_p[42] << 22) | (mask_p[41] << 20)
2301 | (mask_p[40] << 18) | (mask_p[39] << 16)
2302 | (mask_p[38] << 14) | (mask_p[37] << 12)
2303 | (mask_p[36] << 10) | (mask_p[35] << 8)
2304 | (mask_p[34] << 6) | (mask_p[33] << 4)
2305 | (mask_p[32] << 2) | (mask_p[31] << 0);
2306 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2307 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2308
f1dc5600
S		 2309 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2310 | (mask_p[59] << 26) | (mask_p[58] << 24)
2311 | (mask_p[57] << 22) | (mask_p[56] << 20)
2312 | (mask_p[55] << 18) | (mask_p[54] << 16)
2313 | (mask_p[53] << 14) | (mask_p[52] << 12)
2314 | (mask_p[51] << 10) | (mask_p[50] << 8)
2315 | (mask_p[49] << 6) | (mask_p[48] << 4)
2316 | (mask_p[47] << 2) | (mask_p[46] << 0);
2317 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2318 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2319}
2320
3b319aae
JB		 2321static void ath9k_enable_rfkill(struct ath_hw *ah)
2322{
2323 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2324 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2325
2326 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2327 AR_GPIO_INPUT_MUX2_RFSILENT);
2328
2329 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2330 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2331}
2332
cbe61d8a 2333int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 2334 bool bChannelChange)
f078f209 2335{
f078f209 2336 u32 saveLedState;
ae8d2858 2337 struct ath_softc *sc = ah->ah_sc;
2660b81a 2338 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 2339 u32 saveDefAntenna;
2340 u32 macStaId1;
ae8d2858 2341 int i, rx_chainmask, r;
f078f209 2342
2660b81a
S		 2343 ah->extprotspacing = sc->ht_extprotspacing;
2344 ah->txchainmask = sc->tx_chainmask;
2345 ah->rxchainmask = sc->rx_chainmask;
f078f209 2346
ae8d2858
LR		 2347 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2348 return -EIO;
f078f209
LR		 2349
2350 if (curchan)
2351 ath9k_hw_getnf(ah, curchan);
2352
2353 if (bChannelChange &&
2660b81a
S		 2354 (ah->chip_fullsleep != true) &&
2355 (ah->curchan != NULL) &&
2356 (chan->channel != ah->curchan->channel) &&
f078f209 2357 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 2358 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
f078f209 2359 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2660b81a 2360 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
f078f209 2361
ae8d2858 2362 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2660b81a 2363 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 2364 ath9k_hw_start_nfcal(ah);
ae8d2858 2365 return 0;
f078f209
LR		 2366 }
2367 }
2368
2369 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2370 if (saveDefAntenna == 0)
2371 saveDefAntenna = 1;
2372
2373 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2374
2375 saveLedState = REG_READ(ah, AR_CFG_LED) &
2376 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2377 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2378
2379 ath9k_hw_mark_phy_inactive(ah);
2380
d7e7d229
LR		 2381 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2382 REG_WRITE(ah,
2383 AR9271_RESET_POWER_DOWN_CONTROL,
2384 AR9271_RADIO_RF_RST);
2385 udelay(50);
2386 }
2387
f078f209 2388 if (!ath9k_hw_chip_reset(ah, chan)) {
d8baa939 2389 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 2390 return -EINVAL;
f078f209
LR		 2391 }
2392
d7e7d229
LR		 2393 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2394 ah->htc_reset_init = false;
2395 REG_WRITE(ah,
2396 AR9271_RESET_POWER_DOWN_CONTROL,
2397 AR9271_GATE_MAC_CTL);
2398 udelay(50);
2399 }
2400
369391db
VT		 2401 if (AR_SREV_9280_10_OR_LATER(ah))
2402 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 2403
326bebbc 2404 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2405 /* Enable ASYNC FIFO */
2406 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2407 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2408 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2409 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2410 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2411 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2412 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2413 }
ae8d2858
LR		 2414 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2415 if (r)
2416 return r;
f078f209 2417
0ced0e17
JM		 2418 /* Setup MFP options for CCMP */
2419 if (AR_SREV_9280_20_OR_LATER(ah)) {
2420 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2421 * frames when constructing CCMP AAD. */
2422 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2423 0xc7ff);
2424 ah->sw_mgmt_crypto = false;
2425 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2426 /* Disable hardware crypto for management frames */
2427 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2428 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2429 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2430 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2431 ah->sw_mgmt_crypto = true;
2432 } else
2433 ah->sw_mgmt_crypto = true;
2434
f078f209
LR		 2435 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2436 ath9k_hw_set_delta_slope(ah, chan);
2437
2438 if (AR_SREV_9280_10_OR_LATER(ah))
2439 ath9k_hw_9280_spur_mitigate(ah, chan);
2440 else
2441 ath9k_hw_spur_mitigate(ah, chan);
2442
d6509151 2443 ah->eep_ops->set_board_values(ah, chan);
f078f209
LR		 2444
2445 ath9k_hw_decrease_chain_power(ah, chan);
2446
ba52da58
S		 2447 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2448 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
f078f209
LR		 2449 | macStaId1
2450 | AR_STA_ID1_RTS_USE_DEF
2660b81a 2451 | (ah->config.
60b67f51 2452 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 2453 | ah->sta_id1_defaults);
2454 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2455
ba52da58
S		 2456 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2457 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
f078f209
LR		 2458
2459 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2460
ba52da58
S		 2461 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2462 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2463 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 2464
2465 REG_WRITE(ah, AR_ISR, ~0);
2466
2467 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2468
8fbff4b8
VT		 2469 if (AR_SREV_9280_10_OR_LATER(ah))
2470 ath9k_hw_ar9280_set_channel(ah, chan);
2471 else
ae8d2858
LR		 2472 if (!(ath9k_hw_set_channel(ah, chan)))
2473 return -EIO;
f078f209
LR		 2474
2475 for (i = 0; i < AR_NUM_DCU; i++)
2476 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2477
2660b81a
S		 2478 ah->intr_txqs = 0;
2479 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 2480 ath9k_hw_resettxqueue(ah, i);
2481
2660b81a 2482 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 2483 ath9k_hw_init_qos(ah);
2484
2660b81a 2485 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 2486 ath9k_enable_rfkill(ah);
3b319aae 2487
f078f209
LR		 2488 ath9k_hw_init_user_settings(ah);
2489
326bebbc 2490 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2491 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2492 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2493 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2494 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2495 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2496 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2497
2498 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2499 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2500
2501 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2502 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2503 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2504 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2505 }
326bebbc 2506 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2507 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2508 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2509 }
2510
f078f209
LR		 2511 REG_WRITE(ah, AR_STA_ID1,
2512 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2513
2514 ath9k_hw_set_dma(ah);
2515
2516 REG_WRITE(ah, AR_OBS, 8);
2517
0ef1f168 2518 if (ah->config.intr_mitigation) {
f078f209
LR		 2519 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2520 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2521 }
2522
2523 ath9k_hw_init_bb(ah, chan);
2524
ae8d2858 2525 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2526 return -EIO;
f078f209 2527
2660b81a 2528 rx_chainmask = ah->rxchainmask;
f078f209
LR		 2529 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2530 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2531 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2532 }
2533
2534 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2535
d7e7d229
LR		 2536 /*
2537 * For big endian systems turn on swapping for descriptors
2538 */
f078f209
LR		 2539 if (AR_SREV_9100(ah)) {
2540 u32 mask;
2541 mask = REG_READ(ah, AR_CFG);
2542 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2543 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2544 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2545 } else {
2546 mask =
2547 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2548 REG_WRITE(ah, AR_CFG, mask);
2549 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2550 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2551 }
2552 } else {
d7e7d229
LR		 2553 /* Configure AR9271 target WLAN */
2554 if (AR_SREV_9271(ah))
2555 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 2556#ifdef __BIG_ENDIAN
d7e7d229
LR		 2557 else
2558 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 2559#endif
2560 }
2561
42cc41ed
VT		 2562 if (ah->ah_sc->sc_flags & SC_OP_BTCOEX_ENABLED)
2563 ath9k_hw_btcoex_enable(ah);
2564
ae8d2858 2565 return 0;
f078f209
LR		 2566}
2567
f1dc5600
S		 2568/************************/
2569/* Key Cache Management */
2570/************************/
f078f209 2571
cbe61d8a 2572bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 2573{
f1dc5600 2574 u32 keyType;
f078f209 2575
2660b81a 2576 if (entry >= ah->caps.keycache_size) {
d8baa939
S		 2577 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2578 "keychache entry %u out of range\n", entry);
f078f209
LR		 2579 return false;
2580 }
2581
f1dc5600 2582 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2583
f1dc5600
S		 2584 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2585 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2586 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2587 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2588 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2589 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2590 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2591 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2592
f1dc5600
S		 2593 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2594 u16 micentry = entry + 64;
f078f209 2595
f1dc5600
S		 2596 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2597 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2598 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2599 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2600
f078f209
LR		 2601 }
2602
f078f209
LR		 2603 return true;
2604}
2605
cbe61d8a 2606bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 2607{
f1dc5600 2608 u32 macHi, macLo;
f078f209 2609
2660b81a 2610 if (entry >= ah->caps.keycache_size) {
d8baa939
S		 2611 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2612 "keychache entry %u out of range\n", entry);
f1dc5600 2613 return false;
f078f209
LR		 2614 }
2615
f1dc5600
S		 2616 if (mac != NULL) {
2617 macHi = (mac[5] << 8) | mac[4];
2618 macLo = (mac[3] << 24) |
2619 (mac[2] << 16) |
2620 (mac[1] << 8) |
2621 mac[0];
2622 macLo >>= 1;
2623 macLo |= (macHi & 1) << 31;
2624 macHi >>= 1;
f078f209 2625 } else {
f1dc5600 2626 macLo = macHi = 0;
f078f209 2627 }
f1dc5600
S		 2628 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2629 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2630
f1dc5600 2631 return true;
f078f209
LR		 2632}
2633
cbe61d8a 2634bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 2635 const struct ath9k_keyval *k,
e0caf9ea 2636 const u8 *mac)
f078f209 2637{
2660b81a 2638 const struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 2639 u32 key0, key1, key2, key3, key4;
2640 u32 keyType;
f078f209 2641
f1dc5600 2642 if (entry >= pCap->keycache_size) {
d8baa939
S		 2643 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2644 "keycache entry %u out of range\n", entry);
f1dc5600 2645 return false;
f078f209
LR		 2646 }
2647
f1dc5600
S		 2648 switch (k->kv_type) {
2649 case ATH9K_CIPHER_AES_OCB:
2650 keyType = AR_KEYTABLE_TYPE_AES;
2651 break;
2652 case ATH9K_CIPHER_AES_CCM:
2653 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
d8baa939 2654 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2655 "AES-CCM not supported by mac rev 0x%x\n",
d535a42a 2656 ah->hw_version.macRev);
f1dc5600
S		 2657 return false;
2658 }
2659 keyType = AR_KEYTABLE_TYPE_CCM;
2660 break;
2661 case ATH9K_CIPHER_TKIP:
2662 keyType = AR_KEYTABLE_TYPE_TKIP;
2663 if (ATH9K_IS_MIC_ENABLED(ah)
2664 && entry + 64 >= pCap->keycache_size) {
d8baa939 2665 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2666 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2667 return false;
2668 }
2669 break;
2670 case ATH9K_CIPHER_WEP:
e31a16d6 2671 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
d8baa939 2672 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2673 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2674 return false;
2675 }
e31a16d6 2676 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 2677 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 2678 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 2679 keyType = AR_KEYTABLE_TYPE_104;
2680 else
2681 keyType = AR_KEYTABLE_TYPE_128;
2682 break;
2683 case ATH9K_CIPHER_CLR:
2684 keyType = AR_KEYTABLE_TYPE_CLR;
2685 break;
2686 default:
d8baa939 2687 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 2688 "cipher %u not supported\n", k->kv_type);
f1dc5600 2689 return false;
f078f209
LR		 2690 }
2691
e0caf9ea
JM		 2692 key0 = get_unaligned_le32(k->kv_val + 0);
2693 key1 = get_unaligned_le16(k->kv_val + 4);
2694 key2 = get_unaligned_le32(k->kv_val + 6);
2695 key3 = get_unaligned_le16(k->kv_val + 10);
2696 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 2697 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 2698 key4 &= 0xff;
f078f209 2699
672903b3
JM		 2700 /*
2701 * Note: Key cache registers access special memory area that requires
2702 * two 32-bit writes to actually update the values in the internal
2703 * memory. Consequently, the exact order and pairs used here must be
2704 * maintained.
2705 */
2706
f1dc5600
S		 2707 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2708 u16 micentry = entry + 64;
f078f209 2709
672903b3
JM		 2710 /*
2711 * Write inverted key[47:0] first to avoid Michael MIC errors
2712 * on frames that could be sent or received at the same time.
2713 * The correct key will be written in the end once everything
2714 * else is ready.
2715 */
f1dc5600
S		 2716 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2717 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 2718
2719 /* Write key[95:48] */
f1dc5600
S		 2720 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2721 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2722
2723 /* Write key[127:96] and key type */
f1dc5600
S		 2724 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2725 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 2726
2727 /* Write MAC address for the entry */
f1dc5600 2728 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2729
2660b81a 2730 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 2731 /*
2732 * TKIP uses two key cache entries:
2733 * Michael MIC TX/RX keys in the same key cache entry
2734 * (idx = main index + 64):
2735 * key0 [31:0] = RX key [31:0]
2736 * key1 [15:0] = TX key [31:16]
2737 * key1 [31:16] = reserved
2738 * key2 [31:0] = RX key [63:32]
2739 * key3 [15:0] = TX key [15:0]
2740 * key3 [31:16] = reserved
2741 * key4 [31:0] = TX key [63:32]
2742 */
f1dc5600 2743 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2744
f1dc5600
S		 2745 mic0 = get_unaligned_le32(k->kv_mic + 0);
2746 mic2 = get_unaligned_le32(k->kv_mic + 4);
2747 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2748 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2749 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 2750
2751 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 2752 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2753 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 2754
2755 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 2756 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2757 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 2758
2759 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2760 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2761 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2762 AR_KEYTABLE_TYPE_CLR);
f078f209 2763
f1dc5600 2764 } else {
672903b3
JM		 2765 /*
2766 * TKIP uses four key cache entries (two for group
2767 * keys):
2768 * Michael MIC TX/RX keys are in different key cache
2769 * entries (idx = main index + 64 for TX and
2770 * main index + 32 + 96 for RX):
2771 * key0 [31:0] = TX/RX MIC key [31:0]
2772 * key1 [31:0] = reserved
2773 * key2 [31:0] = TX/RX MIC key [63:32]
2774 * key3 [31:0] = reserved
2775 * key4 [31:0] = reserved
2776 *
2777 * Upper layer code will call this function separately
2778 * for TX and RX keys when these registers offsets are
2779 * used.
2780 */
f1dc5600 2781 u32 mic0, mic2;
f078f209 2782
f1dc5600
S		 2783 mic0 = get_unaligned_le32(k->kv_mic + 0);
2784 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 2785
2786 /* Write MIC key[31:0] */
f1dc5600
S		 2787 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2788 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 2789
2790 /* Write MIC key[63:32] */
f1dc5600
S		 2791 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2792 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 2793
2794 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2795 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2796 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2797 AR_KEYTABLE_TYPE_CLR);
2798 }
672903b3
JM		 2799
2800 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 2801 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2802 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 2803
2804 /*
2805 * Write the correct (un-inverted) key[47:0] last to enable
2806 * TKIP now that all other registers are set with correct
2807 * values.
2808 */
f1dc5600
S		 2809 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2810 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2811 } else {
672903b3 2812 /* Write key[47:0] */
f1dc5600
S		 2813 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2814 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 2815
2816 /* Write key[95:48] */
f1dc5600
S		 2817 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2818 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2819
2820 /* Write key[127:96] and key type */
f1dc5600
S		 2821 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2822 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2823
672903b3 2824 /* Write MAC address for the entry */
f1dc5600
S		 2825 (void) ath9k_hw_keysetmac(ah, entry, mac);
2826 }
f078f209 2827
f078f209
LR		 2828 return true;
2829}
2830
cbe61d8a 2831bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 2832{
2660b81a 2833 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 2834 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2835 if (val & AR_KEYTABLE_VALID)
2836 return true;
2837 }
2838 return false;
f078f209
LR		 2839}
2840
f1dc5600
S		 2841/******************************/
2842/* Power Management (Chipset) */
2843/******************************/
2844
cbe61d8a 2845static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2846{
f1dc5600
S		 2847 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2848 if (setChip) {
2849 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2850 AR_RTC_FORCE_WAKE_EN);
2851 if (!AR_SREV_9100(ah))
2852 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2853
d03a66c1 2854 REG_CLR_BIT(ah, (AR_RTC_RESET),
f1dc5600
S		 2855 AR_RTC_RESET_EN);
2856 }
f078f209
LR		 2857}
2858
cbe61d8a 2859static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2860{
f1dc5600
S		 2861 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2862 if (setChip) {
2660b81a 2863 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2864
f1dc5600
S		 2865 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2866 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2867 AR_RTC_FORCE_WAKE_ON_INT);
2868 } else {
2869 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2870 AR_RTC_FORCE_WAKE_EN);
f078f209 2871 }
f078f209 2872 }
f078f209
LR		 2873}
2874
cbe61d8a 2875static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2876{
f1dc5600
S		 2877 u32 val;
2878 int i;
f078f209 2879
f1dc5600
S		 2880 if (setChip) {
2881 if ((REG_READ(ah, AR_RTC_STATUS) &
2882 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2883 if (ath9k_hw_set_reset_reg(ah,
2884 ATH9K_RESET_POWER_ON) != true) {
2885 return false;
2886 }
2887 }
2888 if (AR_SREV_9100(ah))
2889 REG_SET_BIT(ah, AR_RTC_RESET,
2890 AR_RTC_RESET_EN);
f078f209 2891
f1dc5600
S		 2892 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2893 AR_RTC_FORCE_WAKE_EN);
2894 udelay(50);
f078f209 2895
f1dc5600
S		 2896 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2897 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2898 if (val == AR_RTC_STATUS_ON)
2899 break;
2900 udelay(50);
2901 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2902 AR_RTC_FORCE_WAKE_EN);
f078f209 2903 }
f1dc5600 2904 if (i == 0) {
d8baa939 2905 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 2906 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
f1dc5600 2907 return false;
f078f209 2908 }
f078f209
LR		 2909 }
2910
f1dc5600 2911 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2912
f1dc5600 2913 return true;
f078f209
LR		 2914}
2915
04717ccd
GJ		 2916static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2917 enum ath9k_power_mode mode)
f078f209 2918{
cbe61d8a 2919 int status = true, setChip = true;
f1dc5600
S		 2920 static const char *modes[] = {
2921 "AWAKE",
2922 "FULL-SLEEP",
2923 "NETWORK SLEEP",
2924 "UNDEFINED"
2925 };
f1dc5600 2926
cbdec975
GJ		 2927 if (ah->power_mode == mode)
2928 return status;
2929
d8baa939
S		 2930 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2931 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2932
2933 switch (mode) {
2934 case ATH9K_PM_AWAKE:
2935 status = ath9k_hw_set_power_awake(ah, setChip);
2936 break;
2937 case ATH9K_PM_FULL_SLEEP:
2938 ath9k_set_power_sleep(ah, setChip);
2660b81a 2939 ah->chip_fullsleep = true;
f1dc5600
S		 2940 break;
2941 case ATH9K_PM_NETWORK_SLEEP:
2942 ath9k_set_power_network_sleep(ah, setChip);
2943 break;
f078f209 2944 default:
d8baa939 2945 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 2946 "Unknown power mode %u\n", mode);
f078f209
LR		 2947 return false;
2948 }
2660b81a 2949 ah->power_mode = mode;
f1dc5600
S		 2950
2951 return status;
f078f209
LR		 2952}
2953
04717ccd
GJ		 2954bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2955{
2956 unsigned long flags;
2957 bool ret;
2958
2959 spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2960 ret = ath9k_hw_setpower_nolock(ah, mode);
2961 spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2962
2963 return ret;
2964}
2965
0bc0798b
GJ		 2966void ath9k_ps_wakeup(struct ath_softc *sc)
2967{
709ade9e
GJ		 2968 unsigned long flags;
2969
2970 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2971 if (++sc->ps_usecount != 1)
2972 goto unlock;
2973
cbdec975 2974 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
709ade9e
GJ		 2975
2976 unlock:
2977 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
0bc0798b
GJ		 2978}
2979
2980void ath9k_ps_restore(struct ath_softc *sc)
2981{
709ade9e
GJ		 2982 unsigned long flags;
2983
2984 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2985 if (--sc->ps_usecount != 0)
2986 goto unlock;
2987
96148326
GJ		 2988 if (sc->ps_enabled &&
2989 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2990 SC_OP_WAIT_FOR_CAB |
2991 SC_OP_WAIT_FOR_PSPOLL_DATA |
2992 SC_OP_WAIT_FOR_TX_ACK)))
2993 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
709ade9e
GJ		 2994
2995 unlock:
2996 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
0bc0798b
GJ		 2997}
2998
24c1a280
LR		 2999/*
3000 * Helper for ASPM support.
3001 *
3002 * Disable PLL when in L0s as well as receiver clock when in L1.
3003 * This power saving option must be enabled through the SerDes.
3004 *
3005 * Programming the SerDes must go through the same 288 bit serial shift
3006 * register as the other analog registers. Hence the 9 writes.
3007 */
cbe61d8a 3008void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
f078f209 3009{
f1dc5600 3010 u8 i;
f078f209 3011
2660b81a 3012 if (ah->is_pciexpress != true)
f1dc5600 3013 return;
f078f209 3014
24c1a280 3015 /* Do not touch SerDes registers */
2660b81a 3016 if (ah->config.pcie_powersave_enable == 2)
f1dc5600
S		 3017 return;
3018
24c1a280 3019 /* Nothing to do on restore for 11N */
f1dc5600
S		 3020 if (restore)
3021 return;
3022
3023 if (AR_SREV_9280_20_OR_LATER(ah)) {
24c1a280
LR		 3024 /*
3025 * AR9280 2.0 or later chips use SerDes values from the
3026 * initvals.h initialized depending on chipset during
f637cfd6 3027 * ath9k_hw_init()
24c1a280 3028 */
2660b81a
S		 3029 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
3030 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
3031 INI_RA(&ah->iniPcieSerdes, i, 1));
f078f209 3032 }
f1dc5600 3033 } else if (AR_SREV_9280(ah) &&
d535a42a 3034 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
f1dc5600
S		 3035 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3036 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3037
24c1a280 3038 /* RX shut off when elecidle is asserted */
f1dc5600
S		 3039 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3040 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3041 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3042
24c1a280 3043 /* Shut off CLKREQ active in L1 */
2660b81a 3044 if (ah->config.pcie_clock_req)
f1dc5600
S		 3045 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3046 else
3047 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3048
3049 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3050 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3051 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3052
24c1a280 3053 /* Load the new settings */
f1dc5600
S		 3054 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3055
f1dc5600
S		 3056 } else {
3057 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3058 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
24c1a280
LR		 3059
3060 /* RX shut off when elecidle is asserted */
f1dc5600
S		 3061 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3062 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3063 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
24c1a280
LR		 3064
3065 /*
3066 * Ignore ah->ah_config.pcie_clock_req setting for
3067 * pre-AR9280 11n
3068 */
f1dc5600 3069 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
24c1a280 3070
f1dc5600
S		 3071 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3072 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3073 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
24c1a280
LR		 3074
3075 /* Load the new settings */
f1dc5600 3076 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 3077 }
3078
6d08b9b9
LR		 3079 udelay(1000);
3080
24c1a280 3081 /* set bit 19 to allow forcing of pcie core into L1 state */
f1dc5600
S		 3082 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3083
24c1a280 3084 /* Several PCIe massages to ensure proper behaviour */
2660b81a
S		 3085 if (ah->config.pcie_waen) {
3086 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
f1dc5600 3087 } else {
d340b1f0 3088 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah))
e7594072 3089 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
24c1a280
LR		 3090 /*
3091 * On AR9280 chips bit 22 of 0x4004 needs to be set to
3092 * otherwise card may disappear.
3093 */
e7594072
SB		 3094 else if (AR_SREV_9280(ah))
3095 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
f1dc5600 3096 else
e7594072 3097 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
f1dc5600 3098 }
f078f209
LR		 3099}
3100
f1dc5600
S		 3101/**********************/
3102/* Interrupt Handling */
3103/**********************/
3104
cbe61d8a 3105bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 3106{
3107 u32 host_isr;
3108
3109 if (AR_SREV_9100(ah))
3110 return true;
3111
3112 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3113 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3114 return true;
3115
3116 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3117 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3118 && (host_isr != AR_INTR_SPURIOUS))
3119 return true;
3120
3121 return false;
3122}
3123
cbe61d8a 3124bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 3125{
3126 u32 isr = 0;
3127 u32 mask2 = 0;
2660b81a 3128 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3129 u32 sync_cause = 0;
3130 bool fatal_int = false;
3131
3132 if (!AR_SREV_9100(ah)) {
3133 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3134 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3135 == AR_RTC_STATUS_ON) {
3136 isr = REG_READ(ah, AR_ISR);
3137 }
3138 }
3139
f1dc5600
S		 3140 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3141 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 3142
3143 *masked = 0;
3144
3145 if (!isr && !sync_cause)
3146 return false;
3147 } else {
3148 *masked = 0;
3149 isr = REG_READ(ah, AR_ISR);
3150 }
3151
3152 if (isr) {
f078f209
LR		 3153 if (isr & AR_ISR_BCNMISC) {
3154 u32 isr2;
3155 isr2 = REG_READ(ah, AR_ISR_S2);
3156 if (isr2 & AR_ISR_S2_TIM)
3157 mask2 |= ATH9K_INT_TIM;
3158 if (isr2 & AR_ISR_S2_DTIM)
3159 mask2 |= ATH9K_INT_DTIM;
3160 if (isr2 & AR_ISR_S2_DTIMSYNC)
3161 mask2 |= ATH9K_INT_DTIMSYNC;
3162 if (isr2 & (AR_ISR_S2_CABEND))
3163 mask2 |= ATH9K_INT_CABEND;
3164 if (isr2 & AR_ISR_S2_GTT)
3165 mask2 |= ATH9K_INT_GTT;
3166 if (isr2 & AR_ISR_S2_CST)
3167 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 3168 if (isr2 & AR_ISR_S2_TSFOOR)
3169 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 3170 }
3171
3172 isr = REG_READ(ah, AR_ISR_RAC);
3173 if (isr == 0xffffffff) {
3174 *masked = 0;
3175 return false;
3176 }
3177
3178 *masked = isr & ATH9K_INT_COMMON;
3179
0ef1f168 3180 if (ah->config.intr_mitigation) {
f078f209
LR		 3181 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3182 *masked |= ATH9K_INT_RX;
3183 }
3184
3185 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3186 *masked |= ATH9K_INT_RX;
3187 if (isr &
3188 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3189 AR_ISR_TXEOL)) {
3190 u32 s0_s, s1_s;
3191
3192 *masked |= ATH9K_INT_TX;
3193
3194 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 3195 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3196 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 3197
3198 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 3199 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3200 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 3201 }
3202
3203 if (isr & AR_ISR_RXORN) {
3204 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 3205 "receive FIFO overrun interrupt\n");
f078f209
LR		 3206 }
3207
3208 if (!AR_SREV_9100(ah)) {
60b67f51 3209 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3210 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3211 if (isr5 & AR_ISR_S5_TIM_TIMER)
3212 *masked |= ATH9K_INT_TIM_TIMER;
3213 }
3214 }
3215
3216 *masked |= mask2;
3217 }
f1dc5600 3218
f078f209
LR		 3219 if (AR_SREV_9100(ah))
3220 return true;
f1dc5600 3221
ff155a45
VT		 3222 if (isr & AR_ISR_GENTMR) {
3223 u32 s5_s;
3224
3225 s5_s = REG_READ(ah, AR_ISR_S5_S);
3226 if (isr & AR_ISR_GENTMR) {
3227 ah->intr_gen_timer_trigger =
3228 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3229
3230 ah->intr_gen_timer_thresh =
3231 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3232
3233 if (ah->intr_gen_timer_trigger)
3234 *masked |= ATH9K_INT_GENTIMER;
3235
3236 }
3237 }
3238
f078f209
LR		 3239 if (sync_cause) {
3240 fatal_int =
3241 (sync_cause &
3242 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3243 ? true : false;
3244
3245 if (fatal_int) {
3246 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3247 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 3248 "received PCI FATAL interrupt\n");
f078f209
LR		 3249 }
3250 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3251 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 3252 "received PCI PERR interrupt\n");
f078f209 3253 }
a89bff9a 3254 *masked |= ATH9K_INT_FATAL;
f078f209
LR		 3255 }
3256 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3257 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 3258 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 3259 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3260 REG_WRITE(ah, AR_RC, 0);
3261 *masked |= ATH9K_INT_FATAL;
3262 }
3263 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3264 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 3265 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 3266 }
3267
3268 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3269 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3270 }
f1dc5600 3271
f078f209
LR		 3272 return true;
3273}
3274
cbe61d8a 3275enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 3276{
2660b81a 3277 u32 omask = ah->mask_reg;
f078f209 3278 u32 mask, mask2;
2660b81a 3279 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 3280
04bd4638 3281 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 3282
3283 if (omask & ATH9K_INT_GLOBAL) {
04bd4638 3284 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 3285 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3286 (void) REG_READ(ah, AR_IER);
3287 if (!AR_SREV_9100(ah)) {
3288 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3289 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3290
3291 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3292 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3293 }
3294 }
3295
3296 mask = ints & ATH9K_INT_COMMON;
3297 mask2 = 0;
3298
3299 if (ints & ATH9K_INT_TX) {
2660b81a 3300 if (ah->txok_interrupt_mask)
f078f209 3301 mask |= AR_IMR_TXOK;
2660b81a 3302 if (ah->txdesc_interrupt_mask)
f078f209 3303 mask |= AR_IMR_TXDESC;
2660b81a 3304 if (ah->txerr_interrupt_mask)
f078f209 3305 mask |= AR_IMR_TXERR;
2660b81a 3306 if (ah->txeol_interrupt_mask)
f078f209
LR		 3307 mask |= AR_IMR_TXEOL;
3308 }
3309 if (ints & ATH9K_INT_RX) {
3310 mask |= AR_IMR_RXERR;
0ef1f168 3311 if (ah->config.intr_mitigation)
f078f209
LR		 3312 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3313 else
3314 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 3315 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 3316 mask |= AR_IMR_GENTMR;
3317 }
3318
3319 if (ints & (ATH9K_INT_BMISC)) {
3320 mask |= AR_IMR_BCNMISC;
3321 if (ints & ATH9K_INT_TIM)
3322 mask2 |= AR_IMR_S2_TIM;
3323 if (ints & ATH9K_INT_DTIM)
3324 mask2 |= AR_IMR_S2_DTIM;
3325 if (ints & ATH9K_INT_DTIMSYNC)
3326 mask2 |= AR_IMR_S2_DTIMSYNC;
3327 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 3328 mask2 |= AR_IMR_S2_CABEND;
3329 if (ints & ATH9K_INT_TSFOOR)
3330 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 3331 }
3332
3333 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3334 mask |= AR_IMR_BCNMISC;
3335 if (ints & ATH9K_INT_GTT)
3336 mask2 |= AR_IMR_S2_GTT;
3337 if (ints & ATH9K_INT_CST)
3338 mask2 |= AR_IMR_S2_CST;
3339 }
3340
04bd4638 3341 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 3342 REG_WRITE(ah, AR_IMR, mask);
3343 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3344 AR_IMR_S2_DTIM |
3345 AR_IMR_S2_DTIMSYNC |
3346 AR_IMR_S2_CABEND |
3347 AR_IMR_S2_CABTO |
3348 AR_IMR_S2_TSFOOR |
3349 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3350 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2660b81a 3351 ah->mask_reg = ints;
f078f209 3352
60b67f51 3353 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3354 if (ints & ATH9K_INT_TIM_TIMER)
3355 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3356 else
3357 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3358 }
3359
3360 if (ints & ATH9K_INT_GLOBAL) {
04bd4638 3361 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 3362 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3363 if (!AR_SREV_9100(ah)) {
3364 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3365 AR_INTR_MAC_IRQ);
3366 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3367
3368
3369 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3370 AR_INTR_SYNC_DEFAULT);
3371 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3372 AR_INTR_SYNC_DEFAULT);
3373 }
3374 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3375 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3376 }
3377
3378 return omask;
3379}
3380
f1dc5600
S		 3381/*******************/
3382/* Beacon Handling */
3383/*******************/
3384
cbe61d8a 3385void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 3386{
f078f209
LR		 3387 int flags = 0;
3388
2660b81a 3389 ah->beacon_interval = beacon_period;
f078f209 3390
2660b81a 3391 switch (ah->opmode) {
d97809db
CM		 3392 case NL80211_IFTYPE_STATION:
3393 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 3394 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3395 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3396 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3397 flags |= AR_TBTT_TIMER_EN;
3398 break;
d97809db 3399 case NL80211_IFTYPE_ADHOC:
9cb5412b 3400 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 3401 REG_SET_BIT(ah, AR_TXCFG,
3402 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3403 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3404 TU_TO_USEC(next_beacon +
2660b81a
S		 3405 (ah->atim_window ? ah->
3406 atim_window : 1)));
f078f209 3407 flags |= AR_NDP_TIMER_EN;
d97809db 3408 case NL80211_IFTYPE_AP:
f078f209
LR		 3409 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3410 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3411 TU_TO_USEC(next_beacon -
2660b81a 3412 ah->config.
60b67f51 3413 dma_beacon_response_time));
f078f209
LR		 3414 REG_WRITE(ah, AR_NEXT_SWBA,
3415 TU_TO_USEC(next_beacon -
2660b81a 3416 ah->config.
60b67f51 3417 sw_beacon_response_time));
f078f209
LR		 3418 flags |=
3419 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3420 break;
d97809db
CM		 3421 default:
3422 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3423 "%s: unsupported opmode: %d\n",
2660b81a 3424 __func__, ah->opmode);
d97809db
CM		 3425 return;
3426 break;
f078f209
LR		 3427 }
3428
3429 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3430 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3431 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3432 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3433
3434 beacon_period &= ~ATH9K_BEACON_ENA;
3435 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3436 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3437 ath9k_hw_reset_tsf(ah);
3438 }
3439
3440 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3441}
3442
cbe61d8a 3443void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 3444 const struct ath9k_beacon_state *bs)
f078f209
LR		 3445{
3446 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 3447 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3448
3449 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3450
3451 REG_WRITE(ah, AR_BEACON_PERIOD,
3452 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3453 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3454 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3455
3456 REG_RMW_FIELD(ah, AR_RSSI_THR,
3457 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3458
3459 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3460
3461 if (bs->bs_sleepduration > beaconintval)
3462 beaconintval = bs->bs_sleepduration;
3463
3464 dtimperiod = bs->bs_dtimperiod;
3465 if (bs->bs_sleepduration > dtimperiod)
3466 dtimperiod = bs->bs_sleepduration;
3467
3468 if (beaconintval == dtimperiod)
3469 nextTbtt = bs->bs_nextdtim;
3470 else
3471 nextTbtt = bs->bs_nexttbtt;
3472
04bd4638
S		 3473 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3474 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3475 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3476 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3477
f1dc5600
S		 3478 REG_WRITE(ah, AR_NEXT_DTIM,
3479 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3480 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3481
f1dc5600
S		 3482 REG_WRITE(ah, AR_SLEEP1,
3483 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3484 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3485
f1dc5600
S		 3486 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3487 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3488 else
3489 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3490
f1dc5600
S		 3491 REG_WRITE(ah, AR_SLEEP2,
3492 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3493
f1dc5600
S		 3494 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3495 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3496
f1dc5600
S		 3497 REG_SET_BIT(ah, AR_TIMER_MODE,
3498 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3499 AR_DTIM_TIMER_EN);
f078f209 3500
4af9cf4f
S		 3501 /* TSF Out of Range Threshold */
3502 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209
LR		 3503}
3504
f1dc5600
S		 3505/*******************/
3506/* HW Capabilities */
3507/*******************/
3508
eef7a574 3509void ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 3510{
2660b81a 3511 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 3512 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
22f25d0d 3513 struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info;
608b88cb 3514
f1dc5600 3515 u16 capField = 0, eeval;
f078f209 3516
f74df6fb 3517 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 3518 regulatory->current_rd = eeval;
f078f209 3519
f74df6fb 3520 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 3521 if (AR_SREV_9285_10_OR_LATER(ah))
3522 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 3523 regulatory->current_rd_ext = eeval;
f078f209 3524
f74df6fb 3525 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 3526
2660b81a 3527 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 3528 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 3529 if (regulatory->current_rd == 0x64 ||
3530 regulatory->current_rd == 0x65)
3531 regulatory->current_rd += 5;
3532 else if (regulatory->current_rd == 0x41)
3533 regulatory->current_rd = 0x43;
f1dc5600 3534 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
608b88cb 3535 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 3536 }
f078f209 3537
f74df6fb 3538 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
f1dc5600 3539 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3540
f1dc5600
S		 3541 if (eeval & AR5416_OPFLAGS_11A) {
3542 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 3543 if (ah->config.ht_enable) {
f1dc5600
S		 3544 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3545 set_bit(ATH9K_MODE_11NA_HT20,
3546 pCap->wireless_modes);
3547 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3548 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3549 pCap->wireless_modes);
3550 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3551 pCap->wireless_modes);
3552 }
f078f209 3553 }
f078f209
LR		 3554 }
3555
f1dc5600 3556 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 3557 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 3558 if (ah->config.ht_enable) {
f1dc5600
S		 3559 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3560 set_bit(ATH9K_MODE_11NG_HT20,
3561 pCap->wireless_modes);
3562 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3563 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3564 pCap->wireless_modes);
3565 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3566 pCap->wireless_modes);
3567 }
3568 }
f078f209 3569 }
f1dc5600 3570
f74df6fb 3571 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 3572 /*
3573 * For AR9271 we will temporarilly uses the rx chainmax as read from
3574 * the EEPROM.
3575 */
8147f5de 3576 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 3577 !(eeval & AR5416_OPFLAGS_11A) &&
3578 !(AR_SREV_9271(ah)))
3579 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 3580 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3581 else
d7e7d229 3582 /* Use rx_chainmask from EEPROM. */
8147f5de 3583 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 3584
d535a42a 3585 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 3586 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3587
f1dc5600
S		 3588 pCap->low_2ghz_chan = 2312;
3589 pCap->high_2ghz_chan = 2732;
f078f209 3590
f1dc5600
S		 3591 pCap->low_5ghz_chan = 4920;
3592 pCap->high_5ghz_chan = 6100;
f078f209 3593
f1dc5600
S		 3594 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3595 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3596 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3597
f1dc5600
S		 3598 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3599 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3600 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3601
2660b81a 3602 if (ah->config.ht_enable)
f1dc5600
S		 3603 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3604 else
3605 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3606
f1dc5600
S		 3607 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3608 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3609 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3610 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3611
f1dc5600
S		 3612 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3613 pCap->total_queues =
3614 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3615 else
3616 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3617
f1dc5600
S		 3618 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3619 pCap->keycache_size =
3620 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3621 else
3622 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3623
f1dc5600 3624 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f1dc5600 3625 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3626
cb33c412
SB		 3627 if (AR_SREV_9285_10_OR_LATER(ah))
3628 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3629 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3630 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3631 else
3632 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3633
f1dc5600
S		 3634 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3635 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3636 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3637 } else {
3638 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3639 }
3640
f1dc5600
S		 3641 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3642
e97275cb 3643#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 3644 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3645 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3646 ah->rfkill_gpio =
3647 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3648 ah->rfkill_polarity =
3649 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 3650
3651 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3652 }
f1dc5600 3653#endif
f078f209 3654
d535a42a
S		 3655 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3656 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3657 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3658 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
882b7092
VN		 3659 (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3660 (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
f1dc5600 3661 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3662 else
f1dc5600 3663 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3664
e7594072 3665 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3666 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3667 else
3668 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3669
608b88cb 3670 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 3671 pCap->reg_cap =
3672 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3673 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3674 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3675 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3676 } else {
f1dc5600
S		 3677 pCap->reg_cap =
3678 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3679 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3680 }
f078f209 3681
f1dc5600
S		 3682 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3683
3684 pCap->num_antcfg_5ghz =
f74df6fb 3685 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3686 pCap->num_antcfg_2ghz =
f74df6fb 3687 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3688
fe12946e
VT		 3689 if (AR_SREV_9280_10_OR_LATER(ah) &&
3690 ath_btcoex_supported(ah->hw_version.subsysid)) {
22f25d0d
VT		 3691 btcoex_info->btactive_gpio = ATH_BTACTIVE_GPIO;
3692 btcoex_info->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3693
8c8f9ba7 3694 if (AR_SREV_9285(ah)) {
22f25d0d 3695 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_3WIRE;
8c8f9ba7
VT		 3696 btcoex_info->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3697 } else {
22f25d0d 3698 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 3699 }
22f25d0d
VT		 3700 } else {
3701 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 3702 }
f078f209
LR		 3703}
3704
cbe61d8a 3705bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3706 u32 capability, u32 *result)
f078f209 3707{
608b88cb 3708 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 3709 switch (type) {
3710 case ATH9K_CAP_CIPHER:
3711 switch (capability) {
3712 case ATH9K_CIPHER_AES_CCM:
3713 case ATH9K_CIPHER_AES_OCB:
3714 case ATH9K_CIPHER_TKIP:
3715 case ATH9K_CIPHER_WEP:
3716 case ATH9K_CIPHER_MIC:
3717 case ATH9K_CIPHER_CLR:
3718 return true;
3719 default:
3720 return false;
3721 }
3722 case ATH9K_CAP_TKIP_MIC:
3723 switch (capability) {
3724 case 0:
3725 return true;
3726 case 1:
2660b81a 3727 return (ah->sta_id1_defaults &
f1dc5600
S		 3728 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3729 false;
3730 }
3731 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 3732 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 3733 false : true;
f1dc5600
S		 3734 case ATH9K_CAP_DIVERSITY:
3735 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3736 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3737 true : false;
f1dc5600
S		 3738 case ATH9K_CAP_MCAST_KEYSRCH:
3739 switch (capability) {
3740 case 0:
3741 return true;
3742 case 1:
3743 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3744 return false;
3745 } else {
2660b81a 3746 return (ah->sta_id1_defaults &
f1dc5600
S		 3747 AR_STA_ID1_MCAST_KSRCH) ? true :
3748 false;
3749 }
3750 }
3751 return false;
f1dc5600
S		 3752 case ATH9K_CAP_TXPOW:
3753 switch (capability) {
3754 case 0:
3755 return 0;
3756 case 1:
608b88cb 3757 *result = regulatory->power_limit;
f1dc5600
S		 3758 return 0;
3759 case 2:
608b88cb 3760 *result = regulatory->max_power_level;
f1dc5600
S		 3761 return 0;
3762 case 3:
608b88cb 3763 *result = regulatory->tp_scale;
f1dc5600
S		 3764 return 0;
3765 }
3766 return false;
8bd1d07f
SB		 3767 case ATH9K_CAP_DS:
3768 return (AR_SREV_9280_20_OR_LATER(ah) &&
3769 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3770 ? false : true;
f1dc5600
S		 3771 default:
3772 return false;
f078f209 3773 }
f078f209
LR		 3774}
3775
cbe61d8a 3776bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3777 u32 capability, u32 setting, int *status)
f078f209 3778{
f1dc5600 3779 u32 v;
f078f209 3780
f1dc5600
S		 3781 switch (type) {
3782 case ATH9K_CAP_TKIP_MIC:
3783 if (setting)
2660b81a 3784 ah->sta_id1_defaults |=
f1dc5600
S		 3785 AR_STA_ID1_CRPT_MIC_ENABLE;
3786 else
2660b81a 3787 ah->sta_id1_defaults &=
f1dc5600
S		 3788 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3789 return true;
3790 case ATH9K_CAP_DIVERSITY:
3791 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3792 if (setting)
3793 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3794 else
3795 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3796 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3797 return true;
3798 case ATH9K_CAP_MCAST_KEYSRCH:
3799 if (setting)
2660b81a 3800 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3801 else
2660b81a 3802 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3803 return true;
f1dc5600
S		 3804 default:
3805 return false;
f078f209
LR		 3806 }
3807}
3808
f1dc5600
S		 3809/****************************/
3810/* GPIO / RFKILL / Antennae */
3811/****************************/
f078f209 3812
cbe61d8a 3813static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 3814 u32 gpio, u32 type)
3815{
3816 int addr;
3817 u32 gpio_shift, tmp;
f078f209 3818
f1dc5600
S		 3819 if (gpio > 11)
3820 addr = AR_GPIO_OUTPUT_MUX3;
3821 else if (gpio > 5)
3822 addr = AR_GPIO_OUTPUT_MUX2;
3823 else
3824 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3825
f1dc5600 3826 gpio_shift = (gpio % 6) * 5;
f078f209 3827
f1dc5600
S		 3828 if (AR_SREV_9280_20_OR_LATER(ah)
3829 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3830 REG_RMW(ah, addr, (type << gpio_shift),
3831 (0x1f << gpio_shift));
f078f209 3832 } else {
f1dc5600
S		 3833 tmp = REG_READ(ah, addr);
3834 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3835 tmp &= ~(0x1f << gpio_shift);
3836 tmp |= (type << gpio_shift);
3837 REG_WRITE(ah, addr, tmp);
f078f209 3838 }
f078f209
LR		 3839}
3840
cbe61d8a 3841void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 3842{
f1dc5600 3843 u32 gpio_shift;
f078f209 3844
2660b81a 3845 ASSERT(gpio < ah->caps.num_gpio_pins);
f078f209 3846
f1dc5600 3847 gpio_shift = gpio << 1;
f078f209 3848
f1dc5600
S		 3849 REG_RMW(ah,
3850 AR_GPIO_OE_OUT,
3851 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3852 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3853}
3854
cbe61d8a 3855u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 3856{
cb33c412
SB		 3857#define MS_REG_READ(x, y) \
3858 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3859
2660b81a 3860 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 3861 return 0xffffffff;
f078f209 3862
ac88b6ec
VN		 3863 if (AR_SREV_9287_10_OR_LATER(ah))
3864 return MS_REG_READ(AR9287, gpio) != 0;
3865 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 3866 return MS_REG_READ(AR9285, gpio) != 0;
3867 else if (AR_SREV_9280_10_OR_LATER(ah))
3868 return MS_REG_READ(AR928X, gpio) != 0;
3869 else
3870 return MS_REG_READ(AR, gpio) != 0;
f078f209
LR		 3871}
3872
cbe61d8a 3873void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 3874 u32 ah_signal_type)
f078f209 3875{
f1dc5600 3876 u32 gpio_shift;
f078f209 3877
f1dc5600 3878 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3879
f1dc5600 3880 gpio_shift = 2 * gpio;
f078f209 3881
f1dc5600
S		 3882 REG_RMW(ah,
3883 AR_GPIO_OE_OUT,
3884 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3885 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3886}
3887
cbe61d8a 3888void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 3889{
f1dc5600
S		 3890 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3891 AR_GPIO_BIT(gpio));
f078f209
LR		 3892}
3893
cbe61d8a 3894u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 3895{
f1dc5600 3896 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209
LR		 3897}
3898
cbe61d8a 3899void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 3900{
f1dc5600 3901 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209
LR		 3902}
3903
cbe61d8a 3904bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
f1dc5600
S		 3905 enum ath9k_ant_setting settings,
3906 struct ath9k_channel *chan,
3907 u8 *tx_chainmask,
3908 u8 *rx_chainmask,
3909 u8 *antenna_cfgd)
f078f209 3910{
f1dc5600 3911 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
f078f209 3912
f1dc5600
S		 3913 if (AR_SREV_9280(ah)) {
3914 if (!tx_chainmask_cfg) {
f078f209 3915
f1dc5600
S		 3916 tx_chainmask_cfg = *tx_chainmask;
3917 rx_chainmask_cfg = *rx_chainmask;
3918 }
f078f209 3919
f1dc5600
S		 3920 switch (settings) {
3921 case ATH9K_ANT_FIXED_A:
3922 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3923 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3924 *antenna_cfgd = true;
3925 break;
3926 case ATH9K_ANT_FIXED_B:
2660b81a 3927 if (ah->caps.tx_chainmask >
f1dc5600
S		 3928 ATH9K_ANTENNA1_CHAINMASK) {
3929 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3930 }
3931 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3932 *antenna_cfgd = true;
3933 break;
3934 case ATH9K_ANT_VARIABLE:
3935 *tx_chainmask = tx_chainmask_cfg;
3936 *rx_chainmask = rx_chainmask_cfg;
3937 *antenna_cfgd = true;
3938 break;
3939 default:
3940 break;
3941 }
3942 } else {
1cf6873a 3943 ah->config.diversity_control = settings;
f078f209 3944 }
f078f209 3945
f1dc5600 3946 return true;
f078f209
LR		 3947}
3948
f1dc5600
S		 3949/*********************/
3950/* General Operation */
3951/*********************/
3952
cbe61d8a 3953u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 3954{
f1dc5600
S		 3955 u32 bits = REG_READ(ah, AR_RX_FILTER);
3956 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3957
f1dc5600
S		 3958 if (phybits & AR_PHY_ERR_RADAR)
3959 bits |= ATH9K_RX_FILTER_PHYRADAR;
3960 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3961 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3962
f1dc5600 3963 return bits;
f078f209
LR		 3964}
3965
cbe61d8a 3966void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 3967{
f1dc5600 3968 u32 phybits;
f078f209 3969
7ea310be
S		 3970 REG_WRITE(ah, AR_RX_FILTER, bits);
3971
f1dc5600
S		 3972 phybits = 0;
3973 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3974 phybits |= AR_PHY_ERR_RADAR;
3975 if (bits & ATH9K_RX_FILTER_PHYERR)
3976 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3977 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3978
f1dc5600
S		 3979 if (phybits)
3980 REG_WRITE(ah, AR_RXCFG,
3981 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3982 else
3983 REG_WRITE(ah, AR_RXCFG,
3984 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3985}
f078f209 3986
cbe61d8a 3987bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600
S		 3988{
3989 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3990}
f078f209 3991
cbe61d8a 3992bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600
S		 3993{
3994 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3995 return false;
f078f209 3996
f1dc5600 3997 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
f078f209
LR		 3998}
3999
8fbff4b8 4000void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 4001{
608b88cb 4002 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 4003 struct ath9k_channel *chan = ah->curchan;
5f8e077c 4004 struct ieee80211_channel *channel = chan->chan;
f078f209 4005
608b88cb 4006 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 4007
8fbff4b8 4008 ah->eep_ops->set_txpower(ah, chan,
608b88cb 4009 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 4010 channel->max_antenna_gain * 2,
4011 channel->max_power * 2,
4012 min((u32) MAX_RATE_POWER,
608b88cb 4013 (u32) regulatory->power_limit));
6f255425
LR		 4014}
4015
cbe61d8a 4016void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 4017{
ba52da58 4018 memcpy(ah->macaddr, mac, ETH_ALEN);
f078f209
LR		 4019}
4020
cbe61d8a 4021void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 4022{
2660b81a 4023 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209
LR		 4024}
4025
cbe61d8a 4026void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 4027{
f1dc5600
S		 4028 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4029 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209
LR		 4030}
4031
ba52da58 4032void ath9k_hw_setbssidmask(struct ath_softc *sc)
f078f209 4033{
ba52da58
S		 4034 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
4035 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
f078f209
LR		 4036}
4037
ba52da58 4038void ath9k_hw_write_associd(struct ath_softc *sc)
f078f209 4039{
ba52da58
S		 4040 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
4041 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
4042 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 4043}
4044
cbe61d8a 4045u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 4046{
f1dc5600 4047 u64 tsf;
f078f209 4048
f1dc5600
S		 4049 tsf = REG_READ(ah, AR_TSF_U32);
4050 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 4051
f1dc5600
S		 4052 return tsf;
4053}
f078f209 4054
cbe61d8a 4055void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 4056{
27abe060 4057 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 4058 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060
AF		 4059}
4060
cbe61d8a 4061void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 4062{
1b7e528b 4063 ath9k_ps_wakeup(ah->ah_sc);
f9b604f6
GJ		 4064 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4065 AH_TSF_WRITE_TIMEOUT))
4066 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
4067 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4068
f1dc5600 4069 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
1b7e528b 4070 ath9k_ps_restore(ah->ah_sc);
f1dc5600 4071}
f078f209 4072
54e4cec6 4073void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 4074{
f1dc5600 4075 if (setting)
2660b81a 4076 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 4077 else
2660b81a 4078 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 4079}
f078f209 4080
cbe61d8a 4081bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f1dc5600 4082{
f1dc5600 4083 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
04bd4638 4084 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
2660b81a 4085 ah->slottime = (u32) -1;
f1dc5600
S		 4086 return false;
4087 } else {
4088 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
2660b81a 4089 ah->slottime = us;
f1dc5600 4090 return true;
f078f209 4091 }
f1dc5600
S		 4092}
4093
cbe61d8a 4094void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
f1dc5600
S		 4095{
4096 u32 macmode;
4097
4098 if (mode == ATH9K_HT_MACMODE_2040 &&
2660b81a 4099 !ah->config.cwm_ignore_extcca)
f1dc5600
S		 4100 macmode = AR_2040_JOINED_RX_CLEAR;
4101 else
4102 macmode = 0;
f078f209 4103
f1dc5600 4104 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 4105}
ff155a45
VT		 4106
4107/* HW Generic timers configuration */
4108
4109static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4110{
4111 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4112 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4113 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4114 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4115 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4116 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4117 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4118 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4119 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4120 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4121 AR_NDP2_TIMER_MODE, 0x0002},
4122 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4123 AR_NDP2_TIMER_MODE, 0x0004},
4124 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4125 AR_NDP2_TIMER_MODE, 0x0008},
4126 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4127 AR_NDP2_TIMER_MODE, 0x0010},
4128 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4129 AR_NDP2_TIMER_MODE, 0x0020},
4130 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4131 AR_NDP2_TIMER_MODE, 0x0040},
4132 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4133 AR_NDP2_TIMER_MODE, 0x0080}
4134};
4135
4136/* HW generic timer primitives */
4137
4138/* compute and clear index of rightmost 1 */
4139static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4140{
4141 u32 b;
4142
4143 b = *mask;
4144 b &= (0-b);
4145 *mask &= ~b;
4146 b *= debruijn32;
4147 b >>= 27;
4148
4149 return timer_table->gen_timer_index[b];
4150}
4151
1773912b 4152u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 4153{
4154 return REG_READ(ah, AR_TSF_L32);
4155}
4156
4157struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4158 void (*trigger)(void *),
4159 void (*overflow)(void *),
4160 void *arg,
4161 u8 timer_index)
4162{
4163 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4164 struct ath_gen_timer *timer;
4165
4166 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4167
4168 if (timer == NULL) {
4169 printk(KERN_DEBUG "Failed to allocate memory"
4170 "for hw timer[%d]\n", timer_index);
4171 return NULL;
4172 }
4173
4174 /* allocate a hardware generic timer slot */
4175 timer_table->timers[timer_index] = timer;
4176 timer->index = timer_index;
4177 timer->trigger = trigger;
4178 timer->overflow = overflow;
4179 timer->arg = arg;
4180
4181 return timer;
4182}
4183
4184void ath_gen_timer_start(struct ath_hw *ah,
4185 struct ath_gen_timer *timer,
4186 u32 timer_next, u32 timer_period)
4187{
4188 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4189 u32 tsf;
4190
4191 BUG_ON(!timer_period);
4192
4193 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4194
4195 tsf = ath9k_hw_gettsf32(ah);
4196
4197 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, "curent tsf %x period %x"
4198 "timer_next %x\n", tsf, timer_period, timer_next);
4199
4200 /*
4201 * Pull timer_next forward if the current TSF already passed it
4202 * because of software latency
4203 */
4204 if (timer_next < tsf)
4205 timer_next = tsf + timer_period;
4206
4207 /*
4208 * Program generic timer registers
4209 */
4210 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4211 timer_next);
4212 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4213 timer_period);
4214 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4215 gen_tmr_configuration[timer->index].mode_mask);
4216
4217 /* Enable both trigger and thresh interrupt masks */
4218 REG_SET_BIT(ah, AR_IMR_S5,
4219 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4220 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4221
4222 if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
4223 ath9k_hw_set_interrupts(ah, 0);
4224 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
4225 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4226 }
4227}
4228
4229void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4230{
4231 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4232
4233 if ((timer->index < AR_FIRST_NDP_TIMER) ||
4234 (timer->index >= ATH_MAX_GEN_TIMER)) {
4235 return;
4236 }
4237
4238 /* Clear generic timer enable bits. */
4239 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4240 gen_tmr_configuration[timer->index].mode_mask);
4241
4242 /* Disable both trigger and thresh interrupt masks */
4243 REG_CLR_BIT(ah, AR_IMR_S5,
4244 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4245 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4246
4247 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4248
4249 /* if no timer is enabled, turn off interrupt mask */
4250 if (timer_table->timer_mask.val == 0) {
4251 ath9k_hw_set_interrupts(ah, 0);
4252 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
4253 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4254 }
4255}
4256
4257void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4258{
4259 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4260
4261 /* free the hardware generic timer slot */
4262 timer_table->timers[timer->index] = NULL;
4263 kfree(timer);
4264}
4265
4266/*
4267 * Generic Timer Interrupts handling
4268 */
4269void ath_gen_timer_isr(struct ath_hw *ah)
4270{
4271 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4272 struct ath_gen_timer *timer;
4273 u32 trigger_mask, thresh_mask, index;
4274
4275 /* get hardware generic timer interrupt status */
4276 trigger_mask = ah->intr_gen_timer_trigger;
4277 thresh_mask = ah->intr_gen_timer_thresh;
4278 trigger_mask &= timer_table->timer_mask.val;
4279 thresh_mask &= timer_table->timer_mask.val;
4280
4281 trigger_mask &= ~thresh_mask;
4282
4283 while (thresh_mask) {
4284 index = rightmost_index(timer_table, &thresh_mask);
4285 timer = timer_table->timers[index];
4286 BUG_ON(!timer);
4287 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER,
4288 "TSF overflow for Gen timer %d\n", index);
4289 timer->overflow(timer->arg);
4290 }
4291
4292 while (trigger_mask) {
4293 index = rightmost_index(timer_table, &trigger_mask);
4294 timer = timer_table->timers[index];
4295 BUG_ON(!timer);
4296 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER,
4297 "Gen timer[%d] trigger\n", index);
4298 timer->trigger(timer->arg);
4299 }
4300}
7b6840ab
VT		 4301
4302/*
4303 * Primitive to disable ASPM
4304 */
4305void ath_pcie_aspm_disable(struct ath_softc *sc)
4306{
4307 struct pci_dev *pdev = to_pci_dev(sc->dev);
4308 u8 aspm;
4309
4310 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
4311 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
4312 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
4313}
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