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f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
394cf0a1 20#include "ath9k.h"
f078f209
LR		 21#include "initvals.h"
22
138ab2e4
VT		 23static int btcoex_enable;
24module_param(btcoex_enable, bool, 0);
25MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
4febf7b8
LR		 27#define ATH9K_CLOCK_RATE_CCK 22
28#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 30
cbe61d8a
S		 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 33 enum ath9k_ht_macmode macmode);
cbe61d8a 34static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072 35 struct ar5416_eeprom_def *pEepData,
f1dc5600 36 u32 reg, u32 value);
cbe61d8a
S		 37static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
f078f209 39
f1dc5600
S		 40/********************/
41/* Helper Functions */
42/********************/
f078f209 43
cbe61d8a 44static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
f1dc5600 45{
4febf7b8 46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 47
2660b81a 48 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
cbe61d8a 52
4febf7b8 53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 54}
f078f209 55
cbe61d8a 56static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
f1dc5600 57{
4febf7b8 58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 59
4febf7b8 60 if (conf_is_ht40(conf))
f1dc5600
S		 61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64}
f078f209 65
cbe61d8a 66static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 67{
4febf7b8 68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 69
2660b81a 70 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 75}
76
cbe61d8a 77static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 78{
4febf7b8 79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 80
4febf7b8 81 if (conf_is_ht40(conf))
f1dc5600
S		 82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85}
f078f209 86
fb4a3d35
GJ		 87/*
88 * Read and write, they both share the same lock. We do this to serialize
89 * reads and writes on Atheros 802.11n PCI devices only. This is required
90 * as the FIFO on these devices can only accept sanely 2 requests. After
91 * that the device goes bananas. Serializing the reads/writes prevents this
92 * from happening.
93 */
94
95void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
96{
97 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
98 unsigned long flags;
99 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
102 } else
103 iowrite32(val, ah->ah_sc->mem + reg_offset);
104}
105
106unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
107{
108 u32 val;
109 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
110 unsigned long flags;
111 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
114 } else
115 val = ioread32(ah->ah_sc->mem + reg_offset);
116 return val;
117}
118
0caa7b14 119bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 120{
121 int i;
122
0caa7b14
S		 123 BUG_ON(timeout < AH_TIME_QUANTUM);
124
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 126 if ((REG_READ(ah, reg) & mask) == val)
127 return true;
128
129 udelay(AH_TIME_QUANTUM);
130 }
04bd4638 131
d8baa939 132 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
0caa7b14
S		 133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 135
f1dc5600 136 return false;
f078f209
LR		 137}
138
139u32 ath9k_hw_reverse_bits(u32 val, u32 n)
140{
141 u32 retval;
142 int i;
143
144 for (i = 0, retval = 0; i < n; i++) {
145 retval = (retval << 1) | (val & 1);
146 val >>= 1;
147 }
148 return retval;
149}
150
cbe61d8a 151bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 152 u16 flags, u16 *low,
153 u16 *high)
f078f209 154{
2660b81a 155 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 156
f1dc5600
S		 157 if (flags & CHANNEL_5GHZ) {
158 *low = pCap->low_5ghz_chan;
159 *high = pCap->high_5ghz_chan;
160 return true;
f078f209 161 }
f1dc5600
S		 162 if ((flags & CHANNEL_2GHZ)) {
163 *low = pCap->low_2ghz_chan;
164 *high = pCap->high_2ghz_chan;
165 return true;
166 }
167 return false;
f078f209
LR		 168}
169
cbe61d8a 170u16 ath9k_hw_computetxtime(struct ath_hw *ah,
4f0fc7c3 171 const struct ath_rate_table *rates,
f1dc5600
S		 172 u32 frameLen, u16 rateix,
173 bool shortPreamble)
f078f209 174{
f1dc5600
S		 175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
176 u32 kbps;
f078f209 177
e63835b0 178 kbps = rates->info[rateix].ratekbps;
f078f209 179
f1dc5600
S		 180 if (kbps == 0)
181 return 0;
f078f209 182
f1dc5600 183 switch (rates->info[rateix].phy) {
46d14a58 184 case WLAN_RC_PHY_CCK:
f1dc5600 185 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
e63835b0 186 if (shortPreamble && rates->info[rateix].short_preamble)
f1dc5600
S		 187 phyTime >>= 1;
188 numBits = frameLen << 3;
189 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
190 break;
46d14a58 191 case WLAN_RC_PHY_OFDM:
2660b81a 192 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 193 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
194 numBits = OFDM_PLCP_BITS + (frameLen << 3);
195 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196 txTime = OFDM_SIFS_TIME_QUARTER
197 + OFDM_PREAMBLE_TIME_QUARTER
198 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 199 } else if (ah->curchan &&
200 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 201 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
202 numBits = OFDM_PLCP_BITS + (frameLen << 3);
203 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
204 txTime = OFDM_SIFS_TIME_HALF +
205 OFDM_PREAMBLE_TIME_HALF
206 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
207 } else {
208 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
209 numBits = OFDM_PLCP_BITS + (frameLen << 3);
210 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
212 + (numSymbols * OFDM_SYMBOL_TIME);
213 }
214 break;
215 default:
d8baa939 216 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 217 "Unknown phy %u (rate ix %u)\n",
f1dc5600
S		 218 rates->info[rateix].phy, rateix);
219 txTime = 0;
220 break;
221 }
f078f209 222
f1dc5600
S		 223 return txTime;
224}
f078f209 225
cbe61d8a 226void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 227 struct ath9k_channel *chan,
228 struct chan_centers *centers)
f078f209 229{
f1dc5600 230 int8_t extoff;
f078f209 231
f1dc5600
S		 232 if (!IS_CHAN_HT40(chan)) {
233 centers->ctl_center = centers->ext_center =
234 centers->synth_center = chan->channel;
235 return;
f078f209 236 }
f078f209 237
f1dc5600
S		 238 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
239 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
240 centers->synth_center =
241 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
242 extoff = 1;
243 } else {
244 centers->synth_center =
245 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
246 extoff = -1;
247 }
f078f209 248
f1dc5600
S		 249 centers->ctl_center =
250 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
251 centers->ext_center =
252 centers->synth_center + (extoff *
2660b81a 253 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
f1dc5600 254 HT40_CHANNEL_CENTER_SHIFT : 15));
f078f209
LR		 255}
256
f1dc5600
S		 257/******************/
258/* Chip Revisions */
259/******************/
260
cbe61d8a 261static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 262{
f1dc5600 263 u32 val;
f078f209 264
f1dc5600 265 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 266
f1dc5600
S		 267 if (val == 0xFF) {
268 val = REG_READ(ah, AR_SREV);
d535a42a
S		 269 ah->hw_version.macVersion =
270 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 272 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 273 } else {
274 if (!AR_SREV_9100(ah))
d535a42a 275 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 276
d535a42a 277 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 278
d535a42a 279 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 280 ah->is_pciexpress = true;
f1dc5600 281 }
f078f209
LR		 282}
283
cbe61d8a 284static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 285{
f1dc5600
S		 286 u32 val;
287 int i;
f078f209 288
f1dc5600 289 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 290
f1dc5600
S		 291 for (i = 0; i < 8; i++)
292 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
293 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
294 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 295
f1dc5600 296 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 297}
298
f1dc5600
S		 299/************************************/
300/* HW Attach, Detach, Init Routines */
301/************************************/
302
cbe61d8a 303static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 304{
feed029c 305 if (AR_SREV_9100(ah))
f1dc5600 306 return;
f078f209 307
f1dc5600
S		 308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 317
f1dc5600 318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 319}
320
cbe61d8a 321static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 322{
f1dc5600
S		 323 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
324 u32 regHold[2];
325 u32 patternData[4] = { 0x55555555,
326 0xaaaaaaaa,
327 0x66666666,
328 0x99999999 };
329 int i, j;
f078f209 330
f1dc5600
S		 331 for (i = 0; i < 2; i++) {
332 u32 addr = regAddr[i];
333 u32 wrData, rdData;
f078f209 334
f1dc5600
S		 335 regHold[i] = REG_READ(ah, addr);
336 for (j = 0; j < 0x100; j++) {
337 wrData = (j << 16) | j;
338 REG_WRITE(ah, addr, wrData);
339 rdData = REG_READ(ah, addr);
340 if (rdData != wrData) {
d8baa939 341 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 342 "address test failed "
f1dc5600 343 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 344 addr, wrData, rdData);
f1dc5600
S		 345 return false;
346 }
347 }
348 for (j = 0; j < 4; j++) {
349 wrData = patternData[j];
350 REG_WRITE(ah, addr, wrData);
351 rdData = REG_READ(ah, addr);
352 if (wrData != rdData) {
d8baa939 353 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 354 "address test failed "
f1dc5600 355 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 356 addr, wrData, rdData);
f1dc5600
S		 357 return false;
358 }
f078f209 359 }
f1dc5600 360 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 361 }
f1dc5600 362 udelay(100);
cbe61d8a 363
f078f209
LR		 364 return true;
365}
366
f1dc5600 367static const char *ath9k_hw_devname(u16 devid)
f078f209 368{
f1dc5600
S		 369 switch (devid) {
370 case AR5416_DEVID_PCI:
f1dc5600 371 return "Atheros 5416";
392dff83
BP		 372 case AR5416_DEVID_PCIE:
373 return "Atheros 5418";
f1dc5600
S		 374 case AR9160_DEVID_PCI:
375 return "Atheros 9160";
0c1aa495
GJ		 376 case AR5416_AR9100_DEVID:
377 return "Atheros 9100";
f1dc5600
S		 378 case AR9280_DEVID_PCI:
379 case AR9280_DEVID_PCIE:
380 return "Atheros 9280";
e7594072
SB		 381 case AR9285_DEVID_PCIE:
382 return "Atheros 9285";
ac88b6ec
VN		 383 case AR5416_DEVID_AR9287_PCI:
384 case AR5416_DEVID_AR9287_PCIE:
385 return "Atheros 9287";
f078f209
LR		 386 }
387
f1dc5600
S		 388 return NULL;
389}
f078f209 390
b8b0f377 391static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 392{
393 int i;
f078f209 394
2660b81a
S		 395 ah->config.dma_beacon_response_time = 2;
396 ah->config.sw_beacon_response_time = 10;
397 ah->config.additional_swba_backoff = 0;
398 ah->config.ack_6mb = 0x0;
399 ah->config.cwm_ignore_extcca = 0;
400 ah->config.pcie_powersave_enable = 0;
2660b81a 401 ah->config.pcie_clock_req = 0;
2660b81a
S		 402 ah->config.pcie_waen = 0;
403 ah->config.analog_shiftreg = 1;
404 ah->config.ht_enable = 1;
405 ah->config.ofdm_trig_low = 200;
406 ah->config.ofdm_trig_high = 500;
407 ah->config.cck_trig_high = 200;
408 ah->config.cck_trig_low = 100;
409 ah->config.enable_ani = 1;
1cf6873a 410 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
2660b81a 411 ah->config.antenna_switch_swap = 0;
f078f209 412
f1dc5600 413 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 414 ah->config.spurchans[i][0] = AR_NO_SPUR;
415 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 416 }
417
0ef1f168 418 ah->config.intr_mitigation = true;
6158425b
LR		 419
420 /*
421 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
422 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
423 * This means we use it for all AR5416 devices, and the few
424 * minor PCI AR9280 devices out there.
425 *
426 * Serialization is required because these devices do not handle
427 * well the case of two concurrent reads/writes due to the latency
428 * involved. During one read/write another read/write can be issued
429 * on another CPU while the previous read/write may still be working
430 * on our hardware, if we hit this case the hardware poops in a loop.
431 * We prevent this by serializing reads and writes.
432 *
433 * This issue is not present on PCI-Express devices or pre-AR5416
434 * devices (legacy, 802.11abg).
435 */
436 if (num_possible_cpus() > 1)
2d6a5e95 437 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 438}
439
50aca25b 440static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 441{
608b88cb
LR		 442 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
443
444 regulatory->country_code = CTRY_DEFAULT;
445 regulatory->power_limit = MAX_RATE_POWER;
446 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
447
d535a42a 448 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 449 ah->hw_version.subvendorid = 0;
f078f209
LR		 450
451 ah->ah_flags = 0;
8df5d1b7 452 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
d535a42a 453 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
f078f209
LR		 454 if (!AR_SREV_9100(ah))
455 ah->ah_flags = AH_USE_EEPROM;
456
2660b81a 457 ah->atim_window = 0;
2660b81a
S		 458 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
459 ah->beacon_interval = 100;
460 ah->enable_32kHz_clock = DONT_USE_32KHZ;
461 ah->slottime = (u32) -1;
462 ah->acktimeout = (u32) -1;
463 ah->ctstimeout = (u32) -1;
464 ah->globaltxtimeout = (u32) -1;
465
466 ah->gbeacon_rate = 0;
f078f209 467
cbdec975 468 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 469}
470
cbe61d8a 471static int ath9k_hw_rfattach(struct ath_hw *ah)
f078f209 472{
f1dc5600
S		 473 bool rfStatus = false;
474 int ecode = 0;
f078f209 475
f1dc5600
S		 476 rfStatus = ath9k_hw_init_rf(ah, &ecode);
477 if (!rfStatus) {
d8baa939
S		 478 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
479 "RF setup failed, status: %u\n", ecode);
f1dc5600
S		 480 return ecode;
481 }
f078f209 482
f1dc5600 483 return 0;
f078f209
LR		 484}
485
cbe61d8a 486static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 487{
f1dc5600
S		 488 u32 val;
489
490 REG_WRITE(ah, AR_PHY(0), 0x00000007);
491
492 val = ath9k_hw_get_radiorev(ah);
493 switch (val & AR_RADIO_SREV_MAJOR) {
494 case 0:
495 val = AR_RAD5133_SREV_MAJOR;
496 break;
497 case AR_RAD5133_SREV_MAJOR:
498 case AR_RAD5122_SREV_MAJOR:
499 case AR_RAD2133_SREV_MAJOR:
500 case AR_RAD2122_SREV_MAJOR:
501 break;
f078f209 502 default:
d8baa939
S		 503 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
504 "Radio Chip Rev 0x%02X not supported\n",
505 val & AR_RADIO_SREV_MAJOR);
f1dc5600 506 return -EOPNOTSUPP;
f078f209 507 }
f078f209 508
d535a42a 509 ah->hw_version.analog5GhzRev = val;
f078f209 510
f1dc5600 511 return 0;
f078f209
LR		 512}
513
cbe61d8a 514static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209
LR		 515{
516 u32 sum;
517 int i;
518 u16 eeval;
f078f209
LR		 519
520 sum = 0;
521 for (i = 0; i < 3; i++) {
f74df6fb 522 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 523 sum += eeval;
ba52da58
S		 524 ah->macaddr[2 * i] = eeval >> 8;
525 ah->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 526 }
d8baa939 527 if (sum == 0 || sum == 0xffff * 3)
f078f209 528 return -EADDRNOTAVAIL;
f078f209
LR		 529
530 return 0;
531}
532
cbe61d8a 533static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 534{
535 u32 rxgain_type;
9f804202 536
f74df6fb
S		 537 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
538 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 539
540 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 541 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 542 ar9280Modes_backoff_13db_rxgain_9280_2,
543 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
544 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 545 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 546 ar9280Modes_backoff_23db_rxgain_9280_2,
547 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
548 else
2660b81a 549 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 550 ar9280Modes_original_rxgain_9280_2,
551 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 552 } else {
2660b81a 553 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 554 ar9280Modes_original_rxgain_9280_2,
555 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 556 }
9f804202
SB		 557}
558
cbe61d8a 559static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 560{
561 u32 txgain_type;
9f804202 562
f74df6fb
S		 563 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
564 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 565
566 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 567 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 568 ar9280Modes_high_power_tx_gain_9280_2,
569 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
570 else
2660b81a 571 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 572 ar9280Modes_original_tx_gain_9280_2,
573 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 574 } else {
2660b81a 575 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 576 ar9280Modes_original_tx_gain_9280_2,
577 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 578 }
9f804202
SB		 579}
580
f637cfd6 581static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 582{
f1dc5600 583 int ecode;
f078f209 584
d8baa939 585 if (!ath9k_hw_chip_test(ah))
f1dc5600 586 return -ENODEV;
f078f209 587
f1dc5600
S		 588 ecode = ath9k_hw_rf_claim(ah);
589 if (ecode != 0)
f078f209 590 return ecode;
f078f209 591
f637cfd6 592 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 593 if (ecode != 0)
594 return ecode;
7d01b221
S		 595
596 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
597 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
598
f1dc5600
S		 599 ecode = ath9k_hw_rfattach(ah);
600 if (ecode != 0)
601 return ecode;
f078f209 602
f1dc5600
S		 603 if (!AR_SREV_9100(ah)) {
604 ath9k_hw_ani_setup(ah);
f637cfd6 605 ath9k_hw_ani_init(ah);
f078f209
LR		 606 }
607
f078f209
LR		 608 return 0;
609}
610
ee2bb460
LR		 611static bool ath9k_hw_devid_supported(u16 devid)
612{
613 switch (devid) {
614 case AR5416_DEVID_PCI:
615 case AR5416_DEVID_PCIE:
616 case AR5416_AR9100_DEVID:
617 case AR9160_DEVID_PCI:
618 case AR9280_DEVID_PCI:
619 case AR9280_DEVID_PCIE:
620 case AR9285_DEVID_PCIE:
621 case AR5416_DEVID_AR9287_PCI:
622 case AR5416_DEVID_AR9287_PCIE:
623 return true;
624 default:
625 break;
626 }
627 return false;
628}
629
f9d4a668
LR		 630static bool ath9k_hw_macversion_supported(u32 macversion)
631{
632 switch (macversion) {
633 case AR_SREV_VERSION_5416_PCI:
634 case AR_SREV_VERSION_5416_PCIE:
635 case AR_SREV_VERSION_9160:
636 case AR_SREV_VERSION_9100:
637 case AR_SREV_VERSION_9280:
638 case AR_SREV_VERSION_9285:
639 case AR_SREV_VERSION_9287:
640 return true;
d7e7d229
LR		 641 /* Not yet */
642 case AR_SREV_VERSION_9271:
f9d4a668
LR		 643 default:
644 break;
645 }
646 return false;
647}
648
aa4058ae 649static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
f078f209 650{
f1dc5600
S		 651 if (AR_SREV_9160_10_OR_LATER(ah)) {
652 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a
S		 653 ah->iq_caldata.calData = &iq_cal_single_sample;
654 ah->adcgain_caldata.calData =
f1dc5600 655 &adc_gain_cal_single_sample;
2660b81a 656 ah->adcdc_caldata.calData =
f1dc5600 657 &adc_dc_cal_single_sample;
2660b81a 658 ah->adcdc_calinitdata.calData =
f1dc5600
S		 659 &adc_init_dc_cal;
660 } else {
2660b81a
S		 661 ah->iq_caldata.calData = &iq_cal_multi_sample;
662 ah->adcgain_caldata.calData =
f1dc5600 663 &adc_gain_cal_multi_sample;
2660b81a 664 ah->adcdc_caldata.calData =
f1dc5600 665 &adc_dc_cal_multi_sample;
2660b81a 666 ah->adcdc_calinitdata.calData =
f1dc5600
S		 667 &adc_init_dc_cal;
668 }
2660b81a 669 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
f1dc5600 670 }
aa4058ae 671}
f078f209 672
aa4058ae
LR		 673static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
674{
d7e7d229
LR		 675 if (AR_SREV_9271(ah)) {
676 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
677 ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
678 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
679 ARRAY_SIZE(ar9271Common_9271_1_0), 2);
680 return;
681 }
682
ac88b6ec
VN		 683 if (AR_SREV_9287_11_OR_LATER(ah)) {
684 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
685 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
686 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
687 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
688 if (ah->config.pcie_clock_req)
689 INIT_INI_ARRAY(&ah->iniPcieSerdes,
690 ar9287PciePhy_clkreq_off_L1_9287_1_1,
691 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
692 else
693 INIT_INI_ARRAY(&ah->iniPcieSerdes,
694 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
695 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
696 2);
697 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
698 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
699 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
700 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
701 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
702
703 if (ah->config.pcie_clock_req)
704 INIT_INI_ARRAY(&ah->iniPcieSerdes,
705 ar9287PciePhy_clkreq_off_L1_9287_1_0,
706 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
707 else
708 INIT_INI_ARRAY(&ah->iniPcieSerdes,
709 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
710 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
711 2);
712 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
f078f209 713
4e845168 714
2660b81a 715 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
e7594072 716 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
2660b81a 717 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
e7594072
SB		 718 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
719
2660b81a
S		 720 if (ah->config.pcie_clock_req) {
721 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 722 ar9285PciePhy_clkreq_off_L1_9285_1_2,
723 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
724 } else {
2660b81a 725 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 726 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
727 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
728 2);
729 }
730 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
2660b81a 731 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
e7594072 732 ARRAY_SIZE(ar9285Modes_9285), 6);
2660b81a 733 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
e7594072
SB		 734 ARRAY_SIZE(ar9285Common_9285), 2);
735
2660b81a
S		 736 if (ah->config.pcie_clock_req) {
737 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 738 ar9285PciePhy_clkreq_off_L1_9285,
739 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
740 } else {
2660b81a 741 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 742 ar9285PciePhy_clkreq_always_on_L1_9285,
743 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
744 }
745 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a 746 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
f1dc5600 747 ARRAY_SIZE(ar9280Modes_9280_2), 6);
2660b81a 748 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
f1dc5600 749 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 750
2660b81a
S		 751 if (ah->config.pcie_clock_req) {
752 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 753 ar9280PciePhy_clkreq_off_L1_9280,
754 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
755 } else {
2660b81a 756 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 757 ar9280PciePhy_clkreq_always_on_L1_9280,
758 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
759 }
2660b81a 760 INIT_INI_ARRAY(&ah->iniModesAdditional,
f1dc5600
S		 761 ar9280Modes_fast_clock_9280_2,
762 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
763 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 764 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
f1dc5600 765 ARRAY_SIZE(ar9280Modes_9280), 6);
2660b81a 766 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
f1dc5600
S		 767 ARRAY_SIZE(ar9280Common_9280), 2);
768 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2660b81a 769 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
f1dc5600 770 ARRAY_SIZE(ar5416Modes_9160), 6);
2660b81a 771 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
f1dc5600 772 ARRAY_SIZE(ar5416Common_9160), 2);
2660b81a 773 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
f1dc5600 774 ARRAY_SIZE(ar5416Bank0_9160), 2);
2660b81a 775 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
f1dc5600 776 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
2660b81a 777 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
f1dc5600 778 ARRAY_SIZE(ar5416Bank1_9160), 2);
2660b81a 779 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
f1dc5600 780 ARRAY_SIZE(ar5416Bank2_9160), 2);
2660b81a 781 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
f1dc5600 782 ARRAY_SIZE(ar5416Bank3_9160), 3);
2660b81a 783 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
f1dc5600 784 ARRAY_SIZE(ar5416Bank6_9160), 3);
2660b81a 785 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
f1dc5600 786 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
2660b81a 787 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
f1dc5600
S		 788 ARRAY_SIZE(ar5416Bank7_9160), 2);
789 if (AR_SREV_9160_11(ah)) {
2660b81a 790 INIT_INI_ARRAY(&ah->iniAddac,
f1dc5600
S		 791 ar5416Addac_91601_1,
792 ARRAY_SIZE(ar5416Addac_91601_1), 2);
793 } else {
2660b81a 794 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
f1dc5600
S		 795 ARRAY_SIZE(ar5416Addac_9160), 2);
796 }
797 } else if (AR_SREV_9100_OR_LATER(ah)) {
2660b81a 798 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
f1dc5600 799 ARRAY_SIZE(ar5416Modes_9100), 6);
2660b81a 800 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
f1dc5600 801 ARRAY_SIZE(ar5416Common_9100), 2);
2660b81a 802 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
f1dc5600 803 ARRAY_SIZE(ar5416Bank0_9100), 2);
2660b81a 804 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
f1dc5600 805 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
2660b81a 806 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
f1dc5600 807 ARRAY_SIZE(ar5416Bank1_9100), 2);
2660b81a 808 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
f1dc5600 809 ARRAY_SIZE(ar5416Bank2_9100), 2);
2660b81a 810 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
f1dc5600 811 ARRAY_SIZE(ar5416Bank3_9100), 3);
2660b81a 812 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
f1dc5600 813 ARRAY_SIZE(ar5416Bank6_9100), 3);
2660b81a 814 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
f1dc5600 815 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
2660b81a 816 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
f1dc5600 817 ARRAY_SIZE(ar5416Bank7_9100), 2);
2660b81a 818 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
f1dc5600
S		 819 ARRAY_SIZE(ar5416Addac_9100), 2);
820 } else {
2660b81a 821 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
f1dc5600 822 ARRAY_SIZE(ar5416Modes), 6);
2660b81a 823 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
f1dc5600 824 ARRAY_SIZE(ar5416Common), 2);
2660b81a 825 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
f1dc5600 826 ARRAY_SIZE(ar5416Bank0), 2);
2660b81a 827 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
f1dc5600 828 ARRAY_SIZE(ar5416BB_RfGain), 3);
2660b81a 829 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
f1dc5600 830 ARRAY_SIZE(ar5416Bank1), 2);
2660b81a 831 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
f1dc5600 832 ARRAY_SIZE(ar5416Bank2), 2);
2660b81a 833 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
f1dc5600 834 ARRAY_SIZE(ar5416Bank3), 3);
2660b81a 835 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
f1dc5600 836 ARRAY_SIZE(ar5416Bank6), 3);
2660b81a 837 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
f1dc5600 838 ARRAY_SIZE(ar5416Bank6TPC), 3);
2660b81a 839 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
f1dc5600 840 ARRAY_SIZE(ar5416Bank7), 2);
2660b81a 841 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
f1dc5600 842 ARRAY_SIZE(ar5416Addac), 2);
f078f209 843 }
aa4058ae 844}
f078f209 845
aa4058ae
LR		 846static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
847{
ac88b6ec
VN		 848 if (AR_SREV_9287_11(ah))
849 INIT_INI_ARRAY(&ah->iniModesRxGain,
850 ar9287Modes_rx_gain_9287_1_1,
851 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
852 else if (AR_SREV_9287_10(ah))
853 INIT_INI_ARRAY(&ah->iniModesRxGain,
854 ar9287Modes_rx_gain_9287_1_0,
855 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
856 else if (AR_SREV_9280_20(ah))
857 ath9k_hw_init_rxgain_ini(ah);
858
859 if (AR_SREV_9287_11(ah)) {
860 INIT_INI_ARRAY(&ah->iniModesTxGain,
861 ar9287Modes_tx_gain_9287_1_1,
862 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
863 } else if (AR_SREV_9287_10(ah)) {
864 INIT_INI_ARRAY(&ah->iniModesTxGain,
865 ar9287Modes_tx_gain_9287_1_0,
866 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
867 } else if (AR_SREV_9280_20(ah)) {
868 ath9k_hw_init_txgain_ini(ah);
869 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4e845168
SB		 870 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
871
872 /* txgain table */
873 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
874 INIT_INI_ARRAY(&ah->iniModesTxGain,
875 ar9285Modes_high_power_tx_gain_9285_1_2,
876 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
877 } else {
878 INIT_INI_ARRAY(&ah->iniModesTxGain,
879 ar9285Modes_original_tx_gain_9285_1_2,
880 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
881 }
882
883 }
aa4058ae 884}
4e845168 885
aa4058ae
LR		 886static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
887{
888 u32 i, j;
06d0f066
S		 889
890 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
891 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
892
893 /* EEPROM Fixup */
2660b81a
S		 894 for (i = 0; i < ah->iniModes.ia_rows; i++) {
895 u32 reg = INI_RA(&ah->iniModes, i, 0);
f078f209 896
2660b81a
S		 897 for (j = 1; j < ah->iniModes.ia_columns; j++) {
898 u32 val = INI_RA(&ah->iniModes, i, j);
f078f209 899
2660b81a 900 INI_RA(&ah->iniModes, i, j) =
e7594072 901 ath9k_hw_ini_fixup(ah,
2660b81a 902 &ah->eeprom.def,
f1dc5600
S		 903 reg, val);
904 }
f078f209 905 }
f1dc5600 906 }
aa4058ae
LR		 907}
908
f637cfd6 909int ath9k_hw_init(struct ath_hw *ah)
aa4058ae 910{
95fafca2 911 int r = 0;
aa4058ae 912
95fafca2
LR		 913 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
914 return -EOPNOTSUPP;
aa4058ae
LR		 915
916 ath9k_hw_init_defaults(ah);
917 ath9k_hw_init_config(ah);
918
919 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
920 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
95fafca2 921 return -EIO;
aa4058ae
LR		 922 }
923
924 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
925 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 926 return -EIO;
aa4058ae
LR		 927 }
928
929 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
930 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
931 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
932 ah->config.serialize_regmode =
933 SER_REG_MODE_ON;
934 } else {
935 ah->config.serialize_regmode =
936 SER_REG_MODE_OFF;
937 }
938 }
939
940 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
941 ah->config.serialize_regmode);
942
943 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
944 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
945 "Mac Chip Rev 0x%02x.%x is not supported by "
946 "this driver\n", ah->hw_version.macVersion,
947 ah->hw_version.macRev);
95fafca2 948 return -EOPNOTSUPP;
aa4058ae
LR		 949 }
950
951 if (AR_SREV_9100(ah)) {
952 ah->iq_caldata.calData = &iq_cal_multi_sample;
953 ah->supp_cals = IQ_MISMATCH_CAL;
954 ah->is_pciexpress = false;
955 }
d7e7d229
LR		 956
957 if (AR_SREV_9271(ah))
958 ah->is_pciexpress = false;
959
aa4058ae
LR		 960 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
961
962 ath9k_hw_init_cal_settings(ah);
963
964 ah->ani_function = ATH9K_ANI_ALL;
965 if (AR_SREV_9280_10_OR_LATER(ah))
966 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
967
968 ath9k_hw_init_mode_regs(ah);
969
970 if (ah->is_pciexpress)
971 ath9k_hw_configpcipowersave(ah, 0);
972 else
973 ath9k_hw_disablepcie(ah);
974
f637cfd6 975 r = ath9k_hw_post_init(ah);
aa4058ae 976 if (r)
95fafca2 977 return r;
aa4058ae
LR		 978
979 ath9k_hw_init_mode_gain_regs(ah);
980 ath9k_hw_fill_cap_info(ah);
981 ath9k_hw_init_11a_eeprom_fix(ah);
f6688cd8 982
4f3acf81
LR		 983 r = ath9k_hw_init_macaddr(ah);
984 if (r) {
07c10c61 985 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
d8baa939 986 "Failed to initialize MAC address\n");
95fafca2 987 return r;
f078f209
LR		 988 }
989
d7e7d229 990 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 991 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 992 else
2660b81a 993 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 994
f1dc5600 995 ath9k_init_nfcal_hist_buffer(ah);
f078f209 996
4f3acf81 997 return 0;
f078f209
LR		 998}
999
cbe61d8a 1000static void ath9k_hw_init_bb(struct ath_hw *ah,
f1dc5600 1001 struct ath9k_channel *chan)
f078f209 1002{
f1dc5600 1003 u32 synthDelay;
f078f209 1004
f1dc5600 1005 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1006 if (IS_CHAN_B(chan))
f1dc5600
S		 1007 synthDelay = (4 * synthDelay) / 22;
1008 else
1009 synthDelay /= 10;
f078f209 1010
f1dc5600 1011 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 1012
f1dc5600 1013 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 1014}
1015
cbe61d8a 1016static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 1017{
f1dc5600
S		 1018 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1019 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 1020
f1dc5600
S		 1021 REG_WRITE(ah, AR_QOS_NO_ACK,
1022 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1023 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1024 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1025
1026 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1027 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1028 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1029 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1030 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 1031}
1032
cbe61d8a 1033static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 1034 struct ath9k_channel *chan)
f078f209 1035{
f1dc5600 1036 u32 pll;
f078f209 1037
f1dc5600
S		 1038 if (AR_SREV_9100(ah)) {
1039 if (chan && IS_CHAN_5GHZ(chan))
1040 pll = 0x1450;
f078f209 1041 else
f1dc5600
S		 1042 pll = 0x1458;
1043 } else {
1044 if (AR_SREV_9280_10_OR_LATER(ah)) {
1045 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1046
f1dc5600
S		 1047 if (chan && IS_CHAN_HALF_RATE(chan))
1048 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1049 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1050 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1051
f1dc5600
S		 1052 if (chan && IS_CHAN_5GHZ(chan)) {
1053 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 1054
f078f209 1055
f1dc5600
S		 1056 if (AR_SREV_9280_20(ah)) {
1057 if (((chan->channel % 20) == 0)
1058 || ((chan->channel % 10) == 0))
1059 pll = 0x2850;
1060 else
1061 pll = 0x142c;
1062 }
1063 } else {
1064 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1065 }
f078f209 1066
f1dc5600 1067 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 1068
f1dc5600 1069 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1070
f1dc5600
S		 1071 if (chan && IS_CHAN_HALF_RATE(chan))
1072 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1073 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1074 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1075
f1dc5600
S		 1076 if (chan && IS_CHAN_5GHZ(chan))
1077 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1078 else
1079 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1080 } else {
1081 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 1082
f1dc5600
S		 1083 if (chan && IS_CHAN_HALF_RATE(chan))
1084 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1085 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1086 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 1087
f1dc5600
S		 1088 if (chan && IS_CHAN_5GHZ(chan))
1089 pll |= SM(0xa, AR_RTC_PLL_DIV);
1090 else
1091 pll |= SM(0xb, AR_RTC_PLL_DIV);
1092 }
1093 }
d03a66c1 1094 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 1095
f1dc5600
S		 1096 udelay(RTC_PLL_SETTLE_DELAY);
1097
1098 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1099}
1100
cbe61d8a 1101static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
f078f209 1102{
f078f209
LR		 1103 int rx_chainmask, tx_chainmask;
1104
2660b81a
S		 1105 rx_chainmask = ah->rxchainmask;
1106 tx_chainmask = ah->txchainmask;
f078f209
LR		 1107
1108 switch (rx_chainmask) {
1109 case 0x5:
1110 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1111 AR_PHY_SWAP_ALT_CHAIN);
1112 case 0x3:
d535a42a 1113 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
f078f209
LR		 1114 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1115 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1116 break;
1117 }
1118 case 0x1:
1119 case 0x2:
f078f209
LR		 1120 case 0x7:
1121 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1122 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1123 break;
1124 default:
1125 break;
1126 }
1127
1128 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1129 if (tx_chainmask == 0x5) {
1130 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1131 AR_PHY_SWAP_ALT_CHAIN);
1132 }
1133 if (AR_SREV_9100(ah))
1134 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1135 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1136}
1137
cbe61d8a 1138static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 1139 enum nl80211_iftype opmode)
f078f209 1140{
2660b81a 1141 ah->mask_reg = AR_IMR_TXERR |
f1dc5600
S		 1142 AR_IMR_TXURN |
1143 AR_IMR_RXERR |
1144 AR_IMR_RXORN |
1145 AR_IMR_BCNMISC;
f078f209 1146
0ef1f168 1147 if (ah->config.intr_mitigation)
2660b81a 1148 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1149 else
2660b81a 1150 ah->mask_reg |= AR_IMR_RXOK;
f078f209 1151
2660b81a 1152 ah->mask_reg |= AR_IMR_TXOK;
f078f209 1153
d97809db 1154 if (opmode == NL80211_IFTYPE_AP)
2660b81a 1155 ah->mask_reg |= AR_IMR_MIB;
f078f209 1156
2660b81a 1157 REG_WRITE(ah, AR_IMR, ah->mask_reg);
f1dc5600 1158 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1159
f1dc5600
S		 1160 if (!AR_SREV_9100(ah)) {
1161 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1162 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1163 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1164 }
f078f209
LR		 1165}
1166
cbe61d8a 1167static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1168{
f078f209 1169 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
04bd4638 1170 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
2660b81a 1171 ah->acktimeout = (u32) -1;
f078f209
LR		 1172 return false;
1173 } else {
1174 REG_RMW_FIELD(ah, AR_TIME_OUT,
1175 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1176 ah->acktimeout = us;
f078f209
LR		 1177 return true;
1178 }
1179}
1180
cbe61d8a 1181static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
f078f209 1182{
f078f209 1183 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
04bd4638 1184 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
2660b81a 1185 ah->ctstimeout = (u32) -1;
f078f209
LR		 1186 return false;
1187 } else {
1188 REG_RMW_FIELD(ah, AR_TIME_OUT,
1189 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1190 ah->ctstimeout = us;
f078f209
LR		 1191 return true;
1192 }
1193}
f1dc5600 1194
cbe61d8a 1195static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1196{
f078f209
LR		 1197 if (tu > 0xFFFF) {
1198 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
04bd4638 1199 "bad global tx timeout %u\n", tu);
2660b81a 1200 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1201 return false;
1202 } else {
1203 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1204 ah->globaltxtimeout = tu;
f078f209
LR		 1205 return true;
1206 }
1207}
1208
cbe61d8a 1209static void ath9k_hw_init_user_settings(struct ath_hw *ah)
f078f209 1210{
2660b81a
S		 1211 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1212 ah->misc_mode);
f078f209 1213
2660b81a 1214 if (ah->misc_mode != 0)
f1dc5600 1215 REG_WRITE(ah, AR_PCU_MISC,
2660b81a
S		 1216 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1217 if (ah->slottime != (u32) -1)
1218 ath9k_hw_setslottime(ah, ah->slottime);
1219 if (ah->acktimeout != (u32) -1)
1220 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1221 if (ah->ctstimeout != (u32) -1)
1222 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1223 if (ah->globaltxtimeout != (u32) -1)
1224 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600
S		 1225}
1226
1227const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1228{
1229 return vendorid == ATHEROS_VENDOR_ID ?
1230 ath9k_hw_devname(devid) : NULL;
1231}
1232
cbe61d8a 1233void ath9k_hw_detach(struct ath_hw *ah)
f1dc5600
S		 1234{
1235 if (!AR_SREV_9100(ah))
e70c0cfd 1236 ath9k_hw_ani_disable(ah);
f1dc5600 1237
081b35ab 1238 ath9k_hw_rf_free(ah);
f1dc5600
S		 1239 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1240 kfree(ah);
9db6b6a2 1241 ah = NULL;
f1dc5600
S		 1242}
1243
f1dc5600
S		 1244/*******/
1245/* INI */
1246/*******/
1247
cbe61d8a 1248static void ath9k_hw_override_ini(struct ath_hw *ah,
f1dc5600
S		 1249 struct ath9k_channel *chan)
1250{
d7e7d229
LR		 1251 u32 val;
1252
1253 if (AR_SREV_9271(ah)) {
1254 /*
1255 * Enable spectral scan to solution for issues with stuck
1256 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1257 * AR9271 1.1
1258 */
1259 if (AR_SREV_9271_10(ah)) {
1260 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1261 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1262 }
1263 else if (AR_SREV_9271_11(ah))
1264 /*
1265 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1266 * present on AR9271 1.1
1267 */
1268 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1269 return;
1270 }
1271
8aa15e15
SB		 1272 /*
1273 * Set the RX_ABORT and RX_DIS and clear if off only after
1274 * RXE is set for MAC. This prevents frames with corrupted
1275 * descriptor status.
1276 */
1277 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1278
1279
a8c96d3b 1280 if (!AR_SREV_5416_20_OR_LATER(ah) ||
f1dc5600
S		 1281 AR_SREV_9280_10_OR_LATER(ah))
1282 return;
d7e7d229
LR		 1283 /*
1284 * Disable BB clock gating
1285 * Necessary to avoid issues on AR5416 2.0
1286 */
f1dc5600 1287 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1288}
1289
cbe61d8a 1290static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
e7594072 1291 struct ar5416_eeprom_def *pEepData,
f1dc5600 1292 u32 reg, u32 value)
f078f209 1293{
f1dc5600 1294 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
f078f209 1295
d535a42a 1296 switch (ah->hw_version.devid) {
f1dc5600
S		 1297 case AR9280_DEVID_PCI:
1298 if (reg == 0x7894) {
d8baa939 1299 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
f1dc5600
S		 1300 "ini VAL: %x EEPROM: %x\n", value,
1301 (pBase->version & 0xff));
1302
1303 if ((pBase->version & 0xff) > 0x0a) {
d8baa939 1304 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
f1dc5600
S		 1305 "PWDCLKIND: %d\n",
1306 pBase->pwdclkind);
1307 value &= ~AR_AN_TOP2_PWDCLKIND;
1308 value |= AR_AN_TOP2_PWDCLKIND &
1309 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1310 } else {
d8baa939 1311 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
f1dc5600
S		 1312 "PWDCLKIND Earlier Rev\n");
1313 }
1314
d8baa939 1315 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
f1dc5600
S		 1316 "final ini VAL: %x\n", value);
1317 }
1318 break;
1319 }
1320
1321 return value;
f078f209
LR		 1322}
1323
cbe61d8a 1324static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072
SB		 1325 struct ar5416_eeprom_def *pEepData,
1326 u32 reg, u32 value)
1327{
2660b81a 1328 if (ah->eep_map == EEP_MAP_4KBITS)
e7594072
SB		 1329 return value;
1330 else
1331 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1332}
1333
8bd1d07f
SB		 1334static void ath9k_olc_init(struct ath_hw *ah)
1335{
1336 u32 i;
1337
db91f2e4
VN		 1338 if (OLC_FOR_AR9287_10_LATER) {
1339 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1340 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1341 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1342 AR9287_AN_TXPC0_TXPCMODE,
1343 AR9287_AN_TXPC0_TXPCMODE_S,
1344 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1345 udelay(100);
1346 } else {
1347 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1348 ah->originalGain[i] =
1349 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1350 AR_PHY_TX_GAIN);
1351 ah->PDADCdelta = 0;
1352 }
8bd1d07f
SB		 1353}
1354
3a702e49
BC		 1355static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1356 struct ath9k_channel *chan)
1357{
1358 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1359
1360 if (IS_CHAN_B(chan))
1361 ctl |= CTL_11B;
1362 else if (IS_CHAN_G(chan))
1363 ctl |= CTL_11G;
1364 else
1365 ctl |= CTL_11A;
1366
1367 return ctl;
1368}
1369
cbe61d8a 1370static int ath9k_hw_process_ini(struct ath_hw *ah,
f1dc5600
S		 1371 struct ath9k_channel *chan,
1372 enum ath9k_ht_macmode macmode)
f078f209 1373{
608b88cb 1374 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f078f209 1375 int i, regWrites = 0;
5f8e077c 1376 struct ieee80211_channel *channel = chan->chan;
f078f209 1377 u32 modesIndex, freqIndex;
f078f209
LR		 1378
1379 switch (chan->chanmode) {
1380 case CHANNEL_A:
1381 case CHANNEL_A_HT20:
1382 modesIndex = 1;
1383 freqIndex = 1;
1384 break;
1385 case CHANNEL_A_HT40PLUS:
1386 case CHANNEL_A_HT40MINUS:
1387 modesIndex = 2;
1388 freqIndex = 1;
1389 break;
1390 case CHANNEL_G:
1391 case CHANNEL_G_HT20:
1392 case CHANNEL_B:
1393 modesIndex = 4;
1394 freqIndex = 2;
1395 break;
1396 case CHANNEL_G_HT40PLUS:
1397 case CHANNEL_G_HT40MINUS:
1398 modesIndex = 3;
1399 freqIndex = 2;
1400 break;
1401
1402 default:
1403 return -EINVAL;
1404 }
1405
1406 REG_WRITE(ah, AR_PHY(0), 0x00000007);
f078f209 1407 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
f74df6fb 1408 ah->eep_ops->set_addac(ah, chan);
f078f209 1409
a8c96d3b 1410 if (AR_SREV_5416_22_OR_LATER(ah)) {
2660b81a 1411 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
f078f209
LR		 1412 } else {
1413 struct ar5416IniArray temp;
1414 u32 addacSize =
2660b81a
S		 1415 sizeof(u32) * ah->iniAddac.ia_rows *
1416 ah->iniAddac.ia_columns;
f078f209 1417
2660b81a
S		 1418 memcpy(ah->addac5416_21,
1419 ah->iniAddac.ia_array, addacSize);
f078f209 1420
2660b81a 1421 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
f078f209 1422
2660b81a
S		 1423 temp.ia_array = ah->addac5416_21;
1424 temp.ia_columns = ah->iniAddac.ia_columns;
1425 temp.ia_rows = ah->iniAddac.ia_rows;
f078f209
LR		 1426 REG_WRITE_ARRAY(&temp, 1, regWrites);
1427 }
f1dc5600 1428
f078f209
LR		 1429 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1430
2660b81a
S		 1431 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1432 u32 reg = INI_RA(&ah->iniModes, i, 0);
1433 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
f078f209 1434
f078f209
LR		 1435 REG_WRITE(ah, reg, val);
1436
1437 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1438 && ah->config.analog_shiftreg) {
f078f209
LR		 1439 udelay(100);
1440 }
1441
1442 DO_DELAY(regWrites);
1443 }
1444
ac88b6ec 1445 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1446 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
9f804202 1447
ac88b6ec
VN		 1448 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1449 AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1450 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
9f804202 1451
2660b81a
S		 1452 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1453 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1454 u32 val = INI_RA(&ah->iniCommon, i, 1);
f078f209
LR		 1455
1456 REG_WRITE(ah, reg, val);
1457
1458 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1459 && ah->config.analog_shiftreg) {
f078f209
LR		 1460 udelay(100);
1461 }
1462
1463 DO_DELAY(regWrites);
1464 }
1465
1466 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1467
1468 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
2660b81a 1469 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
f078f209
LR		 1470 regWrites);
1471 }
1472
1473 ath9k_hw_override_ini(ah, chan);
1474 ath9k_hw_set_regs(ah, chan, macmode);
1475 ath9k_hw_init_chain_masks(ah);
1476
8bd1d07f
SB		 1477 if (OLC_FOR_AR9280_20_LATER)
1478 ath9k_olc_init(ah);
1479
8fbff4b8 1480 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1481 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 1482 channel->max_antenna_gain * 2,
1483 channel->max_power * 2,
1484 min((u32) MAX_RATE_POWER,
608b88cb 1485 (u32) regulatory->power_limit));
f078f209
LR		 1486
1487 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
d8baa939 1488 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 1489 "ar5416SetRfRegs failed\n");
f078f209
LR		 1490 return -EIO;
1491 }
1492
1493 return 0;
1494}
1495
f1dc5600
S		 1496/****************************************/
1497/* Reset and Channel Switching Routines */
1498/****************************************/
1499
cbe61d8a 1500static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1501{
f1dc5600
S		 1502 u32 rfMode = 0;
1503
1504 if (chan == NULL)
1505 return;
1506
1507 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1508 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1509
1510 if (!AR_SREV_9280_10_OR_LATER(ah))
1511 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1512 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1513
1514 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1515 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1516
1517 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1518}
1519
cbe61d8a 1520static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
f1dc5600
S		 1521{
1522 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1523}
1524
cbe61d8a 1525static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 1526{
1527 u32 regval;
1528
d7e7d229
LR		 1529 /*
1530 * set AHB_MODE not to do cacheline prefetches
1531 */
f1dc5600
S		 1532 regval = REG_READ(ah, AR_AHB_MODE);
1533 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1534
d7e7d229
LR		 1535 /*
1536 * let mac dma reads be in 128 byte chunks
1537 */
f1dc5600
S		 1538 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1539 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1540
d7e7d229
LR		 1541 /*
1542 * Restore TX Trigger Level to its pre-reset value.
1543 * The initial value depends on whether aggregation is enabled, and is
1544 * adjusted whenever underruns are detected.
1545 */
2660b81a 1546 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1547
d7e7d229
LR		 1548 /*
1549 * let mac dma writes be in 128 byte chunks
1550 */
f1dc5600
S		 1551 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1552 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1553
d7e7d229
LR		 1554 /*
1555 * Setup receive FIFO threshold to hold off TX activities
1556 */
f1dc5600
S		 1557 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1558
d7e7d229
LR		 1559 /*
1560 * reduce the number of usable entries in PCU TXBUF to avoid
1561 * wrap around issues.
1562 */
f1dc5600 1563 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1564 /* For AR9285 the number of Fifos are reduced to half.
1565 * So set the usable tx buf size also to half to
1566 * avoid data/delimiter underruns
1567 */
f1dc5600
S		 1568 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1569 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1570 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1571 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1572 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1573 }
1574}
1575
cbe61d8a 1576static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1577{
1578 u32 val;
1579
1580 val = REG_READ(ah, AR_STA_ID1);
1581 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1582 switch (opmode) {
d97809db 1583 case NL80211_IFTYPE_AP:
f1dc5600
S		 1584 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1585 | AR_STA_ID1_KSRCH_MODE);
1586 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1587 break;
d97809db 1588 case NL80211_IFTYPE_ADHOC:
9cb5412b 1589 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 1590 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1591 | AR_STA_ID1_KSRCH_MODE);
1592 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1593 break;
d97809db
CM		 1594 case NL80211_IFTYPE_STATION:
1595 case NL80211_IFTYPE_MONITOR:
f1dc5600 1596 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1597 break;
f1dc5600
S		 1598 }
1599}
1600
cbe61d8a 1601static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
f1dc5600
S		 1602 u32 coef_scaled,
1603 u32 *coef_mantissa,
1604 u32 *coef_exponent)
1605{
1606 u32 coef_exp, coef_man;
1607
1608 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1609 if ((coef_scaled >> coef_exp) & 0x1)
1610 break;
1611
1612 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1613
1614 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1615
1616 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1617 *coef_exponent = coef_exp - 16;
1618}
1619
cbe61d8a 1620static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
f1dc5600
S		 1621 struct ath9k_channel *chan)
1622{
1623 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1624 u32 clockMhzScaled = 0x64000000;
1625 struct chan_centers centers;
1626
1627 if (IS_CHAN_HALF_RATE(chan))
1628 clockMhzScaled = clockMhzScaled >> 1;
1629 else if (IS_CHAN_QUARTER_RATE(chan))
1630 clockMhzScaled = clockMhzScaled >> 2;
1631
1632 ath9k_hw_get_channel_centers(ah, chan, &centers);
1633 coef_scaled = clockMhzScaled / centers.synth_center;
1634
1635 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1636 &ds_coef_exp);
1637
1638 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1639 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1640 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1641 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1642
1643 coef_scaled = (9 * coef_scaled) / 10;
1644
1645 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1646 &ds_coef_exp);
1647
1648 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1649 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1650 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1651 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1652}
1653
cbe61d8a 1654static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1655{
1656 u32 rst_flags;
1657 u32 tmpReg;
1658
70768496
S		 1659 if (AR_SREV_9100(ah)) {
1660 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1661 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1662 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1663 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1664 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1665 }
1666
f1dc5600
S		 1667 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1668 AR_RTC_FORCE_WAKE_ON_INT);
1669
1670 if (AR_SREV_9100(ah)) {
1671 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1672 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1673 } else {
1674 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1675 if (tmpReg &
1676 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1677 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1678 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1679 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1680 } else {
1681 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1682 }
1683
1684 rst_flags = AR_RTC_RC_MAC_WARM;
1685 if (type == ATH9K_RESET_COLD)
1686 rst_flags |= AR_RTC_RC_MAC_COLD;
1687 }
1688
d03a66c1 1689 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1690 udelay(50);
1691
d03a66c1 1692 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1693 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
f1dc5600 1694 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 1695 "RTC stuck in MAC reset\n");
f1dc5600
S		 1696 return false;
1697 }
1698
1699 if (!AR_SREV_9100(ah))
1700 REG_WRITE(ah, AR_RC, 0);
1701
1702 ath9k_hw_init_pll(ah, NULL);
1703
1704 if (AR_SREV_9100(ah))
1705 udelay(50);
1706
1707 return true;
1708}
1709
cbe61d8a 1710static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1711{
1712 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1713 AR_RTC_FORCE_WAKE_ON_INT);
1714
1c29ce67
VT		 1715 if (!AR_SREV_9100(ah))
1716 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1717
d03a66c1 1718 REG_WRITE(ah, AR_RTC_RESET, 0);
8bd1d07f 1719 udelay(2);
1c29ce67
VT		 1720
1721 if (!AR_SREV_9100(ah))
1722 REG_WRITE(ah, AR_RC, 0);
1723
d03a66c1 1724 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1725
1726 if (!ath9k_hw_wait(ah,
1727 AR_RTC_STATUS,
1728 AR_RTC_STATUS_M,
0caa7b14
S		 1729 AR_RTC_STATUS_ON,
1730 AH_WAIT_TIMEOUT)) {
04bd4638 1731 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
f1dc5600 1732 return false;
f078f209
LR		 1733 }
1734
f1dc5600
S		 1735 ath9k_hw_read_revisions(ah);
1736
1737 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1738}
1739
cbe61d8a 1740static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1741{
1742 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1743 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1744
1745 switch (type) {
1746 case ATH9K_RESET_POWER_ON:
1747 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1748 case ATH9K_RESET_WARM:
1749 case ATH9K_RESET_COLD:
1750 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1751 default:
1752 return false;
1753 }
f078f209
LR		 1754}
1755
cbe61d8a 1756static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 1757 enum ath9k_ht_macmode macmode)
f078f209 1758{
f1dc5600 1759 u32 phymode;
e7594072 1760 u32 enableDacFifo = 0;
f078f209 1761
e7594072
SB		 1762 if (AR_SREV_9285_10_OR_LATER(ah))
1763 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1764 AR_PHY_FC_ENABLE_DAC_FIFO);
1765
f1dc5600 1766 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1767 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1768
1769 if (IS_CHAN_HT40(chan)) {
1770 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1771
f1dc5600
S		 1772 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1773 (chan->chanmode == CHANNEL_G_HT40PLUS))
1774 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1775
2660b81a 1776 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
f1dc5600 1777 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
f078f209 1778 }
f1dc5600
S		 1779 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1780
1781 ath9k_hw_set11nmac2040(ah, macmode);
f078f209 1782
f1dc5600
S		 1783 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1784 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1785}
1786
cbe61d8a 1787static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1788 struct ath9k_channel *chan)
f078f209 1789{
8bd1d07f
SB		 1790 if (OLC_FOR_AR9280_20_LATER) {
1791 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1792 return false;
1793 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1794 return false;
f078f209 1795
f1dc5600
S		 1796 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1797 return false;
f078f209 1798
2660b81a 1799 ah->chip_fullsleep = false;
f1dc5600 1800 ath9k_hw_init_pll(ah, chan);
f1dc5600 1801 ath9k_hw_set_rfmode(ah, chan);
f078f209 1802
f1dc5600 1803 return true;
f078f209
LR		 1804}
1805
cbe61d8a 1806static bool ath9k_hw_channel_change(struct ath_hw *ah,
f1dc5600
S		 1807 struct ath9k_channel *chan,
1808 enum ath9k_ht_macmode macmode)
f078f209 1809{
608b88cb 1810 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
5f8e077c 1811 struct ieee80211_channel *channel = chan->chan;
f078f209 1812 u32 synthDelay, qnum;
f078f209
LR		 1813
1814 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1815 if (ath9k_hw_numtxpending(ah, qnum)) {
1816 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
04bd4638 1817 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1818 return false;
1819 }
1820 }
1821
1822 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1823 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
0caa7b14 1824 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
d8baa939 1825 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 1826 "Could not kill baseband RX\n");
f078f209
LR		 1827 return false;
1828 }
1829
1830 ath9k_hw_set_regs(ah, chan, macmode);
1831
1832 if (AR_SREV_9280_10_OR_LATER(ah)) {
8fbff4b8 1833 ath9k_hw_ar9280_set_channel(ah, chan);
f078f209
LR		 1834 } else {
1835 if (!(ath9k_hw_set_channel(ah, chan))) {
d8baa939
S		 1836 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1837 "Failed to set channel\n");
f078f209
LR		 1838 return false;
1839 }
1840 }
1841
8fbff4b8 1842 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1843 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1844 channel->max_antenna_gain * 2,
1845 channel->max_power * 2,
1846 min((u32) MAX_RATE_POWER,
608b88cb 1847 (u32) regulatory->power_limit));
f078f209
LR		 1848
1849 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1850 if (IS_CHAN_B(chan))
f078f209
LR		 1851 synthDelay = (4 * synthDelay) / 22;
1852 else
1853 synthDelay /= 10;
1854
1855 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1856
1857 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1858
f1dc5600
S		 1859 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1860 ath9k_hw_set_delta_slope(ah, chan);
1861
1862 if (AR_SREV_9280_10_OR_LATER(ah))
1863 ath9k_hw_9280_spur_mitigate(ah, chan);
1864 else
1865 ath9k_hw_spur_mitigate(ah, chan);
1866
1867 if (!chan->oneTimeCalsDone)
1868 chan->oneTimeCalsDone = true;
1869
1870 return true;
1871}
1872
cbe61d8a 1873static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 1874{
1875 int bb_spur = AR_NO_SPUR;
1876 int freq;
1877 int bin, cur_bin;
1878 int bb_spur_off, spur_subchannel_sd;
1879 int spur_freq_sd;
1880 int spur_delta_phase;
1881 int denominator;
1882 int upper, lower, cur_vit_mask;
1883 int tmp, newVal;
1884 int i;
1885 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1886 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1887 };
1888 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1889 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1890 };
1891 int inc[4] = { 0, 100, 0, 0 };
1892 struct chan_centers centers;
1893
1894 int8_t mask_m[123];
1895 int8_t mask_p[123];
1896 int8_t mask_amt;
1897 int tmp_mask;
1898 int cur_bb_spur;
1899 bool is2GHz = IS_CHAN_2GHZ(chan);
1900
1901 memset(&mask_m, 0, sizeof(int8_t) * 123);
1902 memset(&mask_p, 0, sizeof(int8_t) * 123);
1903
1904 ath9k_hw_get_channel_centers(ah, chan, &centers);
1905 freq = centers.synth_center;
1906
2660b81a 1907 ah->config.spurmode = SPUR_ENABLE_EEPROM;
f1dc5600 1908 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 1909 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 1910
1911 if (is2GHz)
1912 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1913 else
1914 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1915
1916 if (AR_NO_SPUR == cur_bb_spur)
1917 break;
1918 cur_bb_spur = cur_bb_spur - freq;
1919
1920 if (IS_CHAN_HT40(chan)) {
1921 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1922 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1923 bb_spur = cur_bb_spur;
1924 break;
1925 }
1926 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1927 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1928 bb_spur = cur_bb_spur;
1929 break;
1930 }
1931 }
1932
1933 if (AR_NO_SPUR == bb_spur) {
1934 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1935 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1936 return;
1937 } else {
1938 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1939 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1940 }
1941
1942 bin = bb_spur * 320;
1943
1944 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1945
1946 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1947 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1948 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1949 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1950 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1951
1952 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1953 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1954 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1955 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1956 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1957 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1958
1959 if (IS_CHAN_HT40(chan)) {
1960 if (bb_spur < 0) {
1961 spur_subchannel_sd = 1;
1962 bb_spur_off = bb_spur + 10;
1963 } else {
1964 spur_subchannel_sd = 0;
1965 bb_spur_off = bb_spur - 10;
1966 }
1967 } else {
1968 spur_subchannel_sd = 0;
1969 bb_spur_off = bb_spur;
1970 }
1971
1972 if (IS_CHAN_HT40(chan))
1973 spur_delta_phase =
1974 ((bb_spur * 262144) /
1975 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1976 else
1977 spur_delta_phase =
1978 ((bb_spur * 524288) /
1979 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1980
1981 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1982 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1983
1984 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1985 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1986 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1987 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1988
1989 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1990 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1991
1992 cur_bin = -6000;
1993 upper = bin + 100;
1994 lower = bin - 100;
1995
1996 for (i = 0; i < 4; i++) {
1997 int pilot_mask = 0;
1998 int chan_mask = 0;
1999 int bp = 0;
2000 for (bp = 0; bp < 30; bp++) {
2001 if ((cur_bin > lower) && (cur_bin < upper)) {
2002 pilot_mask = pilot_mask | 0x1 << bp;
2003 chan_mask = chan_mask | 0x1 << bp;
2004 }
2005 cur_bin += 100;
2006 }
2007 cur_bin += inc[i];
2008 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2009 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2010 }
2011
2012 cur_vit_mask = 6100;
2013 upper = bin + 120;
2014 lower = bin - 120;
2015
2016 for (i = 0; i < 123; i++) {
2017 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2018
2019 /* workaround for gcc bug #37014 */
a085ff71 2020 volatile int tmp_v = abs(cur_vit_mask - bin);
f1dc5600 2021
a085ff71 2022 if (tmp_v < 75)
f1dc5600
S		 2023 mask_amt = 1;
2024 else
2025 mask_amt = 0;
2026 if (cur_vit_mask < 0)
2027 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2028 else
2029 mask_p[cur_vit_mask / 100] = mask_amt;
2030 }
2031 cur_vit_mask -= 100;
2032 }
2033
2034 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2035 | (mask_m[48] << 26) | (mask_m[49] << 24)
2036 | (mask_m[50] << 22) | (mask_m[51] << 20)
2037 | (mask_m[52] << 18) | (mask_m[53] << 16)
2038 | (mask_m[54] << 14) | (mask_m[55] << 12)
2039 | (mask_m[56] << 10) | (mask_m[57] << 8)
2040 | (mask_m[58] << 6) | (mask_m[59] << 4)
2041 | (mask_m[60] << 2) | (mask_m[61] << 0);
2042 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2043 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2044
2045 tmp_mask = (mask_m[31] << 28)
2046 | (mask_m[32] << 26) | (mask_m[33] << 24)
2047 | (mask_m[34] << 22) | (mask_m[35] << 20)
2048 | (mask_m[36] << 18) | (mask_m[37] << 16)
2049 | (mask_m[48] << 14) | (mask_m[39] << 12)
2050 | (mask_m[40] << 10) | (mask_m[41] << 8)
2051 | (mask_m[42] << 6) | (mask_m[43] << 4)
2052 | (mask_m[44] << 2) | (mask_m[45] << 0);
2053 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2054 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2055
2056 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2057 | (mask_m[18] << 26) | (mask_m[18] << 24)
2058 | (mask_m[20] << 22) | (mask_m[20] << 20)
2059 | (mask_m[22] << 18) | (mask_m[22] << 16)
2060 | (mask_m[24] << 14) | (mask_m[24] << 12)
2061 | (mask_m[25] << 10) | (mask_m[26] << 8)
2062 | (mask_m[27] << 6) | (mask_m[28] << 4)
2063 | (mask_m[29] << 2) | (mask_m[30] << 0);
2064 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2065 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2066
2067 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2068 | (mask_m[2] << 26) | (mask_m[3] << 24)
2069 | (mask_m[4] << 22) | (mask_m[5] << 20)
2070 | (mask_m[6] << 18) | (mask_m[7] << 16)
2071 | (mask_m[8] << 14) | (mask_m[9] << 12)
2072 | (mask_m[10] << 10) | (mask_m[11] << 8)
2073 | (mask_m[12] << 6) | (mask_m[13] << 4)
2074 | (mask_m[14] << 2) | (mask_m[15] << 0);
2075 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2076 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2077
2078 tmp_mask = (mask_p[15] << 28)
2079 | (mask_p[14] << 26) | (mask_p[13] << 24)
2080 | (mask_p[12] << 22) | (mask_p[11] << 20)
2081 | (mask_p[10] << 18) | (mask_p[9] << 16)
2082 | (mask_p[8] << 14) | (mask_p[7] << 12)
2083 | (mask_p[6] << 10) | (mask_p[5] << 8)
2084 | (mask_p[4] << 6) | (mask_p[3] << 4)
2085 | (mask_p[2] << 2) | (mask_p[1] << 0);
2086 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2087 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2088
f1dc5600
S		 2089 tmp_mask = (mask_p[30] << 28)
2090 | (mask_p[29] << 26) | (mask_p[28] << 24)
2091 | (mask_p[27] << 22) | (mask_p[26] << 20)
2092 | (mask_p[25] << 18) | (mask_p[24] << 16)
2093 | (mask_p[23] << 14) | (mask_p[22] << 12)
2094 | (mask_p[21] << 10) | (mask_p[20] << 8)
2095 | (mask_p[19] << 6) | (mask_p[18] << 4)
2096 | (mask_p[17] << 2) | (mask_p[16] << 0);
2097 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2098 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2099
f1dc5600
S		 2100 tmp_mask = (mask_p[45] << 28)
2101 | (mask_p[44] << 26) | (mask_p[43] << 24)
2102 | (mask_p[42] << 22) | (mask_p[41] << 20)
2103 | (mask_p[40] << 18) | (mask_p[39] << 16)
2104 | (mask_p[38] << 14) | (mask_p[37] << 12)
2105 | (mask_p[36] << 10) | (mask_p[35] << 8)
2106 | (mask_p[34] << 6) | (mask_p[33] << 4)
2107 | (mask_p[32] << 2) | (mask_p[31] << 0);
2108 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2109 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2110
f1dc5600
S		 2111 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2112 | (mask_p[59] << 26) | (mask_p[58] << 24)
2113 | (mask_p[57] << 22) | (mask_p[56] << 20)
2114 | (mask_p[55] << 18) | (mask_p[54] << 16)
2115 | (mask_p[53] << 14) | (mask_p[52] << 12)
2116 | (mask_p[51] << 10) | (mask_p[50] << 8)
2117 | (mask_p[49] << 6) | (mask_p[48] << 4)
2118 | (mask_p[47] << 2) | (mask_p[46] << 0);
2119 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2120 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2121}
2122
cbe61d8a 2123static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 2124{
f1dc5600
S		 2125 int bb_spur = AR_NO_SPUR;
2126 int bin, cur_bin;
2127 int spur_freq_sd;
2128 int spur_delta_phase;
2129 int denominator;
2130 int upper, lower, cur_vit_mask;
2131 int tmp, new;
2132 int i;
2133 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2134 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2135 };
2136 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2137 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2138 };
2139 int inc[4] = { 0, 100, 0, 0 };
f078f209 2140
f1dc5600
S		 2141 int8_t mask_m[123];
2142 int8_t mask_p[123];
2143 int8_t mask_amt;
2144 int tmp_mask;
2145 int cur_bb_spur;
2146 bool is2GHz = IS_CHAN_2GHZ(chan);
f078f209 2147
f1dc5600
S		 2148 memset(&mask_m, 0, sizeof(int8_t) * 123);
2149 memset(&mask_p, 0, sizeof(int8_t) * 123);
f078f209 2150
f1dc5600 2151 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 2152 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 2153 if (AR_NO_SPUR == cur_bb_spur)
2154 break;
2155 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2156 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2157 bb_spur = cur_bb_spur;
2158 break;
2159 }
2160 }
f078f209 2161
f1dc5600
S		 2162 if (AR_NO_SPUR == bb_spur)
2163 return;
f078f209 2164
f1dc5600 2165 bin = bb_spur * 32;
f078f209 2166
f1dc5600
S		 2167 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2168 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2169 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2170 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2171 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
f078f209 2172
f1dc5600 2173 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
f078f209 2174
f1dc5600
S		 2175 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2176 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2177 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2178 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2179 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2180 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
f078f209 2181
f1dc5600
S		 2182 spur_delta_phase = ((bb_spur * 524288) / 100) &
2183 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
f078f209 2184
f1dc5600
S		 2185 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2186 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
f078f209 2187
f1dc5600
S		 2188 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2189 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2190 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2191 REG_WRITE(ah, AR_PHY_TIMING11, new);
f078f209 2192
f1dc5600
S		 2193 cur_bin = -6000;
2194 upper = bin + 100;
2195 lower = bin - 100;
f078f209 2196
f1dc5600
S		 2197 for (i = 0; i < 4; i++) {
2198 int pilot_mask = 0;
2199 int chan_mask = 0;
2200 int bp = 0;
2201 for (bp = 0; bp < 30; bp++) {
2202 if ((cur_bin > lower) && (cur_bin < upper)) {
2203 pilot_mask = pilot_mask | 0x1 << bp;
2204 chan_mask = chan_mask | 0x1 << bp;
2205 }
2206 cur_bin += 100;
2207 }
2208 cur_bin += inc[i];
2209 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2210 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
f078f209 2211 }
f078f209 2212
f1dc5600
S		 2213 cur_vit_mask = 6100;
2214 upper = bin + 120;
2215 lower = bin - 120;
f078f209 2216
f1dc5600
S		 2217 for (i = 0; i < 123; i++) {
2218 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
f078f209 2219
f1dc5600 2220 /* workaround for gcc bug #37014 */
a085ff71 2221 volatile int tmp_v = abs(cur_vit_mask - bin);
f078f209 2222
a085ff71 2223 if (tmp_v < 75)
f1dc5600
S		 2224 mask_amt = 1;
2225 else
2226 mask_amt = 0;
2227 if (cur_vit_mask < 0)
2228 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2229 else
2230 mask_p[cur_vit_mask / 100] = mask_amt;
2231 }
2232 cur_vit_mask -= 100;
f078f209
LR		 2233 }
2234
f1dc5600
S		 2235 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2236 | (mask_m[48] << 26) | (mask_m[49] << 24)
2237 | (mask_m[50] << 22) | (mask_m[51] << 20)
2238 | (mask_m[52] << 18) | (mask_m[53] << 16)
2239 | (mask_m[54] << 14) | (mask_m[55] << 12)
2240 | (mask_m[56] << 10) | (mask_m[57] << 8)
2241 | (mask_m[58] << 6) | (mask_m[59] << 4)
2242 | (mask_m[60] << 2) | (mask_m[61] << 0);
2243 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2244 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
f078f209 2245
f1dc5600
S		 2246 tmp_mask = (mask_m[31] << 28)
2247 | (mask_m[32] << 26) | (mask_m[33] << 24)
2248 | (mask_m[34] << 22) | (mask_m[35] << 20)
2249 | (mask_m[36] << 18) | (mask_m[37] << 16)
2250 | (mask_m[48] << 14) | (mask_m[39] << 12)
2251 | (mask_m[40] << 10) | (mask_m[41] << 8)
2252 | (mask_m[42] << 6) | (mask_m[43] << 4)
2253 | (mask_m[44] << 2) | (mask_m[45] << 0);
2254 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2255 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
f078f209 2256
f1dc5600
S		 2257 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2258 | (mask_m[18] << 26) | (mask_m[18] << 24)
2259 | (mask_m[20] << 22) | (mask_m[20] << 20)
2260 | (mask_m[22] << 18) | (mask_m[22] << 16)
2261 | (mask_m[24] << 14) | (mask_m[24] << 12)
2262 | (mask_m[25] << 10) | (mask_m[26] << 8)
2263 | (mask_m[27] << 6) | (mask_m[28] << 4)
2264 | (mask_m[29] << 2) | (mask_m[30] << 0);
2265 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2266 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
f078f209 2267
f1dc5600
S		 2268 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2269 | (mask_m[2] << 26) | (mask_m[3] << 24)
2270 | (mask_m[4] << 22) | (mask_m[5] << 20)
2271 | (mask_m[6] << 18) | (mask_m[7] << 16)
2272 | (mask_m[8] << 14) | (mask_m[9] << 12)
2273 | (mask_m[10] << 10) | (mask_m[11] << 8)
2274 | (mask_m[12] << 6) | (mask_m[13] << 4)
2275 | (mask_m[14] << 2) | (mask_m[15] << 0);
2276 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2277 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
f078f209 2278
f1dc5600
S		 2279 tmp_mask = (mask_p[15] << 28)
2280 | (mask_p[14] << 26) | (mask_p[13] << 24)
2281 | (mask_p[12] << 22) | (mask_p[11] << 20)
2282 | (mask_p[10] << 18) | (mask_p[9] << 16)
2283 | (mask_p[8] << 14) | (mask_p[7] << 12)
2284 | (mask_p[6] << 10) | (mask_p[5] << 8)
2285 | (mask_p[4] << 6) | (mask_p[3] << 4)
2286 | (mask_p[2] << 2) | (mask_p[1] << 0);
2287 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2288 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2289
f1dc5600
S		 2290 tmp_mask = (mask_p[30] << 28)
2291 | (mask_p[29] << 26) | (mask_p[28] << 24)
2292 | (mask_p[27] << 22) | (mask_p[26] << 20)
2293 | (mask_p[25] << 18) | (mask_p[24] << 16)
2294 | (mask_p[23] << 14) | (mask_p[22] << 12)
2295 | (mask_p[21] << 10) | (mask_p[20] << 8)
2296 | (mask_p[19] << 6) | (mask_p[18] << 4)
2297 | (mask_p[17] << 2) | (mask_p[16] << 0);
2298 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2299 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2300
f1dc5600
S		 2301 tmp_mask = (mask_p[45] << 28)
2302 | (mask_p[44] << 26) | (mask_p[43] << 24)
2303 | (mask_p[42] << 22) | (mask_p[41] << 20)
2304 | (mask_p[40] << 18) | (mask_p[39] << 16)
2305 | (mask_p[38] << 14) | (mask_p[37] << 12)
2306 | (mask_p[36] << 10) | (mask_p[35] << 8)
2307 | (mask_p[34] << 6) | (mask_p[33] << 4)
2308 | (mask_p[32] << 2) | (mask_p[31] << 0);
2309 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2310 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2311
f1dc5600
S		 2312 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2313 | (mask_p[59] << 26) | (mask_p[58] << 24)
2314 | (mask_p[57] << 22) | (mask_p[56] << 20)
2315 | (mask_p[55] << 18) | (mask_p[54] << 16)
2316 | (mask_p[53] << 14) | (mask_p[52] << 12)
2317 | (mask_p[51] << 10) | (mask_p[50] << 8)
2318 | (mask_p[49] << 6) | (mask_p[48] << 4)
2319 | (mask_p[47] << 2) | (mask_p[46] << 0);
2320 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2321 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2322}
2323
3b319aae
JB		 2324static void ath9k_enable_rfkill(struct ath_hw *ah)
2325{
2326 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2327 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2328
2329 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2330 AR_GPIO_INPUT_MUX2_RFSILENT);
2331
2332 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2333 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2334}
2335
cbe61d8a 2336int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 2337 bool bChannelChange)
f078f209 2338{
f078f209 2339 u32 saveLedState;
ae8d2858 2340 struct ath_softc *sc = ah->ah_sc;
2660b81a 2341 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 2342 u32 saveDefAntenna;
2343 u32 macStaId1;
ae8d2858 2344 int i, rx_chainmask, r;
f078f209 2345
2660b81a
S		 2346 ah->extprotspacing = sc->ht_extprotspacing;
2347 ah->txchainmask = sc->tx_chainmask;
2348 ah->rxchainmask = sc->rx_chainmask;
f078f209 2349
ae8d2858
LR		 2350 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2351 return -EIO;
f078f209
LR		 2352
2353 if (curchan)
2354 ath9k_hw_getnf(ah, curchan);
2355
2356 if (bChannelChange &&
2660b81a
S		 2357 (ah->chip_fullsleep != true) &&
2358 (ah->curchan != NULL) &&
2359 (chan->channel != ah->curchan->channel) &&
f078f209 2360 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 2361 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
f078f209 2362 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2660b81a 2363 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
f078f209 2364
ae8d2858 2365 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2660b81a 2366 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 2367 ath9k_hw_start_nfcal(ah);
ae8d2858 2368 return 0;
f078f209
LR		 2369 }
2370 }
2371
2372 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2373 if (saveDefAntenna == 0)
2374 saveDefAntenna = 1;
2375
2376 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2377
2378 saveLedState = REG_READ(ah, AR_CFG_LED) &
2379 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2380 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2381
2382 ath9k_hw_mark_phy_inactive(ah);
2383
d7e7d229
LR		 2384 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2385 REG_WRITE(ah,
2386 AR9271_RESET_POWER_DOWN_CONTROL,
2387 AR9271_RADIO_RF_RST);
2388 udelay(50);
2389 }
2390
f078f209 2391 if (!ath9k_hw_chip_reset(ah, chan)) {
d8baa939 2392 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 2393 return -EINVAL;
f078f209
LR		 2394 }
2395
d7e7d229
LR		 2396 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2397 ah->htc_reset_init = false;
2398 REG_WRITE(ah,
2399 AR9271_RESET_POWER_DOWN_CONTROL,
2400 AR9271_GATE_MAC_CTL);
2401 udelay(50);
2402 }
2403
369391db
VT		 2404 if (AR_SREV_9280_10_OR_LATER(ah))
2405 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 2406
326bebbc 2407 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2408 /* Enable ASYNC FIFO */
2409 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2410 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2411 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2412 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2413 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2414 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2415 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2416 }
ae8d2858
LR		 2417 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2418 if (r)
2419 return r;
f078f209 2420
0ced0e17
JM		 2421 /* Setup MFP options for CCMP */
2422 if (AR_SREV_9280_20_OR_LATER(ah)) {
2423 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2424 * frames when constructing CCMP AAD. */
2425 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2426 0xc7ff);
2427 ah->sw_mgmt_crypto = false;
2428 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2429 /* Disable hardware crypto for management frames */
2430 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2431 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2432 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2433 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2434 ah->sw_mgmt_crypto = true;
2435 } else
2436 ah->sw_mgmt_crypto = true;
2437
f078f209
LR		 2438 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2439 ath9k_hw_set_delta_slope(ah, chan);
2440
2441 if (AR_SREV_9280_10_OR_LATER(ah))
2442 ath9k_hw_9280_spur_mitigate(ah, chan);
2443 else
2444 ath9k_hw_spur_mitigate(ah, chan);
2445
d6509151 2446 ah->eep_ops->set_board_values(ah, chan);
f078f209
LR		 2447
2448 ath9k_hw_decrease_chain_power(ah, chan);
2449
ba52da58
S		 2450 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2451 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
f078f209
LR		 2452 | macStaId1
2453 | AR_STA_ID1_RTS_USE_DEF
2660b81a 2454 | (ah->config.
60b67f51 2455 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 2456 | ah->sta_id1_defaults);
2457 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2458
ba52da58
S		 2459 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2460 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
f078f209
LR		 2461
2462 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2463
ba52da58
S		 2464 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2465 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2466 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 2467
2468 REG_WRITE(ah, AR_ISR, ~0);
2469
2470 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2471
8fbff4b8
VT		 2472 if (AR_SREV_9280_10_OR_LATER(ah))
2473 ath9k_hw_ar9280_set_channel(ah, chan);
2474 else
ae8d2858
LR		 2475 if (!(ath9k_hw_set_channel(ah, chan)))
2476 return -EIO;
f078f209
LR		 2477
2478 for (i = 0; i < AR_NUM_DCU; i++)
2479 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2480
2660b81a
S		 2481 ah->intr_txqs = 0;
2482 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 2483 ath9k_hw_resettxqueue(ah, i);
2484
2660b81a 2485 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 2486 ath9k_hw_init_qos(ah);
2487
2660b81a 2488 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 2489 ath9k_enable_rfkill(ah);
3b319aae 2490
f078f209
LR		 2491 ath9k_hw_init_user_settings(ah);
2492
326bebbc 2493 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2494 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2495 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2496 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2497 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2498 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2499 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2500
2501 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2502 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2503
2504 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2505 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2506 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2507 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2508 }
326bebbc 2509 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2510 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2511 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2512 }
2513
f078f209
LR		 2514 REG_WRITE(ah, AR_STA_ID1,
2515 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2516
2517 ath9k_hw_set_dma(ah);
2518
2519 REG_WRITE(ah, AR_OBS, 8);
2520
0ef1f168 2521 if (ah->config.intr_mitigation) {
f078f209
LR		 2522 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2523 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2524 }
2525
2526 ath9k_hw_init_bb(ah, chan);
2527
ae8d2858 2528 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2529 return -EIO;
f078f209 2530
2660b81a 2531 rx_chainmask = ah->rxchainmask;
f078f209
LR		 2532 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2533 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2534 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2535 }
2536
2537 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2538
d7e7d229
LR		 2539 /*
2540 * For big endian systems turn on swapping for descriptors
2541 */
f078f209
LR		 2542 if (AR_SREV_9100(ah)) {
2543 u32 mask;
2544 mask = REG_READ(ah, AR_CFG);
2545 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2546 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2547 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2548 } else {
2549 mask =
2550 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2551 REG_WRITE(ah, AR_CFG, mask);
2552 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
04bd4638 2553 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2554 }
2555 } else {
d7e7d229
LR		 2556 /* Configure AR9271 target WLAN */
2557 if (AR_SREV_9271(ah))
2558 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 2559#ifdef __BIG_ENDIAN
d7e7d229
LR		 2560 else
2561 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 2562#endif
2563 }
2564
42cc41ed
VT		 2565 if (ah->ah_sc->sc_flags & SC_OP_BTCOEX_ENABLED)
2566 ath9k_hw_btcoex_enable(ah);
2567
ae8d2858 2568 return 0;
f078f209
LR		 2569}
2570
f1dc5600
S		 2571/************************/
2572/* Key Cache Management */
2573/************************/
f078f209 2574
cbe61d8a 2575bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 2576{
f1dc5600 2577 u32 keyType;
f078f209 2578
2660b81a 2579 if (entry >= ah->caps.keycache_size) {
d8baa939
S		 2580 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2581 "keychache entry %u out of range\n", entry);
f078f209
LR		 2582 return false;
2583 }
2584
f1dc5600 2585 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2586
f1dc5600
S		 2587 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2588 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2589 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2590 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2591 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2592 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2593 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2594 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2595
f1dc5600
S		 2596 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2597 u16 micentry = entry + 64;
f078f209 2598
f1dc5600
S		 2599 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2600 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2601 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2602 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2603
f078f209
LR		 2604 }
2605
f078f209
LR		 2606 return true;
2607}
2608
cbe61d8a 2609bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 2610{
f1dc5600 2611 u32 macHi, macLo;
f078f209 2612
2660b81a 2613 if (entry >= ah->caps.keycache_size) {
d8baa939
S		 2614 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2615 "keychache entry %u out of range\n", entry);
f1dc5600 2616 return false;
f078f209
LR		 2617 }
2618
f1dc5600
S		 2619 if (mac != NULL) {
2620 macHi = (mac[5] << 8) | mac[4];
2621 macLo = (mac[3] << 24) |
2622 (mac[2] << 16) |
2623 (mac[1] << 8) |
2624 mac[0];
2625 macLo >>= 1;
2626 macLo |= (macHi & 1) << 31;
2627 macHi >>= 1;
f078f209 2628 } else {
f1dc5600 2629 macLo = macHi = 0;
f078f209 2630 }
f1dc5600
S		 2631 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2632 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2633
f1dc5600 2634 return true;
f078f209
LR		 2635}
2636
cbe61d8a 2637bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 2638 const struct ath9k_keyval *k,
e0caf9ea 2639 const u8 *mac)
f078f209 2640{
2660b81a 2641 const struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 2642 u32 key0, key1, key2, key3, key4;
2643 u32 keyType;
f078f209 2644
f1dc5600 2645 if (entry >= pCap->keycache_size) {
d8baa939
S		 2646 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2647 "keycache entry %u out of range\n", entry);
f1dc5600 2648 return false;
f078f209
LR		 2649 }
2650
f1dc5600
S		 2651 switch (k->kv_type) {
2652 case ATH9K_CIPHER_AES_OCB:
2653 keyType = AR_KEYTABLE_TYPE_AES;
2654 break;
2655 case ATH9K_CIPHER_AES_CCM:
2656 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
d8baa939 2657 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2658 "AES-CCM not supported by mac rev 0x%x\n",
d535a42a 2659 ah->hw_version.macRev);
f1dc5600
S		 2660 return false;
2661 }
2662 keyType = AR_KEYTABLE_TYPE_CCM;
2663 break;
2664 case ATH9K_CIPHER_TKIP:
2665 keyType = AR_KEYTABLE_TYPE_TKIP;
2666 if (ATH9K_IS_MIC_ENABLED(ah)
2667 && entry + 64 >= pCap->keycache_size) {
d8baa939 2668 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2669 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2670 return false;
2671 }
2672 break;
2673 case ATH9K_CIPHER_WEP:
e31a16d6 2674 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
d8baa939 2675 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 2676 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2677 return false;
2678 }
e31a16d6 2679 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 2680 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 2681 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 2682 keyType = AR_KEYTABLE_TYPE_104;
2683 else
2684 keyType = AR_KEYTABLE_TYPE_128;
2685 break;
2686 case ATH9K_CIPHER_CLR:
2687 keyType = AR_KEYTABLE_TYPE_CLR;
2688 break;
2689 default:
d8baa939 2690 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 2691 "cipher %u not supported\n", k->kv_type);
f1dc5600 2692 return false;
f078f209
LR		 2693 }
2694
e0caf9ea
JM		 2695 key0 = get_unaligned_le32(k->kv_val + 0);
2696 key1 = get_unaligned_le16(k->kv_val + 4);
2697 key2 = get_unaligned_le32(k->kv_val + 6);
2698 key3 = get_unaligned_le16(k->kv_val + 10);
2699 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 2700 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 2701 key4 &= 0xff;
f078f209 2702
672903b3
JM		 2703 /*
2704 * Note: Key cache registers access special memory area that requires
2705 * two 32-bit writes to actually update the values in the internal
2706 * memory. Consequently, the exact order and pairs used here must be
2707 * maintained.
2708 */
2709
f1dc5600
S		 2710 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2711 u16 micentry = entry + 64;
f078f209 2712
672903b3
JM		 2713 /*
2714 * Write inverted key[47:0] first to avoid Michael MIC errors
2715 * on frames that could be sent or received at the same time.
2716 * The correct key will be written in the end once everything
2717 * else is ready.
2718 */
f1dc5600
S		 2719 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2720 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 2721
2722 /* Write key[95:48] */
f1dc5600
S		 2723 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2724 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2725
2726 /* Write key[127:96] and key type */
f1dc5600
S		 2727 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2728 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 2729
2730 /* Write MAC address for the entry */
f1dc5600 2731 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2732
2660b81a 2733 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 2734 /*
2735 * TKIP uses two key cache entries:
2736 * Michael MIC TX/RX keys in the same key cache entry
2737 * (idx = main index + 64):
2738 * key0 [31:0] = RX key [31:0]
2739 * key1 [15:0] = TX key [31:16]
2740 * key1 [31:16] = reserved
2741 * key2 [31:0] = RX key [63:32]
2742 * key3 [15:0] = TX key [15:0]
2743 * key3 [31:16] = reserved
2744 * key4 [31:0] = TX key [63:32]
2745 */
f1dc5600 2746 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2747
f1dc5600
S		 2748 mic0 = get_unaligned_le32(k->kv_mic + 0);
2749 mic2 = get_unaligned_le32(k->kv_mic + 4);
2750 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2751 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2752 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 2753
2754 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 2755 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2756 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 2757
2758 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 2759 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2760 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 2761
2762 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2763 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2764 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2765 AR_KEYTABLE_TYPE_CLR);
f078f209 2766
f1dc5600 2767 } else {
672903b3
JM		 2768 /*
2769 * TKIP uses four key cache entries (two for group
2770 * keys):
2771 * Michael MIC TX/RX keys are in different key cache
2772 * entries (idx = main index + 64 for TX and
2773 * main index + 32 + 96 for RX):
2774 * key0 [31:0] = TX/RX MIC key [31:0]
2775 * key1 [31:0] = reserved
2776 * key2 [31:0] = TX/RX MIC key [63:32]
2777 * key3 [31:0] = reserved
2778 * key4 [31:0] = reserved
2779 *
2780 * Upper layer code will call this function separately
2781 * for TX and RX keys when these registers offsets are
2782 * used.
2783 */
f1dc5600 2784 u32 mic0, mic2;
f078f209 2785
f1dc5600
S		 2786 mic0 = get_unaligned_le32(k->kv_mic + 0);
2787 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 2788
2789 /* Write MIC key[31:0] */
f1dc5600
S		 2790 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2791 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 2792
2793 /* Write MIC key[63:32] */
f1dc5600
S		 2794 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2795 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 2796
2797 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2798 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2799 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2800 AR_KEYTABLE_TYPE_CLR);
2801 }
672903b3
JM		 2802
2803 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 2804 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2805 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 2806
2807 /*
2808 * Write the correct (un-inverted) key[47:0] last to enable
2809 * TKIP now that all other registers are set with correct
2810 * values.
2811 */
f1dc5600
S		 2812 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2813 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2814 } else {
672903b3 2815 /* Write key[47:0] */
f1dc5600
S		 2816 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2817 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 2818
2819 /* Write key[95:48] */
f1dc5600
S		 2820 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2821 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2822
2823 /* Write key[127:96] and key type */
f1dc5600
S		 2824 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2825 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2826
672903b3 2827 /* Write MAC address for the entry */
f1dc5600
S		 2828 (void) ath9k_hw_keysetmac(ah, entry, mac);
2829 }
f078f209 2830
f078f209
LR		 2831 return true;
2832}
2833
cbe61d8a 2834bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 2835{
2660b81a 2836 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 2837 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2838 if (val & AR_KEYTABLE_VALID)
2839 return true;
2840 }
2841 return false;
f078f209
LR		 2842}
2843
f1dc5600
S		 2844/******************************/
2845/* Power Management (Chipset) */
2846/******************************/
2847
cbe61d8a 2848static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2849{
f1dc5600
S		 2850 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2851 if (setChip) {
2852 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2853 AR_RTC_FORCE_WAKE_EN);
2854 if (!AR_SREV_9100(ah))
2855 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2856
d03a66c1 2857 REG_CLR_BIT(ah, (AR_RTC_RESET),
f1dc5600
S		 2858 AR_RTC_RESET_EN);
2859 }
f078f209
LR		 2860}
2861
cbe61d8a 2862static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2863{
f1dc5600
S		 2864 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2865 if (setChip) {
2660b81a 2866 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2867
f1dc5600
S		 2868 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2869 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2870 AR_RTC_FORCE_WAKE_ON_INT);
2871 } else {
2872 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2873 AR_RTC_FORCE_WAKE_EN);
f078f209 2874 }
f078f209 2875 }
f078f209
LR		 2876}
2877
cbe61d8a 2878static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2879{
f1dc5600
S		 2880 u32 val;
2881 int i;
f078f209 2882
f1dc5600
S		 2883 if (setChip) {
2884 if ((REG_READ(ah, AR_RTC_STATUS) &
2885 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2886 if (ath9k_hw_set_reset_reg(ah,
2887 ATH9K_RESET_POWER_ON) != true) {
2888 return false;
2889 }
2890 }
2891 if (AR_SREV_9100(ah))
2892 REG_SET_BIT(ah, AR_RTC_RESET,
2893 AR_RTC_RESET_EN);
f078f209 2894
f1dc5600
S		 2895 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2896 AR_RTC_FORCE_WAKE_EN);
2897 udelay(50);
f078f209 2898
f1dc5600
S		 2899 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2900 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2901 if (val == AR_RTC_STATUS_ON)
2902 break;
2903 udelay(50);
2904 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2905 AR_RTC_FORCE_WAKE_EN);
f078f209 2906 }
f1dc5600 2907 if (i == 0) {
d8baa939 2908 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 2909 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
f1dc5600 2910 return false;
f078f209 2911 }
f078f209
LR		 2912 }
2913
f1dc5600 2914 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2915
f1dc5600 2916 return true;
f078f209
LR		 2917}
2918
04717ccd
GJ		 2919static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2920 enum ath9k_power_mode mode)
f078f209 2921{
cbe61d8a 2922 int status = true, setChip = true;
f1dc5600
S		 2923 static const char *modes[] = {
2924 "AWAKE",
2925 "FULL-SLEEP",
2926 "NETWORK SLEEP",
2927 "UNDEFINED"
2928 };
f1dc5600 2929
cbdec975
GJ		 2930 if (ah->power_mode == mode)
2931 return status;
2932
d8baa939
S		 2933 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2934 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2935
2936 switch (mode) {
2937 case ATH9K_PM_AWAKE:
2938 status = ath9k_hw_set_power_awake(ah, setChip);
2939 break;
2940 case ATH9K_PM_FULL_SLEEP:
2941 ath9k_set_power_sleep(ah, setChip);
2660b81a 2942 ah->chip_fullsleep = true;
f1dc5600
S		 2943 break;
2944 case ATH9K_PM_NETWORK_SLEEP:
2945 ath9k_set_power_network_sleep(ah, setChip);
2946 break;
f078f209 2947 default:
d8baa939 2948 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
04bd4638 2949 "Unknown power mode %u\n", mode);
f078f209
LR		 2950 return false;
2951 }
2660b81a 2952 ah->power_mode = mode;
f1dc5600
S		 2953
2954 return status;
f078f209
LR		 2955}
2956
04717ccd
GJ		 2957bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2958{
2959 unsigned long flags;
2960 bool ret;
2961
2962 spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2963 ret = ath9k_hw_setpower_nolock(ah, mode);
2964 spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2965
2966 return ret;
2967}
2968
0bc0798b
GJ		 2969void ath9k_ps_wakeup(struct ath_softc *sc)
2970{
709ade9e
GJ		 2971 unsigned long flags;
2972
2973 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2974 if (++sc->ps_usecount != 1)
2975 goto unlock;
2976
cbdec975 2977 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
709ade9e
GJ		 2978
2979 unlock:
2980 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
0bc0798b
GJ		 2981}
2982
2983void ath9k_ps_restore(struct ath_softc *sc)
2984{
709ade9e
GJ		 2985 unsigned long flags;
2986
2987 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2988 if (--sc->ps_usecount != 0)
2989 goto unlock;
2990
96148326
GJ		 2991 if (sc->ps_enabled &&
2992 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2993 SC_OP_WAIT_FOR_CAB |
2994 SC_OP_WAIT_FOR_PSPOLL_DATA |
2995 SC_OP_WAIT_FOR_TX_ACK)))
2996 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
709ade9e
GJ		 2997
2998 unlock:
2999 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
0bc0798b
GJ		 3000}
3001
24c1a280
LR		 3002/*
3003 * Helper for ASPM support.
3004 *
3005 * Disable PLL when in L0s as well as receiver clock when in L1.
3006 * This power saving option must be enabled through the SerDes.
3007 *
3008 * Programming the SerDes must go through the same 288 bit serial shift
3009 * register as the other analog registers. Hence the 9 writes.
3010 */
cbe61d8a 3011void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
f078f209 3012{
f1dc5600 3013 u8 i;
f078f209 3014
2660b81a 3015 if (ah->is_pciexpress != true)
f1dc5600 3016 return;
f078f209 3017
24c1a280 3018 /* Do not touch SerDes registers */
2660b81a 3019 if (ah->config.pcie_powersave_enable == 2)
f1dc5600
S		 3020 return;
3021
24c1a280 3022 /* Nothing to do on restore for 11N */
f1dc5600
S		 3023 if (restore)
3024 return;
3025
3026 if (AR_SREV_9280_20_OR_LATER(ah)) {
24c1a280
LR		 3027 /*
3028 * AR9280 2.0 or later chips use SerDes values from the
3029 * initvals.h initialized depending on chipset during
f637cfd6 3030 * ath9k_hw_init()
24c1a280 3031 */
2660b81a
S		 3032 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
3033 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
3034 INI_RA(&ah->iniPcieSerdes, i, 1));
f078f209 3035 }
f1dc5600 3036 } else if (AR_SREV_9280(ah) &&
d535a42a 3037 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
f1dc5600
S		 3038 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3039 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3040
24c1a280 3041 /* RX shut off when elecidle is asserted */
f1dc5600
S		 3042 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3043 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3044 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3045
24c1a280 3046 /* Shut off CLKREQ active in L1 */
2660b81a 3047 if (ah->config.pcie_clock_req)
f1dc5600
S		 3048 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3049 else
3050 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3051
3052 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3053 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3054 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3055
24c1a280 3056 /* Load the new settings */
f1dc5600
S		 3057 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3058
f1dc5600
S		 3059 } else {
3060 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3061 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
24c1a280
LR		 3062
3063 /* RX shut off when elecidle is asserted */
f1dc5600
S		 3064 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3065 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3066 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
24c1a280
LR		 3067
3068 /*
3069 * Ignore ah->ah_config.pcie_clock_req setting for
3070 * pre-AR9280 11n
3071 */
f1dc5600 3072 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
24c1a280 3073
f1dc5600
S		 3074 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3075 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3076 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
24c1a280
LR		 3077
3078 /* Load the new settings */
f1dc5600 3079 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 3080 }
3081
6d08b9b9
LR		 3082 udelay(1000);
3083
24c1a280 3084 /* set bit 19 to allow forcing of pcie core into L1 state */
f1dc5600
S		 3085 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3086
24c1a280 3087 /* Several PCIe massages to ensure proper behaviour */
2660b81a
S		 3088 if (ah->config.pcie_waen) {
3089 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
f1dc5600 3090 } else {
d340b1f0 3091 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah))
e7594072 3092 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
24c1a280
LR		 3093 /*
3094 * On AR9280 chips bit 22 of 0x4004 needs to be set to
3095 * otherwise card may disappear.
3096 */
e7594072
SB		 3097 else if (AR_SREV_9280(ah))
3098 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
f1dc5600 3099 else
e7594072 3100 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
f1dc5600 3101 }
f078f209
LR		 3102}
3103
f1dc5600
S		 3104/**********************/
3105/* Interrupt Handling */
3106/**********************/
3107
cbe61d8a 3108bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 3109{
3110 u32 host_isr;
3111
3112 if (AR_SREV_9100(ah))
3113 return true;
3114
3115 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3116 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3117 return true;
3118
3119 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3120 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3121 && (host_isr != AR_INTR_SPURIOUS))
3122 return true;
3123
3124 return false;
3125}
3126
cbe61d8a 3127bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 3128{
3129 u32 isr = 0;
3130 u32 mask2 = 0;
2660b81a 3131 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3132 u32 sync_cause = 0;
3133 bool fatal_int = false;
3134
3135 if (!AR_SREV_9100(ah)) {
3136 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3137 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3138 == AR_RTC_STATUS_ON) {
3139 isr = REG_READ(ah, AR_ISR);
3140 }
3141 }
3142
f1dc5600
S		 3143 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3144 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 3145
3146 *masked = 0;
3147
3148 if (!isr && !sync_cause)
3149 return false;
3150 } else {
3151 *masked = 0;
3152 isr = REG_READ(ah, AR_ISR);
3153 }
3154
3155 if (isr) {
f078f209
LR		 3156 if (isr & AR_ISR_BCNMISC) {
3157 u32 isr2;
3158 isr2 = REG_READ(ah, AR_ISR_S2);
3159 if (isr2 & AR_ISR_S2_TIM)
3160 mask2 |= ATH9K_INT_TIM;
3161 if (isr2 & AR_ISR_S2_DTIM)
3162 mask2 |= ATH9K_INT_DTIM;
3163 if (isr2 & AR_ISR_S2_DTIMSYNC)
3164 mask2 |= ATH9K_INT_DTIMSYNC;
3165 if (isr2 & (AR_ISR_S2_CABEND))
3166 mask2 |= ATH9K_INT_CABEND;
3167 if (isr2 & AR_ISR_S2_GTT)
3168 mask2 |= ATH9K_INT_GTT;
3169 if (isr2 & AR_ISR_S2_CST)
3170 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 3171 if (isr2 & AR_ISR_S2_TSFOOR)
3172 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 3173 }
3174
3175 isr = REG_READ(ah, AR_ISR_RAC);
3176 if (isr == 0xffffffff) {
3177 *masked = 0;
3178 return false;
3179 }
3180
3181 *masked = isr & ATH9K_INT_COMMON;
3182
0ef1f168 3183 if (ah->config.intr_mitigation) {
f078f209
LR		 3184 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3185 *masked |= ATH9K_INT_RX;
3186 }
3187
3188 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3189 *masked |= ATH9K_INT_RX;
3190 if (isr &
3191 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3192 AR_ISR_TXEOL)) {
3193 u32 s0_s, s1_s;
3194
3195 *masked |= ATH9K_INT_TX;
3196
3197 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 3198 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3199 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 3200
3201 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 3202 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3203 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 3204 }
3205
3206 if (isr & AR_ISR_RXORN) {
3207 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 3208 "receive FIFO overrun interrupt\n");
f078f209
LR		 3209 }
3210
3211 if (!AR_SREV_9100(ah)) {
60b67f51 3212 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3213 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3214 if (isr5 & AR_ISR_S5_TIM_TIMER)
3215 *masked |= ATH9K_INT_TIM_TIMER;
3216 }
3217 }
3218
3219 *masked |= mask2;
3220 }
f1dc5600 3221
f078f209
LR		 3222 if (AR_SREV_9100(ah))
3223 return true;
f1dc5600 3224
ff155a45
VT		 3225 if (isr & AR_ISR_GENTMR) {
3226 u32 s5_s;
3227
3228 s5_s = REG_READ(ah, AR_ISR_S5_S);
3229 if (isr & AR_ISR_GENTMR) {
3230 ah->intr_gen_timer_trigger =
3231 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3232
3233 ah->intr_gen_timer_thresh =
3234 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3235
3236 if (ah->intr_gen_timer_trigger)
3237 *masked |= ATH9K_INT_GENTIMER;
3238
3239 }
3240 }
3241
f078f209
LR		 3242 if (sync_cause) {
3243 fatal_int =
3244 (sync_cause &
3245 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3246 ? true : false;
3247
3248 if (fatal_int) {
3249 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3250 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 3251 "received PCI FATAL interrupt\n");
f078f209
LR		 3252 }
3253 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3254 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
04bd4638 3255 "received PCI PERR interrupt\n");
f078f209 3256 }
a89bff9a 3257 *masked |= ATH9K_INT_FATAL;
f078f209
LR		 3258 }
3259 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3260 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 3261 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 3262 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3263 REG_WRITE(ah, AR_RC, 0);
3264 *masked |= ATH9K_INT_FATAL;
3265 }
3266 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3267 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
04bd4638 3268 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 3269 }
3270
3271 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3272 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3273 }
f1dc5600 3274
f078f209
LR		 3275 return true;
3276}
3277
cbe61d8a 3278enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 3279{
2660b81a 3280 u32 omask = ah->mask_reg;
f078f209 3281 u32 mask, mask2;
2660b81a 3282 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 3283
04bd4638 3284 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 3285
3286 if (omask & ATH9K_INT_GLOBAL) {
04bd4638 3287 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 3288 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3289 (void) REG_READ(ah, AR_IER);
3290 if (!AR_SREV_9100(ah)) {
3291 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3292 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3293
3294 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3295 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3296 }
3297 }
3298
3299 mask = ints & ATH9K_INT_COMMON;
3300 mask2 = 0;
3301
3302 if (ints & ATH9K_INT_TX) {
2660b81a 3303 if (ah->txok_interrupt_mask)
f078f209 3304 mask |= AR_IMR_TXOK;
2660b81a 3305 if (ah->txdesc_interrupt_mask)
f078f209 3306 mask |= AR_IMR_TXDESC;
2660b81a 3307 if (ah->txerr_interrupt_mask)
f078f209 3308 mask |= AR_IMR_TXERR;
2660b81a 3309 if (ah->txeol_interrupt_mask)
f078f209
LR		 3310 mask |= AR_IMR_TXEOL;
3311 }
3312 if (ints & ATH9K_INT_RX) {
3313 mask |= AR_IMR_RXERR;
0ef1f168 3314 if (ah->config.intr_mitigation)
f078f209
LR		 3315 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3316 else
3317 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 3318 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 3319 mask |= AR_IMR_GENTMR;
3320 }
3321
3322 if (ints & (ATH9K_INT_BMISC)) {
3323 mask |= AR_IMR_BCNMISC;
3324 if (ints & ATH9K_INT_TIM)
3325 mask2 |= AR_IMR_S2_TIM;
3326 if (ints & ATH9K_INT_DTIM)
3327 mask2 |= AR_IMR_S2_DTIM;
3328 if (ints & ATH9K_INT_DTIMSYNC)
3329 mask2 |= AR_IMR_S2_DTIMSYNC;
3330 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 3331 mask2 |= AR_IMR_S2_CABEND;
3332 if (ints & ATH9K_INT_TSFOOR)
3333 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 3334 }
3335
3336 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3337 mask |= AR_IMR_BCNMISC;
3338 if (ints & ATH9K_INT_GTT)
3339 mask2 |= AR_IMR_S2_GTT;
3340 if (ints & ATH9K_INT_CST)
3341 mask2 |= AR_IMR_S2_CST;
3342 }
3343
04bd4638 3344 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 3345 REG_WRITE(ah, AR_IMR, mask);
3346 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3347 AR_IMR_S2_DTIM |
3348 AR_IMR_S2_DTIMSYNC |
3349 AR_IMR_S2_CABEND |
3350 AR_IMR_S2_CABTO |
3351 AR_IMR_S2_TSFOOR |
3352 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3353 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2660b81a 3354 ah->mask_reg = ints;
f078f209 3355
60b67f51 3356 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3357 if (ints & ATH9K_INT_TIM_TIMER)
3358 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3359 else
3360 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3361 }
3362
3363 if (ints & ATH9K_INT_GLOBAL) {
04bd4638 3364 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 3365 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3366 if (!AR_SREV_9100(ah)) {
3367 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3368 AR_INTR_MAC_IRQ);
3369 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3370
3371
3372 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3373 AR_INTR_SYNC_DEFAULT);
3374 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3375 AR_INTR_SYNC_DEFAULT);
3376 }
3377 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3378 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3379 }
3380
3381 return omask;
3382}
3383
f1dc5600
S		 3384/*******************/
3385/* Beacon Handling */
3386/*******************/
3387
cbe61d8a 3388void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 3389{
f078f209
LR		 3390 int flags = 0;
3391
2660b81a 3392 ah->beacon_interval = beacon_period;
f078f209 3393
2660b81a 3394 switch (ah->opmode) {
d97809db
CM		 3395 case NL80211_IFTYPE_STATION:
3396 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 3397 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3398 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3399 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3400 flags |= AR_TBTT_TIMER_EN;
3401 break;
d97809db 3402 case NL80211_IFTYPE_ADHOC:
9cb5412b 3403 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 3404 REG_SET_BIT(ah, AR_TXCFG,
3405 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3406 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3407 TU_TO_USEC(next_beacon +
2660b81a
S		 3408 (ah->atim_window ? ah->
3409 atim_window : 1)));
f078f209 3410 flags |= AR_NDP_TIMER_EN;
d97809db 3411 case NL80211_IFTYPE_AP:
f078f209
LR		 3412 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3413 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3414 TU_TO_USEC(next_beacon -
2660b81a 3415 ah->config.
60b67f51 3416 dma_beacon_response_time));
f078f209
LR		 3417 REG_WRITE(ah, AR_NEXT_SWBA,
3418 TU_TO_USEC(next_beacon -
2660b81a 3419 ah->config.
60b67f51 3420 sw_beacon_response_time));
f078f209
LR		 3421 flags |=
3422 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3423 break;
d97809db
CM		 3424 default:
3425 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3426 "%s: unsupported opmode: %d\n",
2660b81a 3427 __func__, ah->opmode);
d97809db
CM		 3428 return;
3429 break;
f078f209
LR		 3430 }
3431
3432 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3433 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3434 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3435 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3436
3437 beacon_period &= ~ATH9K_BEACON_ENA;
3438 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3439 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3440 ath9k_hw_reset_tsf(ah);
3441 }
3442
3443 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3444}
3445
cbe61d8a 3446void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 3447 const struct ath9k_beacon_state *bs)
f078f209
LR		 3448{
3449 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 3450 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3451
3452 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3453
3454 REG_WRITE(ah, AR_BEACON_PERIOD,
3455 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3456 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3457 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3458
3459 REG_RMW_FIELD(ah, AR_RSSI_THR,
3460 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3461
3462 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3463
3464 if (bs->bs_sleepduration > beaconintval)
3465 beaconintval = bs->bs_sleepduration;
3466
3467 dtimperiod = bs->bs_dtimperiod;
3468 if (bs->bs_sleepduration > dtimperiod)
3469 dtimperiod = bs->bs_sleepduration;
3470
3471 if (beaconintval == dtimperiod)
3472 nextTbtt = bs->bs_nextdtim;
3473 else
3474 nextTbtt = bs->bs_nexttbtt;
3475
04bd4638
S		 3476 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3477 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3478 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3479 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3480
f1dc5600
S		 3481 REG_WRITE(ah, AR_NEXT_DTIM,
3482 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3483 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3484
f1dc5600
S		 3485 REG_WRITE(ah, AR_SLEEP1,
3486 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3487 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3488
f1dc5600
S		 3489 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3490 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3491 else
3492 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3493
f1dc5600
S		 3494 REG_WRITE(ah, AR_SLEEP2,
3495 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3496
f1dc5600
S		 3497 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3498 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3499
f1dc5600
S		 3500 REG_SET_BIT(ah, AR_TIMER_MODE,
3501 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3502 AR_DTIM_TIMER_EN);
f078f209 3503
4af9cf4f
S		 3504 /* TSF Out of Range Threshold */
3505 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209
LR		 3506}
3507
f1dc5600
S		 3508/*******************/
3509/* HW Capabilities */
3510/*******************/
3511
eef7a574 3512void ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 3513{
2660b81a 3514 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 3515 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
22f25d0d 3516 struct ath_btcoex_info *btcoex_info = &ah->ah_sc->btcoex_info;
608b88cb 3517
f1dc5600 3518 u16 capField = 0, eeval;
f078f209 3519
f74df6fb 3520 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 3521 regulatory->current_rd = eeval;
f078f209 3522
f74df6fb 3523 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 3524 if (AR_SREV_9285_10_OR_LATER(ah))
3525 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 3526 regulatory->current_rd_ext = eeval;
f078f209 3527
f74df6fb 3528 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 3529
2660b81a 3530 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 3531 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 3532 if (regulatory->current_rd == 0x64 ||
3533 regulatory->current_rd == 0x65)
3534 regulatory->current_rd += 5;
3535 else if (regulatory->current_rd == 0x41)
3536 regulatory->current_rd = 0x43;
f1dc5600 3537 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
608b88cb 3538 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 3539 }
f078f209 3540
f74df6fb 3541 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
f1dc5600 3542 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3543
f1dc5600
S		 3544 if (eeval & AR5416_OPFLAGS_11A) {
3545 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 3546 if (ah->config.ht_enable) {
f1dc5600
S		 3547 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3548 set_bit(ATH9K_MODE_11NA_HT20,
3549 pCap->wireless_modes);
3550 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3551 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3552 pCap->wireless_modes);
3553 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3554 pCap->wireless_modes);
3555 }
f078f209 3556 }
f078f209
LR		 3557 }
3558
f1dc5600 3559 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 3560 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 3561 if (ah->config.ht_enable) {
f1dc5600
S		 3562 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3563 set_bit(ATH9K_MODE_11NG_HT20,
3564 pCap->wireless_modes);
3565 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3566 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3567 pCap->wireless_modes);
3568 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3569 pCap->wireless_modes);
3570 }
3571 }
f078f209 3572 }
f1dc5600 3573
f74df6fb 3574 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 3575 /*
3576 * For AR9271 we will temporarilly uses the rx chainmax as read from
3577 * the EEPROM.
3578 */
8147f5de 3579 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 3580 !(eeval & AR5416_OPFLAGS_11A) &&
3581 !(AR_SREV_9271(ah)))
3582 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 3583 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3584 else
d7e7d229 3585 /* Use rx_chainmask from EEPROM. */
8147f5de 3586 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 3587
d535a42a 3588 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 3589 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3590
f1dc5600
S		 3591 pCap->low_2ghz_chan = 2312;
3592 pCap->high_2ghz_chan = 2732;
f078f209 3593
f1dc5600
S		 3594 pCap->low_5ghz_chan = 4920;
3595 pCap->high_5ghz_chan = 6100;
f078f209 3596
f1dc5600
S		 3597 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3598 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3599 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3600
f1dc5600
S		 3601 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3602 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3603 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3604
2660b81a 3605 if (ah->config.ht_enable)
f1dc5600
S		 3606 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3607 else
3608 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3609
f1dc5600
S		 3610 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3611 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3612 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3613 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3614
f1dc5600
S		 3615 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3616 pCap->total_queues =
3617 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3618 else
3619 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3620
f1dc5600
S		 3621 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3622 pCap->keycache_size =
3623 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3624 else
3625 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3626
f1dc5600 3627 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f1dc5600 3628 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3629
cb33c412
SB		 3630 if (AR_SREV_9285_10_OR_LATER(ah))
3631 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3632 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3633 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3634 else
3635 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3636
f1dc5600
S		 3637 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3638 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3639 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3640 } else {
3641 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3642 }
3643
f1dc5600
S		 3644 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3645
e97275cb 3646#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 3647 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3648 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3649 ah->rfkill_gpio =
3650 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3651 ah->rfkill_polarity =
3652 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 3653
3654 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3655 }
f1dc5600 3656#endif
f078f209 3657
d535a42a
S		 3658 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3659 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3660 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3661 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
882b7092
VN		 3662 (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3663 (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
f1dc5600 3664 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3665 else
f1dc5600 3666 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3667
e7594072 3668 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3669 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3670 else
3671 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3672
608b88cb 3673 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 3674 pCap->reg_cap =
3675 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3676 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3677 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3678 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3679 } else {
f1dc5600
S		 3680 pCap->reg_cap =
3681 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3682 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3683 }
f078f209 3684
f1dc5600
S		 3685 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3686
3687 pCap->num_antcfg_5ghz =
f74df6fb 3688 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3689 pCap->num_antcfg_2ghz =
f74df6fb 3690 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3691
138ab2e4 3692 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
22f25d0d
VT		 3693 btcoex_info->btactive_gpio = ATH_BTACTIVE_GPIO;
3694 btcoex_info->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3695
3696 if (AR_SREV_9285(ah))
3697 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_3WIRE;
3698 else
3699 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_2WIRE;
3700 } else {
3701 btcoex_info->btcoex_scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 3702 }
f078f209
LR		 3703}
3704
cbe61d8a 3705bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3706 u32 capability, u32 *result)
f078f209 3707{
608b88cb 3708 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 3709 switch (type) {
3710 case ATH9K_CAP_CIPHER:
3711 switch (capability) {
3712 case ATH9K_CIPHER_AES_CCM:
3713 case ATH9K_CIPHER_AES_OCB:
3714 case ATH9K_CIPHER_TKIP:
3715 case ATH9K_CIPHER_WEP:
3716 case ATH9K_CIPHER_MIC:
3717 case ATH9K_CIPHER_CLR:
3718 return true;
3719 default:
3720 return false;
3721 }
3722 case ATH9K_CAP_TKIP_MIC:
3723 switch (capability) {
3724 case 0:
3725 return true;
3726 case 1:
2660b81a 3727 return (ah->sta_id1_defaults &
f1dc5600
S		 3728 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3729 false;
3730 }
3731 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 3732 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 3733 false : true;
f1dc5600
S		 3734 case ATH9K_CAP_DIVERSITY:
3735 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3736 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3737 true : false;
f1dc5600
S		 3738 case ATH9K_CAP_MCAST_KEYSRCH:
3739 switch (capability) {
3740 case 0:
3741 return true;
3742 case 1:
3743 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3744 return false;
3745 } else {
2660b81a 3746 return (ah->sta_id1_defaults &
f1dc5600
S		 3747 AR_STA_ID1_MCAST_KSRCH) ? true :
3748 false;
3749 }
3750 }
3751 return false;
f1dc5600
S		 3752 case ATH9K_CAP_TXPOW:
3753 switch (capability) {
3754 case 0:
3755 return 0;
3756 case 1:
608b88cb 3757 *result = regulatory->power_limit;
f1dc5600
S		 3758 return 0;
3759 case 2:
608b88cb 3760 *result = regulatory->max_power_level;
f1dc5600
S		 3761 return 0;
3762 case 3:
608b88cb 3763 *result = regulatory->tp_scale;
f1dc5600
S		 3764 return 0;
3765 }
3766 return false;
8bd1d07f
SB		 3767 case ATH9K_CAP_DS:
3768 return (AR_SREV_9280_20_OR_LATER(ah) &&
3769 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3770 ? false : true;
f1dc5600
S		 3771 default:
3772 return false;
f078f209 3773 }
f078f209
LR		 3774}
3775
cbe61d8a 3776bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3777 u32 capability, u32 setting, int *status)
f078f209 3778{
f1dc5600 3779 u32 v;
f078f209 3780
f1dc5600
S		 3781 switch (type) {
3782 case ATH9K_CAP_TKIP_MIC:
3783 if (setting)
2660b81a 3784 ah->sta_id1_defaults |=
f1dc5600
S		 3785 AR_STA_ID1_CRPT_MIC_ENABLE;
3786 else
2660b81a 3787 ah->sta_id1_defaults &=
f1dc5600
S		 3788 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3789 return true;
3790 case ATH9K_CAP_DIVERSITY:
3791 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3792 if (setting)
3793 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3794 else
3795 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3796 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3797 return true;
3798 case ATH9K_CAP_MCAST_KEYSRCH:
3799 if (setting)
2660b81a 3800 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3801 else
2660b81a 3802 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3803 return true;
f1dc5600
S		 3804 default:
3805 return false;
f078f209
LR		 3806 }
3807}
3808
f1dc5600
S		 3809/****************************/
3810/* GPIO / RFKILL / Antennae */
3811/****************************/
f078f209 3812
cbe61d8a 3813static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 3814 u32 gpio, u32 type)
3815{
3816 int addr;
3817 u32 gpio_shift, tmp;
f078f209 3818
f1dc5600
S		 3819 if (gpio > 11)
3820 addr = AR_GPIO_OUTPUT_MUX3;
3821 else if (gpio > 5)
3822 addr = AR_GPIO_OUTPUT_MUX2;
3823 else
3824 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3825
f1dc5600 3826 gpio_shift = (gpio % 6) * 5;
f078f209 3827
f1dc5600
S		 3828 if (AR_SREV_9280_20_OR_LATER(ah)
3829 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3830 REG_RMW(ah, addr, (type << gpio_shift),
3831 (0x1f << gpio_shift));
f078f209 3832 } else {
f1dc5600
S		 3833 tmp = REG_READ(ah, addr);
3834 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3835 tmp &= ~(0x1f << gpio_shift);
3836 tmp |= (type << gpio_shift);
3837 REG_WRITE(ah, addr, tmp);
f078f209 3838 }
f078f209
LR		 3839}
3840
cbe61d8a 3841void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 3842{
f1dc5600 3843 u32 gpio_shift;
f078f209 3844
2660b81a 3845 ASSERT(gpio < ah->caps.num_gpio_pins);
f078f209 3846
f1dc5600 3847 gpio_shift = gpio << 1;
f078f209 3848
f1dc5600
S		 3849 REG_RMW(ah,
3850 AR_GPIO_OE_OUT,
3851 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3852 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3853}
3854
cbe61d8a 3855u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 3856{
cb33c412
SB		 3857#define MS_REG_READ(x, y) \
3858 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3859
2660b81a 3860 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 3861 return 0xffffffff;
f078f209 3862
ac88b6ec
VN		 3863 if (AR_SREV_9287_10_OR_LATER(ah))
3864 return MS_REG_READ(AR9287, gpio) != 0;
3865 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 3866 return MS_REG_READ(AR9285, gpio) != 0;
3867 else if (AR_SREV_9280_10_OR_LATER(ah))
3868 return MS_REG_READ(AR928X, gpio) != 0;
3869 else
3870 return MS_REG_READ(AR, gpio) != 0;
f078f209
LR		 3871}
3872
cbe61d8a 3873void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 3874 u32 ah_signal_type)
f078f209 3875{
f1dc5600 3876 u32 gpio_shift;
f078f209 3877
f1dc5600 3878 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3879
f1dc5600 3880 gpio_shift = 2 * gpio;
f078f209 3881
f1dc5600
S		 3882 REG_RMW(ah,
3883 AR_GPIO_OE_OUT,
3884 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3885 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3886}
3887
cbe61d8a 3888void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 3889{
f1dc5600
S		 3890 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3891 AR_GPIO_BIT(gpio));
f078f209
LR		 3892}
3893
cbe61d8a 3894u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 3895{
f1dc5600 3896 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209
LR		 3897}
3898
cbe61d8a 3899void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 3900{
f1dc5600 3901 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209
LR		 3902}
3903
cbe61d8a 3904bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
f1dc5600
S		 3905 enum ath9k_ant_setting settings,
3906 struct ath9k_channel *chan,
3907 u8 *tx_chainmask,
3908 u8 *rx_chainmask,
3909 u8 *antenna_cfgd)
f078f209 3910{
f1dc5600 3911 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
f078f209 3912
f1dc5600
S		 3913 if (AR_SREV_9280(ah)) {
3914 if (!tx_chainmask_cfg) {
f078f209 3915
f1dc5600
S		 3916 tx_chainmask_cfg = *tx_chainmask;
3917 rx_chainmask_cfg = *rx_chainmask;
3918 }
f078f209 3919
f1dc5600
S		 3920 switch (settings) {
3921 case ATH9K_ANT_FIXED_A:
3922 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3923 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3924 *antenna_cfgd = true;
3925 break;
3926 case ATH9K_ANT_FIXED_B:
2660b81a 3927 if (ah->caps.tx_chainmask >
f1dc5600
S		 3928 ATH9K_ANTENNA1_CHAINMASK) {
3929 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3930 }
3931 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3932 *antenna_cfgd = true;
3933 break;
3934 case ATH9K_ANT_VARIABLE:
3935 *tx_chainmask = tx_chainmask_cfg;
3936 *rx_chainmask = rx_chainmask_cfg;
3937 *antenna_cfgd = true;
3938 break;
3939 default:
3940 break;
3941 }
3942 } else {
1cf6873a 3943 ah->config.diversity_control = settings;
f078f209 3944 }
f078f209 3945
f1dc5600 3946 return true;
f078f209
LR		 3947}
3948
f1dc5600
S		 3949/*********************/
3950/* General Operation */
3951/*********************/
3952
cbe61d8a 3953u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 3954{
f1dc5600
S		 3955 u32 bits = REG_READ(ah, AR_RX_FILTER);
3956 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3957
f1dc5600
S		 3958 if (phybits & AR_PHY_ERR_RADAR)
3959 bits |= ATH9K_RX_FILTER_PHYRADAR;
3960 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3961 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3962
f1dc5600 3963 return bits;
f078f209
LR		 3964}
3965
cbe61d8a 3966void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 3967{
f1dc5600 3968 u32 phybits;
f078f209 3969
7ea310be
S		 3970 REG_WRITE(ah, AR_RX_FILTER, bits);
3971
f1dc5600
S		 3972 phybits = 0;
3973 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3974 phybits |= AR_PHY_ERR_RADAR;
3975 if (bits & ATH9K_RX_FILTER_PHYERR)
3976 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3977 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3978
f1dc5600
S		 3979 if (phybits)
3980 REG_WRITE(ah, AR_RXCFG,
3981 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3982 else
3983 REG_WRITE(ah, AR_RXCFG,
3984 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3985}
f078f209 3986
cbe61d8a 3987bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600
S		 3988{
3989 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3990}
f078f209 3991
cbe61d8a 3992bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600
S		 3993{
3994 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3995 return false;
f078f209 3996
f1dc5600 3997 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
f078f209
LR		 3998}
3999
8fbff4b8 4000void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 4001{
608b88cb 4002 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 4003 struct ath9k_channel *chan = ah->curchan;
5f8e077c 4004 struct ieee80211_channel *channel = chan->chan;
f078f209 4005
608b88cb 4006 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 4007
8fbff4b8 4008 ah->eep_ops->set_txpower(ah, chan,
608b88cb 4009 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 4010 channel->max_antenna_gain * 2,
4011 channel->max_power * 2,
4012 min((u32) MAX_RATE_POWER,
608b88cb 4013 (u32) regulatory->power_limit));
6f255425
LR		 4014}
4015
cbe61d8a 4016void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 4017{
ba52da58 4018 memcpy(ah->macaddr, mac, ETH_ALEN);
f078f209
LR		 4019}
4020
cbe61d8a 4021void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 4022{
2660b81a 4023 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209
LR		 4024}
4025
cbe61d8a 4026void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 4027{
f1dc5600
S		 4028 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4029 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209
LR		 4030}
4031
ba52da58 4032void ath9k_hw_setbssidmask(struct ath_softc *sc)
f078f209 4033{
ba52da58
S		 4034 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
4035 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
f078f209
LR		 4036}
4037
ba52da58 4038void ath9k_hw_write_associd(struct ath_softc *sc)
f078f209 4039{
ba52da58
S		 4040 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
4041 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
4042 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 4043}
4044
cbe61d8a 4045u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 4046{
f1dc5600 4047 u64 tsf;
f078f209 4048
f1dc5600
S		 4049 tsf = REG_READ(ah, AR_TSF_U32);
4050 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 4051
f1dc5600
S		 4052 return tsf;
4053}
f078f209 4054
cbe61d8a 4055void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 4056{
27abe060 4057 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 4058 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060
AF		 4059}
4060
cbe61d8a 4061void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 4062{
1b7e528b 4063 ath9k_ps_wakeup(ah->ah_sc);
f9b604f6
GJ		 4064 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4065 AH_TSF_WRITE_TIMEOUT))
4066 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
4067 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4068
f1dc5600 4069 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
1b7e528b 4070 ath9k_ps_restore(ah->ah_sc);
f1dc5600 4071}
f078f209 4072
54e4cec6 4073void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 4074{
f1dc5600 4075 if (setting)
2660b81a 4076 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 4077 else
2660b81a 4078 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 4079}
f078f209 4080
cbe61d8a 4081bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f1dc5600 4082{
f1dc5600 4083 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
04bd4638 4084 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
2660b81a 4085 ah->slottime = (u32) -1;
f1dc5600
S		 4086 return false;
4087 } else {
4088 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
2660b81a 4089 ah->slottime = us;
f1dc5600 4090 return true;
f078f209 4091 }
f1dc5600
S		 4092}
4093
cbe61d8a 4094void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
f1dc5600
S		 4095{
4096 u32 macmode;
4097
4098 if (mode == ATH9K_HT_MACMODE_2040 &&
2660b81a 4099 !ah->config.cwm_ignore_extcca)
f1dc5600
S		 4100 macmode = AR_2040_JOINED_RX_CLEAR;
4101 else
4102 macmode = 0;
f078f209 4103
f1dc5600 4104 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 4105}
ff155a45
VT		 4106
4107/* HW Generic timers configuration */
4108
4109static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4110{
4111 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4112 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4113 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4114 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4115 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4116 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4117 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4118 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4119 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4120 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4121 AR_NDP2_TIMER_MODE, 0x0002},
4122 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4123 AR_NDP2_TIMER_MODE, 0x0004},
4124 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4125 AR_NDP2_TIMER_MODE, 0x0008},
4126 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4127 AR_NDP2_TIMER_MODE, 0x0010},
4128 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4129 AR_NDP2_TIMER_MODE, 0x0020},
4130 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4131 AR_NDP2_TIMER_MODE, 0x0040},
4132 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4133 AR_NDP2_TIMER_MODE, 0x0080}
4134};
4135
4136/* HW generic timer primitives */
4137
4138/* compute and clear index of rightmost 1 */
4139static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4140{
4141 u32 b;
4142
4143 b = *mask;
4144 b &= (0-b);
4145 *mask &= ~b;
4146 b *= debruijn32;
4147 b >>= 27;
4148
4149 return timer_table->gen_timer_index[b];
4150}
4151
1773912b 4152u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 4153{
4154 return REG_READ(ah, AR_TSF_L32);
4155}
4156
4157struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4158 void (*trigger)(void *),
4159 void (*overflow)(void *),
4160 void *arg,
4161 u8 timer_index)
4162{
4163 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4164 struct ath_gen_timer *timer;
4165
4166 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4167
4168 if (timer == NULL) {
4169 printk(KERN_DEBUG "Failed to allocate memory"
4170 "for hw timer[%d]\n", timer_index);
4171 return NULL;
4172 }
4173
4174 /* allocate a hardware generic timer slot */
4175 timer_table->timers[timer_index] = timer;
4176 timer->index = timer_index;
4177 timer->trigger = trigger;
4178 timer->overflow = overflow;
4179 timer->arg = arg;
4180
4181 return timer;
4182}
4183
4184void ath_gen_timer_start(struct ath_hw *ah,
4185 struct ath_gen_timer *timer,
4186 u32 timer_next, u32 timer_period)
4187{
4188 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4189 u32 tsf;
4190
4191 BUG_ON(!timer_period);
4192
4193 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4194
4195 tsf = ath9k_hw_gettsf32(ah);
4196
4197 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, "curent tsf %x period %x"
4198 "timer_next %x\n", tsf, timer_period, timer_next);
4199
4200 /*
4201 * Pull timer_next forward if the current TSF already passed it
4202 * because of software latency
4203 */
4204 if (timer_next < tsf)
4205 timer_next = tsf + timer_period;
4206
4207 /*
4208 * Program generic timer registers
4209 */
4210 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4211 timer_next);
4212 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4213 timer_period);
4214 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4215 gen_tmr_configuration[timer->index].mode_mask);
4216
4217 /* Enable both trigger and thresh interrupt masks */
4218 REG_SET_BIT(ah, AR_IMR_S5,
4219 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4220 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4221
4222 if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
4223 ath9k_hw_set_interrupts(ah, 0);
4224 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
4225 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4226 }
4227}
4228
4229void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4230{
4231 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4232
4233 if ((timer->index < AR_FIRST_NDP_TIMER) ||
4234 (timer->index >= ATH_MAX_GEN_TIMER)) {
4235 return;
4236 }
4237
4238 /* Clear generic timer enable bits. */
4239 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4240 gen_tmr_configuration[timer->index].mode_mask);
4241
4242 /* Disable both trigger and thresh interrupt masks */
4243 REG_CLR_BIT(ah, AR_IMR_S5,
4244 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4245 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4246
4247 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4248
4249 /* if no timer is enabled, turn off interrupt mask */
4250 if (timer_table->timer_mask.val == 0) {
4251 ath9k_hw_set_interrupts(ah, 0);
4252 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
4253 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4254 }
4255}
4256
4257void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4258{
4259 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4260
4261 /* free the hardware generic timer slot */
4262 timer_table->timers[timer->index] = NULL;
4263 kfree(timer);
4264}
4265
4266/*
4267 * Generic Timer Interrupts handling
4268 */
4269void ath_gen_timer_isr(struct ath_hw *ah)
4270{
4271 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4272 struct ath_gen_timer *timer;
4273 u32 trigger_mask, thresh_mask, index;
4274
4275 /* get hardware generic timer interrupt status */
4276 trigger_mask = ah->intr_gen_timer_trigger;
4277 thresh_mask = ah->intr_gen_timer_thresh;
4278 trigger_mask &= timer_table->timer_mask.val;
4279 thresh_mask &= timer_table->timer_mask.val;
4280
4281 trigger_mask &= ~thresh_mask;
4282
4283 while (thresh_mask) {
4284 index = rightmost_index(timer_table, &thresh_mask);
4285 timer = timer_table->timers[index];
4286 BUG_ON(!timer);
4287 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER,
4288 "TSF overflow for Gen timer %d\n", index);
4289 timer->overflow(timer->arg);
4290 }
4291
4292 while (trigger_mask) {
4293 index = rightmost_index(timer_table, &trigger_mask);
4294 timer = timer_table->timers[index];
4295 BUG_ON(!timer);
4296 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER,
4297 "Gen timer[%d] trigger\n", index);
4298 timer->trigger(timer->arg);
4299 }
4300}
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