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ath9k: free GPIO resource for SOC GPIOs
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
5ca06ebe 22#include <linux/etherdevice.h>
61b559de 23#include <linux/gpio.h>
f078f209
LR		 24#include <asm/unaligned.h>
25
af03abec 26#include "hw.h"
d70357d5 27#include "hw-ops.h"
b622a720 28#include "ar9003_mac.h"
f4701b5a 29#include "ar9003_mci.h"
362cd03f 30#include "ar9003_phy.h"
462e58f2 31#include "ath9k.h"
f078f209 32
cbe61d8a 33static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 34
7322fd19
LR		 35MODULE_AUTHOR("Atheros Communications");
36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38MODULE_LICENSE("Dual BSD/GPL");
39
dfdac8ac 40static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 41{
dfdac8ac 42 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 43 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 44 unsigned int clockrate;
cbe61d8a 45
087b6ff6
FF		 46 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
48 clockrate = 117;
e4744ec7 49 else if (!chan) /* should really check for CCK instead */
dfdac8ac 50 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 51 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 52 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
54 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 55 else
dfdac8ac
FF		 56 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
57
beae416b
MN		 58 if (chan) {
59 if (IS_CHAN_HT40(chan))
60 clockrate *= 2;
e4744ec7 61 if (IS_CHAN_HALF_RATE(chan))
906c7205 62 clockrate /= 2;
e4744ec7 63 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 64 clockrate /= 4;
65 }
66
dfdac8ac 67 common->clockrate = clockrate;
f1dc5600
S		 68}
69
cbe61d8a 70static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 71{
dfdac8ac 72 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 73
dfdac8ac 74 return usecs * common->clockrate;
f1dc5600 75}
f078f209 76
0caa7b14 77bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 78{
79 int i;
80
0caa7b14
S		 81 BUG_ON(timeout < AH_TIME_QUANTUM);
82
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 84 if ((REG_READ(ah, reg) & mask) == val)
85 return true;
86
87 udelay(AH_TIME_QUANTUM);
88 }
04bd4638 89
d2182b69 90 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
92 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 93
f1dc5600 94 return false;
f078f209 95}
7322fd19 96EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 97
7c5adc8d
FF		 98void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
99 int hw_delay)
100{
1a5e6326 101 hw_delay /= 10;
7c5adc8d
FF		 102
103 if (IS_CHAN_HALF_RATE(chan))
104 hw_delay *= 2;
105 else if (IS_CHAN_QUARTER_RATE(chan))
106 hw_delay *= 4;
107
108 udelay(hw_delay + BASE_ACTIVATE_DELAY);
109}
110
0166b4be 111void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 112 int column, unsigned int *writecnt)
113{
114 int r;
115
116 ENABLE_REGWRITE_BUFFER(ah);
117 for (r = 0; r < array->ia_rows; r++) {
118 REG_WRITE(ah, INI_RA(array, r, 0),
119 INI_RA(array, r, column));
120 DO_DELAY(*writecnt);
121 }
122 REGWRITE_BUFFER_FLUSH(ah);
123}
124
a57cb45a
OR		 125void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
126{
127 u32 *tmp_reg_list, *tmp_data;
128 int i;
129
130 tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL);
131 if (!tmp_reg_list) {
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
133 return;
134 }
135
136 tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL);
137 if (!tmp_data) {
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
139 goto error_tmp_data;
140 }
141
142 for (i = 0; i < size; i++)
143 tmp_reg_list[i] = array[i][0];
144
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
146
147 for (i = 0; i < size; i++)
148 array[i][1] = tmp_data[i];
149
150 kfree(tmp_data);
151error_tmp_data:
152 kfree(tmp_reg_list);
153}
154
f078f209
LR		 155u32 ath9k_hw_reverse_bits(u32 val, u32 n)
156{
157 u32 retval;
158 int i;
159
160 for (i = 0, retval = 0; i < n; i++) {
161 retval = (retval << 1) | (val & 1);
162 val >>= 1;
163 }
164 return retval;
165}
166
cbe61d8a 167u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 168 u8 phy, int kbps,
f1dc5600
S		 169 u32 frameLen, u16 rateix,
170 bool shortPreamble)
f078f209 171{
f1dc5600 172 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 173
f1dc5600
S		 174 if (kbps == 0)
175 return 0;
f078f209 176
545750d3 177 switch (phy) {
46d14a58 178 case WLAN_RC_PHY_CCK:
f1dc5600 179 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 180 if (shortPreamble)
f1dc5600
S		 181 phyTime >>= 1;
182 numBits = frameLen << 3;
183 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
184 break;
46d14a58 185 case WLAN_RC_PHY_OFDM:
2660b81a 186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_QUARTER
191 + OFDM_PREAMBLE_TIME_QUARTER
192 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 193 } else if (ah->curchan &&
194 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 195 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
196 numBits = OFDM_PLCP_BITS + (frameLen << 3);
197 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
198 txTime = OFDM_SIFS_TIME_HALF +
199 OFDM_PREAMBLE_TIME_HALF
200 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
201 } else {
202 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
203 numBits = OFDM_PLCP_BITS + (frameLen << 3);
204 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
205 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
206 + (numSymbols * OFDM_SYMBOL_TIME);
207 }
208 break;
209 default:
3800276a
JP		 210 ath_err(ath9k_hw_common(ah),
211 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 212 txTime = 0;
213 break;
214 }
f078f209 215
f1dc5600
S		 216 return txTime;
217}
7322fd19 218EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 219
cbe61d8a 220void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 221 struct ath9k_channel *chan,
222 struct chan_centers *centers)
f078f209 223{
f1dc5600 224 int8_t extoff;
f078f209 225
f1dc5600
S		 226 if (!IS_CHAN_HT40(chan)) {
227 centers->ctl_center = centers->ext_center =
228 centers->synth_center = chan->channel;
229 return;
f078f209 230 }
f078f209 231
8896934c 232 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 233 centers->synth_center =
234 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
235 extoff = 1;
236 } else {
237 centers->synth_center =
238 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
239 extoff = -1;
240 }
f078f209 241
f1dc5600
S		 242 centers->ctl_center =
243 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 244 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 245 centers->ext_center =
6420014c 246 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 247}
248
f1dc5600
S		 249/******************/
250/* Chip Revisions */
251/******************/
252
cbe61d8a 253static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 254{
f1dc5600 255 u32 val;
f078f209 256
09c74f7b
FF		 257 if (ah->get_mac_revision)
258 ah->hw_version.macRev = ah->get_mac_revision();
259
ecb1d385
VT		 260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
263 break;
3762561a
GJ		 264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
09c74f7b 266 if (!ah->get_mac_revision) {
3762561a
GJ		 267 val = REG_READ(ah, AR_SREV);
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
269 }
270 return;
ecb1d385
VT		 271 case AR9300_DEVID_AR9340:
272 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
ecb1d385 273 return;
813831dc
GJ		 274 case AR9300_DEVID_QCA955X:
275 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
276 return;
e6b1e46e
SM		 277 case AR9300_DEVID_AR953X:
278 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
279 return;
2131fabb
MP		 280 case AR9300_DEVID_QCA956X:
281 ah->hw_version.macVersion = AR_SREV_VERSION_9561;
7865598e 282 return;
ecb1d385
VT		 283 }
284
f1dc5600 285 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 286
f1dc5600
S		 287 if (val == 0xFF) {
288 val = REG_READ(ah, AR_SREV);
d535a42a
S		 289 ah->hw_version.macVersion =
290 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
291 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 292
77fac465 293 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 294 ah->is_pciexpress = true;
295 else
296 ah->is_pciexpress = (val &
297 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 298 } else {
299 if (!AR_SREV_9100(ah))
d535a42a 300 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 301
d535a42a 302 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 303
d535a42a 304 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 305 ah->is_pciexpress = true;
f1dc5600 306 }
f078f209
LR		 307}
308
f1dc5600
S		 309/************************************/
310/* HW Attach, Detach, Init Routines */
311/************************************/
312
cbe61d8a 313static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 314{
040b74f7 315 if (!AR_SREV_5416(ah))
f1dc5600 316 return;
f078f209 317
f1dc5600
S		 318 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
325 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 327
f1dc5600 328 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 329}
330
1f3f0618 331/* This should work for all families including legacy */
cbe61d8a 332static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 333{
c46917bb 334 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 335 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 336 u32 regHold[2];
07b2fa5a
JP		 337 static const u32 patternData[4] = {
338 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
339 };
1f3f0618 340 int i, j, loop_max;
f078f209 341
1f3f0618
SB		 342 if (!AR_SREV_9300_20_OR_LATER(ah)) {
343 loop_max = 2;
344 regAddr[1] = AR_PHY_BASE + (8 << 2);
345 } else
346 loop_max = 1;
347
348 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 349 u32 addr = regAddr[i];
350 u32 wrData, rdData;
f078f209 351
f1dc5600
S		 352 regHold[i] = REG_READ(ah, addr);
353 for (j = 0; j < 0x100; j++) {
354 wrData = (j << 16) | j;
355 REG_WRITE(ah, addr, wrData);
356 rdData = REG_READ(ah, addr);
357 if (rdData != wrData) {
3800276a
JP		 358 ath_err(common,
359 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
360 addr, wrData, rdData);
f1dc5600
S		 361 return false;
362 }
363 }
364 for (j = 0; j < 4; j++) {
365 wrData = patternData[j];
366 REG_WRITE(ah, addr, wrData);
367 rdData = REG_READ(ah, addr);
368 if (wrData != rdData) {
3800276a
JP		 369 ath_err(common,
370 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
371 addr, wrData, rdData);
f1dc5600
S		 372 return false;
373 }
f078f209 374 }
f1dc5600 375 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 376 }
f1dc5600 377 udelay(100);
cbe61d8a 378
f078f209
LR		 379 return true;
380}
381
b8b0f377 382static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 383{
f57cf939
SM		 384 struct ath_common *common = ath9k_hw_common(ah);
385
689e756f
FF		 386 ah->config.dma_beacon_response_time = 1;
387 ah->config.sw_beacon_response_time = 6;
621a5f7a 388 ah->config.cwm_ignore_extcca = false;
2660b81a 389 ah->config.analog_shiftreg = 1;
f078f209 390
0ce024cb 391 ah->config.rx_intr_mitigation = true;
6158425b 392
a64e1a45
SM		 393 if (AR_SREV_9300_20_OR_LATER(ah)) {
394 ah->config.rimt_last = 500;
395 ah->config.rimt_first = 2000;
396 } else {
397 ah->config.rimt_last = 250;
398 ah->config.rimt_first = 700;
399 }
400
656cd75c
SM		 401 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
402 ah->config.pll_pwrsave = 7;
403
6158425b
LR		 404 /*
405 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
406 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
407 * This means we use it for all AR5416 devices, and the few
408 * minor PCI AR9280 devices out there.
409 *
410 * Serialization is required because these devices do not handle
411 * well the case of two concurrent reads/writes due to the latency
412 * involved. During one read/write another read/write can be issued
413 * on another CPU while the previous read/write may still be working
414 * on our hardware, if we hit this case the hardware poops in a loop.
415 * We prevent this by serializing reads and writes.
416 *
417 * This issue is not present on PCI-Express devices or pre-AR5416
418 * devices (legacy, 802.11abg).
419 */
420 if (num_possible_cpus() > 1)
2d6a5e95 421 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f57cf939
SM		 422
423 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
424 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
425 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
426 !ah->is_pciexpress)) {
427 ah->config.serialize_regmode = SER_REG_MODE_ON;
428 } else {
429 ah->config.serialize_regmode = SER_REG_MODE_OFF;
430 }
431 }
432
433 ath_dbg(common, RESET, "serialize_regmode is %d\n",
434 ah->config.serialize_regmode);
435
436 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
437 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
438 else
439 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
f078f209
LR		 440}
441
50aca25b 442static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 443{
608b88cb
LR		 444 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
445
446 regulatory->country_code = CTRY_DEFAULT;
447 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 448
d535a42a 449 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 450 ah->hw_version.subvendorid = 0;
f078f209 451
f57cf939
SM		 452 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
453 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 454 if (AR_SREV_9100(ah))
455 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
f57cf939 456
e3f2acc7 457 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 458 ah->globaltxtimeout = (u32) -1;
cbdec975 459 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 460 ah->htc_reset_init = true;
f57cf939 461
c09396eb 462 ah->tpc_enabled = false;
a9abe302 463
f57cf939
SM		 464 ah->ani_function = ATH9K_ANI_ALL;
465 if (!AR_SREV_9300_20_OR_LATER(ah))
466 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
467
468 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
469 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
470 else
471 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209
LR		 472}
473
cbe61d8a 474static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 475{
1510718d 476 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 477 u32 sum;
478 int i;
479 u16 eeval;
07b2fa5a 480 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 481
482 sum = 0;
483 for (i = 0; i < 3; i++) {
49101676 484 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 485 sum += eeval;
1510718d
LR		 486 common->macaddr[2 * i] = eeval >> 8;
487 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 488 }
5ca06ebe
FF		 489 if (!is_valid_ether_addr(common->macaddr)) {
490 ath_err(common,
491 "eeprom contains invalid mac address: %pM\n",
492 common->macaddr);
493
494 random_ether_addr(common->macaddr);
495 ath_err(common,
496 "random mac address will be used: %pM\n",
497 common->macaddr);
498 }
f078f209
LR		 499
500 return 0;
501}
502
f637cfd6 503static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 504{
6cae913d 505 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 506 int ecode;
f078f209 507
6cae913d 508 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 509 if (!ath9k_hw_chip_test(ah))
510 return -ENODEV;
511 }
f078f209 512
ebd5a14a
LR		 513 if (!AR_SREV_9300_20_OR_LATER(ah)) {
514 ecode = ar9002_hw_rf_claim(ah);
515 if (ecode != 0)
516 return ecode;
517 }
f078f209 518
f637cfd6 519 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 520 if (ecode != 0)
521 return ecode;
7d01b221 522
d2182b69 523 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 524 ah->eep_ops->get_eeprom_ver(ah),
525 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 526
e323300d 527 ath9k_hw_ani_init(ah);
f078f209 528
d3b371cb
SM		 529 /*
530 * EEPROM needs to be initialized before we do this.
531 * This is required for regulatory compliance.
532 */
0c7c2bb4 533 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 534 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
535 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 536 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
537 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 538 }
539 }
540
f078f209
LR		 541 return 0;
542}
543
c1b976d2 544static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 545{
c1b976d2
FF		 546 if (!AR_SREV_9300_20_OR_LATER(ah))
547 return ar9002_hw_attach_ops(ah);
548
549 ar9003_hw_attach_ops(ah);
550 return 0;
aa4058ae
LR		 551}
552
d70357d5
LR		 553/* Called for all hardware families */
554static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 555{
c46917bb 556 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 557 int r = 0;
aa4058ae 558
ac45c12d
SB		 559 ath9k_hw_read_revisions(ah);
560
de82582b
SM		 561 switch (ah->hw_version.macVersion) {
562 case AR_SREV_VERSION_5416_PCI:
563 case AR_SREV_VERSION_5416_PCIE:
564 case AR_SREV_VERSION_9160:
565 case AR_SREV_VERSION_9100:
566 case AR_SREV_VERSION_9280:
567 case AR_SREV_VERSION_9285:
568 case AR_SREV_VERSION_9287:
569 case AR_SREV_VERSION_9271:
570 case AR_SREV_VERSION_9300:
571 case AR_SREV_VERSION_9330:
572 case AR_SREV_VERSION_9485:
573 case AR_SREV_VERSION_9340:
574 case AR_SREV_VERSION_9462:
575 case AR_SREV_VERSION_9550:
576 case AR_SREV_VERSION_9565:
e6b1e46e 577 case AR_SREV_VERSION_9531:
2131fabb 578 case AR_SREV_VERSION_9561:
de82582b
SM		 579 break;
580 default:
581 ath_err(common,
582 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
583 ah->hw_version.macVersion, ah->hw_version.macRev);
584 return -EOPNOTSUPP;
585 }
586
0a8d7cb0
SB		 587 /*
588 * Read back AR_WA into a permanent copy and set bits 14 and 17.
589 * We need to do this to avoid RMW of this register. We cannot
590 * read the reg when chip is asleep.
591 */
27251e00
SM		 592 if (AR_SREV_9300_20_OR_LATER(ah)) {
593 ah->WARegVal = REG_READ(ah, AR_WA);
594 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
595 AR_WA_ASPM_TIMER_BASED_DISABLE);
596 }
0a8d7cb0 597
aa4058ae 598 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 599 ath_err(common, "Couldn't reset chip\n");
95fafca2 600 return -EIO;
aa4058ae
LR		 601 }
602
a4a2954f
SM		 603 if (AR_SREV_9565(ah)) {
604 ah->WARegVal |= AR_WA_BIT22;
605 REG_WRITE(ah, AR_WA, ah->WARegVal);
606 }
607
bab1f62e
LR		 608 ath9k_hw_init_defaults(ah);
609 ath9k_hw_init_config(ah);
610
c1b976d2
FF		 611 r = ath9k_hw_attach_ops(ah);
612 if (r)
613 return r;
d70357d5 614
9ecdef4b 615 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 616 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 617 return -EIO;
aa4058ae
LR		 618 }
619
2c8e5937 620 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 621 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 622 ah->is_pciexpress = false;
623
aa4058ae 624 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 625 ath9k_hw_init_cal_settings(ah);
626
69ce674b 627 if (!ah->is_pciexpress)
aa4058ae
LR		 628 ath9k_hw_disablepcie(ah);
629
f637cfd6 630 r = ath9k_hw_post_init(ah);
aa4058ae 631 if (r)
95fafca2 632 return r;
aa4058ae
LR		 633
634 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 635 r = ath9k_hw_fill_cap_info(ah);
636 if (r)
637 return r;
638
4f3acf81
LR		 639 r = ath9k_hw_init_macaddr(ah);
640 if (r) {
3800276a 641 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 642 return r;
f078f209
LR		 643 }
644
4598702d 645 ath9k_hw_init_hang_checks(ah);
f078f209 646
211f5859
LR		 647 common->state = ATH_HW_INITIALIZED;
648
4f3acf81 649 return 0;
f078f209
LR		 650}
651
d70357d5 652int ath9k_hw_init(struct ath_hw *ah)
f078f209 653{
d70357d5
LR		 654 int ret;
655 struct ath_common *common = ath9k_hw_common(ah);
f078f209 656
77fac465 657 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 658 switch (ah->hw_version.devid) {
659 case AR5416_DEVID_PCI:
660 case AR5416_DEVID_PCIE:
661 case AR5416_AR9100_DEVID:
662 case AR9160_DEVID_PCI:
663 case AR9280_DEVID_PCI:
664 case AR9280_DEVID_PCIE:
665 case AR9285_DEVID_PCIE:
db3cc53a
SB		 666 case AR9287_DEVID_PCI:
667 case AR9287_DEVID_PCIE:
d70357d5 668 case AR2427_DEVID_PCIE:
db3cc53a 669 case AR9300_DEVID_PCIE:
3050c914 670 case AR9300_DEVID_AR9485_PCIE:
999a7a88 671 case AR9300_DEVID_AR9330:
bca04689 672 case AR9300_DEVID_AR9340:
2b943a33 673 case AR9300_DEVID_QCA955X:
5a63ef0f 674 case AR9300_DEVID_AR9580:
423e38e8 675 case AR9300_DEVID_AR9462:
d4e5979c 676 case AR9485_DEVID_AR1111:
77fac465 677 case AR9300_DEVID_AR9565:
e6b1e46e 678 case AR9300_DEVID_AR953X:
2131fabb 679 case AR9300_DEVID_QCA956X:
d70357d5
LR		 680 break;
681 default:
682 if (common->bus_ops->ath_bus_type == ATH_USB)
683 break;
3800276a
JP		 684 ath_err(common, "Hardware device ID 0x%04x not supported\n",
685 ah->hw_version.devid);
d70357d5
LR		 686 return -EOPNOTSUPP;
687 }
f078f209 688
d70357d5
LR		 689 ret = __ath9k_hw_init(ah);
690 if (ret) {
3800276a
JP		 691 ath_err(common,
692 "Unable to initialize hardware; initialization status: %d\n",
693 ret);
d70357d5
LR		 694 return ret;
695 }
f078f209 696
c774d57f
LB		 697 ath_dynack_init(ah);
698
d70357d5 699 return 0;
f078f209 700}
d70357d5 701EXPORT_SYMBOL(ath9k_hw_init);
f078f209 702
cbe61d8a 703static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 704{
7d0d0df0
S		 705 ENABLE_REGWRITE_BUFFER(ah);
706
f1dc5600
S		 707 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
708 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 709
f1dc5600
S		 710 REG_WRITE(ah, AR_QOS_NO_ACK,
711 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
712 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
713 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
714
715 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
716 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
717 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
718 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
719 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 720
721 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 722}
723
b84628eb 724u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 725{
f18e3c6b
MSS		 726 struct ath_common *common = ath9k_hw_common(ah);
727 int i = 0;
728
ca7a4deb
FF		 729 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
730 udelay(100);
731 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 732
f18e3c6b
MSS		 733 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
734
ca7a4deb 735 udelay(100);
b1415819 736
f18e3c6b
MSS		 737 if (WARN_ON_ONCE(i >= 100)) {
738 ath_err(common, "PLL4 meaurement not done\n");
739 break;
740 }
741
742 i++;
743 }
744
ca7a4deb 745 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 746}
747EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
748
cbe61d8a 749static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 750 struct ath9k_channel *chan)
f078f209 751{
d09b17f7
VT		 752 u32 pll;
753
5fb9b1b9
FF		 754 pll = ath9k_hw_compute_pll_control(ah, chan);
755
a4a2954f 756 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 757 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
758 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
759 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
760 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
761 AR_CH0_DPLL2_KD, 0x40);
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
763 AR_CH0_DPLL2_KI, 0x4);
22983c30 764
3dfd7f60
VT		 765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
766 AR_CH0_BB_DPLL1_REFDIV, 0x5);
767 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
768 AR_CH0_BB_DPLL1_NINI, 0x58);
769 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
770 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 771
772 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 773 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
774 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
775 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 776 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 777 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 778
3dfd7f60 779 /* program BB PLL phase_shift to 0x6 */
22983c30 780 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 781 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
782
783 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
784 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 785 udelay(1000);
a5415d62
GJ		 786 } else if (AR_SREV_9330(ah)) {
787 u32 ddr_dpll2, pll_control2, kd;
788
789 if (ah->is_clk_25mhz) {
790 ddr_dpll2 = 0x18e82f01;
791 pll_control2 = 0xe04a3d;
792 kd = 0x1d;
793 } else {
794 ddr_dpll2 = 0x19e82f01;
795 pll_control2 = 0x886666;
796 kd = 0x3d;
797 }
798
799 /* program DDR PLL ki and kd value */
800 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
801
802 /* program DDR PLL phase_shift */
803 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
804 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
805
5fb9b1b9
FF		 806 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
807 pll | AR_RTC_9300_PLL_BYPASS);
a5415d62
GJ		 808 udelay(1000);
809
810 /* program refdiv, nint, frac to RTC register */
811 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
812
813 /* program BB PLL kd and ki value */
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
815 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
816
817 /* program BB PLL phase_shift */
818 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
819 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
ede6a5e7
MP		 820 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
821 AR_SREV_9561(ah)) {
0b488ac6
VT		 822 u32 regval, pll2_divint, pll2_divfrac, refdiv;
823
5fb9b1b9
FF		 824 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
825 pll | AR_RTC_9300_SOC_PLL_BYPASS);
0b488ac6
VT		 826 udelay(1000);
827
828 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
829 udelay(100);
830
831 if (ah->is_clk_25mhz) {
ede6a5e7 832 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
2c323058
SM		 833 pll2_divint = 0x1c;
834 pll2_divfrac = 0xa3d2;
835 refdiv = 1;
836 } else {
837 pll2_divint = 0x54;
838 pll2_divfrac = 0x1eb85;
839 refdiv = 3;
840 }
0b488ac6 841 } else {
fc05a317
GJ		 842 if (AR_SREV_9340(ah)) {
843 pll2_divint = 88;
844 pll2_divfrac = 0;
845 refdiv = 5;
846 } else {
847 pll2_divint = 0x11;
ede6a5e7
MP		 848 pll2_divfrac = (AR_SREV_9531(ah) ||
849 AR_SREV_9561(ah)) ?
850 0x26665 : 0x26666;
fc05a317
GJ		 851 refdiv = 1;
852 }
0b488ac6
VT		 853 }
854
855 regval = REG_READ(ah, AR_PHY_PLL_MODE);
ede6a5e7 856 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
2c323058
SM		 857 regval |= (0x1 << 22);
858 else
859 regval |= (0x1 << 16);
0b488ac6
VT		 860 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
861 udelay(100);
862
863 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
864 (pll2_divint << 18) | pll2_divfrac);
865 udelay(100);
866
867 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317 868 if (AR_SREV_9340(ah))
2c323058
SM		 869 regval = (regval & 0x80071fff) |
870 (0x1 << 30) |
871 (0x1 << 13) |
872 (0x4 << 26) |
873 (0x18 << 19);
ede6a5e7 874 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
2c323058
SM		 875 regval = (regval & 0x01c00fff) |
876 (0x1 << 31) |
877 (0x2 << 29) |
878 (0xa << 25) |
ede6a5e7
MP		 879 (0x1 << 19);
880
881 if (AR_SREV_9531(ah))
882 regval |= (0x6 << 12);
883 } else
2c323058
SM		 884 regval = (regval & 0x80071fff) |
885 (0x3 << 30) |
886 (0x1 << 13) |
887 (0x4 << 26) |
888 (0x60 << 19);
0b488ac6 889 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
2c323058 890
ede6a5e7 891 if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
2c323058
SM		 892 REG_WRITE(ah, AR_PHY_PLL_MODE,
893 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
894 else
895 REG_WRITE(ah, AR_PHY_PLL_MODE,
896 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
897
0b488ac6 898 udelay(1000);
22983c30 899 }
d09b17f7 900
8565f8bf
SM		 901 if (AR_SREV_9565(ah))
902 pll |= 0x40000;
d03a66c1 903 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 904
fc05a317
GJ		 905 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
906 AR_SREV_9550(ah))
3dfd7f60
VT		 907 udelay(1000);
908
c75724d1
LR		 909 /* Switch the core clock for ar9271 to 117Mhz */
910 if (AR_SREV_9271(ah)) {
25e2ab17
S		 911 udelay(500);
912 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 913 }
914
f1dc5600
S		 915 udelay(RTC_PLL_SETTLE_DELAY);
916
917 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 918}
919
cbe61d8a 920static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 921 enum nl80211_iftype opmode)
f078f209 922{
79d1d2b8 923 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 924 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 925 AR_IMR_TXURN |
926 AR_IMR_RXERR |
927 AR_IMR_RXORN |
928 AR_IMR_BCNMISC;
f078f209 929
ede6a5e7
MP		 930 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
931 AR_SREV_9561(ah))
79d1d2b8
VT		 932 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
933
66860240
VT		 934 if (AR_SREV_9300_20_OR_LATER(ah)) {
935 imr_reg |= AR_IMR_RXOK_HP;
936 if (ah->config.rx_intr_mitigation)
937 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
938 else
939 imr_reg |= AR_IMR_RXOK_LP;
f078f209 940
66860240
VT		 941 } else {
942 if (ah->config.rx_intr_mitigation)
943 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
944 else
945 imr_reg |= AR_IMR_RXOK;
946 }
f078f209 947
66860240
VT		 948 if (ah->config.tx_intr_mitigation)
949 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
950 else
951 imr_reg |= AR_IMR_TXOK;
f078f209 952
7d0d0df0
S		 953 ENABLE_REGWRITE_BUFFER(ah);
954
152d530d 955 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 956 ah->imrs2_reg |= AR_IMR_S2_GTT;
957 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 958
f1dc5600
S		 959 if (!AR_SREV_9100(ah)) {
960 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 961 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 962 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
963 }
66860240 964
7d0d0df0 965 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 966
66860240
VT		 967 if (AR_SREV_9300_20_OR_LATER(ah)) {
968 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
969 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
970 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
971 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
972 }
f078f209
LR		 973}
974
b6ba41bb
FF		 975static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
976{
977 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
978 val = min(val, (u32) 0xFFFF);
979 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
980}
981
8e15e094 982void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 983{
0005baf4
FF		 984 u32 val = ath9k_hw_mac_to_clks(ah, us);
985 val = min(val, (u32) 0xFFFF);
986 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 987}
988
8e15e094 989void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 990{
0005baf4
FF		 991 u32 val = ath9k_hw_mac_to_clks(ah, us);
992 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
993 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
994}
995
8e15e094 996void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
0005baf4
FF		 997{
998 u32 val = ath9k_hw_mac_to_clks(ah, us);
999 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1000 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 1001}
f1dc5600 1002
cbe61d8a 1003static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1004{
f078f209 1005 if (tu > 0xFFFF) {
d2182b69
JP		 1006 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1007 tu);
2660b81a 1008 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1009 return false;
1010 } else {
1011 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1012 ah->globaltxtimeout = tu;
f078f209
LR		 1013 return true;
1014 }
1015}
1016
0005baf4 1017void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1018{
b6ba41bb 1019 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 1020 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1021 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1022 int slottime;
0005baf4 1023 int sifstime;
b6ba41bb
FF		 1024 int rx_lat = 0, tx_lat = 0, eifs = 0;
1025 u32 reg;
0005baf4 1026
d2182b69 1027 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1028 ah->misc_mode);
f078f209 1029
b6ba41bb
FF		 1030 if (!chan)
1031 return;
1032
2660b81a 1033 if (ah->misc_mode != 0)
ca7a4deb 1034 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1035
81a91d57
RM		 1036 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1037 rx_lat = 41;
1038 else
1039 rx_lat = 37;
b6ba41bb
FF		 1040 tx_lat = 54;
1041
e88e4861
FF		 1042 if (IS_CHAN_5GHZ(chan))
1043 sifstime = 16;
1044 else
1045 sifstime = 10;
1046
b6ba41bb
FF		 1047 if (IS_CHAN_HALF_RATE(chan)) {
1048 eifs = 175;
1049 rx_lat *= 2;
1050 tx_lat *= 2;
1051 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1052 tx_lat += 11;
1053
92367fe7 1054 sifstime = 32;
e115b7ec 1055 ack_offset = 16;
b6ba41bb 1056 slottime = 13;
b6ba41bb
FF		 1057 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1058 eifs = 340;
81a91d57 1059 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1060 tx_lat *= 4;
1061 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1062 tx_lat += 22;
1063
92367fe7 1064 sifstime = 64;
e115b7ec 1065 ack_offset = 32;
b6ba41bb 1066 slottime = 21;
b6ba41bb 1067 } else {
a7be039d
RM		 1068 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1069 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1070 reg = AR_USEC_ASYNC_FIFO;
1071 } else {
1072 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1073 common->clockrate;
1074 reg = REG_READ(ah, AR_USEC);
1075 }
b6ba41bb
FF		 1076 rx_lat = MS(reg, AR_USEC_RX_LAT);
1077 tx_lat = MS(reg, AR_USEC_TX_LAT);
1078
1079 slottime = ah->slottime;
b6ba41bb 1080 }
0005baf4 1081
e239d859 1082 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1083 slottime += 3 * ah->coverage_class;
1084 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1085 ctstimeout = acktimeout;
42c4568a
FF		 1086
1087 /*
1088 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1089 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1090 * This was initially only meant to work around an issue with delayed
1091 * BA frames in some implementations, but it has been found to fix ACK
1092 * timeout issues in other cases as well.
1093 */
e4744ec7 1094 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1095 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1096 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1097 ctstimeout += 48 - sifstime - ah->slottime;
1098 }
1099
7aefa8aa
LB		 1100 if (ah->dynack.enabled) {
1101 acktimeout = ah->dynack.ackto;
1102 ctstimeout = acktimeout;
1103 slottime = (acktimeout - 3) / 2;
1104 } else {
1105 ah->dynack.ackto = acktimeout;
1106 }
1107
b6ba41bb
FF		 1108 ath9k_hw_set_sifs_time(ah, sifstime);
1109 ath9k_hw_setslottime(ah, slottime);
0005baf4 1110 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1111 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1112 if (ah->globaltxtimeout != (u32) -1)
1113 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1114
1115 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1116 REG_RMW(ah, AR_USEC,
1117 (common->clockrate - 1) |
1118 SM(rx_lat, AR_USEC_RX_LAT) |
1119 SM(tx_lat, AR_USEC_TX_LAT),
1120 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1121
f1dc5600 1122}
0005baf4 1123EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1124
285f2dda 1125void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1126{
211f5859
LR		 1127 struct ath_common *common = ath9k_hw_common(ah);
1128
736b3a27 1129 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1130 return;
211f5859 1131
9ecdef4b 1132 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1133}
285f2dda 1134EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1135
f1dc5600
S		 1136/*******/
1137/* INI */
1138/*******/
1139
8fe65368 1140u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1141{
1142 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1143
6b21fd20 1144 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1145 ctl |= CTL_11G;
1146 else
1147 ctl |= CTL_11A;
1148
1149 return ctl;
1150}
1151
f1dc5600
S		 1152/****************************************/
1153/* Reset and Channel Switching Routines */
1154/****************************************/
f1dc5600 1155
cbe61d8a 1156static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1157{
57b32227 1158 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1159 int txbuf_size;
f1dc5600 1160
7d0d0df0
S		 1161 ENABLE_REGWRITE_BUFFER(ah);
1162
d7e7d229
LR		 1163 /*
1164 * set AHB_MODE not to do cacheline prefetches
1165 */
ca7a4deb
FF		 1166 if (!AR_SREV_9300_20_OR_LATER(ah))
1167 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1168
d7e7d229
LR		 1169 /*
1170 * let mac dma reads be in 128 byte chunks
1171 */
ca7a4deb 1172 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1173
7d0d0df0 1174 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1175
d7e7d229
LR		 1176 /*
1177 * Restore TX Trigger Level to its pre-reset value.
1178 * The initial value depends on whether aggregation is enabled, and is
1179 * adjusted whenever underruns are detected.
1180 */
57b32227
FF		 1181 if (!AR_SREV_9300_20_OR_LATER(ah))
1182 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1183
7d0d0df0 1184 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1185
d7e7d229
LR		 1186 /*
1187 * let mac dma writes be in 128 byte chunks
1188 */
ca7a4deb 1189 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1190
d7e7d229
LR		 1191 /*
1192 * Setup receive FIFO threshold to hold off TX activities
1193 */
f1dc5600
S		 1194 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1195
57b32227
FF		 1196 if (AR_SREV_9300_20_OR_LATER(ah)) {
1197 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1198 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1199
1200 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1201 ah->caps.rx_status_len);
1202 }
1203
d7e7d229
LR		 1204 /*
1205 * reduce the number of usable entries in PCU TXBUF to avoid
1206 * wrap around issues.
1207 */
f1dc5600 1208 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1209 /* For AR9285 the number of Fifos are reduced to half.
1210 * So set the usable tx buf size also to half to
1211 * avoid data/delimiter underruns
1212 */
86c157b3
FF		 1213 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1214 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1215 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1216 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1217 } else {
1218 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1219 }
744d4025 1220
86c157b3
FF		 1221 if (!AR_SREV_9271(ah))
1222 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1223
7d0d0df0 1224 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1225
744d4025
VT		 1226 if (AR_SREV_9300_20_OR_LATER(ah))
1227 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1228}
1229
cbe61d8a 1230static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1231{
ca7a4deb
FF		 1232 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1233 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1234
7b37e0d4 1235 ENABLE_REG_RMW_BUFFER(ah);
f1dc5600 1236 switch (opmode) {
d97809db 1237 case NL80211_IFTYPE_ADHOC:
83322eb8
FF		 1238 if (!AR_SREV_9340_13(ah)) {
1239 set |= AR_STA_ID1_ADHOC;
1240 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1241 break;
1242 }
1243 /* fall through */
862a336c 1244 case NL80211_IFTYPE_OCB:
2664d666 1245 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1246 case NL80211_IFTYPE_AP:
1247 set |= AR_STA_ID1_STA_AP;
1248 /* fall through */
d97809db 1249 case NL80211_IFTYPE_STATION:
ca7a4deb 1250 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1251 break;
5f841b41 1252 default:
ca7a4deb
FF		 1253 if (!ah->is_monitoring)
1254 set = 0;
5f841b41 1255 break;
f1dc5600 1256 }
ca7a4deb 1257 REG_RMW(ah, AR_STA_ID1, set, mask);
7b37e0d4 1258 REG_RMW_BUFFER_FLUSH(ah);
f1dc5600
S		 1259}
1260
8fe65368
LR		 1261void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1262 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1263{
1264 u32 coef_exp, coef_man;
1265
1266 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1267 if ((coef_scaled >> coef_exp) & 0x1)
1268 break;
1269
1270 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1271
1272 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1273
1274 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1275 *coef_exponent = coef_exp - 16;
1276}
1277
d7df7a55
SM		 1278/* AR9330 WAR:
1279 * call external reset function to reset WMAC if:
1280 * - doing a cold reset
1281 * - we have pending frames in the TX queues.
1282 */
1283static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1284{
1285 int i, npend = 0;
1286
1287 for (i = 0; i < AR_NUM_QCU; i++) {
1288 npend = ath9k_hw_numtxpending(ah, i);
1289 if (npend)
1290 break;
1291 }
1292
1293 if (ah->external_reset &&
1294 (npend || type == ATH9K_RESET_COLD)) {
1295 int reset_err = 0;
1296
1297 ath_dbg(ath9k_hw_common(ah), RESET,
1298 "reset MAC via external reset\n");
1299
1300 reset_err = ah->external_reset();
1301 if (reset_err) {
1302 ath_err(ath9k_hw_common(ah),
1303 "External reset failed, err=%d\n",
1304 reset_err);
1305 return false;
1306 }
1307
1308 REG_WRITE(ah, AR_RTC_RESET, 1);
1309 }
1310
1311 return true;
1312}
1313
cbe61d8a 1314static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1315{
1316 u32 rst_flags;
1317 u32 tmpReg;
1318
70768496 1319 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1320 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1321 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1322 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1323 }
1324
7d0d0df0
S		 1325 ENABLE_REGWRITE_BUFFER(ah);
1326
9a658d2b
LR		 1327 if (AR_SREV_9300_20_OR_LATER(ah)) {
1328 REG_WRITE(ah, AR_WA, ah->WARegVal);
1329 udelay(10);
1330 }
1331
f1dc5600
S		 1332 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1333 AR_RTC_FORCE_WAKE_ON_INT);
1334
1335 if (AR_SREV_9100(ah)) {
1336 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1337 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1338 } else {
1339 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1340 if (AR_SREV_9340(ah))
1341 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1342 else
1343 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1344 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1345
1346 if (tmpReg) {
42d5bc3f 1347 u32 val;
f1dc5600 1348 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1349
1350 val = AR_RC_HOSTIF;
1351 if (!AR_SREV_9300_20_OR_LATER(ah))
1352 val |= AR_RC_AHB;
1353 REG_WRITE(ah, AR_RC, val);
1354
1355 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1356 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1357
1358 rst_flags = AR_RTC_RC_MAC_WARM;
1359 if (type == ATH9K_RESET_COLD)
1360 rst_flags |= AR_RTC_RC_MAC_COLD;
1361 }
1362
7d95847c 1363 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1364 if (!ath9k_hw_ar9330_reset_war(ah, type))
1365 return false;
7d95847c
GJ		 1366 }
1367
3863495b 1368 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1369 ar9003_mci_check_gpm_offset(ah);
3863495b 1370
466b0f02
MP		 1371 /* DMA HALT added to resolve ar9300 and ar9580 bus error during
1372 * RTC_RC reg read
1373 */
1374 if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
1375 REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1376 ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
1377 20 * AH_WAIT_TIMEOUT);
1378 REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1379 }
1380
d03a66c1 1381 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1382
1383 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1384
4dc78c43
SM		 1385 if (AR_SREV_9300_20_OR_LATER(ah))
1386 udelay(50);
1387 else if (AR_SREV_9100(ah))
3683a07b 1388 mdelay(10);
4dc78c43
SM		 1389 else
1390 udelay(100);
f1dc5600 1391
d03a66c1 1392 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1393 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1394 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1395 return false;
1396 }
1397
1398 if (!AR_SREV_9100(ah))
1399 REG_WRITE(ah, AR_RC, 0);
1400
f1dc5600
S		 1401 if (AR_SREV_9100(ah))
1402 udelay(50);
1403
1404 return true;
1405}
1406
cbe61d8a 1407static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1408{
7d0d0df0
S		 1409 ENABLE_REGWRITE_BUFFER(ah);
1410
9a658d2b
LR		 1411 if (AR_SREV_9300_20_OR_LATER(ah)) {
1412 REG_WRITE(ah, AR_WA, ah->WARegVal);
1413 udelay(10);
1414 }
1415
f1dc5600
S		 1416 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1417 AR_RTC_FORCE_WAKE_ON_INT);
1418
42d5bc3f 1419 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1420 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1421
d03a66c1 1422 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1423
7d0d0df0 1424 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1425
afe36533 1426 udelay(2);
84e2169b
SB		 1427
1428 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1429 REG_WRITE(ah, AR_RC, 0);
1430
d03a66c1 1431 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1432
1433 if (!ath9k_hw_wait(ah,
1434 AR_RTC_STATUS,
1435 AR_RTC_STATUS_M,
0caa7b14
S		 1436 AR_RTC_STATUS_ON,
1437 AH_WAIT_TIMEOUT)) {
d2182b69 1438 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1439 return false;
f078f209
LR		 1440 }
1441
f1dc5600
S		 1442 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1443}
1444
cbe61d8a 1445static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1446{
7a9233ff 1447 bool ret = false;
2577c6e8 1448
9a658d2b
LR		 1449 if (AR_SREV_9300_20_OR_LATER(ah)) {
1450 REG_WRITE(ah, AR_WA, ah->WARegVal);
1451 udelay(10);
1452 }
1453
f1dc5600
S		 1454 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1455 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1456
ceb26a60
FF		 1457 if (!ah->reset_power_on)
1458 type = ATH9K_RESET_POWER_ON;
1459
f1dc5600
S		 1460 switch (type) {
1461 case ATH9K_RESET_POWER_ON:
7a9233ff 1462 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1463 if (ret)
ceb26a60 1464 ah->reset_power_on = true;
7a9233ff 1465 break;
f1dc5600
S		 1466 case ATH9K_RESET_WARM:
1467 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1468 ret = ath9k_hw_set_reset(ah, type);
1469 break;
f1dc5600 1470 default:
7a9233ff 1471 break;
f1dc5600 1472 }
7a9233ff 1473
7a9233ff 1474 return ret;
f078f209
LR		 1475}
1476
cbe61d8a 1477static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1478 struct ath9k_channel *chan)
f078f209 1479{
9c083af8
FF		 1480 int reset_type = ATH9K_RESET_WARM;
1481
1482 if (AR_SREV_9280(ah)) {
1483 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1484 reset_type = ATH9K_RESET_POWER_ON;
1485 else
1486 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1487 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1488 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1489 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1490
1491 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1492 return false;
f078f209 1493
9ecdef4b 1494 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1495 return false;
f078f209 1496
2660b81a 1497 ah->chip_fullsleep = false;
bfc441a4
FF		 1498
1499 if (AR_SREV_9330(ah))
1500 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1501 ath9k_hw_init_pll(ah, chan);
f078f209 1502
f1dc5600 1503 return true;
f078f209
LR		 1504}
1505
cbe61d8a 1506static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1507 struct ath9k_channel *chan)
f078f209 1508{
c46917bb 1509 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1510 struct ath9k_hw_capabilities *pCap = &ah->caps;
1511 bool band_switch = false, mode_diff = false;
70e89a71 1512 u8 ini_reloaded = 0;
8fe65368 1513 u32 qnum;
0a3b7bac 1514 int r;
5f0c04ea 1515
b840cffe 1516 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1517 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1518 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1519 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1520 }
f078f209
LR		 1521
1522 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1523 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1524 ath_dbg(common, QUEUE,
226afe68 1525 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1526 return false;
1527 }
1528 }
1529
8fe65368 1530 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1531 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1532 return false;
1533 }
1534
b840cffe 1535 if (band_switch || mode_diff) {
5f0c04ea
RM		 1536 ath9k_hw_mark_phy_inactive(ah);
1537 udelay(5);
1538
5f35c0fa
SM		 1539 if (band_switch)
1540 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1541
1542 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1543 ath_err(common, "Failed to do fast channel change\n");
1544 return false;
1545 }
1546 }
1547
8fe65368 1548 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1549
8fe65368 1550 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1551 if (r) {
3800276a 1552 ath_err(common, "Failed to set channel\n");
0a3b7bac 1553 return false;
f078f209 1554 }
dfdac8ac 1555 ath9k_hw_set_clockrate(ah);
64ea57d0 1556 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1557
81c507a8 1558 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1559 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1560
70e89a71
SM		 1561 if (band_switch || ini_reloaded)
1562 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1563
70e89a71
SM		 1564 ath9k_hw_init_bb(ah, chan);
1565 ath9k_hw_rfbus_done(ah);
5f0c04ea 1566
70e89a71
SM		 1567 if (band_switch || ini_reloaded) {
1568 ah->ah_flags |= AH_FASTCC;
1569 ath9k_hw_init_cal(ah, chan);
a126ff51 1570 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1571 }
1572
f1dc5600
S		 1573 return true;
1574}
1575
691680b8
FF		 1576static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1577{
1578 u32 gpio_mask = ah->gpio_mask;
1579 int i;
1580
1581 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1582 if (!(gpio_mask & 1))
1583 continue;
1584
b2d70d49
MP		 1585 ath9k_hw_gpio_request_out(ah, i, NULL,
1586 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
691680b8 1587 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
db222190 1588 ath9k_hw_gpio_free(ah, i);
691680b8
FF		 1589 }
1590}
1591
1e516ca7
SM		 1592void ath9k_hw_check_nav(struct ath_hw *ah)
1593{
1594 struct ath_common *common = ath9k_hw_common(ah);
1595 u32 val;
1596
1597 val = REG_READ(ah, AR_NAV);
1598 if (val != 0xdeadbeef && val > 0x7fff) {
1599 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1600 REG_WRITE(ah, AR_NAV, 0);
1601 }
1602}
1603EXPORT_SYMBOL(ath9k_hw_check_nav);
1604
c9c99e5e 1605bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1606{
c9c99e5e 1607 int count = 50;
d31a36a6 1608 u32 reg, last_val;
c9c99e5e 1609
01e18918
RM		 1610 if (AR_SREV_9300(ah))
1611 return !ath9k_hw_detect_mac_hang(ah);
1612
e17f83ea 1613 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1614 return true;
1615
d31a36a6 1616 last_val = REG_READ(ah, AR_OBS_BUS_1);
c9c99e5e
FF		 1617 do {
1618 reg = REG_READ(ah, AR_OBS_BUS_1);
d31a36a6
FF		 1619 if (reg != last_val)
1620 return true;
3b319aae 1621
105ff411 1622 udelay(1);
d31a36a6 1623 last_val = reg;
c9c99e5e
FF		 1624 if ((reg & 0x7E7FFFEF) == 0x00702400)
1625 continue;
1626
1627 switch (reg & 0x7E000B00) {
1628 case 0x1E000000:
1629 case 0x52000B00:
1630 case 0x18000B00:
1631 continue;
1632 default:
1633 return true;
1634 }
1635 } while (count-- > 0);
3b319aae 1636
c9c99e5e 1637 return false;
3b319aae 1638}
c9c99e5e 1639EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1640
15d2b585
SM		 1641static void ath9k_hw_init_mfp(struct ath_hw *ah)
1642{
1643 /* Setup MFP options for CCMP */
1644 if (AR_SREV_9280_20_OR_LATER(ah)) {
1645 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1646 * frames when constructing CCMP AAD. */
1647 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1648 0xc7ff);
60fc4962
CYY		 1649 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1650 ah->sw_mgmt_crypto_tx = true;
1651 else
1652 ah->sw_mgmt_crypto_tx = false;
e6510b11 1653 ah->sw_mgmt_crypto_rx = false;
15d2b585
SM		 1654 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1655 /* Disable hardware crypto for management frames */
1656 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1657 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1658 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1659 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
e6510b11
CYY		 1660 ah->sw_mgmt_crypto_tx = true;
1661 ah->sw_mgmt_crypto_rx = true;
15d2b585 1662 } else {
e6510b11
CYY		 1663 ah->sw_mgmt_crypto_tx = true;
1664 ah->sw_mgmt_crypto_rx = true;
15d2b585
SM		 1665 }
1666}
1667
1668static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1669 u32 macStaId1, u32 saveDefAntenna)
1670{
1671 struct ath_common *common = ath9k_hw_common(ah);
1672
1673 ENABLE_REGWRITE_BUFFER(ah);
1674
ecbbed32 1675 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585 1676 | AR_STA_ID1_RTS_USE_DEF
ecbbed32
FF		 1677 | ah->sta_id1_defaults,
1678 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1679 ath_hw_setbssidmask(common);
1680 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1681 ath9k_hw_write_associd(ah);
1682 REG_WRITE(ah, AR_ISR, ~0);
1683 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1684
1685 REGWRITE_BUFFER_FLUSH(ah);
1686
1687 ath9k_hw_set_operating_mode(ah, ah->opmode);
1688}
1689
1690static void ath9k_hw_init_queues(struct ath_hw *ah)
1691{
1692 int i;
1693
1694 ENABLE_REGWRITE_BUFFER(ah);
1695
1696 for (i = 0; i < AR_NUM_DCU; i++)
1697 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1698
1699 REGWRITE_BUFFER_FLUSH(ah);
1700
1701 ah->intr_txqs = 0;
1702 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1703 ath9k_hw_resettxqueue(ah, i);
1704}
1705
1706/*
1707 * For big endian systems turn on swapping for descriptors
1708 */
1709static void ath9k_hw_init_desc(struct ath_hw *ah)
1710{
1711 struct ath_common *common = ath9k_hw_common(ah);
1712
1713 if (AR_SREV_9100(ah)) {
1714 u32 mask;
1715 mask = REG_READ(ah, AR_CFG);
1716 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1717 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1718 mask);
1719 } else {
1720 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1721 REG_WRITE(ah, AR_CFG, mask);
1722 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1723 REG_READ(ah, AR_CFG));
1724 }
1725 } else {
1726 if (common->bus_ops->ath_bus_type == ATH_USB) {
1727 /* Configure AR9271 target WLAN */
1728 if (AR_SREV_9271(ah))
1729 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1730 else
1731 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1732 }
1733#ifdef __BIG_ENDIAN
1734 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
ede6a5e7
MP		 1735 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1736 AR_SREV_9561(ah))
15d2b585
SM		 1737 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1738 else
1739 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1740#endif
1741 }
1742}
1743
caed6579
SM		 1744/*
1745 * Fast channel change:
1746 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1747 */
1748static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1749{
1750 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1751 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1752 int ret;
1753
1754 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1755 goto fail;
1756
1757 if (ah->chip_fullsleep)
1758 goto fail;
1759
1760 if (!ah->curchan)
1761 goto fail;
1762
1763 if (chan->channel == ah->curchan->channel)
1764 goto fail;
1765
feb7bc99
FF		 1766 if ((ah->curchan->channelFlags | chan->channelFlags) &
1767 (CHANNEL_HALF | CHANNEL_QUARTER))
1768 goto fail;
1769
b840cffe 1770 /*
6b21fd20 1771 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1772 */
6b21fd20 1773 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1774 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1775 goto fail;
caed6579
SM		 1776
1777 if (!ath9k_hw_check_alive(ah))
1778 goto fail;
1779
1780 /*
1781 * For AR9462, make sure that calibration data for
1782 * re-using are present.
1783 */
8a90555f 1784 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1785 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1786 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1787 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1788 goto fail;
1789
1790 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1791 ah->curchan->channel, chan->channel);
1792
1793 ret = ath9k_hw_channel_change(ah, chan);
1794 if (!ret)
1795 goto fail;
1796
5955b2b0 1797 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1798 ar9003_mci_2g5g_switch(ah, false);
caed6579 1799
88033318
RM		 1800 ath9k_hw_loadnf(ah, ah->curchan);
1801 ath9k_hw_start_nfcal(ah, true);
1802
caed6579
SM		 1803 if (AR_SREV_9271(ah))
1804 ar9002_hw_load_ani_reg(ah, chan);
1805
1806 return 0;
1807fail:
1808 return -EINVAL;
1809}
1810
8d7e09dd
FF		 1811u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1812{
1813 struct timespec ts;
1814 s64 usec;
1815
1816 if (!cur) {
1817 getrawmonotonic(&ts);
1818 cur = &ts;
1819 }
1820
1821 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1822 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1823
1824 return (u32) usec;
1825}
1826EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1827
cbe61d8a 1828int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1829 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1830{
1510718d 1831 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1832 u32 saveLedState;
f078f209
LR		 1833 u32 saveDefAntenna;
1834 u32 macStaId1;
46fe782c 1835 u64 tsf = 0;
09d8e315 1836 s64 usec = 0;
15d2b585 1837 int r;
caed6579 1838 bool start_mci_reset = false;
63d32967
MSS		 1839 bool save_fullsleep = ah->chip_fullsleep;
1840
5955b2b0 1841 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1842 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1843 if (start_mci_reset)
1844 return 0;
63d32967
MSS		 1845 }
1846
9ecdef4b 1847 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1848 return -EIO;
f078f209 1849
caed6579
SM		 1850 if (ah->curchan && !ah->chip_fullsleep)
1851 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1852
20bd2a09 1853 ah->caldata = caldata;
fcb9a3de 1854 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1855 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1856 /* Operating channel changed, reset channel calibration data */
1857 memset(caldata, 0, sizeof(*caldata));
1858 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1859 } else if (caldata) {
4b9b42bf 1860 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1861 }
5bc225ac 1862 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1863
caed6579
SM		 1864 if (fastcc) {
1865 r = ath9k_hw_do_fastcc(ah, chan);
1866 if (!r)
1867 return r;
f078f209
LR		 1868 }
1869
5955b2b0 1870 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1871 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1872
f078f209
LR		 1873 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1874 if (saveDefAntenna == 0)
1875 saveDefAntenna = 1;
1876
1877 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1878
09d8e315
FF		 1879 /* Save TSF before chip reset, a cold reset clears it */
1880 tsf = ath9k_hw_gettsf64(ah);
6438e0dd 1881 usec = ktime_to_us(ktime_get_raw());
46fe782c 1882
f078f209
LR		 1883 saveLedState = REG_READ(ah, AR_CFG_LED) &
1884 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1885 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1886
1887 ath9k_hw_mark_phy_inactive(ah);
1888
45ef6a0b
VT		 1889 ah->paprd_table_write_done = false;
1890
05020d23 1891 /* Only required on the first reset */
d7e7d229
LR		 1892 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1893 REG_WRITE(ah,
1894 AR9271_RESET_POWER_DOWN_CONTROL,
1895 AR9271_RADIO_RF_RST);
1896 udelay(50);
1897 }
1898
f078f209 1899 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1900 ath_err(common, "Chip reset failed\n");
ae8d2858 1901 return -EINVAL;
f078f209
LR		 1902 }
1903
05020d23 1904 /* Only required on the first reset */
d7e7d229
LR		 1905 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1906 ah->htc_reset_init = false;
1907 REG_WRITE(ah,
1908 AR9271_RESET_POWER_DOWN_CONTROL,
1909 AR9271_GATE_MAC_CTL);
1910 udelay(50);
1911 }
1912
46fe782c 1913 /* Restore TSF */
6438e0dd 1914 usec = ktime_to_us(ktime_get_raw()) - usec;
09d8e315 1915 ath9k_hw_settsf64(ah, tsf + usec);
46fe782c 1916
7a37081e 1917 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1918 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1919
e9141f71
S		 1920 if (!AR_SREV_9300_20_OR_LATER(ah))
1921 ar9002_hw_enable_async_fifo(ah);
1922
25c56eec 1923 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1924 if (r)
1925 return r;
f078f209 1926
935d00cc
LB		 1927 ath9k_hw_set_rfmode(ah, chan);
1928
5955b2b0 1929 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1930 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1931
f860d526
FF		 1932 /*
1933 * Some AR91xx SoC devices frequently fail to accept TSF writes
1934 * right after the chip reset. When that happens, write a new
1935 * value after the initvals have been applied, with an offset
1936 * based on measured time difference
1937 */
1938 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1939 tsf += 1500;
1940 ath9k_hw_settsf64(ah, tsf);
1941 }
1942
15d2b585 1943 ath9k_hw_init_mfp(ah);
0ced0e17 1944
81c507a8 1945 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1946 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1947 ah->eep_ops->set_board_values(ah, chan);
a7765828 1948
15d2b585 1949 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1950
8fe65368 1951 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1952 if (r)
1953 return r;
f078f209 1954
dfdac8ac
FF		 1955 ath9k_hw_set_clockrate(ah);
1956
15d2b585 1957 ath9k_hw_init_queues(ah);
2660b81a 1958 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1959 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1960 ath9k_hw_init_qos(ah);
1961
2660b81a 1962 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
b2d70d49 1963 ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill");
3b319aae 1964
0005baf4 1965 ath9k_hw_init_global_settings(ah);
f078f209 1966
fe2b6afb
FF		 1967 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1968 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1969 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1970 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1971 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1972 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1973 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1974 }
1975
ca7a4deb 1976 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1977
1978 ath9k_hw_set_dma(ah);
1979
ed6ebd8b
RM		 1980 if (!ath9k_hw_mci_is_enabled(ah))
1981 REG_WRITE(ah, AR_OBS, 8);
f078f209 1982
7b37e0d4 1983 ENABLE_REG_RMW_BUFFER(ah);
0ce024cb 1984 if (ah->config.rx_intr_mitigation) {
a64e1a45
SM		 1985 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1986 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
f078f209
LR		 1987 }
1988
7f62a136
VT		 1989 if (ah->config.tx_intr_mitigation) {
1990 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1991 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1992 }
7b37e0d4 1993 REG_RMW_BUFFER_FLUSH(ah);
7f62a136 1994
f078f209
LR		 1995 ath9k_hw_init_bb(ah, chan);
1996
77a5a664 1997 if (caldata) {
4b9b42bf
SM		 1998 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1999 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 2000 }
ae8d2858 2001 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2002 return -EIO;
f078f209 2003
5955b2b0 2004 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 2005 return -EIO;
63d32967 2006
7d0d0df0 2007 ENABLE_REGWRITE_BUFFER(ah);
f078f209 2008
8fe65368 2009 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 2010 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2011
7d0d0df0 2012 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2013
f4c34af4
SM		 2014 ath9k_hw_gen_timer_start_tsf2(ah);
2015
15d2b585 2016 ath9k_hw_init_desc(ah);
f078f209 2017
dbccdd1d 2018 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 2019 ath9k_hw_btcoex_enable(ah);
2020
5955b2b0 2021 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 2022 ar9003_mci_check_bt(ah);
63d32967 2023
7b89fccf
FF		 2024 if (AR_SREV_9300_20_OR_LATER(ah)) {
2025 ath9k_hw_loadnf(ah, chan);
2026 ath9k_hw_start_nfcal(ah, true);
2027 }
1fe860ed 2028
a7abaf7d 2029 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 2030 ar9003_hw_bb_watchdog_config(ah);
a7abaf7d
SM		 2031
2032 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
51ac8cbb 2033 ar9003_hw_disable_phy_restart(ah);
51ac8cbb 2034
691680b8
FF		 2035 ath9k_hw_apply_gpio_override(ah);
2036
7bdea96a 2037 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 2038 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2039
4307b0fe
LB		 2040 if (ah->hw->conf.radar_enabled) {
2041 /* set HW specific DFS configuration */
7a0a260a 2042 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
4307b0fe
LB		 2043 ath9k_hw_set_radar_params(ah);
2044 }
2045
ae8d2858 2046 return 0;
f078f209 2047}
7322fd19 2048EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2049
f1dc5600
S		 2050/******************************/
2051/* Power Management (Chipset) */
2052/******************************/
2053
42d5bc3f
LR		 2054/*
2055 * Notify Power Mgt is disabled in self-generated frames.
2056 * If requested, force chip to sleep.
2057 */
31604cf0 2058static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 2059{
f1dc5600 2060 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 2061
a4a2954f 2062 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 2063 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2064 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2065 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 2066 /* xxx Required for WLAN only case ? */
2067 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2068 udelay(100);
2069 }
2577c6e8 2070
31604cf0
SM		 2071 /*
2072 * Clear the RTC force wake bit to allow the
2073 * mac to go to sleep.
2074 */
2075 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2076
153dccd4 2077 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2078 udelay(100);
2577c6e8 2079
31604cf0
SM		 2080 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2081 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2082
31604cf0
SM		 2083 /* Shutdown chip. Active low */
2084 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2085 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2086 udelay(2);
f1dc5600 2087 }
9a658d2b
LR		 2088
2089 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2090 if (AR_SREV_9300_20_OR_LATER(ah))
2091 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2092}
2093
bbd79af5
LR		 2094/*
2095 * Notify Power Management is enabled in self-generating
2096 * frames. If request, set power mode of chip to
2097 * auto/normal. Duration in units of 128us (1/8 TU).
2098 */
31604cf0 2099static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2100{
31604cf0 2101 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2102
f1dc5600 2103 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2104
31604cf0
SM		 2105 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2106 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2107 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2108 AR_RTC_FORCE_WAKE_ON_INT);
2109 } else {
2577c6e8 2110
31604cf0
SM		 2111 /* When chip goes into network sleep, it could be waken
2112 * up by MCI_INT interrupt caused by BT's HW messages
2113 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2114 * rate (~100us). This will cause chip to leave and
2115 * re-enter network sleep mode frequently, which in
2116 * consequence will have WLAN MCI HW to generate lots of
2117 * SYS_WAKING and SYS_SLEEPING messages which will make
2118 * BT CPU to busy to process.
2119 */
153dccd4
RM		 2120 if (ath9k_hw_mci_is_enabled(ah))
2121 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2122 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2123 /*
2124 * Clear the RTC force wake bit to allow the
2125 * mac to go to sleep.
2126 */
153dccd4 2127 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2128
153dccd4 2129 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2130 udelay(30);
f078f209 2131 }
9a658d2b
LR		 2132
2133 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2134 if (AR_SREV_9300_20_OR_LATER(ah))
2135 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2136}
2137
31604cf0 2138static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2139{
f1dc5600
S		 2140 u32 val;
2141 int i;
f078f209 2142
9a658d2b
LR		 2143 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2144 if (AR_SREV_9300_20_OR_LATER(ah)) {
2145 REG_WRITE(ah, AR_WA, ah->WARegVal);
2146 udelay(10);
2147 }
2148
31604cf0
SM		 2149 if ((REG_READ(ah, AR_RTC_STATUS) &
2150 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2151 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2152 return false;
f1dc5600 2153 }
31604cf0
SM		 2154 if (!AR_SREV_9300_20_OR_LATER(ah))
2155 ath9k_hw_init_pll(ah, NULL);
2156 }
2157 if (AR_SREV_9100(ah))
2158 REG_SET_BIT(ah, AR_RTC_RESET,
2159 AR_RTC_RESET_EN);
2160
2161 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2162 AR_RTC_FORCE_WAKE_EN);
04575f21 2163 if (AR_SREV_9100(ah))
3683a07b 2164 mdelay(10);
04575f21
SM		 2165 else
2166 udelay(50);
f078f209 2167
31604cf0
SM		 2168 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2169 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2170 if (val == AR_RTC_STATUS_ON)
2171 break;
2172 udelay(50);
f1dc5600
S		 2173 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2174 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2175 }
2176 if (i == 0) {
2177 ath_err(ath9k_hw_common(ah),
2178 "Failed to wakeup in %uus\n",
2179 POWER_UP_TIME / 20);
2180 return false;
f078f209
LR		 2181 }
2182
cdbe408d
RM		 2183 if (ath9k_hw_mci_is_enabled(ah))
2184 ar9003_mci_set_power_awake(ah);
2185
f1dc5600 2186 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2187
f1dc5600 2188 return true;
f078f209
LR		 2189}
2190
9ecdef4b 2191bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2192{
c46917bb 2193 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2194 int status = true;
f1dc5600
S		 2195 static const char *modes[] = {
2196 "AWAKE",
2197 "FULL-SLEEP",
2198 "NETWORK SLEEP",
2199 "UNDEFINED"
2200 };
f1dc5600 2201
cbdec975
GJ		 2202 if (ah->power_mode == mode)
2203 return status;
2204
d2182b69 2205 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2206 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2207
2208 switch (mode) {
2209 case ATH9K_PM_AWAKE:
31604cf0 2210 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2211 break;
2212 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2213 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2214 ar9003_mci_set_full_sleep(ah);
1010911e 2215
31604cf0 2216 ath9k_set_power_sleep(ah);
2660b81a 2217 ah->chip_fullsleep = true;
f1dc5600
S		 2218 break;
2219 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2220 ath9k_set_power_network_sleep(ah);
f1dc5600 2221 break;
f078f209 2222 default:
3800276a 2223 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2224 return false;
2225 }
2660b81a 2226 ah->power_mode = mode;
f1dc5600 2227
69f4aab1
LR		 2228 /*
2229 * XXX: If this warning never comes up after a while then
2230 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2231 * ath9k_hw_setpower() return type void.
2232 */
97dcec57
SM		 2233
2234 if (!(ah->ah_flags & AH_UNPLUGGED))
2235 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2236
f1dc5600 2237 return status;
f078f209 2238}
7322fd19 2239EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2240
f1dc5600
S		 2241/*******************/
2242/* Beacon Handling */
2243/*******************/
2244
cbe61d8a 2245void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2246{
f078f209
LR		 2247 int flags = 0;
2248
7d0d0df0
S		 2249 ENABLE_REGWRITE_BUFFER(ah);
2250
2660b81a 2251 switch (ah->opmode) {
d97809db 2252 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2253 REG_SET_BIT(ah, AR_TXCFG,
2254 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2255 case NL80211_IFTYPE_MESH_POINT:
d97809db 2256 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2257 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2258 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2259 TU_TO_USEC(ah->config.dma_beacon_response_time));
2260 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2261 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2262 flags |=
2263 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2264 break;
d97809db 2265 default:
d2182b69
JP		 2266 ath_dbg(ath9k_hw_common(ah), BEACON,
2267 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2268 return;
2269 break;
f078f209
LR		 2270 }
2271
dd347f2f
FF		 2272 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2273 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2274 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2275
7d0d0df0 2276 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2277
f078f209
LR		 2278 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2279}
7322fd19 2280EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2281
cbe61d8a 2282void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2283 const struct ath9k_beacon_state *bs)
f078f209
LR		 2284{
2285 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2286 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2287 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2288
7d0d0df0
S		 2289 ENABLE_REGWRITE_BUFFER(ah);
2290
4ed15762
FF		 2291 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2292 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2293 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2294
7d0d0df0 2295 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2296
f078f209
LR		 2297 REG_RMW_FIELD(ah, AR_RSSI_THR,
2298 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2299
f29f5c08 2300 beaconintval = bs->bs_intval;
f078f209
LR		 2301
2302 if (bs->bs_sleepduration > beaconintval)
2303 beaconintval = bs->bs_sleepduration;
2304
2305 dtimperiod = bs->bs_dtimperiod;
2306 if (bs->bs_sleepduration > dtimperiod)
2307 dtimperiod = bs->bs_sleepduration;
2308
2309 if (beaconintval == dtimperiod)
2310 nextTbtt = bs->bs_nextdtim;
2311 else
2312 nextTbtt = bs->bs_nexttbtt;
2313
58bb9ca8
JD		 2314 ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim);
2315 ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt);
2316 ath_dbg(common, BEACON, "beacon period %u\n", beaconintval);
2317 ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod);
f078f209 2318
7d0d0df0
S		 2319 ENABLE_REGWRITE_BUFFER(ah);
2320
4ed15762
FF		 2321 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2322 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2323
f1dc5600
S		 2324 REG_WRITE(ah, AR_SLEEP1,
2325 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2326 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2327
f1dc5600
S		 2328 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2329 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2330 else
2331 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2332
f1dc5600
S		 2333 REG_WRITE(ah, AR_SLEEP2,
2334 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2335
4ed15762
FF		 2336 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2337 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2338
7d0d0df0 2339 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2340
f1dc5600
S		 2341 REG_SET_BIT(ah, AR_TIMER_MODE,
2342 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2343 AR_DTIM_TIMER_EN);
f078f209 2344
4af9cf4f
S		 2345 /* TSF Out of Range Threshold */
2346 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2347}
7322fd19 2348EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2349
f1dc5600
S		 2350/*******************/
2351/* HW Capabilities */
2352/*******************/
2353
6054069a
FF		 2354static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2355{
2356 eeprom_chainmask &= chip_chainmask;
2357 if (eeprom_chainmask)
2358 return eeprom_chainmask;
2359 else
2360 return chip_chainmask;
2361}
2362
9a66af33
ZK		 2363/**
2364 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2365 * @ah: the atheros hardware data structure
2366 *
2367 * We enable DFS support upstream on chipsets which have passed a series
2368 * of tests. The testing requirements are going to be documented. Desired
2369 * test requirements are documented at:
2370 *
2371 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2372 *
2373 * Once a new chipset gets properly tested an individual commit can be used
2374 * to document the testing for DFS for that chipset.
2375 */
2376static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2377{
2378
2379 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2380 /* for temporary testing DFS with 9280 */
2381 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2382 /* AR9580 will likely be our first target to get testing on */
2383 case AR_SREV_VERSION_9580:
73e4937d 2384 return true;
9a66af33
ZK		 2385 default:
2386 return false;
2387 }
2388}
2389
a01ab81b
MP		 2390static void ath9k_gpio_cap_init(struct ath_hw *ah)
2391{
2392 struct ath9k_hw_capabilities *pCap = &ah->caps;
2393
2394 if (AR_SREV_9271(ah)) {
2395 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2396 pCap->gpio_mask = AR9271_GPIO_MASK;
2397 } else if (AR_DEVID_7010(ah)) {
2398 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2399 pCap->gpio_mask = AR7010_GPIO_MASK;
2400 } else if (AR_SREV_9287(ah)) {
2401 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2402 pCap->gpio_mask = AR9287_GPIO_MASK;
2403 } else if (AR_SREV_9285(ah)) {
2404 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2405 pCap->gpio_mask = AR9285_GPIO_MASK;
2406 } else if (AR_SREV_9280(ah)) {
2407 pCap->num_gpio_pins = AR9280_NUM_GPIO;
2408 pCap->gpio_mask = AR9280_GPIO_MASK;
2409 } else if (AR_SREV_9300(ah)) {
2410 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2411 pCap->gpio_mask = AR9300_GPIO_MASK;
2412 } else if (AR_SREV_9330(ah)) {
2413 pCap->num_gpio_pins = AR9330_NUM_GPIO;
2414 pCap->gpio_mask = AR9330_GPIO_MASK;
2415 } else if (AR_SREV_9340(ah)) {
2416 pCap->num_gpio_pins = AR9340_NUM_GPIO;
2417 pCap->gpio_mask = AR9340_GPIO_MASK;
2418 } else if (AR_SREV_9462(ah)) {
2419 pCap->num_gpio_pins = AR9462_NUM_GPIO;
2420 pCap->gpio_mask = AR9462_GPIO_MASK;
2421 } else if (AR_SREV_9485(ah)) {
2422 pCap->num_gpio_pins = AR9485_NUM_GPIO;
2423 pCap->gpio_mask = AR9485_GPIO_MASK;
2424 } else if (AR_SREV_9531(ah)) {
2425 pCap->num_gpio_pins = AR9531_NUM_GPIO;
2426 pCap->gpio_mask = AR9531_GPIO_MASK;
2427 } else if (AR_SREV_9550(ah)) {
2428 pCap->num_gpio_pins = AR9550_NUM_GPIO;
2429 pCap->gpio_mask = AR9550_GPIO_MASK;
2430 } else if (AR_SREV_9561(ah)) {
2431 pCap->num_gpio_pins = AR9561_NUM_GPIO;
2432 pCap->gpio_mask = AR9561_GPIO_MASK;
2433 } else if (AR_SREV_9565(ah)) {
2434 pCap->num_gpio_pins = AR9565_NUM_GPIO;
2435 pCap->gpio_mask = AR9565_GPIO_MASK;
2436 } else if (AR_SREV_9580(ah)) {
2437 pCap->num_gpio_pins = AR9580_NUM_GPIO;
2438 pCap->gpio_mask = AR9580_GPIO_MASK;
2439 } else {
2440 pCap->num_gpio_pins = AR_NUM_GPIO;
2441 pCap->gpio_mask = AR_GPIO_MASK;
2442 }
2443}
2444
a9a29ce6 2445int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2446{
2660b81a 2447 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2448 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2449 struct ath_common *common = ath9k_hw_common(ah);
608b88cb 2450
0ff2b5c0 2451 u16 eeval;
47c80de6 2452 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2453
f74df6fb 2454 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2455 regulatory->current_rd = eeval;
f078f209 2456
2660b81a 2457 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2458 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2459 if (regulatory->current_rd == 0x64 ||
2460 regulatory->current_rd == 0x65)
2461 regulatory->current_rd += 5;
2462 else if (regulatory->current_rd == 0x41)
2463 regulatory->current_rd = 0x43;
d2182b69
JP		 2464 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2465 regulatory->current_rd);
f1dc5600 2466 }
f078f209 2467
f74df6fb 2468 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3468968e
FF		 2469
2470 if (eeval & AR5416_OPFLAGS_11A) {
2471 if (ah->disable_5ghz)
2472 ath_warn(common, "disabling 5GHz band\n");
2473 else
2474 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
a9a29ce6
GJ		 2475 }
2476
3468968e
FF		 2477 if (eeval & AR5416_OPFLAGS_11G) {
2478 if (ah->disable_2ghz)
2479 ath_warn(common, "disabling 2GHz band\n");
2480 else
2481 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2482 }
f078f209 2483
3468968e
FF		 2484 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2485 ath_err(common, "both bands are disabled\n");
2486 return -EINVAL;
2487 }
f1dc5600 2488
e41db61d
SM		 2489 if (AR_SREV_9485(ah) ||
2490 AR_SREV_9285(ah) ||
2491 AR_SREV_9330(ah) ||
2492 AR_SREV_9565(ah))
ee79ccd9 2493 pCap->chip_chainmask = 1;
6054069a 2494 else if (!AR_SREV_9280_20_OR_LATER(ah))
ee79ccd9
SM		 2495 pCap->chip_chainmask = 7;
2496 else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2497 AR_SREV_9340(ah) ||
2498 AR_SREV_9462(ah) ||
2499 AR_SREV_9531(ah))
2500 pCap->chip_chainmask = 3;
6054069a 2501 else
ee79ccd9 2502 pCap->chip_chainmask = 7;
6054069a 2503
f74df6fb 2504 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2505 /*
2506 * For AR9271 we will temporarilly uses the rx chainmax as read from
2507 * the EEPROM.
2508 */
8147f5de 2509 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2510 !(eeval & AR5416_OPFLAGS_11A) &&
2511 !(AR_SREV_9271(ah)))
2512 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2513 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2514 else if (AR_SREV_9100(ah))
2515 pCap->rx_chainmask = 0x7;
8147f5de 2516 else
d7e7d229 2517 /* Use rx_chainmask from EEPROM. */
8147f5de 2518 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2519
ee79ccd9
SM		 2520 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2521 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2522 ah->txchainmask = pCap->tx_chainmask;
2523 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2524
7a37081e 2525 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2526
02d2ebb2
FF		 2527 /* enable key search for every frame in an aggregate */
2528 if (AR_SREV_9300_20_OR_LATER(ah))
2529 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2530
ce2220d1
BR		 2531 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2532
0db156e9 2533 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2534 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2535 else
2536 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2537
a01ab81b 2538 ath9k_gpio_cap_init(ah);
f078f209 2539
1b2538b2 2540 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2541 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2542 else
f1dc5600 2543 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2544
74e13060 2545#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2546 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2547 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2548 ah->rfkill_gpio =
2549 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2550 ah->rfkill_polarity =
2551 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2552
2553 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2554 }
f1dc5600 2555#endif
d5d1154f 2556 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2557 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2558 else
2559 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2560
e7594072 2561 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2562 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2563 else
2564 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2565
ceb26445 2566 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2567 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
ede6a5e7
MP		 2568 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2569 !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2570 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2571
ceb26445
VT		 2572 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2573 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2574 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2575 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2576 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2577 } else {
2578 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2579 if (AR_SREV_9280_20(ah))
6b42e8d0 2580 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2581 }
1adf02ff 2582
6c84ce08
VT		 2583 if (AR_SREV_9300_20_OR_LATER(ah))
2584 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2585
ede6a5e7
MP		 2586 if (AR_SREV_9561(ah))
2587 ah->ent_mode = 0x3BDA000;
2588 else if (AR_SREV_9300_20_OR_LATER(ah))
6ee63f55
SB		 2589 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2590
a42acef0 2591 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2592 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2593
f85c3371 2594 if (AR_SREV_9285(ah)) {
754dc536
VT		 2595 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2596 ant_div_ctl1 =
2597 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2598 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2599 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2600 ath_info(common, "Enable LNA combining\n");
2601 }
754dc536 2602 }
f85c3371
SM		 2603 }
2604
ea066d5a
MSS		 2605 if (AR_SREV_9300_20_OR_LATER(ah)) {
2606 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2607 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2608 }
2609
06236e53 2610 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2611 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2612 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2613 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2614 ath_info(common, "Enable LNA combining\n");
2615 }
21d2c63a 2616 }
754dc536 2617
9a66af33
ZK		 2618 if (ath9k_hw_dfs_tested(ah))
2619 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2620
47c80de6
VT		 2621 tx_chainmask = pCap->tx_chainmask;
2622 rx_chainmask = pCap->rx_chainmask;
2623 while (tx_chainmask || rx_chainmask) {
2624 if (tx_chainmask & BIT(0))
2625 pCap->max_txchains++;
2626 if (rx_chainmask & BIT(0))
2627 pCap->max_rxchains++;
2628
2629 tx_chainmask >>= 1;
2630 rx_chainmask >>= 1;
2631 }
2632
a4a2954f 2633 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2634 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2635 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2636
2b5e54e2 2637 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2638 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2639 }
2640
0f21ee8d
SM		 2641 if (AR_SREV_9300_20_OR_LATER(ah) &&
2642 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2643 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2644
12a44422
SM		 2645#ifdef CONFIG_ATH9K_WOW
2646 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2647 ah->wow.max_patterns = MAX_NUM_PATTERN;
2648 else
2649 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2650#endif
2651
a9a29ce6 2652 return 0;
f078f209
LR		 2653}
2654
f1dc5600
S		 2655/****************************/
2656/* GPIO / RFKILL / Antennae */
2657/****************************/
f078f209 2658
b2d70d49 2659static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
f1dc5600
S		 2660{
2661 int addr;
2662 u32 gpio_shift, tmp;
f078f209 2663
f1dc5600
S		 2664 if (gpio > 11)
2665 addr = AR_GPIO_OUTPUT_MUX3;
2666 else if (gpio > 5)
2667 addr = AR_GPIO_OUTPUT_MUX2;
2668 else
2669 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2670
f1dc5600 2671 gpio_shift = (gpio % 6) * 5;
f078f209 2672
b2d70d49
MP		 2673 if (AR_SREV_9280_20_OR_LATER(ah) ||
2674 (addr != AR_GPIO_OUTPUT_MUX1)) {
f1dc5600
S		 2675 REG_RMW(ah, addr, (type << gpio_shift),
2676 (0x1f << gpio_shift));
f078f209 2677 } else {
f1dc5600
S		 2678 tmp = REG_READ(ah, addr);
2679 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2680 tmp &= ~(0x1f << gpio_shift);
2681 tmp |= (type << gpio_shift);
2682 REG_WRITE(ah, addr, tmp);
f078f209 2683 }
f078f209
LR		 2684}
2685
b2d70d49
MP		 2686/* BSP should set the corresponding MUX register correctly.
2687 */
2688static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out,
2689 const char *label)
f078f209 2690{
b2d70d49
MP		 2691 if (ah->caps.gpio_requested & BIT(gpio))
2692 return;
f078f209 2693
b2d70d49
MP		 2694 /* may be requested by BSP, free anyway */
2695 gpio_free(gpio);
f078f209 2696
b2d70d49 2697 if (gpio_request_one(gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label))
88c1f4f6 2698 return;
f078f209 2699
b2d70d49 2700 ah->caps.gpio_requested |= BIT(gpio);
f078f209
LR		 2701}
2702
b2d70d49
MP		 2703static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out,
2704 u32 ah_signal_type)
f078f209 2705{
b2d70d49 2706 u32 gpio_set, gpio_shift = gpio;
f078f209 2707
88c1f4f6 2708 if (AR_DEVID_7010(ah)) {
b2d70d49
MP		 2709 gpio_set = out ?
2710 AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT;
2711 REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift,
2712 AR7010_GPIO_OE_MASK << gpio_shift);
2713 } else if (AR_SREV_SOC(ah)) {
2714 gpio_set = out ? 1 : 0;
2715 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2716 gpio_set << gpio_shift);
2717 } else {
2718 gpio_shift = gpio << 1;
2719 gpio_set = out ?
2720 AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO;
2721 REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift,
2722 AR_GPIO_OE_OUT_DRV << gpio_shift);
2723
2724 if (out)
2725 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2726 }
f078f209
LR		 2727}
2728
b2d70d49
MP		 2729static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out,
2730 const char *label, u32 ah_signal_type)
f078f209 2731{
b2d70d49 2732 WARN_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2733
b2d70d49
MP		 2734 if (BIT(gpio) & ah->caps.gpio_mask)
2735 ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type);
2736 else if (AR_SREV_SOC(ah))
2737 ath9k_hw_gpio_cfg_soc(ah, gpio, out, label);
2738 else
2739 WARN_ON(1);
2740}
f078f209 2741
b2d70d49
MP		 2742void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label)
2743{
2744 ath9k_hw_gpio_request(ah, gpio, false, label, 0);
f078f209 2745}
b2d70d49 2746EXPORT_SYMBOL(ath9k_hw_gpio_request_in);
f078f209 2747
b2d70d49
MP		 2748void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
2749 u32 ah_signal_type)
f078f209 2750{
b2d70d49
MP		 2751 ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type);
2752}
2753EXPORT_SYMBOL(ath9k_hw_gpio_request_out);
2754
2755void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio)
2756{
2757 if (!AR_SREV_SOC(ah))
88c1f4f6 2758 return;
b2d70d49
MP		 2759
2760 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2761
2762 if (ah->caps.gpio_requested & BIT(gpio)) {
2763 gpio_free(gpio);
2764 ah->caps.gpio_requested &= ~BIT(gpio);
88c1f4f6 2765 }
b2d70d49
MP		 2766}
2767EXPORT_SYMBOL(ath9k_hw_gpio_free);
88c1f4f6 2768
b2d70d49
MP		 2769u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2770{
2771 u32 val = 0xffffffff;
5b5fa355 2772
b2d70d49
MP		 2773#define MS_REG_READ(x, y) \
2774 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y))
2775
2776 WARN_ON(gpio >= ah->caps.num_gpio_pins);
2777
2778 if (BIT(gpio) & ah->caps.gpio_mask) {
2779 if (AR_SREV_9271(ah))
2780 val = MS_REG_READ(AR9271, gpio);
2781 else if (AR_SREV_9287(ah))
2782 val = MS_REG_READ(AR9287, gpio);
2783 else if (AR_SREV_9285(ah))
2784 val = MS_REG_READ(AR9285, gpio);
2785 else if (AR_SREV_9280(ah))
2786 val = MS_REG_READ(AR928X, gpio);
2787 else if (AR_DEVID_7010(ah))
2788 val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);
2789 else if (AR_SREV_9300_20_OR_LATER(ah))
2790 val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio);
2791 else
2792 val = MS_REG_READ(AR, gpio);
2793 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2794 val = gpio_get_value(gpio) & BIT(gpio);
2795 } else {
2796 WARN_ON(1);
2797 }
2798
2799 return val;
f078f209 2800}
b2d70d49 2801EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2802
b2d70d49 2803void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
61b559de 2804{
b2d70d49 2805 WARN_ON(gpio >= ah->caps.num_gpio_pins);
61b559de 2806
b2d70d49
MP		 2807 if (AR_DEVID_7010(ah) || AR_SREV_9271(ah))
2808 val = !val;
2809 else
2810 val = !!val;
2811
2812 if (BIT(gpio) & ah->caps.gpio_mask) {
2813 u32 out_addr = AR_DEVID_7010(ah) ?
2814 AR7010_GPIO_OUT : AR_GPIO_IN_OUT;
2815
2816 REG_RMW(ah, out_addr, val << gpio, BIT(gpio));
2817 } else if (BIT(gpio) & ah->caps.gpio_requested) {
2818 gpio_set_value(gpio, val);
2819 } else {
2820 WARN_ON(1);
2821 }
61b559de 2822}
b2d70d49 2823EXPORT_SYMBOL(ath9k_hw_set_gpio);
61b559de 2824
cbe61d8a 2825void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2826{
f1dc5600 2827 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2828}
7322fd19 2829EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2830
f1dc5600
S		 2831/*********************/
2832/* General Operation */
2833/*********************/
2834
cbe61d8a 2835u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2836{
f1dc5600
S		 2837 u32 bits = REG_READ(ah, AR_RX_FILTER);
2838 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2839
f1dc5600
S		 2840 if (phybits & AR_PHY_ERR_RADAR)
2841 bits |= ATH9K_RX_FILTER_PHYRADAR;
2842 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2843 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2844
f1dc5600 2845 return bits;
f078f209 2846}
7322fd19 2847EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2848
cbe61d8a 2849void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2850{
f1dc5600 2851 u32 phybits;
f078f209 2852
7d0d0df0
S		 2853 ENABLE_REGWRITE_BUFFER(ah);
2854
7ea310be
S		 2855 REG_WRITE(ah, AR_RX_FILTER, bits);
2856
f1dc5600
S		 2857 phybits = 0;
2858 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2859 phybits |= AR_PHY_ERR_RADAR;
2860 if (bits & ATH9K_RX_FILTER_PHYERR)
2861 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2862 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2863
f1dc5600 2864 if (phybits)
ca7a4deb 2865 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2866 else
ca7a4deb 2867 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2868
2869 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2870}
7322fd19 2871EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2872
cbe61d8a 2873bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2874{
99922a45
RM		 2875 if (ath9k_hw_mci_is_enabled(ah))
2876 ar9003_mci_bt_gain_ctrl(ah);
2877
63a75b91
SB		 2878 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2879 return false;
2880
2881 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2882 ah->htc_reset_init = true;
63a75b91 2883 return true;
f1dc5600 2884}
7322fd19 2885EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2886
cbe61d8a 2887bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2888{
9ecdef4b 2889 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2890 return false;
f078f209 2891
63a75b91
SB		 2892 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2893 return false;
2894
2895 ath9k_hw_init_pll(ah, NULL);
2896 return true;
f078f209 2897}
7322fd19 2898EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2899
ca2c68cc
FF		 2900static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2901{
2902 enum eeprom_param gain_param;
2903
2904 if (IS_CHAN_2GHZ(chan))
2905 gain_param = EEP_ANTENNA_GAIN_2G;
2906 else
2907 gain_param = EEP_ANTENNA_GAIN_5G;
2908
2909 return ah->eep_ops->get_eeprom(ah, gain_param);
2910}
2911
64ea57d0
GJ		 2912void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2913 bool test)
ca2c68cc
FF		 2914{
2915 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2916 struct ieee80211_channel *channel;
2917 int chan_pwr, new_pwr, max_gain;
2918 int ant_gain, ant_reduction = 0;
2919
2920 if (!chan)
2921 return;
2922
2923 channel = chan->chan;
2924 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2925 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2926 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2927
2928 ant_gain = get_antenna_gain(ah, chan);
2929 if (ant_gain > max_gain)
2930 ant_reduction = ant_gain - max_gain;
2931
2932 ah->eep_ops->set_txpower(ah, chan,
2933 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2934 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2935}
2936
de40f316 2937void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2938{
ca2c68cc 2939 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2940 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2941 struct ieee80211_channel *channel = chan->chan;
9c204b46 2942
48ef5c42 2943 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2944 if (test)
ca2c68cc 2945 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2946
64ea57d0 2947 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2948
ca2c68cc
FF		 2949 if (test)
2950 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2951}
7322fd19 2952EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2953
cbe61d8a 2954void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2955{
2660b81a 2956 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2957}
7322fd19 2958EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2959
cbe61d8a 2960void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2961{
f1dc5600
S		 2962 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2963 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2964}
7322fd19 2965EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2966
f2b2143e 2967void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2968{
1510718d
LR		 2969 struct ath_common *common = ath9k_hw_common(ah);
2970
2971 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2972 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2973 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2974}
7322fd19 2975EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2976
1c0fc65e
BP		 2977#define ATH9K_MAX_TSF_READ 10
2978
cbe61d8a 2979u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2980{
1c0fc65e
BP		 2981 u32 tsf_lower, tsf_upper1, tsf_upper2;
2982 int i;
2983
2984 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2985 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2986 tsf_lower = REG_READ(ah, AR_TSF_L32);
2987 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2988 if (tsf_upper2 == tsf_upper1)
2989 break;
2990 tsf_upper1 = tsf_upper2;
2991 }
f078f209 2992
1c0fc65e 2993 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2994
1c0fc65e 2995 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2996}
7322fd19 2997EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2998
cbe61d8a 2999void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 3000{
27abe060 3001 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 3002 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 3003}
7322fd19 3004EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 3005
cbe61d8a 3006void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 3007{
f9b604f6
GJ		 3008 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3009 AH_TSF_WRITE_TIMEOUT))
d2182b69 3010 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 3011 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 3012
f1dc5600
S		 3013 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3014}
7322fd19 3015EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 3016
60ca9f87 3017void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 3018{
60ca9f87 3019 if (set)
2660b81a 3020 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 3021 else
2660b81a 3022 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 3023}
7322fd19 3024EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 3025
e4744ec7 3026void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 3027{
3028 u32 macmode;
3029
e4744ec7 3030 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 3031 macmode = AR_2040_JOINED_RX_CLEAR;
3032 else
3033 macmode = 0;
f078f209 3034
f1dc5600 3035 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 3036}
ff155a45
VT		 3037
3038/* HW Generic timers configuration */
3039
3040static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3041{
3042 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3043 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3044 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3045 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3046 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3047 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3048 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3049 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3050 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3051 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3052 AR_NDP2_TIMER_MODE, 0x0002},
3053 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3054 AR_NDP2_TIMER_MODE, 0x0004},
3055 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3056 AR_NDP2_TIMER_MODE, 0x0008},
3057 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3058 AR_NDP2_TIMER_MODE, 0x0010},
3059 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3060 AR_NDP2_TIMER_MODE, 0x0020},
3061 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3062 AR_NDP2_TIMER_MODE, 0x0040},
3063 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3064 AR_NDP2_TIMER_MODE, 0x0080}
3065};
3066
3067/* HW generic timer primitives */
3068
dd347f2f 3069u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 3070{
3071 return REG_READ(ah, AR_TSF_L32);
3072}
dd347f2f 3073EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45 3074
f4c34af4
SM		 3075void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
3076{
3077 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3078
3079 if (timer_table->tsf2_enabled) {
3080 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
3081 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
3082 }
3083}
3084
ff155a45
VT		 3085struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3086 void (*trigger)(void *),
3087 void (*overflow)(void *),
3088 void *arg,
3089 u8 timer_index)
3090{
3091 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3092 struct ath_gen_timer *timer;
3093
c67ce339 3094 if ((timer_index < AR_FIRST_NDP_TIMER) ||
f4c34af4
SM		 3095 (timer_index >= ATH_MAX_GEN_TIMER))
3096 return NULL;
3097
3098 if ((timer_index > AR_FIRST_NDP_TIMER) &&
3099 !AR_SREV_9300_20_OR_LATER(ah))
c67ce339
FF		 3100 return NULL;
3101
ff155a45 3102 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 3103 if (timer == NULL)
ff155a45 3104 return NULL;
ff155a45
VT		 3105
3106 /* allocate a hardware generic timer slot */
3107 timer_table->timers[timer_index] = timer;
3108 timer->index = timer_index;
3109 timer->trigger = trigger;
3110 timer->overflow = overflow;
3111 timer->arg = arg;
3112
f4c34af4
SM		 3113 if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
3114 timer_table->tsf2_enabled = true;
3115 ath9k_hw_gen_timer_start_tsf2(ah);
3116 }
3117
ff155a45
VT		 3118 return timer;
3119}
7322fd19 3120EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3121
cd9bf689
LR		 3122void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3123 struct ath_gen_timer *timer,
c67ce339 3124 u32 timer_next,
cd9bf689 3125 u32 timer_period)
ff155a45
VT		 3126{
3127 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 3128 u32 mask = 0;
788f6875 3129
c67ce339 3130 timer_table->timer_mask |= BIT(timer->index);
ff155a45 3131
ff155a45
VT		 3132 /*
3133 * Program generic timer registers
3134 */
3135 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3136 timer_next);
3137 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3138 timer_period);
3139 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3140 gen_tmr_configuration[timer->index].mode_mask);
3141
a4a2954f 3142 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 3143 /*
423e38e8 3144 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3145 * to use. But we still follow the old rule, 0 - 7 use tsf and
3146 * 8 - 15 use tsf2.
3147 */
3148 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3149 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3150 (1 << timer->index));
3151 else
3152 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3153 (1 << timer->index));
3154 }
3155
c67ce339
FF		 3156 if (timer->trigger)
3157 mask |= SM(AR_GENTMR_BIT(timer->index),
3158 AR_IMR_S5_GENTIMER_TRIG);
3159 if (timer->overflow)
3160 mask |= SM(AR_GENTMR_BIT(timer->index),
3161 AR_IMR_S5_GENTIMER_THRESH);
3162
3163 REG_SET_BIT(ah, AR_IMR_S5, mask);
3164
3165 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3166 ah->imask |= ATH9K_INT_GENTIMER;
3167 ath9k_hw_set_interrupts(ah);
3168 }
ff155a45 3169}
7322fd19 3170EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3171
cd9bf689 3172void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3173{
3174 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3175
ff155a45
VT		 3176 /* Clear generic timer enable bits. */
3177 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3178 gen_tmr_configuration[timer->index].mode_mask);
3179
b7f59766
SM		 3180 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3181 /*
3182 * Need to switch back to TSF if it was using TSF2.
3183 */
3184 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3185 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3186 (1 << timer->index));
3187 }
3188 }
3189
ff155a45
VT		 3190 /* Disable both trigger and thresh interrupt masks */
3191 REG_CLR_BIT(ah, AR_IMR_S5,
3192 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3193 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3194
c67ce339
FF		 3195 timer_table->timer_mask &= ~BIT(timer->index);
3196
3197 if (timer_table->timer_mask == 0) {
3198 ah->imask &= ~ATH9K_INT_GENTIMER;
3199 ath9k_hw_set_interrupts(ah);
3200 }
ff155a45 3201}
7322fd19 3202EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3203
3204void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3205{
3206 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3207
3208 /* free the hardware generic timer slot */
3209 timer_table->timers[timer->index] = NULL;
3210 kfree(timer);
3211}
7322fd19 3212EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3213
3214/*
3215 * Generic Timer Interrupts handling
3216 */
3217void ath_gen_timer_isr(struct ath_hw *ah)
3218{
3219 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3220 struct ath_gen_timer *timer;
c67ce339
FF		 3221 unsigned long trigger_mask, thresh_mask;
3222 unsigned int index;
ff155a45
VT		 3223
3224 /* get hardware generic timer interrupt status */
3225 trigger_mask = ah->intr_gen_timer_trigger;
3226 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 3227 trigger_mask &= timer_table->timer_mask;
3228 thresh_mask &= timer_table->timer_mask;
ff155a45 3229
c67ce339 3230 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3231 timer = timer_table->timers[index];
c67ce339
FF		 3232 if (!timer)
3233 continue;
3234 if (!timer->overflow)
3235 continue;
a6a172b2
FF		 3236
3237 trigger_mask &= ~BIT(index);
ff155a45
VT		 3238 timer->overflow(timer->arg);
3239 }
3240
c67ce339 3241 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3242 timer = timer_table->timers[index];
c67ce339
FF		 3243 if (!timer)
3244 continue;
3245 if (!timer->trigger)
3246 continue;
ff155a45
VT		 3247 timer->trigger(timer->arg);
3248 }
3249}
7322fd19 3250EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3251
05020d23
S		 3252/********/
3253/* HTC */
3254/********/
3255
2da4f01a
LR		 3256static struct {
3257 u32 version;
3258 const char * name;
3259} ath_mac_bb_names[] = {
3260 /* Devices with external radios */
3261 { AR_SREV_VERSION_5416_PCI, "5416" },
3262 { AR_SREV_VERSION_5416_PCIE, "5418" },
3263 { AR_SREV_VERSION_9100, "9100" },
3264 { AR_SREV_VERSION_9160, "9160" },
3265 /* Single-chip solutions */
3266 { AR_SREV_VERSION_9280, "9280" },
3267 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3268 { AR_SREV_VERSION_9287, "9287" },
3269 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3270 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3271 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3272 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3273 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3274 { AR_SREV_VERSION_9462, "9462" },
485124cb 3275 { AR_SREV_VERSION_9550, "9550" },
77fac465 3276 { AR_SREV_VERSION_9565, "9565" },
c08148bb 3277 { AR_SREV_VERSION_9531, "9531" },
1165dd90 3278 { AR_SREV_VERSION_9561, "9561" },
2da4f01a
LR		 3279};
3280
3281/* For devices with external radios */
3282static struct {
3283 u16 version;
3284 const char * name;
3285} ath_rf_names[] = {
3286 { 0, "5133" },
3287 { AR_RAD5133_SREV_MAJOR, "5133" },
3288 { AR_RAD5122_SREV_MAJOR, "5122" },
3289 { AR_RAD2133_SREV_MAJOR, "2133" },
3290 { AR_RAD2122_SREV_MAJOR, "2122" }
3291};
3292
3293/*
3294 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3295 */
f934c4d9 3296static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3297{
3298 int i;
3299
3300 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3301 if (ath_mac_bb_names[i].version == mac_bb_version) {
3302 return ath_mac_bb_names[i].name;
3303 }
3304 }
3305
3306 return "????";
3307}
2da4f01a
LR		 3308
3309/*
3310 * Return the RF name. "????" is returned if the RF is unknown.
3311 * Used for devices with external radios.
3312 */
f934c4d9 3313static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3314{
3315 int i;
3316
3317 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3318 if (ath_rf_names[i].version == rf_version) {
3319 return ath_rf_names[i].name;
3320 }
3321 }
3322
3323 return "????";
3324}
f934c4d9
LR		 3325
3326void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3327{
3328 int used;
3329
3330 /* chipsets >= AR9280 are single-chip */
7a37081e 3331 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3332 used = scnprintf(hw_name, len,
3333 "Atheros AR%s Rev:%x",
3334 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3335 ah->hw_version.macRev);
f934c4d9
LR		 3336 }
3337 else {
5e88ba62
ZK		 3338 used = scnprintf(hw_name, len,
3339 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3340 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3341 ah->hw_version.macRev,
3342 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3343 & AR_RADIO_SREV_MAJOR)),
3344 ah->hw_version.phyRev);
f934c4d9
LR		 3345 }
3346
3347 hw_name[used] = '\0';
3348}
3349EXPORT_SYMBOL(ath9k_hw_name);
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