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f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef HW_H | |
18 | #define HW_H | |
19 | ||
20 | #include <linux/if_ether.h> | |
21 | #include <linux/delay.h> | |
394cf0a1 S |
22 | #include <linux/io.h> |
23 | ||
24 | #include "mac.h" | |
25 | #include "ani.h" | |
26 | #include "eeprom.h" | |
27 | #include "calib.h" | |
394cf0a1 S |
28 | #include "reg.h" |
29 | #include "phy.h" | |
af03abec | 30 | #include "btcoex.h" |
394cf0a1 | 31 | |
203c4805 | 32 | #include "../regd.h" |
3a702e49 | 33 | |
394cf0a1 | 34 | #define ATHEROS_VENDOR_ID 0x168c |
7976b426 | 35 | |
394cf0a1 S |
36 | #define AR5416_DEVID_PCI 0x0023 |
37 | #define AR5416_DEVID_PCIE 0x0024 | |
38 | #define AR9160_DEVID_PCI 0x0027 | |
39 | #define AR9280_DEVID_PCI 0x0029 | |
40 | #define AR9280_DEVID_PCIE 0x002a | |
41 | #define AR9285_DEVID_PCIE 0x002b | |
5ffaf8a3 | 42 | #define AR2427_DEVID_PCIE 0x002c |
db3cc53a SB |
43 | #define AR9287_DEVID_PCI 0x002d |
44 | #define AR9287_DEVID_PCIE 0x002e | |
45 | #define AR9300_DEVID_PCIE 0x0030 | |
b99a7be4 | 46 | #define AR9300_DEVID_AR9340 0x0031 |
3050c914 | 47 | #define AR9300_DEVID_AR9485_PCIE 0x0032 |
03689301 | 48 | #define AR9300_DEVID_AR9330 0x0035 |
7976b426 | 49 | |
394cf0a1 | 50 | #define AR5416_AR9100_DEVID 0x000b |
7976b426 | 51 | |
394cf0a1 S |
52 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
53 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | |
54 | #define AR5416_MAGIC 0x19641014 | |
55 | ||
fe12946e VT |
56 | #define AR9280_COEX2WIRE_SUBSYSID 0x309b |
57 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa | |
58 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab | |
59 | ||
a6ef530f VN |
60 | #define AR9300_NUM_BT_WEIGHTS 4 |
61 | #define AR9300_NUM_WLAN_WEIGHTS 4 | |
62 | ||
e3d01bfc LR |
63 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
64 | ||
cfe8cba9 LR |
65 | #define ATH_DEFAULT_NOISE_FLOOR -95 |
66 | ||
04658fba | 67 | #define ATH9K_RSSI_BAD -128 |
990b70ab | 68 | |
cac4220b FF |
69 | #define ATH9K_NUM_CHANNELS 38 |
70 | ||
394cf0a1 | 71 | /* Register read/write primitives */ |
9e4bffd2 | 72 | #define REG_WRITE(_ah, _reg, _val) \ |
f9f84e96 | 73 | (_ah)->reg_ops.write((_ah), (_val), (_reg)) |
9e4bffd2 LR |
74 | |
75 | #define REG_READ(_ah, _reg) \ | |
f9f84e96 | 76 | (_ah)->reg_ops.read((_ah), (_reg)) |
394cf0a1 | 77 | |
09a525d3 | 78 | #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ |
f9f84e96 | 79 | (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) |
09a525d3 | 80 | |
845e03c9 FF |
81 | #define REG_RMW(_ah, _reg, _set, _clr) \ |
82 | (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) | |
83 | ||
20b3efd9 S |
84 | #define ENABLE_REGWRITE_BUFFER(_ah) \ |
85 | do { \ | |
f9f84e96 FF |
86 | if ((_ah)->reg_ops.enable_write_buffer) \ |
87 | (_ah)->reg_ops.enable_write_buffer((_ah)); \ | |
20b3efd9 S |
88 | } while (0) |
89 | ||
20b3efd9 S |
90 | #define REGWRITE_BUFFER_FLUSH(_ah) \ |
91 | do { \ | |
f9f84e96 FF |
92 | if ((_ah)->reg_ops.write_flush) \ |
93 | (_ah)->reg_ops.write_flush((_ah)); \ | |
20b3efd9 S |
94 | } while (0) |
95 | ||
394cf0a1 S |
96 | #define SM(_v, _f) (((_v) << _f##_S) & _f) |
97 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | |
394cf0a1 | 98 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ |
845e03c9 | 99 | REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) |
1547da37 LR |
100 | #define REG_READ_FIELD(_a, _r, _f) \ |
101 | (((REG_READ(_a, _r) & _f) >> _f##_S)) | |
394cf0a1 | 102 | #define REG_SET_BIT(_a, _r, _f) \ |
845e03c9 | 103 | REG_RMW(_a, _r, (_f), 0) |
394cf0a1 | 104 | #define REG_CLR_BIT(_a, _r, _f) \ |
845e03c9 | 105 | REG_RMW(_a, _r, 0, (_f)) |
f078f209 | 106 | |
e7fc6338 RM |
107 | #define DO_DELAY(x) do { \ |
108 | if (((++(x) % 64) == 0) && \ | |
109 | (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ | |
110 | != ATH_USB)) \ | |
111 | udelay(1); \ | |
394cf0a1 | 112 | } while (0) |
f078f209 | 113 | |
a9b6b256 FF |
114 | #define REG_WRITE_ARRAY(iniarray, column, regWr) \ |
115 | ath9k_hw_write_array(ah, iniarray, column, &(regWr)) | |
f078f209 | 116 | |
394cf0a1 S |
117 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
118 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | |
119 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | |
120 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 | |
1773912b | 121 | #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 |
394cf0a1 S |
122 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
123 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | |
f078f209 | 124 | |
394cf0a1 S |
125 | #define AR_GPIOD_MASK 0x00001FFF |
126 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | |
f078f209 | 127 | |
394cf0a1 | 128 | #define BASE_ACTIVATE_DELAY 100 |
0b488ac6 | 129 | #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) |
394cf0a1 S |
130 | #define COEF_SCALE_S 24 |
131 | #define HT40_CHANNEL_CENTER_SHIFT 10 | |
f078f209 | 132 | |
394cf0a1 S |
133 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
134 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 | |
135 | ||
136 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 | |
137 | #define ATH9K_NUM_QUEUES 10 | |
138 | ||
139 | #define MAX_RATE_POWER 63 | |
0caa7b14 | 140 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
f9b604f6 | 141 | #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ |
394cf0a1 S |
142 | #define AH_TIME_QUANTUM 10 |
143 | #define AR_KEYTABLE_SIZE 128 | |
d8caa839 | 144 | #define POWER_UP_TIME 10000 |
394cf0a1 S |
145 | #define SPUR_RSSI_THRESH 40 |
146 | ||
147 | #define CAB_TIMEOUT_VAL 10 | |
148 | #define BEACON_TIMEOUT_VAL 10 | |
149 | #define MIN_BEACON_TIMEOUT_VAL 1 | |
150 | #define SLEEP_SLOP 3 | |
151 | ||
152 | #define INIT_CONFIG_STATUS 0x00000000 | |
153 | #define INIT_RSSI_THR 0x00000700 | |
154 | #define INIT_BCON_CNTRL_REG 0x00000000 | |
155 | ||
156 | #define TU_TO_USEC(_tu) ((_tu) << 10) | |
157 | ||
ceb26445 VT |
158 | #define ATH9K_HW_RX_HP_QDEPTH 16 |
159 | #define ATH9K_HW_RX_LP_QDEPTH 128 | |
160 | ||
0e44d48c MSS |
161 | #define PAPRD_GAIN_TABLE_ENTRIES 32 |
162 | #define PAPRD_TABLE_SZ 24 | |
163 | #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 | |
717f6bed | 164 | |
066dae93 FF |
165 | enum ath_hw_txq_subtype { |
166 | ATH_TXQ_AC_BE = 0, | |
167 | ATH_TXQ_AC_BK = 1, | |
168 | ATH_TXQ_AC_VI = 2, | |
169 | ATH_TXQ_AC_VO = 3, | |
170 | }; | |
171 | ||
13ce3e99 LR |
172 | enum ath_ini_subsys { |
173 | ATH_INI_PRE = 0, | |
174 | ATH_INI_CORE, | |
175 | ATH_INI_POST, | |
176 | ATH_INI_NUM_SPLIT, | |
177 | }; | |
178 | ||
394cf0a1 | 179 | enum ath9k_hw_caps { |
364734fa FF |
180 | ATH9K_HW_CAP_HT = BIT(0), |
181 | ATH9K_HW_CAP_RFSILENT = BIT(1), | |
182 | ATH9K_HW_CAP_CST = BIT(2), | |
364734fa FF |
183 | ATH9K_HW_CAP_AUTOSLEEP = BIT(4), |
184 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5), | |
185 | ATH9K_HW_CAP_EDMA = BIT(6), | |
186 | ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7), | |
187 | ATH9K_HW_CAP_LDPC = BIT(8), | |
188 | ATH9K_HW_CAP_FASTCLOCK = BIT(9), | |
189 | ATH9K_HW_CAP_SGI_20 = BIT(10), | |
190 | ATH9K_HW_CAP_PAPRD = BIT(11), | |
191 | ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12), | |
d4659912 FF |
192 | ATH9K_HW_CAP_2GHZ = BIT(13), |
193 | ATH9K_HW_CAP_5GHZ = BIT(14), | |
ea066d5a | 194 | ATH9K_HW_CAP_APM = BIT(15), |
394cf0a1 | 195 | }; |
f078f209 | 196 | |
394cf0a1 S |
197 | struct ath9k_hw_capabilities { |
198 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | |
394cf0a1 S |
199 | u16 rts_aggr_limit; |
200 | u8 tx_chainmask; | |
201 | u8 rx_chainmask; | |
47c80de6 VT |
202 | u8 max_txchains; |
203 | u8 max_rxchains; | |
394cf0a1 | 204 | u8 num_gpio_pins; |
ceb26445 VT |
205 | u8 rx_hp_qdepth; |
206 | u8 rx_lp_qdepth; | |
207 | u8 rx_status_len; | |
162c3be3 | 208 | u8 tx_desc_len; |
5088c2f1 | 209 | u8 txs_len; |
8060e169 VT |
210 | u16 pcie_lcr_offset; |
211 | bool pcie_lcr_extsync_en; | |
394cf0a1 | 212 | }; |
f078f209 | 213 | |
394cf0a1 S |
214 | struct ath9k_ops_config { |
215 | int dma_beacon_response_time; | |
216 | int sw_beacon_response_time; | |
217 | int additional_swba_backoff; | |
218 | int ack_6mb; | |
41f3e54d | 219 | u32 cwm_ignore_extcca; |
394cf0a1 | 220 | u8 pcie_powersave_enable; |
6a0ec30a | 221 | bool pcieSerDesWrite; |
394cf0a1 S |
222 | u8 pcie_clock_req; |
223 | u32 pcie_waen; | |
394cf0a1 | 224 | u8 analog_shiftreg; |
6f481010 | 225 | u8 paprd_disable; |
394cf0a1 S |
226 | u32 ofdm_trig_low; |
227 | u32 ofdm_trig_high; | |
228 | u32 cck_trig_high; | |
229 | u32 cck_trig_low; | |
230 | u32 enable_ani; | |
394cf0a1 | 231 | int serialize_regmode; |
0ce024cb | 232 | bool rx_intr_mitigation; |
55e82df4 | 233 | bool tx_intr_mitigation; |
394cf0a1 S |
234 | #define SPUR_DISABLE 0 |
235 | #define SPUR_ENABLE_IOCTL 1 | |
236 | #define SPUR_ENABLE_EEPROM 2 | |
394cf0a1 S |
237 | #define AR_SPUR_5413_1 1640 |
238 | #define AR_SPUR_5413_2 1200 | |
239 | #define AR_NO_SPUR 0x8000 | |
240 | #define AR_BASE_FREQ_2GHZ 2300 | |
241 | #define AR_BASE_FREQ_5GHZ 4900 | |
242 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | |
243 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | |
244 | int spurmode; | |
245 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; | |
f4709fdf | 246 | u8 max_txtrig_level; |
e36b27af | 247 | u16 ani_poll_interval; /* ANI poll interval in ms */ |
394cf0a1 | 248 | }; |
f078f209 | 249 | |
394cf0a1 S |
250 | enum ath9k_int { |
251 | ATH9K_INT_RX = 0x00000001, | |
252 | ATH9K_INT_RXDESC = 0x00000002, | |
b5c80475 FF |
253 | ATH9K_INT_RXHP = 0x00000001, |
254 | ATH9K_INT_RXLP = 0x00000002, | |
394cf0a1 S |
255 | ATH9K_INT_RXNOFRM = 0x00000008, |
256 | ATH9K_INT_RXEOL = 0x00000010, | |
257 | ATH9K_INT_RXORN = 0x00000020, | |
258 | ATH9K_INT_TX = 0x00000040, | |
259 | ATH9K_INT_TXDESC = 0x00000080, | |
260 | ATH9K_INT_TIM_TIMER = 0x00000100, | |
aea702b7 | 261 | ATH9K_INT_BB_WATCHDOG = 0x00000400, |
394cf0a1 S |
262 | ATH9K_INT_TXURN = 0x00000800, |
263 | ATH9K_INT_MIB = 0x00001000, | |
264 | ATH9K_INT_RXPHY = 0x00004000, | |
265 | ATH9K_INT_RXKCM = 0x00008000, | |
266 | ATH9K_INT_SWBA = 0x00010000, | |
267 | ATH9K_INT_BMISS = 0x00040000, | |
268 | ATH9K_INT_BNR = 0x00100000, | |
269 | ATH9K_INT_TIM = 0x00200000, | |
270 | ATH9K_INT_DTIM = 0x00400000, | |
271 | ATH9K_INT_DTIMSYNC = 0x00800000, | |
272 | ATH9K_INT_GPIO = 0x01000000, | |
273 | ATH9K_INT_CABEND = 0x02000000, | |
4af9cf4f | 274 | ATH9K_INT_TSFOOR = 0x04000000, |
ff155a45 | 275 | ATH9K_INT_GENTIMER = 0x08000000, |
394cf0a1 S |
276 | ATH9K_INT_CST = 0x10000000, |
277 | ATH9K_INT_GTT = 0x20000000, | |
278 | ATH9K_INT_FATAL = 0x40000000, | |
279 | ATH9K_INT_GLOBAL = 0x80000000, | |
280 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | |
281 | ATH9K_INT_DTIM | | |
282 | ATH9K_INT_DTIMSYNC | | |
4af9cf4f | 283 | ATH9K_INT_TSFOOR | |
394cf0a1 S |
284 | ATH9K_INT_CABEND, |
285 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | |
286 | ATH9K_INT_RXDESC | | |
287 | ATH9K_INT_RXEOL | | |
288 | ATH9K_INT_RXORN | | |
289 | ATH9K_INT_TXURN | | |
290 | ATH9K_INT_TXDESC | | |
291 | ATH9K_INT_MIB | | |
292 | ATH9K_INT_RXPHY | | |
293 | ATH9K_INT_RXKCM | | |
294 | ATH9K_INT_SWBA | | |
295 | ATH9K_INT_BMISS | | |
296 | ATH9K_INT_GPIO, | |
297 | ATH9K_INT_NOCARD = 0xffffffff | |
298 | }; | |
f078f209 | 299 | |
394cf0a1 S |
300 | #define CHANNEL_CW_INT 0x00002 |
301 | #define CHANNEL_CCK 0x00020 | |
302 | #define CHANNEL_OFDM 0x00040 | |
303 | #define CHANNEL_2GHZ 0x00080 | |
304 | #define CHANNEL_5GHZ 0x00100 | |
305 | #define CHANNEL_PASSIVE 0x00200 | |
306 | #define CHANNEL_DYN 0x00400 | |
307 | #define CHANNEL_HALF 0x04000 | |
308 | #define CHANNEL_QUARTER 0x08000 | |
309 | #define CHANNEL_HT20 0x10000 | |
310 | #define CHANNEL_HT40PLUS 0x20000 | |
311 | #define CHANNEL_HT40MINUS 0x40000 | |
312 | ||
394cf0a1 S |
313 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
314 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) | |
315 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) | |
316 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) | |
317 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) | |
318 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) | |
319 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) | |
320 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) | |
321 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) | |
322 | #define CHANNEL_ALL \ | |
323 | (CHANNEL_OFDM| \ | |
324 | CHANNEL_CCK| \ | |
325 | CHANNEL_2GHZ | \ | |
326 | CHANNEL_5GHZ | \ | |
327 | CHANNEL_HT20 | \ | |
328 | CHANNEL_HT40PLUS | \ | |
329 | CHANNEL_HT40MINUS) | |
330 | ||
20bd2a09 | 331 | struct ath9k_hw_cal_data { |
394cf0a1 S |
332 | u16 channel; |
333 | u32 channelFlags; | |
394cf0a1 | 334 | int32_t CalValid; |
394cf0a1 S |
335 | int8_t iCoff; |
336 | int8_t qCoff; | |
717f6bed | 337 | bool paprd_done; |
4254bc1c | 338 | bool nfcal_pending; |
70cf1533 | 339 | bool nfcal_interference; |
717f6bed FF |
340 | u16 small_signal_gain[AR9300_MAX_CHAINS]; |
341 | u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; | |
20bd2a09 FF |
342 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
343 | }; | |
344 | ||
345 | struct ath9k_channel { | |
346 | struct ieee80211_channel *chan; | |
093115b7 | 347 | struct ar5416AniState ani; |
20bd2a09 FF |
348 | u16 channel; |
349 | u32 channelFlags; | |
350 | u32 chanmode; | |
d9891c78 | 351 | s16 noisefloor; |
394cf0a1 | 352 | }; |
f078f209 | 353 | |
394cf0a1 S |
354 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ |
355 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ | |
356 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ | |
357 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) | |
358 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) | |
359 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) | |
360 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) | |
394cf0a1 S |
361 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) |
362 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) | |
6b42e8d0 | 363 | #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ |
394cf0a1 | 364 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ |
6b42e8d0 | 365 | ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) |
394cf0a1 S |
366 | |
367 | /* These macros check chanmode and not channelFlags */ | |
368 | #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) | |
369 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ | |
370 | ((_c)->chanmode == CHANNEL_G_HT20)) | |
371 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ | |
372 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ | |
373 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ | |
374 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) | |
375 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) | |
376 | ||
377 | enum ath9k_power_mode { | |
378 | ATH9K_PM_AWAKE = 0, | |
379 | ATH9K_PM_FULL_SLEEP, | |
380 | ATH9K_PM_NETWORK_SLEEP, | |
381 | ATH9K_PM_UNDEFINED | |
382 | }; | |
f078f209 | 383 | |
394cf0a1 S |
384 | enum ath9k_tp_scale { |
385 | ATH9K_TP_SCALE_MAX = 0, | |
386 | ATH9K_TP_SCALE_50, | |
387 | ATH9K_TP_SCALE_25, | |
388 | ATH9K_TP_SCALE_12, | |
389 | ATH9K_TP_SCALE_MIN | |
390 | }; | |
f078f209 | 391 | |
394cf0a1 S |
392 | enum ser_reg_mode { |
393 | SER_REG_MODE_OFF = 0, | |
394 | SER_REG_MODE_ON = 1, | |
395 | SER_REG_MODE_AUTO = 2, | |
396 | }; | |
f078f209 | 397 | |
ad7b8060 VT |
398 | enum ath9k_rx_qtype { |
399 | ATH9K_RX_QUEUE_HP, | |
400 | ATH9K_RX_QUEUE_LP, | |
401 | ATH9K_RX_QUEUE_MAX, | |
402 | }; | |
403 | ||
394cf0a1 S |
404 | struct ath9k_beacon_state { |
405 | u32 bs_nexttbtt; | |
406 | u32 bs_nextdtim; | |
407 | u32 bs_intval; | |
4af9cf4f | 408 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
394cf0a1 S |
409 | u32 bs_dtimperiod; |
410 | u16 bs_cfpperiod; | |
411 | u16 bs_cfpmaxduration; | |
412 | u32 bs_cfpnext; | |
413 | u16 bs_timoffset; | |
414 | u16 bs_bmissthreshold; | |
415 | u32 bs_sleepduration; | |
4af9cf4f | 416 | u32 bs_tsfoor_threshold; |
394cf0a1 | 417 | }; |
f078f209 | 418 | |
394cf0a1 S |
419 | struct chan_centers { |
420 | u16 synth_center; | |
421 | u16 ctl_center; | |
422 | u16 ext_center; | |
423 | }; | |
f078f209 | 424 | |
394cf0a1 S |
425 | enum { |
426 | ATH9K_RESET_POWER_ON, | |
427 | ATH9K_RESET_WARM, | |
428 | ATH9K_RESET_COLD, | |
429 | }; | |
f078f209 | 430 | |
d535a42a S |
431 | struct ath9k_hw_version { |
432 | u32 magic; | |
433 | u16 devid; | |
434 | u16 subvendorid; | |
435 | u32 macVersion; | |
436 | u16 macRev; | |
437 | u16 phyRev; | |
438 | u16 analog5GhzRev; | |
439 | u16 analog2GhzRev; | |
aeac355d | 440 | u16 subsysid; |
0b5ead91 | 441 | enum ath_usb_dev usbdev; |
d535a42a | 442 | }; |
394cf0a1 | 443 | |
ff155a45 VT |
444 | /* Generic TSF timer definitions */ |
445 | ||
446 | #define ATH_MAX_GEN_TIMER 16 | |
447 | ||
448 | #define AR_GENTMR_BIT(_index) (1 << (_index)) | |
449 | ||
450 | /* | |
77c2061d | 451 | * Using de Bruijin sequence to look up 1's index in a 32 bit number |
ff155a45 VT |
452 | * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 |
453 | */ | |
c90017dd | 454 | #define debruijn32 0x077CB531U |
ff155a45 VT |
455 | |
456 | struct ath_gen_timer_configuration { | |
457 | u32 next_addr; | |
458 | u32 period_addr; | |
459 | u32 mode_addr; | |
460 | u32 mode_mask; | |
461 | }; | |
462 | ||
463 | struct ath_gen_timer { | |
464 | void (*trigger)(void *arg); | |
465 | void (*overflow)(void *arg); | |
466 | void *arg; | |
467 | u8 index; | |
468 | }; | |
469 | ||
470 | struct ath_gen_timer_table { | |
471 | u32 gen_timer_index[32]; | |
472 | struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; | |
473 | union { | |
474 | unsigned long timer_bits; | |
475 | u16 val; | |
476 | } timer_mask; | |
477 | }; | |
478 | ||
21cc630f VT |
479 | struct ath_hw_antcomb_conf { |
480 | u8 main_lna_conf; | |
481 | u8 alt_lna_conf; | |
482 | u8 fast_div_bias; | |
c6ba9feb MSS |
483 | u8 main_gaintb; |
484 | u8 alt_gaintb; | |
485 | int lna1_lna2_delta; | |
8afbcc8b | 486 | u8 div_group; |
21cc630f VT |
487 | }; |
488 | ||
4e8c14e9 FF |
489 | /** |
490 | * struct ath_hw_radar_conf - radar detection initialization parameters | |
491 | * | |
492 | * @pulse_inband: threshold for checking the ratio of in-band power | |
493 | * to total power for short radar pulses (half dB steps) | |
494 | * @pulse_inband_step: threshold for checking an in-band power to total | |
495 | * power ratio increase for short radar pulses (half dB steps) | |
496 | * @pulse_height: threshold for detecting the beginning of a short | |
497 | * radar pulse (dB step) | |
498 | * @pulse_rssi: threshold for detecting if a short radar pulse is | |
499 | * gone (dB step) | |
500 | * @pulse_maxlen: maximum pulse length (0.8 us steps) | |
501 | * | |
502 | * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) | |
503 | * @radar_inband: threshold for checking the ratio of in-band power | |
504 | * to total power for long radar pulses (half dB steps) | |
505 | * @fir_power: threshold for detecting the end of a long radar pulse (dB) | |
506 | * | |
507 | * @ext_channel: enable extension channel radar detection | |
508 | */ | |
509 | struct ath_hw_radar_conf { | |
510 | unsigned int pulse_inband; | |
511 | unsigned int pulse_inband_step; | |
512 | unsigned int pulse_height; | |
513 | unsigned int pulse_rssi; | |
514 | unsigned int pulse_maxlen; | |
515 | ||
516 | unsigned int radar_rssi; | |
517 | unsigned int radar_inband; | |
518 | int fir_power; | |
519 | ||
520 | bool ext_channel; | |
521 | }; | |
522 | ||
d70357d5 LR |
523 | /** |
524 | * struct ath_hw_private_ops - callbacks used internally by hardware code | |
525 | * | |
526 | * This structure contains private callbacks designed to only be used internally | |
527 | * by the hardware core. | |
528 | * | |
795f5e2c LR |
529 | * @init_cal_settings: setup types of calibrations supported |
530 | * @init_cal: starts actual calibration | |
531 | * | |
d70357d5 | 532 | * @init_mode_regs: Initializes mode registers |
991312d8 | 533 | * @init_mode_gain_regs: Initialize TX/RX gain registers |
8fe65368 LR |
534 | * |
535 | * @rf_set_freq: change frequency | |
536 | * @spur_mitigate_freq: spur mitigation | |
537 | * @rf_alloc_ext_banks: | |
538 | * @rf_free_ext_banks: | |
539 | * @set_rf_regs: | |
64773964 LR |
540 | * @compute_pll_control: compute the PLL control value to use for |
541 | * AR_RTC_PLL_CONTROL for a given channel | |
795f5e2c LR |
542 | * @setup_calibration: set up calibration |
543 | * @iscal_supported: used to query if a type of calibration is supported | |
ac0bb767 | 544 | * |
e36b27af LR |
545 | * @ani_cache_ini_regs: cache the values for ANI from the initial |
546 | * register settings through the register initialization. | |
d70357d5 LR |
547 | */ |
548 | struct ath_hw_private_ops { | |
795f5e2c | 549 | /* Calibration ops */ |
d70357d5 | 550 | void (*init_cal_settings)(struct ath_hw *ah); |
795f5e2c LR |
551 | bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); |
552 | ||
d70357d5 | 553 | void (*init_mode_regs)(struct ath_hw *ah); |
991312d8 | 554 | void (*init_mode_gain_regs)(struct ath_hw *ah); |
795f5e2c LR |
555 | void (*setup_calibration)(struct ath_hw *ah, |
556 | struct ath9k_cal_list *currCal); | |
8fe65368 LR |
557 | |
558 | /* PHY ops */ | |
559 | int (*rf_set_freq)(struct ath_hw *ah, | |
560 | struct ath9k_channel *chan); | |
561 | void (*spur_mitigate_freq)(struct ath_hw *ah, | |
562 | struct ath9k_channel *chan); | |
563 | int (*rf_alloc_ext_banks)(struct ath_hw *ah); | |
564 | void (*rf_free_ext_banks)(struct ath_hw *ah); | |
565 | bool (*set_rf_regs)(struct ath_hw *ah, | |
566 | struct ath9k_channel *chan, | |
567 | u16 modesIndex); | |
568 | void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); | |
569 | void (*init_bb)(struct ath_hw *ah, | |
570 | struct ath9k_channel *chan); | |
571 | int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); | |
572 | void (*olc_init)(struct ath_hw *ah); | |
573 | void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); | |
574 | void (*mark_phy_inactive)(struct ath_hw *ah); | |
575 | void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); | |
576 | bool (*rfbus_req)(struct ath_hw *ah); | |
577 | void (*rfbus_done)(struct ath_hw *ah); | |
8fe65368 LR |
578 | void (*restore_chainmask)(struct ath_hw *ah); |
579 | void (*set_diversity)(struct ath_hw *ah, bool value); | |
64773964 LR |
580 | u32 (*compute_pll_control)(struct ath_hw *ah, |
581 | struct ath9k_channel *chan); | |
c16fcb49 FF |
582 | bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, |
583 | int param); | |
641d9921 | 584 | void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); |
4e8c14e9 FF |
585 | void (*set_radar_params)(struct ath_hw *ah, |
586 | struct ath_hw_radar_conf *conf); | |
ac0bb767 LR |
587 | |
588 | /* ANI */ | |
e36b27af | 589 | void (*ani_cache_ini_regs)(struct ath_hw *ah); |
d70357d5 LR |
590 | }; |
591 | ||
592 | /** | |
593 | * struct ath_hw_ops - callbacks used by hardware code and driver code | |
594 | * | |
595 | * This structure contains callbacks designed to to be used internally by | |
596 | * hardware code and also by the lower level driver. | |
597 | * | |
598 | * @config_pci_powersave: | |
795f5e2c | 599 | * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC |
d70357d5 LR |
600 | */ |
601 | struct ath_hw_ops { | |
602 | void (*config_pci_powersave)(struct ath_hw *ah, | |
603 | int restore, | |
604 | int power_off); | |
cee1f625 | 605 | void (*rx_enable)(struct ath_hw *ah); |
87d5efbb | 606 | void (*set_desc_link)(void *ds, u32 link); |
795f5e2c LR |
607 | bool (*calibrate)(struct ath_hw *ah, |
608 | struct ath9k_channel *chan, | |
609 | u8 rxchainmask, | |
610 | bool longcal); | |
55e82df4 | 611 | bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); |
cc610ac0 VT |
612 | void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen, |
613 | bool is_firstseg, bool is_is_lastseg, | |
614 | const void *ds0, dma_addr_t buf_addr, | |
615 | unsigned int qcu); | |
616 | int (*proc_txdesc)(struct ath_hw *ah, void *ds, | |
617 | struct ath_tx_status *ts); | |
618 | void (*set11n_txdesc)(struct ath_hw *ah, void *ds, | |
619 | u32 pktLen, enum ath9k_pkt_type type, | |
620 | u32 txPower, u32 keyIx, | |
621 | enum ath9k_key_type keyType, | |
622 | u32 flags); | |
623 | void (*set11n_ratescenario)(struct ath_hw *ah, void *ds, | |
624 | void *lastds, | |
625 | u32 durUpdateEn, u32 rtsctsRate, | |
626 | u32 rtsctsDuration, | |
627 | struct ath9k_11n_rate_series series[], | |
628 | u32 nseries, u32 flags); | |
629 | void (*set11n_aggr_first)(struct ath_hw *ah, void *ds, | |
630 | u32 aggrLen); | |
631 | void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds, | |
632 | u32 numDelims); | |
633 | void (*set11n_aggr_last)(struct ath_hw *ah, void *ds); | |
634 | void (*clr11n_aggr)(struct ath_hw *ah, void *ds); | |
5519541d | 635 | void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val); |
69de3721 MSS |
636 | void (*antdiv_comb_conf_get)(struct ath_hw *ah, |
637 | struct ath_hw_antcomb_conf *antconf); | |
638 | void (*antdiv_comb_conf_set)(struct ath_hw *ah, | |
639 | struct ath_hw_antcomb_conf *antconf); | |
640 | ||
d70357d5 LR |
641 | }; |
642 | ||
f2552e28 FF |
643 | struct ath_nf_limits { |
644 | s16 max; | |
645 | s16 min; | |
646 | s16 nominal; | |
647 | }; | |
648 | ||
97dcec57 SM |
649 | /* ah_flags */ |
650 | #define AH_USE_EEPROM 0x1 | |
651 | #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ | |
652 | ||
cbe61d8a | 653 | struct ath_hw { |
f9f84e96 FF |
654 | struct ath_ops reg_ops; |
655 | ||
b002a4a9 | 656 | struct ieee80211_hw *hw; |
27c51f1a | 657 | struct ath_common common; |
cbe61d8a | 658 | struct ath9k_hw_version hw_version; |
2660b81a S |
659 | struct ath9k_ops_config config; |
660 | struct ath9k_hw_capabilities caps; | |
cac4220b | 661 | struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; |
2660b81a | 662 | struct ath9k_channel *curchan; |
394cf0a1 | 663 | |
cbe61d8a S |
664 | union { |
665 | struct ar5416_eeprom_def def; | |
666 | struct ar5416_eeprom_4k map4k; | |
475f5989 | 667 | struct ar9287_eeprom map9287; |
15c9ee7a | 668 | struct ar9300_eeprom ar9300_eep; |
2660b81a | 669 | } eeprom; |
f74df6fb | 670 | const struct eeprom_ops *eep_ops; |
cbe61d8a S |
671 | |
672 | bool sw_mgmt_crypto; | |
2660b81a | 673 | bool is_pciexpress; |
5f841b41 | 674 | bool is_monitoring; |
2eb46d9b | 675 | bool need_an_top2_fixup; |
2660b81a | 676 | u16 tx_trig_level; |
f2552e28 | 677 | |
bbacee13 | 678 | u32 nf_regs[6]; |
f2552e28 FF |
679 | struct ath_nf_limits nf_2g; |
680 | struct ath_nf_limits nf_5g; | |
2660b81a S |
681 | u16 rfsilent; |
682 | u32 rfkill_gpio; | |
683 | u32 rfkill_polarity; | |
cbe61d8a | 684 | u32 ah_flags; |
394cf0a1 | 685 | |
d7e7d229 LR |
686 | bool htc_reset_init; |
687 | ||
2660b81a S |
688 | enum nl80211_iftype opmode; |
689 | enum ath9k_power_mode power_mode; | |
f078f209 | 690 | |
20bd2a09 | 691 | struct ath9k_hw_cal_data *caldata; |
a13883b0 | 692 | struct ath9k_pacal_info pacal_info; |
2660b81a S |
693 | struct ar5416Stats stats; |
694 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; | |
695 | ||
696 | int16_t curchan_rad_index; | |
3069168c | 697 | enum ath9k_int imask; |
74bad5cb | 698 | u32 imrs2_reg; |
2660b81a S |
699 | u32 txok_interrupt_mask; |
700 | u32 txerr_interrupt_mask; | |
701 | u32 txdesc_interrupt_mask; | |
702 | u32 txeol_interrupt_mask; | |
703 | u32 txurn_interrupt_mask; | |
704 | bool chip_fullsleep; | |
705 | u32 atim_window; | |
6a2b9e8c S |
706 | |
707 | /* Calibration */ | |
6497827f | 708 | u32 supp_cals; |
cbfe9468 S |
709 | struct ath9k_cal_list iq_caldata; |
710 | struct ath9k_cal_list adcgain_caldata; | |
cbfe9468 | 711 | struct ath9k_cal_list adcdc_caldata; |
df23acaa | 712 | struct ath9k_cal_list tempCompCalData; |
cbfe9468 S |
713 | struct ath9k_cal_list *cal_list; |
714 | struct ath9k_cal_list *cal_list_last; | |
715 | struct ath9k_cal_list *cal_list_curr; | |
2660b81a S |
716 | #define totalPowerMeasI meas0.unsign |
717 | #define totalPowerMeasQ meas1.unsign | |
718 | #define totalIqCorrMeas meas2.sign | |
719 | #define totalAdcIOddPhase meas0.unsign | |
720 | #define totalAdcIEvenPhase meas1.unsign | |
721 | #define totalAdcQOddPhase meas2.unsign | |
722 | #define totalAdcQEvenPhase meas3.unsign | |
723 | #define totalAdcDcOffsetIOddPhase meas0.sign | |
724 | #define totalAdcDcOffsetIEvenPhase meas1.sign | |
725 | #define totalAdcDcOffsetQOddPhase meas2.sign | |
726 | #define totalAdcDcOffsetQEvenPhase meas3.sign | |
f078f209 LR |
727 | union { |
728 | u32 unsign[AR5416_MAX_CHAINS]; | |
729 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 730 | } meas0; |
f078f209 LR |
731 | union { |
732 | u32 unsign[AR5416_MAX_CHAINS]; | |
733 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 734 | } meas1; |
f078f209 LR |
735 | union { |
736 | u32 unsign[AR5416_MAX_CHAINS]; | |
737 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 738 | } meas2; |
f078f209 LR |
739 | union { |
740 | u32 unsign[AR5416_MAX_CHAINS]; | |
741 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a S |
742 | } meas3; |
743 | u16 cal_samples; | |
6a2b9e8c | 744 | |
2660b81a S |
745 | u32 sta_id1_defaults; |
746 | u32 misc_mode; | |
f078f209 LR |
747 | enum { |
748 | AUTO_32KHZ, | |
749 | USE_32KHZ, | |
750 | DONT_USE_32KHZ, | |
2660b81a | 751 | } enable_32kHz_clock; |
6a2b9e8c | 752 | |
d70357d5 LR |
753 | /* Private to hardware code */ |
754 | struct ath_hw_private_ops private_ops; | |
755 | /* Accessed by the lower level driver */ | |
756 | struct ath_hw_ops ops; | |
757 | ||
e68a060b | 758 | /* Used to program the radio on non single-chip devices */ |
2660b81a S |
759 | u32 *analogBank0Data; |
760 | u32 *analogBank1Data; | |
761 | u32 *analogBank2Data; | |
762 | u32 *analogBank3Data; | |
763 | u32 *analogBank6Data; | |
764 | u32 *analogBank6TPCData; | |
765 | u32 *analogBank7Data; | |
766 | u32 *addac5416_21; | |
767 | u32 *bank6Temp; | |
768 | ||
597a94b3 | 769 | u8 txpower_limit; |
e239d859 | 770 | int coverage_class; |
2660b81a | 771 | u32 slottime; |
2660b81a | 772 | u32 globaltxtimeout; |
6a2b9e8c S |
773 | |
774 | /* ANI */ | |
2660b81a | 775 | u32 proc_phyerr; |
2660b81a | 776 | u32 aniperiod; |
2660b81a S |
777 | int totalSizeDesired[5]; |
778 | int coarse_high[5]; | |
779 | int coarse_low[5]; | |
780 | int firpwr[5]; | |
781 | enum ath9k_ani_cmd ani_function; | |
782 | ||
af03abec | 783 | /* Bluetooth coexistance */ |
766ec4a9 | 784 | struct ath_btcoex_hw btcoex_hw; |
a6ef530f VN |
785 | u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; |
786 | u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; | |
af03abec | 787 | |
2660b81a | 788 | u32 intr_txqs; |
2660b81a S |
789 | u8 txchainmask; |
790 | u8 rxchainmask; | |
791 | ||
c5d0855a FF |
792 | struct ath_hw_radar_conf radar_conf; |
793 | ||
8bd1d07f SB |
794 | u32 originalGain[22]; |
795 | int initPDADC; | |
796 | int PDADCdelta; | |
6de66dd9 | 797 | int led_pin; |
691680b8 FF |
798 | u32 gpio_mask; |
799 | u32 gpio_val; | |
8bd1d07f | 800 | |
2660b81a S |
801 | struct ar5416IniArray iniModes; |
802 | struct ar5416IniArray iniCommon; | |
803 | struct ar5416IniArray iniBank0; | |
804 | struct ar5416IniArray iniBB_RfGain; | |
805 | struct ar5416IniArray iniBank1; | |
806 | struct ar5416IniArray iniBank2; | |
807 | struct ar5416IniArray iniBank3; | |
808 | struct ar5416IniArray iniBank6; | |
809 | struct ar5416IniArray iniBank6TPC; | |
810 | struct ar5416IniArray iniBank7; | |
811 | struct ar5416IniArray iniAddac; | |
812 | struct ar5416IniArray iniPcieSerdes; | |
13ce3e99 | 813 | struct ar5416IniArray iniPcieSerdesLowPower; |
2660b81a | 814 | struct ar5416IniArray iniModesAdditional; |
d89baac8 | 815 | struct ar5416IniArray iniModesAdditional_40M; |
2660b81a S |
816 | struct ar5416IniArray iniModesRxGain; |
817 | struct ar5416IniArray iniModesTxGain; | |
8564328d | 818 | struct ar5416IniArray iniModes_9271_1_0_only; |
193cd458 S |
819 | struct ar5416IniArray iniCckfirNormal; |
820 | struct ar5416IniArray iniCckfirJapan2484; | |
70807e99 S |
821 | struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; |
822 | struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; | |
823 | struct ar5416IniArray iniModes_9271_ANI_reg; | |
824 | struct ar5416IniArray iniModes_high_power_tx_gain_9271; | |
825 | struct ar5416IniArray iniModes_normal_power_tx_gain_9271; | |
ff155a45 | 826 | |
13ce3e99 LR |
827 | struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; |
828 | struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; | |
829 | struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; | |
830 | struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; | |
831 | ||
ff155a45 VT |
832 | u32 intr_gen_timer_trigger; |
833 | u32 intr_gen_timer_thresh; | |
834 | struct ath_gen_timer_table hw_gen_timers; | |
744d4025 VT |
835 | |
836 | struct ar9003_txs *ts_ring; | |
837 | void *ts_start; | |
838 | u32 ts_paddr_start; | |
839 | u32 ts_paddr_end; | |
840 | u16 ts_tail; | |
841 | u8 ts_size; | |
aea702b7 LR |
842 | |
843 | u32 bb_watchdog_last_status; | |
844 | u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ | |
51ac8cbb | 845 | u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ |
717f6bed | 846 | |
1bf38661 FF |
847 | unsigned int paprd_target_power; |
848 | unsigned int paprd_training_power; | |
7072bf62 | 849 | unsigned int paprd_ratemask; |
f1a8abb0 | 850 | unsigned int paprd_ratemask_ht40; |
45ef6a0b | 851 | bool paprd_table_write_done; |
717f6bed FF |
852 | u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; |
853 | u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; | |
9a658d2b LR |
854 | /* |
855 | * Store the permanent value of Reg 0x4004in WARegVal | |
856 | * so we dont have to R/M/W. We should not be reading | |
857 | * this register when in sleep states. | |
858 | */ | |
859 | u32 WARegVal; | |
6ee63f55 SB |
860 | |
861 | /* Enterprise mode cap */ | |
862 | u32 ent_mode; | |
f2f5f2a1 VT |
863 | |
864 | bool is_clk_25mhz; | |
f078f209 | 865 | }; |
f078f209 | 866 | |
0cb9e06b FF |
867 | struct ath_bus_ops { |
868 | enum ath_bus_type ath_bus_type; | |
869 | void (*read_cachesize)(struct ath_common *common, int *csz); | |
870 | bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); | |
871 | void (*bt_coex_prep)(struct ath_common *common); | |
872 | void (*extn_synch_en)(struct ath_common *common); | |
873 | }; | |
874 | ||
9e4bffd2 LR |
875 | static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) |
876 | { | |
877 | return &ah->common; | |
878 | } | |
879 | ||
880 | static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) | |
881 | { | |
882 | return &(ath9k_hw_common(ah)->regulatory); | |
883 | } | |
884 | ||
d70357d5 LR |
885 | static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) |
886 | { | |
887 | return &ah->private_ops; | |
888 | } | |
889 | ||
890 | static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) | |
891 | { | |
892 | return &ah->ops; | |
893 | } | |
894 | ||
895ad7eb VT |
895 | static inline u8 get_streams(int mask) |
896 | { | |
897 | return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); | |
898 | } | |
899 | ||
f637cfd6 | 900 | /* Initialization, Detach, Reset */ |
394cf0a1 | 901 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); |
285f2dda | 902 | void ath9k_hw_deinit(struct ath_hw *ah); |
f637cfd6 | 903 | int ath9k_hw_init(struct ath_hw *ah); |
cbe61d8a | 904 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
20bd2a09 | 905 | struct ath9k_hw_cal_data *caldata, bool bChannelChange); |
a9a29ce6 | 906 | int ath9k_hw_fill_cap_info(struct ath_hw *ah); |
8fe65368 | 907 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); |
394cf0a1 | 908 | |
394cf0a1 | 909 | /* GPIO / RFKILL / Antennae */ |
cbe61d8a S |
910 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); |
911 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); | |
912 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, | |
394cf0a1 | 913 | u32 ah_signal_type); |
cbe61d8a | 914 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
cbe61d8a S |
915 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah); |
916 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); | |
394cf0a1 S |
917 | |
918 | /* General Operation */ | |
0caa7b14 | 919 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
a9b6b256 FF |
920 | void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, |
921 | int column, unsigned int *writecnt); | |
394cf0a1 | 922 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
4f0fc7c3 | 923 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 924 | u8 phy, int kbps, |
394cf0a1 | 925 | u32 frameLen, u16 rateix, bool shortPreamble); |
cbe61d8a | 926 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
394cf0a1 S |
927 | struct ath9k_channel *chan, |
928 | struct chan_centers *centers); | |
cbe61d8a S |
929 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
930 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); | |
931 | bool ath9k_hw_phy_disable(struct ath_hw *ah); | |
932 | bool ath9k_hw_disable(struct ath_hw *ah); | |
de40f316 | 933 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); |
cbe61d8a S |
934 | void ath9k_hw_setopmode(struct ath_hw *ah); |
935 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); | |
f2b2143e LR |
936 | void ath9k_hw_setbssidmask(struct ath_hw *ah); |
937 | void ath9k_hw_write_associd(struct ath_hw *ah); | |
dd347f2f | 938 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); |
cbe61d8a S |
939 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
940 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); | |
941 | void ath9k_hw_reset_tsf(struct ath_hw *ah); | |
54e4cec6 | 942 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); |
0005baf4 | 943 | void ath9k_hw_init_global_settings(struct ath_hw *ah); |
b84628eb | 944 | u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); |
25c56eec | 945 | void ath9k_hw_set11nmac2040(struct ath_hw *ah); |
cbe61d8a S |
946 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); |
947 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |
394cf0a1 | 948 | const struct ath9k_beacon_state *bs); |
c9c99e5e | 949 | bool ath9k_hw_check_alive(struct ath_hw *ah); |
a91d75ae | 950 | |
9ecdef4b | 951 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); |
a91d75ae | 952 | |
ff155a45 VT |
953 | /* Generic hw timer primitives */ |
954 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
955 | void (*trigger)(void *), | |
956 | void (*overflow)(void *), | |
957 | void *arg, | |
958 | u8 timer_index); | |
cd9bf689 LR |
959 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
960 | struct ath_gen_timer *timer, | |
961 | u32 timer_next, | |
962 | u32 timer_period); | |
963 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); | |
964 | ||
ff155a45 VT |
965 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); |
966 | void ath_gen_timer_isr(struct ath_hw *hw); | |
967 | ||
f934c4d9 | 968 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); |
2da4f01a | 969 | |
05020d23 S |
970 | /* HTC */ |
971 | void ath9k_hw_htc_resetinit(struct ath_hw *ah); | |
972 | ||
8fe65368 LR |
973 | /* PHY */ |
974 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, | |
975 | u32 *coef_mantissa, u32 *coef_exponent); | |
976 | ||
ebd5a14a LR |
977 | /* |
978 | * Code Specific to AR5008, AR9001 or AR9002, | |
979 | * we stuff these here to avoid callbacks for AR9003. | |
980 | */ | |
d8f492b7 | 981 | void ar9002_hw_cck_chan14_spread(struct ath_hw *ah); |
ebd5a14a | 982 | int ar9002_hw_rf_claim(struct ath_hw *ah); |
78ec2677 | 983 | void ar9002_hw_enable_async_fifo(struct ath_hw *ah); |
e9141f71 | 984 | void ar9002_hw_update_async_fifo(struct ath_hw *ah); |
6c94fdc9 | 985 | void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah); |
d8f492b7 | 986 | |
641d9921 | 987 | /* |
aea702b7 | 988 | * Code specific to AR9003, we stuff these here to avoid callbacks |
641d9921 FF |
989 | * for older families |
990 | */ | |
aea702b7 LR |
991 | void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); |
992 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); | |
993 | void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); | |
51ac8cbb | 994 | void ar9003_hw_disable_phy_restart(struct ath_hw *ah); |
717f6bed FF |
995 | void ar9003_paprd_enable(struct ath_hw *ah, bool val); |
996 | void ar9003_paprd_populate_single_table(struct ath_hw *ah, | |
20bd2a09 FF |
997 | struct ath9k_hw_cal_data *caldata, |
998 | int chain); | |
999 | int ar9003_paprd_create_curve(struct ath_hw *ah, | |
1000 | struct ath9k_hw_cal_data *caldata, int chain); | |
717f6bed FF |
1001 | int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); |
1002 | int ar9003_paprd_init_table(struct ath_hw *ah); | |
1003 | bool ar9003_paprd_is_done(struct ath_hw *ah); | |
1004 | void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains); | |
641d9921 FF |
1005 | |
1006 | /* Hardware family op attach helpers */ | |
8fe65368 | 1007 | void ar5008_hw_attach_phy_ops(struct ath_hw *ah); |
8525f280 LR |
1008 | void ar9002_hw_attach_phy_ops(struct ath_hw *ah); |
1009 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah); | |
8fe65368 | 1010 | |
795f5e2c LR |
1011 | void ar9002_hw_attach_calib_ops(struct ath_hw *ah); |
1012 | void ar9003_hw_attach_calib_ops(struct ath_hw *ah); | |
1013 | ||
b3950e6a LR |
1014 | void ar9002_hw_attach_ops(struct ath_hw *ah); |
1015 | void ar9003_hw_attach_ops(struct ath_hw *ah); | |
1016 | ||
c2ba3342 | 1017 | void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); |
ac0bb767 LR |
1018 | /* |
1019 | * ANI work can be shared between all families but a next | |
1020 | * generation implementation of ANI will be used only for AR9003 only | |
1021 | * for now as the other families still need to be tested with the same | |
e36b27af LR |
1022 | * next generation ANI. Feel free to start testing it though for the |
1023 | * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani. | |
ac0bb767 | 1024 | */ |
e36b27af | 1025 | extern int modparam_force_new_ani; |
8eb4980c | 1026 | void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); |
bfc472bb | 1027 | void ath9k_hw_proc_mib_event(struct ath_hw *ah); |
95792178 | 1028 | void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); |
ac0bb767 | 1029 | |
7b6840ab VT |
1030 | #define ATH_PCIE_CAP_LINK_CTRL 0x70 |
1031 | #define ATH_PCIE_CAP_LINK_L0S 1 | |
1032 | #define ATH_PCIE_CAP_LINK_L1 2 | |
1033 | ||
73377256 LR |
1034 | #define ATH9K_CLOCK_RATE_CCK 22 |
1035 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 | |
1036 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 | |
1037 | #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 | |
1038 | ||
f078f209 | 1039 | #endif |