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f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef HW_H | |
18 | #define HW_H | |
19 | ||
20 | #include <linux/if_ether.h> | |
21 | #include <linux/delay.h> | |
394cf0a1 S |
22 | #include <linux/io.h> |
23 | ||
24 | #include "mac.h" | |
25 | #include "ani.h" | |
26 | #include "eeprom.h" | |
27 | #include "calib.h" | |
394cf0a1 S |
28 | #include "reg.h" |
29 | #include "phy.h" | |
af03abec | 30 | #include "btcoex.h" |
394cf0a1 | 31 | |
203c4805 | 32 | #include "../regd.h" |
3a702e49 | 33 | |
394cf0a1 | 34 | #define ATHEROS_VENDOR_ID 0x168c |
7976b426 | 35 | |
394cf0a1 S |
36 | #define AR5416_DEVID_PCI 0x0023 |
37 | #define AR5416_DEVID_PCIE 0x0024 | |
38 | #define AR9160_DEVID_PCI 0x0027 | |
39 | #define AR9280_DEVID_PCI 0x0029 | |
40 | #define AR9280_DEVID_PCIE 0x002a | |
41 | #define AR9285_DEVID_PCIE 0x002b | |
5ffaf8a3 | 42 | #define AR2427_DEVID_PCIE 0x002c |
db3cc53a SB |
43 | #define AR9287_DEVID_PCI 0x002d |
44 | #define AR9287_DEVID_PCIE 0x002e | |
45 | #define AR9300_DEVID_PCIE 0x0030 | |
b99a7be4 | 46 | #define AR9300_DEVID_AR9340 0x0031 |
3050c914 | 47 | #define AR9300_DEVID_AR9485_PCIE 0x0032 |
5a63ef0f | 48 | #define AR9300_DEVID_AR9580 0x0033 |
423e38e8 | 49 | #define AR9300_DEVID_AR9462 0x0034 |
03689301 | 50 | #define AR9300_DEVID_AR9330 0x0035 |
7976b426 | 51 | |
394cf0a1 | 52 | #define AR5416_AR9100_DEVID 0x000b |
7976b426 | 53 | |
394cf0a1 S |
54 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
55 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | |
56 | #define AR5416_MAGIC 0x19641014 | |
57 | ||
fe12946e VT |
58 | #define AR9280_COEX2WIRE_SUBSYSID 0x309b |
59 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa | |
60 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab | |
61 | ||
e3d01bfc LR |
62 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
63 | ||
cfe8cba9 LR |
64 | #define ATH_DEFAULT_NOISE_FLOOR -95 |
65 | ||
04658fba | 66 | #define ATH9K_RSSI_BAD -128 |
990b70ab | 67 | |
cac4220b FF |
68 | #define ATH9K_NUM_CHANNELS 38 |
69 | ||
394cf0a1 | 70 | /* Register read/write primitives */ |
9e4bffd2 | 71 | #define REG_WRITE(_ah, _reg, _val) \ |
f9f84e96 | 72 | (_ah)->reg_ops.write((_ah), (_val), (_reg)) |
9e4bffd2 LR |
73 | |
74 | #define REG_READ(_ah, _reg) \ | |
f9f84e96 | 75 | (_ah)->reg_ops.read((_ah), (_reg)) |
394cf0a1 | 76 | |
09a525d3 | 77 | #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ |
f9f84e96 | 78 | (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) |
09a525d3 | 79 | |
845e03c9 FF |
80 | #define REG_RMW(_ah, _reg, _set, _clr) \ |
81 | (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) | |
82 | ||
20b3efd9 S |
83 | #define ENABLE_REGWRITE_BUFFER(_ah) \ |
84 | do { \ | |
f9f84e96 FF |
85 | if ((_ah)->reg_ops.enable_write_buffer) \ |
86 | (_ah)->reg_ops.enable_write_buffer((_ah)); \ | |
20b3efd9 S |
87 | } while (0) |
88 | ||
20b3efd9 S |
89 | #define REGWRITE_BUFFER_FLUSH(_ah) \ |
90 | do { \ | |
f9f84e96 FF |
91 | if ((_ah)->reg_ops.write_flush) \ |
92 | (_ah)->reg_ops.write_flush((_ah)); \ | |
20b3efd9 S |
93 | } while (0) |
94 | ||
26526202 RM |
95 | #define PR_EEP(_s, _val) \ |
96 | do { \ | |
97 | len += snprintf(buf + len, size - len, "%20s : %10d\n", \ | |
98 | _s, (_val)); \ | |
99 | } while (0) | |
100 | ||
394cf0a1 S |
101 | #define SM(_v, _f) (((_v) << _f##_S) & _f) |
102 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | |
394cf0a1 | 103 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ |
845e03c9 | 104 | REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) |
1547da37 LR |
105 | #define REG_READ_FIELD(_a, _r, _f) \ |
106 | (((REG_READ(_a, _r) & _f) >> _f##_S)) | |
394cf0a1 | 107 | #define REG_SET_BIT(_a, _r, _f) \ |
845e03c9 | 108 | REG_RMW(_a, _r, (_f), 0) |
394cf0a1 | 109 | #define REG_CLR_BIT(_a, _r, _f) \ |
845e03c9 | 110 | REG_RMW(_a, _r, 0, (_f)) |
f078f209 | 111 | |
e7fc6338 RM |
112 | #define DO_DELAY(x) do { \ |
113 | if (((++(x) % 64) == 0) && \ | |
114 | (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ | |
115 | != ATH_USB)) \ | |
116 | udelay(1); \ | |
394cf0a1 | 117 | } while (0) |
f078f209 | 118 | |
a9b6b256 FF |
119 | #define REG_WRITE_ARRAY(iniarray, column, regWr) \ |
120 | ath9k_hw_write_array(ah, iniarray, column, &(regWr)) | |
f078f209 | 121 | |
394cf0a1 S |
122 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
123 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | |
124 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | |
125 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 | |
1773912b | 126 | #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 |
394cf0a1 S |
127 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
128 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | |
93d36e99 MSS |
129 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 |
130 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 | |
131 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 | |
132 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 | |
133 | #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 | |
134 | #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 | |
135 | #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 | |
136 | #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 | |
137 | #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d | |
138 | #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e | |
f078f209 | 139 | |
394cf0a1 S |
140 | #define AR_GPIOD_MASK 0x00001FFF |
141 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | |
f078f209 | 142 | |
394cf0a1 | 143 | #define BASE_ACTIVATE_DELAY 100 |
0b488ac6 | 144 | #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) |
394cf0a1 S |
145 | #define COEF_SCALE_S 24 |
146 | #define HT40_CHANNEL_CENTER_SHIFT 10 | |
f078f209 | 147 | |
394cf0a1 S |
148 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
149 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 | |
150 | ||
151 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 | |
152 | #define ATH9K_NUM_QUEUES 10 | |
153 | ||
154 | #define MAX_RATE_POWER 63 | |
0caa7b14 | 155 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
f9b604f6 | 156 | #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ |
394cf0a1 S |
157 | #define AH_TIME_QUANTUM 10 |
158 | #define AR_KEYTABLE_SIZE 128 | |
d8caa839 | 159 | #define POWER_UP_TIME 10000 |
394cf0a1 | 160 | #define SPUR_RSSI_THRESH 40 |
331c5ea2 MSS |
161 | #define UPPER_5G_SUB_BAND_START 5700 |
162 | #define MID_5G_SUB_BAND_START 5400 | |
394cf0a1 S |
163 | |
164 | #define CAB_TIMEOUT_VAL 10 | |
165 | #define BEACON_TIMEOUT_VAL 10 | |
166 | #define MIN_BEACON_TIMEOUT_VAL 1 | |
167 | #define SLEEP_SLOP 3 | |
168 | ||
169 | #define INIT_CONFIG_STATUS 0x00000000 | |
170 | #define INIT_RSSI_THR 0x00000700 | |
171 | #define INIT_BCON_CNTRL_REG 0x00000000 | |
172 | ||
173 | #define TU_TO_USEC(_tu) ((_tu) << 10) | |
174 | ||
ceb26445 VT |
175 | #define ATH9K_HW_RX_HP_QDEPTH 16 |
176 | #define ATH9K_HW_RX_LP_QDEPTH 128 | |
177 | ||
0e44d48c MSS |
178 | #define PAPRD_GAIN_TABLE_ENTRIES 32 |
179 | #define PAPRD_TABLE_SZ 24 | |
180 | #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 | |
717f6bed | 181 | |
066dae93 FF |
182 | enum ath_hw_txq_subtype { |
183 | ATH_TXQ_AC_BE = 0, | |
184 | ATH_TXQ_AC_BK = 1, | |
185 | ATH_TXQ_AC_VI = 2, | |
186 | ATH_TXQ_AC_VO = 3, | |
187 | }; | |
188 | ||
13ce3e99 LR |
189 | enum ath_ini_subsys { |
190 | ATH_INI_PRE = 0, | |
191 | ATH_INI_CORE, | |
192 | ATH_INI_POST, | |
193 | ATH_INI_NUM_SPLIT, | |
194 | }; | |
195 | ||
394cf0a1 | 196 | enum ath9k_hw_caps { |
364734fa FF |
197 | ATH9K_HW_CAP_HT = BIT(0), |
198 | ATH9K_HW_CAP_RFSILENT = BIT(1), | |
1b2538b2 MSS |
199 | ATH9K_HW_CAP_AUTOSLEEP = BIT(2), |
200 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), | |
201 | ATH9K_HW_CAP_EDMA = BIT(4), | |
202 | ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), | |
203 | ATH9K_HW_CAP_LDPC = BIT(6), | |
204 | ATH9K_HW_CAP_FASTCLOCK = BIT(7), | |
205 | ATH9K_HW_CAP_SGI_20 = BIT(8), | |
206 | ATH9K_HW_CAP_PAPRD = BIT(9), | |
207 | ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), | |
208 | ATH9K_HW_CAP_2GHZ = BIT(11), | |
209 | ATH9K_HW_CAP_5GHZ = BIT(12), | |
210 | ATH9K_HW_CAP_APM = BIT(13), | |
211 | ATH9K_HW_CAP_RTT = BIT(14), | |
212 | ATH9K_HW_CAP_MCI = BIT(15), | |
213 | ATH9K_HW_CAP_DFS = BIT(16), | |
394cf0a1 | 214 | }; |
f078f209 | 215 | |
394cf0a1 S |
216 | struct ath9k_hw_capabilities { |
217 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | |
394cf0a1 S |
218 | u16 rts_aggr_limit; |
219 | u8 tx_chainmask; | |
220 | u8 rx_chainmask; | |
47c80de6 VT |
221 | u8 max_txchains; |
222 | u8 max_rxchains; | |
394cf0a1 | 223 | u8 num_gpio_pins; |
ceb26445 VT |
224 | u8 rx_hp_qdepth; |
225 | u8 rx_lp_qdepth; | |
226 | u8 rx_status_len; | |
162c3be3 | 227 | u8 tx_desc_len; |
5088c2f1 | 228 | u8 txs_len; |
8060e169 VT |
229 | u16 pcie_lcr_offset; |
230 | bool pcie_lcr_extsync_en; | |
394cf0a1 | 231 | }; |
f078f209 | 232 | |
394cf0a1 S |
233 | struct ath9k_ops_config { |
234 | int dma_beacon_response_time; | |
235 | int sw_beacon_response_time; | |
236 | int additional_swba_backoff; | |
237 | int ack_6mb; | |
41f3e54d | 238 | u32 cwm_ignore_extcca; |
6a0ec30a | 239 | bool pcieSerDesWrite; |
394cf0a1 S |
240 | u8 pcie_clock_req; |
241 | u32 pcie_waen; | |
394cf0a1 | 242 | u8 analog_shiftreg; |
6f481010 | 243 | u8 paprd_disable; |
394cf0a1 S |
244 | u32 ofdm_trig_low; |
245 | u32 ofdm_trig_high; | |
246 | u32 cck_trig_high; | |
247 | u32 cck_trig_low; | |
248 | u32 enable_ani; | |
394cf0a1 | 249 | int serialize_regmode; |
0ce024cb | 250 | bool rx_intr_mitigation; |
55e82df4 | 251 | bool tx_intr_mitigation; |
394cf0a1 S |
252 | #define SPUR_DISABLE 0 |
253 | #define SPUR_ENABLE_IOCTL 1 | |
254 | #define SPUR_ENABLE_EEPROM 2 | |
394cf0a1 S |
255 | #define AR_SPUR_5413_1 1640 |
256 | #define AR_SPUR_5413_2 1200 | |
257 | #define AR_NO_SPUR 0x8000 | |
258 | #define AR_BASE_FREQ_2GHZ 2300 | |
259 | #define AR_BASE_FREQ_5GHZ 4900 | |
260 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | |
261 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | |
262 | int spurmode; | |
263 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; | |
f4709fdf | 264 | u8 max_txtrig_level; |
e36b27af | 265 | u16 ani_poll_interval; /* ANI poll interval in ms */ |
394cf0a1 | 266 | }; |
f078f209 | 267 | |
394cf0a1 S |
268 | enum ath9k_int { |
269 | ATH9K_INT_RX = 0x00000001, | |
270 | ATH9K_INT_RXDESC = 0x00000002, | |
b5c80475 FF |
271 | ATH9K_INT_RXHP = 0x00000001, |
272 | ATH9K_INT_RXLP = 0x00000002, | |
394cf0a1 S |
273 | ATH9K_INT_RXNOFRM = 0x00000008, |
274 | ATH9K_INT_RXEOL = 0x00000010, | |
275 | ATH9K_INT_RXORN = 0x00000020, | |
276 | ATH9K_INT_TX = 0x00000040, | |
277 | ATH9K_INT_TXDESC = 0x00000080, | |
278 | ATH9K_INT_TIM_TIMER = 0x00000100, | |
2ee4bd1e | 279 | ATH9K_INT_MCI = 0x00000200, |
aea702b7 | 280 | ATH9K_INT_BB_WATCHDOG = 0x00000400, |
394cf0a1 S |
281 | ATH9K_INT_TXURN = 0x00000800, |
282 | ATH9K_INT_MIB = 0x00001000, | |
283 | ATH9K_INT_RXPHY = 0x00004000, | |
284 | ATH9K_INT_RXKCM = 0x00008000, | |
285 | ATH9K_INT_SWBA = 0x00010000, | |
286 | ATH9K_INT_BMISS = 0x00040000, | |
287 | ATH9K_INT_BNR = 0x00100000, | |
288 | ATH9K_INT_TIM = 0x00200000, | |
289 | ATH9K_INT_DTIM = 0x00400000, | |
290 | ATH9K_INT_DTIMSYNC = 0x00800000, | |
291 | ATH9K_INT_GPIO = 0x01000000, | |
292 | ATH9K_INT_CABEND = 0x02000000, | |
4af9cf4f | 293 | ATH9K_INT_TSFOOR = 0x04000000, |
ff155a45 | 294 | ATH9K_INT_GENTIMER = 0x08000000, |
394cf0a1 S |
295 | ATH9K_INT_CST = 0x10000000, |
296 | ATH9K_INT_GTT = 0x20000000, | |
297 | ATH9K_INT_FATAL = 0x40000000, | |
298 | ATH9K_INT_GLOBAL = 0x80000000, | |
299 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | |
300 | ATH9K_INT_DTIM | | |
301 | ATH9K_INT_DTIMSYNC | | |
4af9cf4f | 302 | ATH9K_INT_TSFOOR | |
394cf0a1 S |
303 | ATH9K_INT_CABEND, |
304 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | |
305 | ATH9K_INT_RXDESC | | |
306 | ATH9K_INT_RXEOL | | |
307 | ATH9K_INT_RXORN | | |
308 | ATH9K_INT_TXURN | | |
309 | ATH9K_INT_TXDESC | | |
310 | ATH9K_INT_MIB | | |
311 | ATH9K_INT_RXPHY | | |
312 | ATH9K_INT_RXKCM | | |
313 | ATH9K_INT_SWBA | | |
314 | ATH9K_INT_BMISS | | |
315 | ATH9K_INT_GPIO, | |
316 | ATH9K_INT_NOCARD = 0xffffffff | |
317 | }; | |
f078f209 | 318 | |
394cf0a1 S |
319 | #define CHANNEL_CW_INT 0x00002 |
320 | #define CHANNEL_CCK 0x00020 | |
321 | #define CHANNEL_OFDM 0x00040 | |
322 | #define CHANNEL_2GHZ 0x00080 | |
323 | #define CHANNEL_5GHZ 0x00100 | |
324 | #define CHANNEL_PASSIVE 0x00200 | |
325 | #define CHANNEL_DYN 0x00400 | |
326 | #define CHANNEL_HALF 0x04000 | |
327 | #define CHANNEL_QUARTER 0x08000 | |
328 | #define CHANNEL_HT20 0x10000 | |
329 | #define CHANNEL_HT40PLUS 0x20000 | |
330 | #define CHANNEL_HT40MINUS 0x40000 | |
331 | ||
394cf0a1 S |
332 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
333 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) | |
334 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) | |
335 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) | |
336 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) | |
337 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) | |
338 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) | |
339 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) | |
340 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) | |
341 | #define CHANNEL_ALL \ | |
342 | (CHANNEL_OFDM| \ | |
343 | CHANNEL_CCK| \ | |
344 | CHANNEL_2GHZ | \ | |
345 | CHANNEL_5GHZ | \ | |
346 | CHANNEL_HT20 | \ | |
347 | CHANNEL_HT40PLUS | \ | |
348 | CHANNEL_HT40MINUS) | |
349 | ||
324c74ad RM |
350 | #define MAX_RTT_TABLE_ENTRY 6 |
351 | #define RTT_HIST_MAX 3 | |
352 | struct ath9k_rtt_hist { | |
353 | u32 table[AR9300_MAX_CHAINS][RTT_HIST_MAX][MAX_RTT_TABLE_ENTRY]; | |
354 | u8 num_readings; | |
355 | }; | |
356 | ||
5f0c04ea | 357 | #define MAX_IQCAL_MEASUREMENT 8 |
77a5a664 | 358 | #define MAX_CL_TAB_ENTRY 16 |
5f0c04ea | 359 | |
20bd2a09 | 360 | struct ath9k_hw_cal_data { |
394cf0a1 S |
361 | u16 channel; |
362 | u32 channelFlags; | |
394cf0a1 | 363 | int32_t CalValid; |
394cf0a1 S |
364 | int8_t iCoff; |
365 | int8_t qCoff; | |
717f6bed | 366 | bool paprd_done; |
4254bc1c | 367 | bool nfcal_pending; |
70cf1533 | 368 | bool nfcal_interference; |
5f0c04ea | 369 | bool done_txiqcal_once; |
77a5a664 | 370 | bool done_txclcal_once; |
717f6bed FF |
371 | u16 small_signal_gain[AR9300_MAX_CHAINS]; |
372 | u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; | |
5f0c04ea RM |
373 | u32 num_measures[AR9300_MAX_CHAINS]; |
374 | int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; | |
77a5a664 | 375 | u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; |
20bd2a09 | 376 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
324c74ad | 377 | struct ath9k_rtt_hist rtt_hist; |
20bd2a09 FF |
378 | }; |
379 | ||
380 | struct ath9k_channel { | |
381 | struct ieee80211_channel *chan; | |
093115b7 | 382 | struct ar5416AniState ani; |
20bd2a09 FF |
383 | u16 channel; |
384 | u32 channelFlags; | |
385 | u32 chanmode; | |
d9891c78 | 386 | s16 noisefloor; |
394cf0a1 | 387 | }; |
f078f209 | 388 | |
394cf0a1 S |
389 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ |
390 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ | |
391 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ | |
392 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) | |
393 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) | |
394 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) | |
395 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) | |
394cf0a1 S |
396 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) |
397 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) | |
6b42e8d0 | 398 | #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ |
394cf0a1 | 399 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ |
6b42e8d0 | 400 | ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) |
394cf0a1 S |
401 | |
402 | /* These macros check chanmode and not channelFlags */ | |
403 | #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) | |
404 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ | |
405 | ((_c)->chanmode == CHANNEL_G_HT20)) | |
406 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ | |
407 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ | |
408 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ | |
409 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) | |
410 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) | |
411 | ||
412 | enum ath9k_power_mode { | |
413 | ATH9K_PM_AWAKE = 0, | |
414 | ATH9K_PM_FULL_SLEEP, | |
415 | ATH9K_PM_NETWORK_SLEEP, | |
416 | ATH9K_PM_UNDEFINED | |
417 | }; | |
f078f209 | 418 | |
394cf0a1 S |
419 | enum ser_reg_mode { |
420 | SER_REG_MODE_OFF = 0, | |
421 | SER_REG_MODE_ON = 1, | |
422 | SER_REG_MODE_AUTO = 2, | |
423 | }; | |
f078f209 | 424 | |
ad7b8060 VT |
425 | enum ath9k_rx_qtype { |
426 | ATH9K_RX_QUEUE_HP, | |
427 | ATH9K_RX_QUEUE_LP, | |
428 | ATH9K_RX_QUEUE_MAX, | |
429 | }; | |
430 | ||
2ee4bd1e MSS |
431 | enum mci_message_header { /* length of payload */ |
432 | MCI_LNA_CTRL = 0x10, /* len = 0 */ | |
433 | MCI_CONT_NACK = 0x20, /* len = 0 */ | |
434 | MCI_CONT_INFO = 0x30, /* len = 4 */ | |
435 | MCI_CONT_RST = 0x40, /* len = 0 */ | |
436 | MCI_SCHD_INFO = 0x50, /* len = 16 */ | |
437 | MCI_CPU_INT = 0x60, /* len = 4 */ | |
438 | MCI_SYS_WAKING = 0x70, /* len = 0 */ | |
439 | MCI_GPM = 0x80, /* len = 16 */ | |
440 | MCI_LNA_INFO = 0x90, /* len = 1 */ | |
441 | MCI_LNA_STATE = 0x94, | |
442 | MCI_LNA_TAKE = 0x98, | |
443 | MCI_LNA_TRANS = 0x9c, | |
444 | MCI_SYS_SLEEPING = 0xa0, /* len = 0 */ | |
445 | MCI_REQ_WAKE = 0xc0, /* len = 0 */ | |
446 | MCI_DEBUG_16 = 0xfe, /* len = 2 */ | |
447 | MCI_REMOTE_RESET = 0xff /* len = 16 */ | |
448 | }; | |
449 | ||
7dc181c2 RM |
450 | enum ath_mci_gpm_coex_profile_type { |
451 | MCI_GPM_COEX_PROFILE_UNKNOWN, | |
452 | MCI_GPM_COEX_PROFILE_RFCOMM, | |
453 | MCI_GPM_COEX_PROFILE_A2DP, | |
454 | MCI_GPM_COEX_PROFILE_HID, | |
455 | MCI_GPM_COEX_PROFILE_BNEP, | |
456 | MCI_GPM_COEX_PROFILE_VOICE, | |
457 | MCI_GPM_COEX_PROFILE_MAX | |
458 | }; | |
459 | ||
2ee4bd1e MSS |
460 | /* MCI GPM/Coex opcode/type definitions */ |
461 | enum { | |
462 | MCI_GPM_COEX_W_GPM_PAYLOAD = 1, | |
463 | MCI_GPM_COEX_B_GPM_TYPE = 4, | |
464 | MCI_GPM_COEX_B_GPM_OPCODE = 5, | |
465 | /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */ | |
466 | MCI_GPM_WLAN_CAL_W_SEQUENCE = 2, | |
467 | ||
468 | /* MCI_GPM_COEX_VERSION_QUERY */ | |
469 | /* MCI_GPM_COEX_VERSION_RESPONSE */ | |
470 | MCI_GPM_COEX_B_MAJOR_VERSION = 6, | |
471 | MCI_GPM_COEX_B_MINOR_VERSION = 7, | |
472 | /* MCI_GPM_COEX_STATUS_QUERY */ | |
473 | MCI_GPM_COEX_B_BT_BITMAP = 6, | |
474 | MCI_GPM_COEX_B_WLAN_BITMAP = 7, | |
475 | /* MCI_GPM_COEX_HALT_BT_GPM */ | |
476 | MCI_GPM_COEX_B_HALT_STATE = 6, | |
477 | /* MCI_GPM_COEX_WLAN_CHANNELS */ | |
478 | MCI_GPM_COEX_B_CHANNEL_MAP = 6, | |
479 | /* MCI_GPM_COEX_BT_PROFILE_INFO */ | |
480 | MCI_GPM_COEX_B_PROFILE_TYPE = 6, | |
481 | MCI_GPM_COEX_B_PROFILE_LINKID = 7, | |
482 | MCI_GPM_COEX_B_PROFILE_STATE = 8, | |
483 | MCI_GPM_COEX_B_PROFILE_ROLE = 9, | |
484 | MCI_GPM_COEX_B_PROFILE_RATE = 10, | |
485 | MCI_GPM_COEX_B_PROFILE_VOTYPE = 11, | |
486 | MCI_GPM_COEX_H_PROFILE_T = 12, | |
487 | MCI_GPM_COEX_B_PROFILE_W = 14, | |
488 | MCI_GPM_COEX_B_PROFILE_A = 15, | |
489 | /* MCI_GPM_COEX_BT_STATUS_UPDATE */ | |
490 | MCI_GPM_COEX_B_STATUS_TYPE = 6, | |
491 | MCI_GPM_COEX_B_STATUS_LINKID = 7, | |
492 | MCI_GPM_COEX_B_STATUS_STATE = 8, | |
493 | /* MCI_GPM_COEX_BT_UPDATE_FLAGS */ | |
494 | MCI_GPM_COEX_W_BT_FLAGS = 6, | |
495 | MCI_GPM_COEX_B_BT_FLAGS_OP = 10 | |
496 | }; | |
497 | ||
498 | enum mci_gpm_subtype { | |
499 | MCI_GPM_BT_CAL_REQ = 0, | |
500 | MCI_GPM_BT_CAL_GRANT = 1, | |
501 | MCI_GPM_BT_CAL_DONE = 2, | |
502 | MCI_GPM_WLAN_CAL_REQ = 3, | |
503 | MCI_GPM_WLAN_CAL_GRANT = 4, | |
504 | MCI_GPM_WLAN_CAL_DONE = 5, | |
505 | MCI_GPM_COEX_AGENT = 0x0c, | |
506 | MCI_GPM_RSVD_PATTERN = 0xfe, | |
507 | MCI_GPM_RSVD_PATTERN32 = 0xfefefefe, | |
508 | MCI_GPM_BT_DEBUG = 0xff | |
509 | }; | |
510 | ||
511 | enum mci_bt_state { | |
512 | MCI_BT_SLEEP, | |
513 | MCI_BT_AWAKE, | |
514 | MCI_BT_CAL_START, | |
515 | MCI_BT_CAL | |
516 | }; | |
517 | ||
518 | /* Type of state query */ | |
519 | enum mci_state_type { | |
520 | MCI_STATE_ENABLE, | |
521 | MCI_STATE_INIT_GPM_OFFSET, | |
522 | MCI_STATE_NEXT_GPM_OFFSET, | |
523 | MCI_STATE_LAST_GPM_OFFSET, | |
524 | MCI_STATE_BT, | |
525 | MCI_STATE_SET_BT_SLEEP, | |
526 | MCI_STATE_SET_BT_AWAKE, | |
527 | MCI_STATE_SET_BT_CAL_START, | |
528 | MCI_STATE_SET_BT_CAL, | |
529 | MCI_STATE_LAST_SCHD_MSG_OFFSET, | |
530 | MCI_STATE_REMOTE_SLEEP, | |
531 | MCI_STATE_CONT_RSSI_POWER, | |
532 | MCI_STATE_CONT_PRIORITY, | |
533 | MCI_STATE_CONT_TXRX, | |
534 | MCI_STATE_RESET_REQ_WAKE, | |
535 | MCI_STATE_SEND_WLAN_COEX_VERSION, | |
536 | MCI_STATE_SET_BT_COEX_VERSION, | |
537 | MCI_STATE_SEND_WLAN_CHANNELS, | |
538 | MCI_STATE_SEND_VERSION_QUERY, | |
539 | MCI_STATE_SEND_STATUS_QUERY, | |
540 | MCI_STATE_NEED_FLUSH_BT_INFO, | |
541 | MCI_STATE_SET_CONCUR_TX_PRI, | |
542 | MCI_STATE_RECOVER_RX, | |
543 | MCI_STATE_NEED_FTP_STOMP, | |
544 | MCI_STATE_NEED_TUNING, | |
545 | MCI_STATE_DEBUG, | |
546 | MCI_STATE_MAX | |
547 | }; | |
548 | ||
549 | enum mci_gpm_coex_opcode { | |
550 | MCI_GPM_COEX_VERSION_QUERY, | |
551 | MCI_GPM_COEX_VERSION_RESPONSE, | |
552 | MCI_GPM_COEX_STATUS_QUERY, | |
553 | MCI_GPM_COEX_HALT_BT_GPM, | |
554 | MCI_GPM_COEX_WLAN_CHANNELS, | |
555 | MCI_GPM_COEX_BT_PROFILE_INFO, | |
556 | MCI_GPM_COEX_BT_STATUS_UPDATE, | |
557 | MCI_GPM_COEX_BT_UPDATE_FLAGS | |
558 | }; | |
559 | ||
560 | #define MCI_GPM_NOMORE 0 | |
561 | #define MCI_GPM_MORE 1 | |
562 | #define MCI_GPM_INVALID 0xffffffff | |
563 | ||
564 | #define MCI_GPM_RECYCLE(_p_gpm) do { \ | |
565 | *(((u32 *)_p_gpm) + MCI_GPM_COEX_W_GPM_PAYLOAD) = \ | |
566 | MCI_GPM_RSVD_PATTERN32; \ | |
567 | } while (0) | |
568 | ||
569 | #define MCI_GPM_TYPE(_p_gpm) \ | |
570 | (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff) | |
571 | ||
572 | #define MCI_GPM_OPCODE(_p_gpm) \ | |
573 | (*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff) | |
574 | ||
575 | #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) do { \ | |
576 | *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff;\ | |
577 | } while (0) | |
578 | ||
579 | #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) do { \ | |
580 | *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \ | |
581 | *(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;\ | |
582 | } while (0) | |
583 | ||
584 | #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE) | |
585 | ||
394cf0a1 S |
586 | struct ath9k_beacon_state { |
587 | u32 bs_nexttbtt; | |
588 | u32 bs_nextdtim; | |
589 | u32 bs_intval; | |
4af9cf4f | 590 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
394cf0a1 S |
591 | u32 bs_dtimperiod; |
592 | u16 bs_cfpperiod; | |
593 | u16 bs_cfpmaxduration; | |
594 | u32 bs_cfpnext; | |
595 | u16 bs_timoffset; | |
596 | u16 bs_bmissthreshold; | |
597 | u32 bs_sleepduration; | |
4af9cf4f | 598 | u32 bs_tsfoor_threshold; |
394cf0a1 | 599 | }; |
f078f209 | 600 | |
394cf0a1 S |
601 | struct chan_centers { |
602 | u16 synth_center; | |
603 | u16 ctl_center; | |
604 | u16 ext_center; | |
605 | }; | |
f078f209 | 606 | |
394cf0a1 S |
607 | enum { |
608 | ATH9K_RESET_POWER_ON, | |
609 | ATH9K_RESET_WARM, | |
610 | ATH9K_RESET_COLD, | |
611 | }; | |
f078f209 | 612 | |
d535a42a S |
613 | struct ath9k_hw_version { |
614 | u32 magic; | |
615 | u16 devid; | |
616 | u16 subvendorid; | |
617 | u32 macVersion; | |
618 | u16 macRev; | |
619 | u16 phyRev; | |
620 | u16 analog5GhzRev; | |
621 | u16 analog2GhzRev; | |
0b5ead91 | 622 | enum ath_usb_dev usbdev; |
d535a42a | 623 | }; |
394cf0a1 | 624 | |
ff155a45 VT |
625 | /* Generic TSF timer definitions */ |
626 | ||
627 | #define ATH_MAX_GEN_TIMER 16 | |
628 | ||
629 | #define AR_GENTMR_BIT(_index) (1 << (_index)) | |
630 | ||
631 | /* | |
77c2061d | 632 | * Using de Bruijin sequence to look up 1's index in a 32 bit number |
ff155a45 VT |
633 | * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 |
634 | */ | |
c90017dd | 635 | #define debruijn32 0x077CB531U |
ff155a45 VT |
636 | |
637 | struct ath_gen_timer_configuration { | |
638 | u32 next_addr; | |
639 | u32 period_addr; | |
640 | u32 mode_addr; | |
641 | u32 mode_mask; | |
642 | }; | |
643 | ||
644 | struct ath_gen_timer { | |
645 | void (*trigger)(void *arg); | |
646 | void (*overflow)(void *arg); | |
647 | void *arg; | |
648 | u8 index; | |
649 | }; | |
650 | ||
651 | struct ath_gen_timer_table { | |
652 | u32 gen_timer_index[32]; | |
653 | struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; | |
654 | union { | |
655 | unsigned long timer_bits; | |
656 | u16 val; | |
657 | } timer_mask; | |
658 | }; | |
659 | ||
21cc630f VT |
660 | struct ath_hw_antcomb_conf { |
661 | u8 main_lna_conf; | |
662 | u8 alt_lna_conf; | |
663 | u8 fast_div_bias; | |
c6ba9feb MSS |
664 | u8 main_gaintb; |
665 | u8 alt_gaintb; | |
666 | int lna1_lna2_delta; | |
8afbcc8b | 667 | u8 div_group; |
21cc630f VT |
668 | }; |
669 | ||
4e8c14e9 FF |
670 | /** |
671 | * struct ath_hw_radar_conf - radar detection initialization parameters | |
672 | * | |
673 | * @pulse_inband: threshold for checking the ratio of in-band power | |
674 | * to total power for short radar pulses (half dB steps) | |
675 | * @pulse_inband_step: threshold for checking an in-band power to total | |
676 | * power ratio increase for short radar pulses (half dB steps) | |
677 | * @pulse_height: threshold for detecting the beginning of a short | |
678 | * radar pulse (dB step) | |
679 | * @pulse_rssi: threshold for detecting if a short radar pulse is | |
680 | * gone (dB step) | |
681 | * @pulse_maxlen: maximum pulse length (0.8 us steps) | |
682 | * | |
683 | * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) | |
684 | * @radar_inband: threshold for checking the ratio of in-band power | |
685 | * to total power for long radar pulses (half dB steps) | |
686 | * @fir_power: threshold for detecting the end of a long radar pulse (dB) | |
687 | * | |
688 | * @ext_channel: enable extension channel radar detection | |
689 | */ | |
690 | struct ath_hw_radar_conf { | |
691 | unsigned int pulse_inband; | |
692 | unsigned int pulse_inband_step; | |
693 | unsigned int pulse_height; | |
694 | unsigned int pulse_rssi; | |
695 | unsigned int pulse_maxlen; | |
696 | ||
697 | unsigned int radar_rssi; | |
698 | unsigned int radar_inband; | |
699 | int fir_power; | |
700 | ||
701 | bool ext_channel; | |
702 | }; | |
703 | ||
d70357d5 LR |
704 | /** |
705 | * struct ath_hw_private_ops - callbacks used internally by hardware code | |
706 | * | |
707 | * This structure contains private callbacks designed to only be used internally | |
708 | * by the hardware core. | |
709 | * | |
795f5e2c LR |
710 | * @init_cal_settings: setup types of calibrations supported |
711 | * @init_cal: starts actual calibration | |
712 | * | |
d70357d5 | 713 | * @init_mode_regs: Initializes mode registers |
991312d8 | 714 | * @init_mode_gain_regs: Initialize TX/RX gain registers |
8fe65368 LR |
715 | * |
716 | * @rf_set_freq: change frequency | |
717 | * @spur_mitigate_freq: spur mitigation | |
718 | * @rf_alloc_ext_banks: | |
719 | * @rf_free_ext_banks: | |
720 | * @set_rf_regs: | |
64773964 LR |
721 | * @compute_pll_control: compute the PLL control value to use for |
722 | * AR_RTC_PLL_CONTROL for a given channel | |
795f5e2c LR |
723 | * @setup_calibration: set up calibration |
724 | * @iscal_supported: used to query if a type of calibration is supported | |
ac0bb767 | 725 | * |
e36b27af LR |
726 | * @ani_cache_ini_regs: cache the values for ANI from the initial |
727 | * register settings through the register initialization. | |
d70357d5 LR |
728 | */ |
729 | struct ath_hw_private_ops { | |
795f5e2c | 730 | /* Calibration ops */ |
d70357d5 | 731 | void (*init_cal_settings)(struct ath_hw *ah); |
795f5e2c LR |
732 | bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); |
733 | ||
d70357d5 | 734 | void (*init_mode_regs)(struct ath_hw *ah); |
991312d8 | 735 | void (*init_mode_gain_regs)(struct ath_hw *ah); |
795f5e2c LR |
736 | void (*setup_calibration)(struct ath_hw *ah, |
737 | struct ath9k_cal_list *currCal); | |
8fe65368 LR |
738 | |
739 | /* PHY ops */ | |
740 | int (*rf_set_freq)(struct ath_hw *ah, | |
741 | struct ath9k_channel *chan); | |
742 | void (*spur_mitigate_freq)(struct ath_hw *ah, | |
743 | struct ath9k_channel *chan); | |
744 | int (*rf_alloc_ext_banks)(struct ath_hw *ah); | |
745 | void (*rf_free_ext_banks)(struct ath_hw *ah); | |
746 | bool (*set_rf_regs)(struct ath_hw *ah, | |
747 | struct ath9k_channel *chan, | |
748 | u16 modesIndex); | |
749 | void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); | |
750 | void (*init_bb)(struct ath_hw *ah, | |
751 | struct ath9k_channel *chan); | |
752 | int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); | |
753 | void (*olc_init)(struct ath_hw *ah); | |
754 | void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); | |
755 | void (*mark_phy_inactive)(struct ath_hw *ah); | |
756 | void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); | |
757 | bool (*rfbus_req)(struct ath_hw *ah); | |
758 | void (*rfbus_done)(struct ath_hw *ah); | |
8fe65368 | 759 | void (*restore_chainmask)(struct ath_hw *ah); |
64773964 LR |
760 | u32 (*compute_pll_control)(struct ath_hw *ah, |
761 | struct ath9k_channel *chan); | |
c16fcb49 FF |
762 | bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, |
763 | int param); | |
641d9921 | 764 | void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); |
4e8c14e9 FF |
765 | void (*set_radar_params)(struct ath_hw *ah, |
766 | struct ath_hw_radar_conf *conf); | |
5f0c04ea RM |
767 | int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, |
768 | u8 *ini_reloaded); | |
ac0bb767 LR |
769 | |
770 | /* ANI */ | |
e36b27af | 771 | void (*ani_cache_ini_regs)(struct ath_hw *ah); |
d70357d5 LR |
772 | }; |
773 | ||
774 | /** | |
775 | * struct ath_hw_ops - callbacks used by hardware code and driver code | |
776 | * | |
777 | * This structure contains callbacks designed to to be used internally by | |
778 | * hardware code and also by the lower level driver. | |
779 | * | |
780 | * @config_pci_powersave: | |
795f5e2c | 781 | * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC |
d70357d5 LR |
782 | */ |
783 | struct ath_hw_ops { | |
784 | void (*config_pci_powersave)(struct ath_hw *ah, | |
84c87dc8 | 785 | bool power_off); |
cee1f625 | 786 | void (*rx_enable)(struct ath_hw *ah); |
87d5efbb | 787 | void (*set_desc_link)(void *ds, u32 link); |
795f5e2c LR |
788 | bool (*calibrate)(struct ath_hw *ah, |
789 | struct ath9k_channel *chan, | |
790 | u8 rxchainmask, | |
791 | bool longcal); | |
55e82df4 | 792 | bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); |
2b63a41d FF |
793 | void (*set_txdesc)(struct ath_hw *ah, void *ds, |
794 | struct ath_tx_info *i); | |
cc610ac0 VT |
795 | int (*proc_txdesc)(struct ath_hw *ah, void *ds, |
796 | struct ath_tx_status *ts); | |
69de3721 MSS |
797 | void (*antdiv_comb_conf_get)(struct ath_hw *ah, |
798 | struct ath_hw_antcomb_conf *antconf); | |
799 | void (*antdiv_comb_conf_set)(struct ath_hw *ah, | |
800 | struct ath_hw_antcomb_conf *antconf); | |
801 | ||
d70357d5 LR |
802 | }; |
803 | ||
f2552e28 FF |
804 | struct ath_nf_limits { |
805 | s16 max; | |
806 | s16 min; | |
807 | s16 nominal; | |
808 | }; | |
809 | ||
8ad74c4d RM |
810 | enum ath_cal_list { |
811 | TX_IQ_CAL = BIT(0), | |
812 | TX_IQ_ON_AGC_CAL = BIT(1), | |
813 | TX_CL_CAL = BIT(2), | |
814 | }; | |
815 | ||
97dcec57 SM |
816 | /* ah_flags */ |
817 | #define AH_USE_EEPROM 0x1 | |
818 | #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ | |
a126ff51 | 819 | #define AH_FASTCC 0x4 |
97dcec57 | 820 | |
cbe61d8a | 821 | struct ath_hw { |
f9f84e96 FF |
822 | struct ath_ops reg_ops; |
823 | ||
b002a4a9 | 824 | struct ieee80211_hw *hw; |
27c51f1a | 825 | struct ath_common common; |
cbe61d8a | 826 | struct ath9k_hw_version hw_version; |
2660b81a S |
827 | struct ath9k_ops_config config; |
828 | struct ath9k_hw_capabilities caps; | |
cac4220b | 829 | struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; |
2660b81a | 830 | struct ath9k_channel *curchan; |
394cf0a1 | 831 | |
cbe61d8a S |
832 | union { |
833 | struct ar5416_eeprom_def def; | |
834 | struct ar5416_eeprom_4k map4k; | |
475f5989 | 835 | struct ar9287_eeprom map9287; |
15c9ee7a | 836 | struct ar9300_eeprom ar9300_eep; |
2660b81a | 837 | } eeprom; |
f74df6fb | 838 | const struct eeprom_ops *eep_ops; |
cbe61d8a S |
839 | |
840 | bool sw_mgmt_crypto; | |
2660b81a | 841 | bool is_pciexpress; |
d4930086 | 842 | bool aspm_enabled; |
5f841b41 | 843 | bool is_monitoring; |
2eb46d9b | 844 | bool need_an_top2_fixup; |
2660b81a | 845 | u16 tx_trig_level; |
f2552e28 | 846 | |
bbacee13 | 847 | u32 nf_regs[6]; |
f2552e28 FF |
848 | struct ath_nf_limits nf_2g; |
849 | struct ath_nf_limits nf_5g; | |
2660b81a S |
850 | u16 rfsilent; |
851 | u32 rfkill_gpio; | |
852 | u32 rfkill_polarity; | |
cbe61d8a | 853 | u32 ah_flags; |
394cf0a1 | 854 | |
d7e7d229 LR |
855 | bool htc_reset_init; |
856 | ||
2660b81a S |
857 | enum nl80211_iftype opmode; |
858 | enum ath9k_power_mode power_mode; | |
f078f209 | 859 | |
f23fba49 | 860 | s8 noise; |
20bd2a09 | 861 | struct ath9k_hw_cal_data *caldata; |
a13883b0 | 862 | struct ath9k_pacal_info pacal_info; |
2660b81a S |
863 | struct ar5416Stats stats; |
864 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; | |
865 | ||
866 | int16_t curchan_rad_index; | |
3069168c | 867 | enum ath9k_int imask; |
74bad5cb | 868 | u32 imrs2_reg; |
2660b81a S |
869 | u32 txok_interrupt_mask; |
870 | u32 txerr_interrupt_mask; | |
871 | u32 txdesc_interrupt_mask; | |
872 | u32 txeol_interrupt_mask; | |
873 | u32 txurn_interrupt_mask; | |
e8fe7336 | 874 | atomic_t intr_ref_cnt; |
2660b81a S |
875 | bool chip_fullsleep; |
876 | u32 atim_window; | |
5f0c04ea | 877 | u32 modes_index; |
6a2b9e8c S |
878 | |
879 | /* Calibration */ | |
6497827f | 880 | u32 supp_cals; |
cbfe9468 S |
881 | struct ath9k_cal_list iq_caldata; |
882 | struct ath9k_cal_list adcgain_caldata; | |
cbfe9468 | 883 | struct ath9k_cal_list adcdc_caldata; |
df23acaa | 884 | struct ath9k_cal_list tempCompCalData; |
cbfe9468 S |
885 | struct ath9k_cal_list *cal_list; |
886 | struct ath9k_cal_list *cal_list_last; | |
887 | struct ath9k_cal_list *cal_list_curr; | |
2660b81a S |
888 | #define totalPowerMeasI meas0.unsign |
889 | #define totalPowerMeasQ meas1.unsign | |
890 | #define totalIqCorrMeas meas2.sign | |
891 | #define totalAdcIOddPhase meas0.unsign | |
892 | #define totalAdcIEvenPhase meas1.unsign | |
893 | #define totalAdcQOddPhase meas2.unsign | |
894 | #define totalAdcQEvenPhase meas3.unsign | |
895 | #define totalAdcDcOffsetIOddPhase meas0.sign | |
896 | #define totalAdcDcOffsetIEvenPhase meas1.sign | |
897 | #define totalAdcDcOffsetQOddPhase meas2.sign | |
898 | #define totalAdcDcOffsetQEvenPhase meas3.sign | |
f078f209 LR |
899 | union { |
900 | u32 unsign[AR5416_MAX_CHAINS]; | |
901 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 902 | } meas0; |
f078f209 LR |
903 | union { |
904 | u32 unsign[AR5416_MAX_CHAINS]; | |
905 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 906 | } meas1; |
f078f209 LR |
907 | union { |
908 | u32 unsign[AR5416_MAX_CHAINS]; | |
909 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 910 | } meas2; |
f078f209 LR |
911 | union { |
912 | u32 unsign[AR5416_MAX_CHAINS]; | |
913 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a S |
914 | } meas3; |
915 | u16 cal_samples; | |
8ad74c4d | 916 | u8 enabled_cals; |
6a2b9e8c | 917 | |
2660b81a S |
918 | u32 sta_id1_defaults; |
919 | u32 misc_mode; | |
f078f209 LR |
920 | enum { |
921 | AUTO_32KHZ, | |
922 | USE_32KHZ, | |
923 | DONT_USE_32KHZ, | |
2660b81a | 924 | } enable_32kHz_clock; |
6a2b9e8c | 925 | |
d70357d5 LR |
926 | /* Private to hardware code */ |
927 | struct ath_hw_private_ops private_ops; | |
928 | /* Accessed by the lower level driver */ | |
929 | struct ath_hw_ops ops; | |
930 | ||
e68a060b | 931 | /* Used to program the radio on non single-chip devices */ |
2660b81a S |
932 | u32 *analogBank0Data; |
933 | u32 *analogBank1Data; | |
934 | u32 *analogBank2Data; | |
935 | u32 *analogBank3Data; | |
936 | u32 *analogBank6Data; | |
937 | u32 *analogBank6TPCData; | |
938 | u32 *analogBank7Data; | |
939 | u32 *addac5416_21; | |
940 | u32 *bank6Temp; | |
941 | ||
597a94b3 | 942 | u8 txpower_limit; |
e239d859 | 943 | int coverage_class; |
2660b81a | 944 | u32 slottime; |
2660b81a | 945 | u32 globaltxtimeout; |
6a2b9e8c S |
946 | |
947 | /* ANI */ | |
2660b81a | 948 | u32 proc_phyerr; |
2660b81a | 949 | u32 aniperiod; |
2660b81a S |
950 | int totalSizeDesired[5]; |
951 | int coarse_high[5]; | |
952 | int coarse_low[5]; | |
953 | int firpwr[5]; | |
954 | enum ath9k_ani_cmd ani_function; | |
955 | ||
af03abec | 956 | /* Bluetooth coexistance */ |
766ec4a9 | 957 | struct ath_btcoex_hw btcoex_hw; |
af03abec | 958 | |
2660b81a | 959 | u32 intr_txqs; |
2660b81a S |
960 | u8 txchainmask; |
961 | u8 rxchainmask; | |
962 | ||
c5d0855a FF |
963 | struct ath_hw_radar_conf radar_conf; |
964 | ||
8bd1d07f SB |
965 | u32 originalGain[22]; |
966 | int initPDADC; | |
967 | int PDADCdelta; | |
6de66dd9 | 968 | int led_pin; |
691680b8 FF |
969 | u32 gpio_mask; |
970 | u32 gpio_val; | |
8bd1d07f | 971 | |
2660b81a S |
972 | struct ar5416IniArray iniModes; |
973 | struct ar5416IniArray iniCommon; | |
974 | struct ar5416IniArray iniBank0; | |
975 | struct ar5416IniArray iniBB_RfGain; | |
976 | struct ar5416IniArray iniBank1; | |
977 | struct ar5416IniArray iniBank2; | |
978 | struct ar5416IniArray iniBank3; | |
979 | struct ar5416IniArray iniBank6; | |
980 | struct ar5416IniArray iniBank6TPC; | |
981 | struct ar5416IniArray iniBank7; | |
982 | struct ar5416IniArray iniAddac; | |
983 | struct ar5416IniArray iniPcieSerdes; | |
13ce3e99 | 984 | struct ar5416IniArray iniPcieSerdesLowPower; |
2660b81a | 985 | struct ar5416IniArray iniModesAdditional; |
d89baac8 | 986 | struct ar5416IniArray iniModesAdditional_40M; |
2660b81a S |
987 | struct ar5416IniArray iniModesRxGain; |
988 | struct ar5416IniArray iniModesTxGain; | |
8564328d | 989 | struct ar5416IniArray iniModes_9271_1_0_only; |
193cd458 S |
990 | struct ar5416IniArray iniCckfirNormal; |
991 | struct ar5416IniArray iniCckfirJapan2484; | |
ce407afc | 992 | struct ar5416IniArray ini_japan2484; |
70807e99 S |
993 | struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; |
994 | struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; | |
995 | struct ar5416IniArray iniModes_9271_ANI_reg; | |
996 | struct ar5416IniArray iniModes_high_power_tx_gain_9271; | |
997 | struct ar5416IniArray iniModes_normal_power_tx_gain_9271; | |
ce407afc SB |
998 | struct ar5416IniArray ini_radio_post_sys2ant; |
999 | struct ar5416IniArray ini_BTCOEX_MAX_TXPWR; | |
ff155a45 | 1000 | |
13ce3e99 LR |
1001 | struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; |
1002 | struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; | |
1003 | struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; | |
1004 | struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; | |
1005 | ||
ff155a45 VT |
1006 | u32 intr_gen_timer_trigger; |
1007 | u32 intr_gen_timer_thresh; | |
1008 | struct ath_gen_timer_table hw_gen_timers; | |
744d4025 VT |
1009 | |
1010 | struct ar9003_txs *ts_ring; | |
1011 | void *ts_start; | |
1012 | u32 ts_paddr_start; | |
1013 | u32 ts_paddr_end; | |
1014 | u16 ts_tail; | |
1015 | u8 ts_size; | |
aea702b7 LR |
1016 | |
1017 | u32 bb_watchdog_last_status; | |
1018 | u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ | |
51ac8cbb | 1019 | u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ |
717f6bed | 1020 | |
1bf38661 FF |
1021 | unsigned int paprd_target_power; |
1022 | unsigned int paprd_training_power; | |
7072bf62 | 1023 | unsigned int paprd_ratemask; |
f1a8abb0 | 1024 | unsigned int paprd_ratemask_ht40; |
45ef6a0b | 1025 | bool paprd_table_write_done; |
717f6bed FF |
1026 | u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; |
1027 | u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; | |
9a658d2b LR |
1028 | /* |
1029 | * Store the permanent value of Reg 0x4004in WARegVal | |
1030 | * so we dont have to R/M/W. We should not be reading | |
1031 | * this register when in sleep states. | |
1032 | */ | |
1033 | u32 WARegVal; | |
6ee63f55 SB |
1034 | |
1035 | /* Enterprise mode cap */ | |
1036 | u32 ent_mode; | |
f2f5f2a1 VT |
1037 | |
1038 | bool is_clk_25mhz; | |
3762561a | 1039 | int (*get_mac_revision)(void); |
7d95847c | 1040 | int (*external_reset)(void); |
f078f209 | 1041 | }; |
f078f209 | 1042 | |
0cb9e06b FF |
1043 | struct ath_bus_ops { |
1044 | enum ath_bus_type ath_bus_type; | |
1045 | void (*read_cachesize)(struct ath_common *common, int *csz); | |
1046 | bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); | |
1047 | void (*bt_coex_prep)(struct ath_common *common); | |
1048 | void (*extn_synch_en)(struct ath_common *common); | |
d4930086 | 1049 | void (*aspm_init)(struct ath_common *common); |
0cb9e06b FF |
1050 | }; |
1051 | ||
9e4bffd2 LR |
1052 | static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) |
1053 | { | |
1054 | return &ah->common; | |
1055 | } | |
1056 | ||
1057 | static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) | |
1058 | { | |
1059 | return &(ath9k_hw_common(ah)->regulatory); | |
1060 | } | |
1061 | ||
d70357d5 LR |
1062 | static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) |
1063 | { | |
1064 | return &ah->private_ops; | |
1065 | } | |
1066 | ||
1067 | static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) | |
1068 | { | |
1069 | return &ah->ops; | |
1070 | } | |
1071 | ||
895ad7eb VT |
1072 | static inline u8 get_streams(int mask) |
1073 | { | |
1074 | return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); | |
1075 | } | |
1076 | ||
f637cfd6 | 1077 | /* Initialization, Detach, Reset */ |
394cf0a1 | 1078 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); |
285f2dda | 1079 | void ath9k_hw_deinit(struct ath_hw *ah); |
f637cfd6 | 1080 | int ath9k_hw_init(struct ath_hw *ah); |
cbe61d8a | 1081 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
20bd2a09 | 1082 | struct ath9k_hw_cal_data *caldata, bool bChannelChange); |
a9a29ce6 | 1083 | int ath9k_hw_fill_cap_info(struct ath_hw *ah); |
8fe65368 | 1084 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); |
394cf0a1 | 1085 | |
394cf0a1 | 1086 | /* GPIO / RFKILL / Antennae */ |
cbe61d8a S |
1087 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); |
1088 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); | |
1089 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, | |
394cf0a1 | 1090 | u32 ah_signal_type); |
cbe61d8a | 1091 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
cbe61d8a S |
1092 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah); |
1093 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); | |
394cf0a1 S |
1094 | |
1095 | /* General Operation */ | |
0caa7b14 | 1096 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
a9b6b256 FF |
1097 | void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, |
1098 | int column, unsigned int *writecnt); | |
394cf0a1 | 1099 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
4f0fc7c3 | 1100 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 1101 | u8 phy, int kbps, |
394cf0a1 | 1102 | u32 frameLen, u16 rateix, bool shortPreamble); |
cbe61d8a | 1103 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
394cf0a1 S |
1104 | struct ath9k_channel *chan, |
1105 | struct chan_centers *centers); | |
cbe61d8a S |
1106 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
1107 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); | |
1108 | bool ath9k_hw_phy_disable(struct ath_hw *ah); | |
1109 | bool ath9k_hw_disable(struct ath_hw *ah); | |
de40f316 | 1110 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); |
cbe61d8a S |
1111 | void ath9k_hw_setopmode(struct ath_hw *ah); |
1112 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); | |
f2b2143e | 1113 | void ath9k_hw_write_associd(struct ath_hw *ah); |
dd347f2f | 1114 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); |
cbe61d8a S |
1115 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
1116 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); | |
1117 | void ath9k_hw_reset_tsf(struct ath_hw *ah); | |
54e4cec6 | 1118 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); |
0005baf4 | 1119 | void ath9k_hw_init_global_settings(struct ath_hw *ah); |
b84628eb | 1120 | u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); |
25c56eec | 1121 | void ath9k_hw_set11nmac2040(struct ath_hw *ah); |
cbe61d8a S |
1122 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); |
1123 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |
394cf0a1 | 1124 | const struct ath9k_beacon_state *bs); |
c9c99e5e | 1125 | bool ath9k_hw_check_alive(struct ath_hw *ah); |
a91d75ae | 1126 | |
9ecdef4b | 1127 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); |
a91d75ae | 1128 | |
ff155a45 VT |
1129 | /* Generic hw timer primitives */ |
1130 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
1131 | void (*trigger)(void *), | |
1132 | void (*overflow)(void *), | |
1133 | void *arg, | |
1134 | u8 timer_index); | |
cd9bf689 LR |
1135 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
1136 | struct ath_gen_timer *timer, | |
1137 | u32 timer_next, | |
1138 | u32 timer_period); | |
1139 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); | |
1140 | ||
ff155a45 VT |
1141 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); |
1142 | void ath_gen_timer_isr(struct ath_hw *hw); | |
1143 | ||
f934c4d9 | 1144 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); |
2da4f01a | 1145 | |
05020d23 S |
1146 | /* HTC */ |
1147 | void ath9k_hw_htc_resetinit(struct ath_hw *ah); | |
1148 | ||
8fe65368 LR |
1149 | /* PHY */ |
1150 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, | |
1151 | u32 *coef_mantissa, u32 *coef_exponent); | |
ca2c68cc | 1152 | void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan); |
8fe65368 | 1153 | |
ebd5a14a LR |
1154 | /* |
1155 | * Code Specific to AR5008, AR9001 or AR9002, | |
1156 | * we stuff these here to avoid callbacks for AR9003. | |
1157 | */ | |
d8f492b7 | 1158 | void ar9002_hw_cck_chan14_spread(struct ath_hw *ah); |
ebd5a14a | 1159 | int ar9002_hw_rf_claim(struct ath_hw *ah); |
78ec2677 | 1160 | void ar9002_hw_enable_async_fifo(struct ath_hw *ah); |
d8f492b7 | 1161 | |
641d9921 | 1162 | /* |
aea702b7 | 1163 | * Code specific to AR9003, we stuff these here to avoid callbacks |
641d9921 FF |
1164 | * for older families |
1165 | */ | |
aea702b7 LR |
1166 | void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); |
1167 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); | |
1168 | void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); | |
51ac8cbb | 1169 | void ar9003_hw_disable_phy_restart(struct ath_hw *ah); |
717f6bed FF |
1170 | void ar9003_paprd_enable(struct ath_hw *ah, bool val); |
1171 | void ar9003_paprd_populate_single_table(struct ath_hw *ah, | |
20bd2a09 FF |
1172 | struct ath9k_hw_cal_data *caldata, |
1173 | int chain); | |
1174 | int ar9003_paprd_create_curve(struct ath_hw *ah, | |
1175 | struct ath9k_hw_cal_data *caldata, int chain); | |
717f6bed FF |
1176 | int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); |
1177 | int ar9003_paprd_init_table(struct ath_hw *ah); | |
1178 | bool ar9003_paprd_is_done(struct ath_hw *ah); | |
1179 | void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains); | |
641d9921 FF |
1180 | |
1181 | /* Hardware family op attach helpers */ | |
8fe65368 | 1182 | void ar5008_hw_attach_phy_ops(struct ath_hw *ah); |
8525f280 LR |
1183 | void ar9002_hw_attach_phy_ops(struct ath_hw *ah); |
1184 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah); | |
8fe65368 | 1185 | |
795f5e2c LR |
1186 | void ar9002_hw_attach_calib_ops(struct ath_hw *ah); |
1187 | void ar9003_hw_attach_calib_ops(struct ath_hw *ah); | |
1188 | ||
b3950e6a LR |
1189 | void ar9002_hw_attach_ops(struct ath_hw *ah); |
1190 | void ar9003_hw_attach_ops(struct ath_hw *ah); | |
1191 | ||
c2ba3342 | 1192 | void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); |
ac0bb767 LR |
1193 | /* |
1194 | * ANI work can be shared between all families but a next | |
1195 | * generation implementation of ANI will be used only for AR9003 only | |
1196 | * for now as the other families still need to be tested with the same | |
e36b27af LR |
1197 | * next generation ANI. Feel free to start testing it though for the |
1198 | * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani. | |
ac0bb767 | 1199 | */ |
e36b27af | 1200 | extern int modparam_force_new_ani; |
8eb4980c | 1201 | void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); |
bfc472bb | 1202 | void ath9k_hw_proc_mib_event(struct ath_hw *ah); |
95792178 | 1203 | void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); |
ac0bb767 | 1204 | |
bbefb871 MSS |
1205 | bool ar9003_mci_send_message(struct ath_hw *ah, u8 header, u32 flag, |
1206 | u32 *payload, u8 len, bool wait_done, | |
1207 | bool check_bt); | |
1208 | void ar9003_mci_mute_bt(struct ath_hw *ah); | |
1209 | u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data); | |
1210 | void ar9003_mci_setup(struct ath_hw *ah, u32 gpm_addr, void *gpm_buf, | |
1211 | u16 len, u32 sched_addr); | |
1212 | void ar9003_mci_cleanup(struct ath_hw *ah); | |
1213 | void ar9003_mci_send_coex_halt_bt_gpm(struct ath_hw *ah, bool halt, | |
1214 | bool wait_done); | |
1215 | u32 ar9003_mci_wait_for_gpm(struct ath_hw *ah, u8 gpm_type, | |
1216 | u8 gpm_opcode, int time_out); | |
1217 | void ar9003_mci_2g5g_changed(struct ath_hw *ah, bool is_2g); | |
1218 | void ar9003_mci_disable_interrupt(struct ath_hw *ah); | |
1219 | void ar9003_mci_enable_interrupt(struct ath_hw *ah); | |
1220 | void ar9003_mci_2g5g_switch(struct ath_hw *ah, bool wait_done); | |
1221 | void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g, | |
1222 | bool is_full_sleep); | |
1223 | bool ar9003_mci_check_int(struct ath_hw *ah, u32 ints); | |
1224 | void ar9003_mci_remote_reset(struct ath_hw *ah, bool wait_done); | |
1225 | void ar9003_mci_send_sys_waking(struct ath_hw *ah, bool wait_done); | |
1226 | void ar9003_mci_send_lna_transfer(struct ath_hw *ah, bool wait_done); | |
1227 | void ar9003_mci_sync_bt_state(struct ath_hw *ah); | |
1228 | void ar9003_mci_get_interrupt(struct ath_hw *ah, u32 *raw_intr, | |
1229 | u32 *rx_msg_intr); | |
1230 | ||
73377256 LR |
1231 | #define ATH9K_CLOCK_RATE_CCK 22 |
1232 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 | |
1233 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 | |
1234 | #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 | |
1235 | ||
f078f209 | 1236 | #endif |