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atheros: define shared bssidmask setting
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
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f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
3a702e49 33
394cf0a1
S		 34#define ATHEROS_VENDOR_ID 0x168c
35#define AR5416_DEVID_PCI 0x0023
36#define AR5416_DEVID_PCIE 0x0024
37#define AR9160_DEVID_PCI 0x0027
38#define AR9280_DEVID_PCI 0x0029
39#define AR9280_DEVID_PCIE 0x002a
40#define AR9285_DEVID_PCIE 0x002b
41#define AR5416_AR9100_DEVID 0x000b
42#define AR_SUBVENDOR_ID_NOG 0x0e11
43#define AR_SUBVENDOR_ID_NEW_A 0x7065
44#define AR5416_MAGIC 0x19641014
45
ac88b6ec
VN		 46#define AR5416_DEVID_AR9287_PCI 0x002D
47#define AR5416_DEVID_AR9287_PCIE 0x002E
48
fe12946e
VT		 49#define AR9280_COEX2WIRE_SUBSYSID 0x309b
50#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
51#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
52
394cf0a1 53/* Register read/write primitives */
9e4bffd2
LR		 54#define REG_WRITE(_ah, _reg, _val) \
55 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
56
57#define REG_READ(_ah, _reg) \
58 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
394cf0a1
S		 59
60#define SM(_v, _f) (((_v) << _f##_S) & _f)
61#define MS(_v, _f) (((_v) & _f) >> _f##_S)
62#define REG_RMW(_a, _r, _set, _clr) \
63 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
64#define REG_RMW_FIELD(_a, _r, _f, _v) \
65 REG_WRITE(_a, _r, \
66 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
67#define REG_SET_BIT(_a, _r, _f) \
68 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
69#define REG_CLR_BIT(_a, _r, _f) \
70 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 71
394cf0a1
S		 72#define DO_DELAY(x) do { \
73 if ((++(x) % 64) == 0) \
74 udelay(1); \
75 } while (0)
f078f209 76
394cf0a1
S		 77#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
78 int r; \
79 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
80 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
81 INI_RA((iniarray), r, (column))); \
82 DO_DELAY(regWr); \
83 } \
84 } while (0)
f078f209 85
394cf0a1
S		 86#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
87#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
88#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
89#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 90#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 91#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
92#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 93
394cf0a1
S		 94#define AR_GPIOD_MASK 0x00001FFF
95#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 96
394cf0a1
S		 97#define BASE_ACTIVATE_DELAY 100
98#define RTC_PLL_SETTLE_DELAY 1000
99#define COEF_SCALE_S 24
100#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 101
394cf0a1
S		 102#define ATH9K_ANTENNA0_CHAINMASK 0x1
103#define ATH9K_ANTENNA1_CHAINMASK 0x2
104
105#define ATH9K_NUM_DMA_DEBUG_REGS 8
106#define ATH9K_NUM_QUEUES 10
107
108#define MAX_RATE_POWER 63
0caa7b14 109#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 110#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 111#define AH_TIME_QUANTUM 10
112#define AR_KEYTABLE_SIZE 128
d8caa839 113#define POWER_UP_TIME 10000
394cf0a1
S		 114#define SPUR_RSSI_THRESH 40
115
116#define CAB_TIMEOUT_VAL 10
117#define BEACON_TIMEOUT_VAL 10
118#define MIN_BEACON_TIMEOUT_VAL 1
119#define SLEEP_SLOP 3
120
121#define INIT_CONFIG_STATUS 0x00000000
122#define INIT_RSSI_THR 0x00000700
123#define INIT_BCON_CNTRL_REG 0x00000000
124
125#define TU_TO_USEC(_tu) ((_tu) << 10)
126
127enum wireless_mode {
128 ATH9K_MODE_11A = 0,
b9b6e15a
LR		 129 ATH9K_MODE_11G,
130 ATH9K_MODE_11NA_HT20,
131 ATH9K_MODE_11NG_HT20,
132 ATH9K_MODE_11NA_HT40PLUS,
133 ATH9K_MODE_11NA_HT40MINUS,
134 ATH9K_MODE_11NG_HT40PLUS,
135 ATH9K_MODE_11NG_HT40MINUS,
136 ATH9K_MODE_MAX,
394cf0a1 137};
f078f209 138
1cf6873a
S		 139enum ath9k_ant_setting {
140 ATH9K_ANT_VARIABLE = 0,
141 ATH9K_ANT_FIXED_A,
142 ATH9K_ANT_FIXED_B
143};
144
394cf0a1 145enum ath9k_hw_caps {
bdbdf46d
S		 146 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
147 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
148 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
149 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
150 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
151 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
152 ATH9K_HW_CAP_VEOL = BIT(6),
153 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
154 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
155 ATH9K_HW_CAP_HT = BIT(9),
156 ATH9K_HW_CAP_GTT = BIT(10),
157 ATH9K_HW_CAP_FASTCC = BIT(11),
158 ATH9K_HW_CAP_RFSILENT = BIT(12),
159 ATH9K_HW_CAP_CST = BIT(13),
160 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
161 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
162 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
394cf0a1 163};
f078f209 164
394cf0a1
S		 165enum ath9k_capability_type {
166 ATH9K_CAP_CIPHER = 0,
167 ATH9K_CAP_TKIP_MIC,
168 ATH9K_CAP_TKIP_SPLIT,
394cf0a1
S		 169 ATH9K_CAP_DIVERSITY,
170 ATH9K_CAP_TXPOW,
394cf0a1 171 ATH9K_CAP_MCAST_KEYSRCH,
8bd1d07f 172 ATH9K_CAP_DS
394cf0a1 173};
f078f209 174
394cf0a1
S		 175struct ath9k_hw_capabilities {
176 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
177 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
178 u16 total_queues;
179 u16 keycache_size;
180 u16 low_5ghz_chan, high_5ghz_chan;
181 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 182 u16 rts_aggr_limit;
183 u8 tx_chainmask;
184 u8 rx_chainmask;
185 u16 tx_triglevel_max;
186 u16 reg_cap;
187 u8 num_gpio_pins;
188 u8 num_antcfg_2ghz;
189 u8 num_antcfg_5ghz;
190};
f078f209 191
394cf0a1
S		 192struct ath9k_ops_config {
193 int dma_beacon_response_time;
194 int sw_beacon_response_time;
195 int additional_swba_backoff;
196 int ack_6mb;
197 int cwm_ignore_extcca;
198 u8 pcie_powersave_enable;
394cf0a1
S		 199 u8 pcie_clock_req;
200 u32 pcie_waen;
394cf0a1
S		 201 u8 analog_shiftreg;
202 u8 ht_enable;
203 u32 ofdm_trig_low;
204 u32 ofdm_trig_high;
205 u32 cck_trig_high;
206 u32 cck_trig_low;
207 u32 enable_ani;
1cf6873a 208 enum ath9k_ant_setting diversity_control;
394cf0a1
S		 209 u16 antenna_switch_swap;
210 int serialize_regmode;
0ef1f168 211 bool intr_mitigation;
394cf0a1
S		 212#define SPUR_DISABLE 0
213#define SPUR_ENABLE_IOCTL 1
214#define SPUR_ENABLE_EEPROM 2
215#define AR_EEPROM_MODAL_SPURS 5
216#define AR_SPUR_5413_1 1640
217#define AR_SPUR_5413_2 1200
218#define AR_NO_SPUR 0x8000
219#define AR_BASE_FREQ_2GHZ 2300
220#define AR_BASE_FREQ_5GHZ 4900
221#define AR_SPUR_FEEQ_BOUND_HT40 19
222#define AR_SPUR_FEEQ_BOUND_HT20 10
223 int spurmode;
224 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
225};
f078f209 226
394cf0a1
S		 227enum ath9k_int {
228 ATH9K_INT_RX = 0x00000001,
229 ATH9K_INT_RXDESC = 0x00000002,
230 ATH9K_INT_RXNOFRM = 0x00000008,
231 ATH9K_INT_RXEOL = 0x00000010,
232 ATH9K_INT_RXORN = 0x00000020,
233 ATH9K_INT_TX = 0x00000040,
234 ATH9K_INT_TXDESC = 0x00000080,
235 ATH9K_INT_TIM_TIMER = 0x00000100,
236 ATH9K_INT_TXURN = 0x00000800,
237 ATH9K_INT_MIB = 0x00001000,
238 ATH9K_INT_RXPHY = 0x00004000,
239 ATH9K_INT_RXKCM = 0x00008000,
240 ATH9K_INT_SWBA = 0x00010000,
241 ATH9K_INT_BMISS = 0x00040000,
242 ATH9K_INT_BNR = 0x00100000,
243 ATH9K_INT_TIM = 0x00200000,
244 ATH9K_INT_DTIM = 0x00400000,
245 ATH9K_INT_DTIMSYNC = 0x00800000,
246 ATH9K_INT_GPIO = 0x01000000,
247 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 248 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 249 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 250 ATH9K_INT_CST = 0x10000000,
251 ATH9K_INT_GTT = 0x20000000,
252 ATH9K_INT_FATAL = 0x40000000,
253 ATH9K_INT_GLOBAL = 0x80000000,
254 ATH9K_INT_BMISC = ATH9K_INT_TIM |
255 ATH9K_INT_DTIM |
256 ATH9K_INT_DTIMSYNC |
4af9cf4f 257 ATH9K_INT_TSFOOR |
394cf0a1
S		 258 ATH9K_INT_CABEND,
259 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
260 ATH9K_INT_RXDESC |
261 ATH9K_INT_RXEOL |
262 ATH9K_INT_RXORN |
263 ATH9K_INT_TXURN |
264 ATH9K_INT_TXDESC |
265 ATH9K_INT_MIB |
266 ATH9K_INT_RXPHY |
267 ATH9K_INT_RXKCM |
268 ATH9K_INT_SWBA |
269 ATH9K_INT_BMISS |
270 ATH9K_INT_GPIO,
271 ATH9K_INT_NOCARD = 0xffffffff
272};
f078f209 273
394cf0a1
S		 274#define CHANNEL_CW_INT 0x00002
275#define CHANNEL_CCK 0x00020
276#define CHANNEL_OFDM 0x00040
277#define CHANNEL_2GHZ 0x00080
278#define CHANNEL_5GHZ 0x00100
279#define CHANNEL_PASSIVE 0x00200
280#define CHANNEL_DYN 0x00400
281#define CHANNEL_HALF 0x04000
282#define CHANNEL_QUARTER 0x08000
283#define CHANNEL_HT20 0x10000
284#define CHANNEL_HT40PLUS 0x20000
285#define CHANNEL_HT40MINUS 0x40000
286
394cf0a1
S		 287#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
288#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
289#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
290#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
291#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
292#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
293#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
294#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
295#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
296#define CHANNEL_ALL \
297 (CHANNEL_OFDM| \
298 CHANNEL_CCK| \
299 CHANNEL_2GHZ | \
300 CHANNEL_5GHZ | \
301 CHANNEL_HT20 | \
302 CHANNEL_HT40PLUS | \
303 CHANNEL_HT40MINUS)
304
305struct ath9k_channel {
306 struct ieee80211_channel *chan;
307 u16 channel;
308 u32 channelFlags;
309 u32 chanmode;
310 int32_t CalValid;
311 bool oneTimeCalsDone;
312 int8_t iCoff;
313 int8_t qCoff;
314 int16_t rawNoiseFloor;
315};
f078f209 316
394cf0a1
S		 317#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
318 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
319 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
320 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
321#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
322#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
323#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 324#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
325#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
326#define IS_CHAN_A_5MHZ_SPACED(_c) \
327 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
328 (((_c)->channel % 20) != 0) && \
329 (((_c)->channel % 10) != 0))
330
331/* These macros check chanmode and not channelFlags */
332#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
333#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
334 ((_c)->chanmode == CHANNEL_G_HT20))
335#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
336 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
337 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
338 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
339#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
340
341enum ath9k_power_mode {
342 ATH9K_PM_AWAKE = 0,
343 ATH9K_PM_FULL_SLEEP,
344 ATH9K_PM_NETWORK_SLEEP,
345 ATH9K_PM_UNDEFINED
346};
f078f209 347
394cf0a1
S		 348enum ath9k_tp_scale {
349 ATH9K_TP_SCALE_MAX = 0,
350 ATH9K_TP_SCALE_50,
351 ATH9K_TP_SCALE_25,
352 ATH9K_TP_SCALE_12,
353 ATH9K_TP_SCALE_MIN
354};
f078f209 355
394cf0a1
S		 356enum ser_reg_mode {
357 SER_REG_MODE_OFF = 0,
358 SER_REG_MODE_ON = 1,
359 SER_REG_MODE_AUTO = 2,
360};
f078f209 361
394cf0a1
S		 362struct ath9k_beacon_state {
363 u32 bs_nexttbtt;
364 u32 bs_nextdtim;
365 u32 bs_intval;
366#define ATH9K_BEACON_PERIOD 0x0000ffff
367#define ATH9K_BEACON_ENA 0x00800000
368#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 369#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 370 u32 bs_dtimperiod;
371 u16 bs_cfpperiod;
372 u16 bs_cfpmaxduration;
373 u32 bs_cfpnext;
374 u16 bs_timoffset;
375 u16 bs_bmissthreshold;
376 u32 bs_sleepduration;
4af9cf4f 377 u32 bs_tsfoor_threshold;
394cf0a1 378};
f078f209 379
394cf0a1
S		 380struct chan_centers {
381 u16 synth_center;
382 u16 ctl_center;
383 u16 ext_center;
384};
f078f209 385
394cf0a1
S		 386enum {
387 ATH9K_RESET_POWER_ON,
388 ATH9K_RESET_WARM,
389 ATH9K_RESET_COLD,
390};
f078f209 391
d535a42a
S		 392struct ath9k_hw_version {
393 u32 magic;
394 u16 devid;
395 u16 subvendorid;
396 u32 macVersion;
397 u16 macRev;
398 u16 phyRev;
399 u16 analog5GhzRev;
400 u16 analog2GhzRev;
aeac355d 401 u16 subsysid;
d535a42a 402};
394cf0a1 403
ff155a45
VT		 404/* Generic TSF timer definitions */
405
406#define ATH_MAX_GEN_TIMER 16
407
408#define AR_GENTMR_BIT(_index) (1 << (_index))
409
410/*
411 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
412 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
413 */
414#define debruijn32 0x077CB531UL
415
416struct ath_gen_timer_configuration {
417 u32 next_addr;
418 u32 period_addr;
419 u32 mode_addr;
420 u32 mode_mask;
421};
422
423struct ath_gen_timer {
424 void (*trigger)(void *arg);
425 void (*overflow)(void *arg);
426 void *arg;
427 u8 index;
428};
429
430struct ath_gen_timer_table {
431 u32 gen_timer_index[32];
432 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
433 union {
434 unsigned long timer_bits;
435 u16 val;
436 } timer_mask;
437};
438
cbe61d8a 439struct ath_hw {
394cf0a1 440 struct ath_softc *ah_sc;
27c51f1a 441 struct ath_common common;
cbe61d8a 442 struct ath9k_hw_version hw_version;
2660b81a
S		 443 struct ath9k_ops_config config;
444 struct ath9k_hw_capabilities caps;
2660b81a
S		 445 struct ath9k_channel channels[38];
446 struct ath9k_channel *curchan;
394cf0a1 447
cbe61d8a
S		 448 union {
449 struct ar5416_eeprom_def def;
450 struct ar5416_eeprom_4k map4k;
475f5989 451 struct ar9287_eeprom map9287;
2660b81a 452 } eeprom;
f74df6fb 453 const struct eeprom_ops *eep_ops;
2660b81a 454 enum ath9k_eep_map eep_map;
cbe61d8a
S		 455
456 bool sw_mgmt_crypto;
2660b81a 457 bool is_pciexpress;
2660b81a
S		 458 u16 tx_trig_level;
459 u16 rfsilent;
460 u32 rfkill_gpio;
461 u32 rfkill_polarity;
cbe61d8a 462 u32 ah_flags;
394cf0a1 463
d7e7d229
LR		 464 bool htc_reset_init;
465
2660b81a
S		 466 enum nl80211_iftype opmode;
467 enum ath9k_power_mode power_mode;
f078f209 468
cbe61d8a 469 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
a13883b0 470 struct ath9k_pacal_info pacal_info;
2660b81a
S		 471 struct ar5416Stats stats;
472 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
473
474 int16_t curchan_rad_index;
475 u32 mask_reg;
476 u32 txok_interrupt_mask;
477 u32 txerr_interrupt_mask;
478 u32 txdesc_interrupt_mask;
479 u32 txeol_interrupt_mask;
480 u32 txurn_interrupt_mask;
481 bool chip_fullsleep;
482 u32 atim_window;
6a2b9e8c
S		 483
484 /* Calibration */
cbfe9468
S		 485 enum ath9k_cal_types supp_cals;
486 struct ath9k_cal_list iq_caldata;
487 struct ath9k_cal_list adcgain_caldata;
488 struct ath9k_cal_list adcdc_calinitdata;
489 struct ath9k_cal_list adcdc_caldata;
490 struct ath9k_cal_list *cal_list;
491 struct ath9k_cal_list *cal_list_last;
492 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 493#define totalPowerMeasI meas0.unsign
494#define totalPowerMeasQ meas1.unsign
495#define totalIqCorrMeas meas2.sign
496#define totalAdcIOddPhase meas0.unsign
497#define totalAdcIEvenPhase meas1.unsign
498#define totalAdcQOddPhase meas2.unsign
499#define totalAdcQEvenPhase meas3.unsign
500#define totalAdcDcOffsetIOddPhase meas0.sign
501#define totalAdcDcOffsetIEvenPhase meas1.sign
502#define totalAdcDcOffsetQOddPhase meas2.sign
503#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 504 union {
505 u32 unsign[AR5416_MAX_CHAINS];
506 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 507 } meas0;
f078f209
LR		 508 union {
509 u32 unsign[AR5416_MAX_CHAINS];
510 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 511 } meas1;
f078f209
LR		 512 union {
513 u32 unsign[AR5416_MAX_CHAINS];
514 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 515 } meas2;
f078f209
LR		 516 union {
517 u32 unsign[AR5416_MAX_CHAINS];
518 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 519 } meas3;
520 u16 cal_samples;
6a2b9e8c 521
2660b81a
S		 522 u32 sta_id1_defaults;
523 u32 misc_mode;
f078f209
LR		 524 enum {
525 AUTO_32KHZ,
526 USE_32KHZ,
527 DONT_USE_32KHZ,
2660b81a 528 } enable_32kHz_clock;
6a2b9e8c
S		 529
530 /* RF */
2660b81a
S		 531 u32 *analogBank0Data;
532 u32 *analogBank1Data;
533 u32 *analogBank2Data;
534 u32 *analogBank3Data;
535 u32 *analogBank6Data;
536 u32 *analogBank6TPCData;
537 u32 *analogBank7Data;
538 u32 *addac5416_21;
539 u32 *bank6Temp;
540
541 int16_t txpower_indexoffset;
542 u32 beacon_interval;
543 u32 slottime;
544 u32 acktimeout;
545 u32 ctstimeout;
546 u32 globaltxtimeout;
547 u8 gbeacon_rate;
6a2b9e8c
S		 548
549 /* ANI */
2660b81a 550 u32 proc_phyerr;
2660b81a
S		 551 u32 aniperiod;
552 struct ar5416AniState *curani;
553 struct ar5416AniState ani[255];
554 int totalSizeDesired[5];
555 int coarse_high[5];
556 int coarse_low[5];
557 int firpwr[5];
558 enum ath9k_ani_cmd ani_function;
559
af03abec 560 /* Bluetooth coexistance */
766ec4a9 561 struct ath_btcoex_hw btcoex_hw;
af03abec 562
2660b81a 563 u32 intr_txqs;
2660b81a
S		 564 enum ath9k_ht_extprotspacing extprotspacing;
565 u8 txchainmask;
566 u8 rxchainmask;
567
8bd1d07f
SB		 568 u32 originalGain[22];
569 int initPDADC;
570 int PDADCdelta;
08fc5c1b 571 u8 led_pin;
8bd1d07f 572
2660b81a
S		 573 struct ar5416IniArray iniModes;
574 struct ar5416IniArray iniCommon;
575 struct ar5416IniArray iniBank0;
576 struct ar5416IniArray iniBB_RfGain;
577 struct ar5416IniArray iniBank1;
578 struct ar5416IniArray iniBank2;
579 struct ar5416IniArray iniBank3;
580 struct ar5416IniArray iniBank6;
581 struct ar5416IniArray iniBank6TPC;
582 struct ar5416IniArray iniBank7;
583 struct ar5416IniArray iniAddac;
584 struct ar5416IniArray iniPcieSerdes;
585 struct ar5416IniArray iniModesAdditional;
586 struct ar5416IniArray iniModesRxGain;
587 struct ar5416IniArray iniModesTxGain;
ff155a45
VT		 588
589 u32 intr_gen_timer_trigger;
590 u32 intr_gen_timer_thresh;
591 struct ath_gen_timer_table hw_gen_timers;
f078f209 592};
f078f209 593
9e4bffd2
LR		 594static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
595{
596 return &ah->common;
597}
598
599static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
600{
601 return &(ath9k_hw_common(ah)->regulatory);
602}
603
f637cfd6 604/* Initialization, Detach, Reset */
394cf0a1 605const char *ath9k_hw_probe(u16 vendorid, u16 devid);
cbe61d8a 606void ath9k_hw_detach(struct ath_hw *ah);
f637cfd6 607int ath9k_hw_init(struct ath_hw *ah);
081b35ab 608void ath9k_hw_rf_free(struct ath_hw *ah);
cbe61d8a 609int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
394cf0a1 610 bool bChannelChange);
eef7a574 611void ath9k_hw_fill_cap_info(struct ath_hw *ah);
cbe61d8a 612bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 613 u32 capability, u32 *result);
cbe61d8a 614bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1
S		 615 u32 capability, u32 setting, int *status);
616
617/* Key Cache Management */
cbe61d8a
S		 618bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
619bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
620bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
394cf0a1 621 const struct ath9k_keyval *k,
e0caf9ea 622 const u8 *mac);
cbe61d8a 623bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
394cf0a1
S		 624
625/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 626void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
627u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
628void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 629 u32 ah_signal_type);
cbe61d8a 630void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 631u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
632void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
633bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
394cf0a1
S		 634 enum ath9k_ant_setting settings,
635 struct ath9k_channel *chan,
636 u8 *tx_chainmask, u8 *rx_chainmask,
637 u8 *antenna_cfgd);
638
639/* General Operation */
0caa7b14 640bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 641u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 642bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3
LR		 643u16 ath9k_hw_computetxtime(struct ath_hw *ah,
644 const struct ath_rate_table *rates,
394cf0a1 645 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 646void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 647 struct ath9k_channel *chan,
648 struct chan_centers *centers);
cbe61d8a
S		 649u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
650void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
651bool ath9k_hw_phy_disable(struct ath_hw *ah);
652bool ath9k_hw_disable(struct ath_hw *ah);
8fbff4b8 653void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
cbe61d8a
S		 654void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
655void ath9k_hw_setopmode(struct ath_hw *ah);
656void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 657void ath9k_hw_setbssidmask(struct ath_hw *ah);
658void ath9k_hw_write_associd(struct ath_hw *ah);
cbe61d8a
S		 659u64 ath9k_hw_gettsf64(struct ath_hw *ah);
660void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
661void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 662void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
cbe61d8a
S		 663bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
664void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
665void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
666void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 667 const struct ath9k_beacon_state *bs);
a91d75ae 668
9ecdef4b 669bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 670
93b1b37f 671void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
394cf0a1
S		 672
673/* Interrupt Handling */
cbe61d8a
S		 674bool ath9k_hw_intrpend(struct ath_hw *ah);
675bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
cbe61d8a 676enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
394cf0a1 677
ff155a45
VT		 678/* Generic hw timer primitives */
679struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
680 void (*trigger)(void *),
681 void (*overflow)(void *),
682 void *arg,
683 u8 timer_index);
684void ath_gen_timer_start(struct ath_hw *ah, struct ath_gen_timer *timer,
685 u32 timer_next, u32 timer_period);
686void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
687void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
688void ath_gen_timer_isr(struct ath_hw *hw);
1773912b 689u32 ath9k_hw_gettsf32(struct ath_hw *ah);
ff155a45 690
7b6840ab
VT		 691#define ATH_PCIE_CAP_LINK_CTRL 0x70
692#define ATH_PCIE_CAP_LINK_L0S 1
693#define ATH_PCIE_CAP_LINK_L1 2
694
f078f209 695#endif
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