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ath9k: Cleanup Powersave flags
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
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f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
c46917bb 33#include "../debug.h"
3a702e49 34
394cf0a1 35#define ATHEROS_VENDOR_ID 0x168c
7976b426 36
394cf0a1
S		 37#define AR5416_DEVID_PCI 0x0023
38#define AR5416_DEVID_PCIE 0x0024
39#define AR9160_DEVID_PCI 0x0027
40#define AR9280_DEVID_PCI 0x0029
41#define AR9280_DEVID_PCIE 0x002a
42#define AR9285_DEVID_PCIE 0x002b
7976b426 43
394cf0a1 44#define AR5416_AR9100_DEVID 0x000b
7976b426
LR		 45
46#define AR9271_USB 0x9271
47
394cf0a1
S		 48#define AR_SUBVENDOR_ID_NOG 0x0e11
49#define AR_SUBVENDOR_ID_NEW_A 0x7065
50#define AR5416_MAGIC 0x19641014
51
ac88b6ec
VN		 52#define AR5416_DEVID_AR9287_PCI 0x002D
53#define AR5416_DEVID_AR9287_PCIE 0x002E
54
fe12946e
VT		 55#define AR9280_COEX2WIRE_SUBSYSID 0x309b
56#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
57#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58
e3d01bfc
LR		 59#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60
cfe8cba9
LR		 61#define ATH_DEFAULT_NOISE_FLOOR -95
62
04658fba 63#define ATH9K_RSSI_BAD -128
990b70ab 64
394cf0a1 65/* Register read/write primitives */
9e4bffd2
LR		 66#define REG_WRITE(_ah, _reg, _val) \
67 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
68
69#define REG_READ(_ah, _reg) \
70 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
394cf0a1
S		 71
72#define SM(_v, _f) (((_v) << _f##_S) & _f)
73#define MS(_v, _f) (((_v) & _f) >> _f##_S)
74#define REG_RMW(_a, _r, _set, _clr) \
75 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
76#define REG_RMW_FIELD(_a, _r, _f, _v) \
77 REG_WRITE(_a, _r, \
78 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
79#define REG_SET_BIT(_a, _r, _f) \
80 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
81#define REG_CLR_BIT(_a, _r, _f) \
82 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 83
394cf0a1
S		 84#define DO_DELAY(x) do { \
85 if ((++(x) % 64) == 0) \
86 udelay(1); \
87 } while (0)
f078f209 88
394cf0a1
S		 89#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
90 int r; \
91 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
92 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
93 INI_RA((iniarray), r, (column))); \
94 DO_DELAY(regWr); \
95 } \
96 } while (0)
f078f209 97
394cf0a1
S		 98#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
99#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
100#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
101#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 102#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 103#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
104#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 105
394cf0a1
S		 106#define AR_GPIOD_MASK 0x00001FFF
107#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 108
394cf0a1 109#define BASE_ACTIVATE_DELAY 100
63a75b91 110#define RTC_PLL_SETTLE_DELAY 100
394cf0a1
S		 111#define COEF_SCALE_S 24
112#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 113
394cf0a1
S		 114#define ATH9K_ANTENNA0_CHAINMASK 0x1
115#define ATH9K_ANTENNA1_CHAINMASK 0x2
116
117#define ATH9K_NUM_DMA_DEBUG_REGS 8
118#define ATH9K_NUM_QUEUES 10
119
120#define MAX_RATE_POWER 63
0caa7b14 121#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 122#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 123#define AH_TIME_QUANTUM 10
124#define AR_KEYTABLE_SIZE 128
d8caa839 125#define POWER_UP_TIME 10000
394cf0a1
S		 126#define SPUR_RSSI_THRESH 40
127
128#define CAB_TIMEOUT_VAL 10
129#define BEACON_TIMEOUT_VAL 10
130#define MIN_BEACON_TIMEOUT_VAL 1
131#define SLEEP_SLOP 3
132
133#define INIT_CONFIG_STATUS 0x00000000
134#define INIT_RSSI_THR 0x00000700
135#define INIT_BCON_CNTRL_REG 0x00000000
136
137#define TU_TO_USEC(_tu) ((_tu) << 10)
138
139enum wireless_mode {
140 ATH9K_MODE_11A = 0,
b9b6e15a
LR		 141 ATH9K_MODE_11G,
142 ATH9K_MODE_11NA_HT20,
143 ATH9K_MODE_11NG_HT20,
144 ATH9K_MODE_11NA_HT40PLUS,
145 ATH9K_MODE_11NA_HT40MINUS,
146 ATH9K_MODE_11NG_HT40PLUS,
147 ATH9K_MODE_11NG_HT40MINUS,
148 ATH9K_MODE_MAX,
394cf0a1 149};
f078f209 150
394cf0a1 151enum ath9k_hw_caps {
bdbdf46d
S		 152 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
153 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
154 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
155 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
156 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
157 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
158 ATH9K_HW_CAP_VEOL = BIT(6),
159 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
160 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
161 ATH9K_HW_CAP_HT = BIT(9),
162 ATH9K_HW_CAP_GTT = BIT(10),
163 ATH9K_HW_CAP_FASTCC = BIT(11),
164 ATH9K_HW_CAP_RFSILENT = BIT(12),
165 ATH9K_HW_CAP_CST = BIT(13),
166 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
167 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
168 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
394cf0a1 169};
f078f209 170
394cf0a1
S		 171enum ath9k_capability_type {
172 ATH9K_CAP_CIPHER = 0,
173 ATH9K_CAP_TKIP_MIC,
174 ATH9K_CAP_TKIP_SPLIT,
394cf0a1
S		 175 ATH9K_CAP_DIVERSITY,
176 ATH9K_CAP_TXPOW,
394cf0a1 177 ATH9K_CAP_MCAST_KEYSRCH,
8bd1d07f 178 ATH9K_CAP_DS
394cf0a1 179};
f078f209 180
394cf0a1
S		 181struct ath9k_hw_capabilities {
182 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
183 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
184 u16 total_queues;
185 u16 keycache_size;
186 u16 low_5ghz_chan, high_5ghz_chan;
187 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 188 u16 rts_aggr_limit;
189 u8 tx_chainmask;
190 u8 rx_chainmask;
191 u16 tx_triglevel_max;
192 u16 reg_cap;
193 u8 num_gpio_pins;
194 u8 num_antcfg_2ghz;
195 u8 num_antcfg_5ghz;
196};
f078f209 197
394cf0a1
S		 198struct ath9k_ops_config {
199 int dma_beacon_response_time;
200 int sw_beacon_response_time;
201 int additional_swba_backoff;
202 int ack_6mb;
203 int cwm_ignore_extcca;
204 u8 pcie_powersave_enable;
394cf0a1
S		 205 u8 pcie_clock_req;
206 u32 pcie_waen;
394cf0a1
S		 207 u8 analog_shiftreg;
208 u8 ht_enable;
209 u32 ofdm_trig_low;
210 u32 ofdm_trig_high;
211 u32 cck_trig_high;
212 u32 cck_trig_low;
213 u32 enable_ani;
394cf0a1 214 int serialize_regmode;
0ce024cb 215 bool rx_intr_mitigation;
394cf0a1
S		 216#define SPUR_DISABLE 0
217#define SPUR_ENABLE_IOCTL 1
218#define SPUR_ENABLE_EEPROM 2
219#define AR_EEPROM_MODAL_SPURS 5
220#define AR_SPUR_5413_1 1640
221#define AR_SPUR_5413_2 1200
222#define AR_NO_SPUR 0x8000
223#define AR_BASE_FREQ_2GHZ 2300
224#define AR_BASE_FREQ_5GHZ 4900
225#define AR_SPUR_FEEQ_BOUND_HT40 19
226#define AR_SPUR_FEEQ_BOUND_HT20 10
227 int spurmode;
228 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 229 u8 max_txtrig_level;
394cf0a1 230};
f078f209 231
394cf0a1
S		 232enum ath9k_int {
233 ATH9K_INT_RX = 0x00000001,
234 ATH9K_INT_RXDESC = 0x00000002,
235 ATH9K_INT_RXNOFRM = 0x00000008,
236 ATH9K_INT_RXEOL = 0x00000010,
237 ATH9K_INT_RXORN = 0x00000020,
238 ATH9K_INT_TX = 0x00000040,
239 ATH9K_INT_TXDESC = 0x00000080,
240 ATH9K_INT_TIM_TIMER = 0x00000100,
241 ATH9K_INT_TXURN = 0x00000800,
242 ATH9K_INT_MIB = 0x00001000,
243 ATH9K_INT_RXPHY = 0x00004000,
244 ATH9K_INT_RXKCM = 0x00008000,
245 ATH9K_INT_SWBA = 0x00010000,
246 ATH9K_INT_BMISS = 0x00040000,
247 ATH9K_INT_BNR = 0x00100000,
248 ATH9K_INT_TIM = 0x00200000,
249 ATH9K_INT_DTIM = 0x00400000,
250 ATH9K_INT_DTIMSYNC = 0x00800000,
251 ATH9K_INT_GPIO = 0x01000000,
252 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 253 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 254 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 255 ATH9K_INT_CST = 0x10000000,
256 ATH9K_INT_GTT = 0x20000000,
257 ATH9K_INT_FATAL = 0x40000000,
258 ATH9K_INT_GLOBAL = 0x80000000,
259 ATH9K_INT_BMISC = ATH9K_INT_TIM |
260 ATH9K_INT_DTIM |
261 ATH9K_INT_DTIMSYNC |
4af9cf4f 262 ATH9K_INT_TSFOOR |
394cf0a1
S		 263 ATH9K_INT_CABEND,
264 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
265 ATH9K_INT_RXDESC |
266 ATH9K_INT_RXEOL |
267 ATH9K_INT_RXORN |
268 ATH9K_INT_TXURN |
269 ATH9K_INT_TXDESC |
270 ATH9K_INT_MIB |
271 ATH9K_INT_RXPHY |
272 ATH9K_INT_RXKCM |
273 ATH9K_INT_SWBA |
274 ATH9K_INT_BMISS |
275 ATH9K_INT_GPIO,
276 ATH9K_INT_NOCARD = 0xffffffff
277};
f078f209 278
394cf0a1
S		 279#define CHANNEL_CW_INT 0x00002
280#define CHANNEL_CCK 0x00020
281#define CHANNEL_OFDM 0x00040
282#define CHANNEL_2GHZ 0x00080
283#define CHANNEL_5GHZ 0x00100
284#define CHANNEL_PASSIVE 0x00200
285#define CHANNEL_DYN 0x00400
286#define CHANNEL_HALF 0x04000
287#define CHANNEL_QUARTER 0x08000
288#define CHANNEL_HT20 0x10000
289#define CHANNEL_HT40PLUS 0x20000
290#define CHANNEL_HT40MINUS 0x40000
291
394cf0a1
S		 292#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
293#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
294#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
295#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
296#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
297#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
298#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
299#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
300#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
301#define CHANNEL_ALL \
302 (CHANNEL_OFDM| \
303 CHANNEL_CCK| \
304 CHANNEL_2GHZ | \
305 CHANNEL_5GHZ | \
306 CHANNEL_HT20 | \
307 CHANNEL_HT40PLUS | \
308 CHANNEL_HT40MINUS)
309
310struct ath9k_channel {
311 struct ieee80211_channel *chan;
312 u16 channel;
313 u32 channelFlags;
314 u32 chanmode;
315 int32_t CalValid;
316 bool oneTimeCalsDone;
317 int8_t iCoff;
318 int8_t qCoff;
319 int16_t rawNoiseFloor;
320};
f078f209 321
394cf0a1
S		 322#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
323 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
324 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
325 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
326#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
327#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
328#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 329#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
330#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
331#define IS_CHAN_A_5MHZ_SPACED(_c) \
332 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
333 (((_c)->channel % 20) != 0) && \
334 (((_c)->channel % 10) != 0))
335
336/* These macros check chanmode and not channelFlags */
337#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
338#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
339 ((_c)->chanmode == CHANNEL_G_HT20))
340#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
341 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
342 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
343 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
344#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
345
346enum ath9k_power_mode {
347 ATH9K_PM_AWAKE = 0,
348 ATH9K_PM_FULL_SLEEP,
349 ATH9K_PM_NETWORK_SLEEP,
350 ATH9K_PM_UNDEFINED
351};
f078f209 352
394cf0a1
S		 353enum ath9k_tp_scale {
354 ATH9K_TP_SCALE_MAX = 0,
355 ATH9K_TP_SCALE_50,
356 ATH9K_TP_SCALE_25,
357 ATH9K_TP_SCALE_12,
358 ATH9K_TP_SCALE_MIN
359};
f078f209 360
394cf0a1
S		 361enum ser_reg_mode {
362 SER_REG_MODE_OFF = 0,
363 SER_REG_MODE_ON = 1,
364 SER_REG_MODE_AUTO = 2,
365};
f078f209 366
394cf0a1
S		 367struct ath9k_beacon_state {
368 u32 bs_nexttbtt;
369 u32 bs_nextdtim;
370 u32 bs_intval;
371#define ATH9K_BEACON_PERIOD 0x0000ffff
372#define ATH9K_BEACON_ENA 0x00800000
373#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 374#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 375 u32 bs_dtimperiod;
376 u16 bs_cfpperiod;
377 u16 bs_cfpmaxduration;
378 u32 bs_cfpnext;
379 u16 bs_timoffset;
380 u16 bs_bmissthreshold;
381 u32 bs_sleepduration;
4af9cf4f 382 u32 bs_tsfoor_threshold;
394cf0a1 383};
f078f209 384
394cf0a1
S		 385struct chan_centers {
386 u16 synth_center;
387 u16 ctl_center;
388 u16 ext_center;
389};
f078f209 390
394cf0a1
S		 391enum {
392 ATH9K_RESET_POWER_ON,
393 ATH9K_RESET_WARM,
394 ATH9K_RESET_COLD,
395};
f078f209 396
d535a42a
S		 397struct ath9k_hw_version {
398 u32 magic;
399 u16 devid;
400 u16 subvendorid;
401 u32 macVersion;
402 u16 macRev;
403 u16 phyRev;
404 u16 analog5GhzRev;
405 u16 analog2GhzRev;
aeac355d 406 u16 subsysid;
d535a42a 407};
394cf0a1 408
ff155a45
VT		 409/* Generic TSF timer definitions */
410
411#define ATH_MAX_GEN_TIMER 16
412
413#define AR_GENTMR_BIT(_index) (1 << (_index))
414
415/*
416 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
417 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
418 */
c90017dd 419#define debruijn32 0x077CB531U
ff155a45
VT		 420
421struct ath_gen_timer_configuration {
422 u32 next_addr;
423 u32 period_addr;
424 u32 mode_addr;
425 u32 mode_mask;
426};
427
428struct ath_gen_timer {
429 void (*trigger)(void *arg);
430 void (*overflow)(void *arg);
431 void *arg;
432 u8 index;
433};
434
435struct ath_gen_timer_table {
436 u32 gen_timer_index[32];
437 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
438 union {
439 unsigned long timer_bits;
440 u16 val;
441 } timer_mask;
442};
443
cbe61d8a 444struct ath_hw {
b002a4a9 445 struct ieee80211_hw *hw;
27c51f1a 446 struct ath_common common;
cbe61d8a 447 struct ath9k_hw_version hw_version;
2660b81a
S		 448 struct ath9k_ops_config config;
449 struct ath9k_hw_capabilities caps;
2660b81a
S		 450 struct ath9k_channel channels[38];
451 struct ath9k_channel *curchan;
394cf0a1 452
cbe61d8a
S		 453 union {
454 struct ar5416_eeprom_def def;
455 struct ar5416_eeprom_4k map4k;
475f5989 456 struct ar9287_eeprom map9287;
2660b81a 457 } eeprom;
f74df6fb 458 const struct eeprom_ops *eep_ops;
2660b81a 459 enum ath9k_eep_map eep_map;
cbe61d8a
S		 460
461 bool sw_mgmt_crypto;
2660b81a 462 bool is_pciexpress;
2660b81a
S		 463 u16 tx_trig_level;
464 u16 rfsilent;
465 u32 rfkill_gpio;
466 u32 rfkill_polarity;
cbe61d8a 467 u32 ah_flags;
394cf0a1 468
d7e7d229
LR		 469 bool htc_reset_init;
470
2660b81a
S		 471 enum nl80211_iftype opmode;
472 enum ath9k_power_mode power_mode;
f078f209 473
cbe61d8a 474 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
a13883b0 475 struct ath9k_pacal_info pacal_info;
2660b81a
S		 476 struct ar5416Stats stats;
477 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
478
479 int16_t curchan_rad_index;
480 u32 mask_reg;
481 u32 txok_interrupt_mask;
482 u32 txerr_interrupt_mask;
483 u32 txdesc_interrupt_mask;
484 u32 txeol_interrupt_mask;
485 u32 txurn_interrupt_mask;
486 bool chip_fullsleep;
487 u32 atim_window;
6a2b9e8c
S		 488
489 /* Calibration */
cbfe9468
S		 490 enum ath9k_cal_types supp_cals;
491 struct ath9k_cal_list iq_caldata;
492 struct ath9k_cal_list adcgain_caldata;
493 struct ath9k_cal_list adcdc_calinitdata;
494 struct ath9k_cal_list adcdc_caldata;
495 struct ath9k_cal_list *cal_list;
496 struct ath9k_cal_list *cal_list_last;
497 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 498#define totalPowerMeasI meas0.unsign
499#define totalPowerMeasQ meas1.unsign
500#define totalIqCorrMeas meas2.sign
501#define totalAdcIOddPhase meas0.unsign
502#define totalAdcIEvenPhase meas1.unsign
503#define totalAdcQOddPhase meas2.unsign
504#define totalAdcQEvenPhase meas3.unsign
505#define totalAdcDcOffsetIOddPhase meas0.sign
506#define totalAdcDcOffsetIEvenPhase meas1.sign
507#define totalAdcDcOffsetQOddPhase meas2.sign
508#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 509 union {
510 u32 unsign[AR5416_MAX_CHAINS];
511 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 512 } meas0;
f078f209
LR		 513 union {
514 u32 unsign[AR5416_MAX_CHAINS];
515 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 516 } meas1;
f078f209
LR		 517 union {
518 u32 unsign[AR5416_MAX_CHAINS];
519 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 520 } meas2;
f078f209
LR		 521 union {
522 u32 unsign[AR5416_MAX_CHAINS];
523 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 524 } meas3;
525 u16 cal_samples;
6a2b9e8c 526
2660b81a
S		 527 u32 sta_id1_defaults;
528 u32 misc_mode;
f078f209
LR		 529 enum {
530 AUTO_32KHZ,
531 USE_32KHZ,
532 DONT_USE_32KHZ,
2660b81a 533 } enable_32kHz_clock;
6a2b9e8c 534
e68a060b
LR		 535 /* Callback for radio frequency change */
536 int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
ae478cf6
LR		 537
538 /* Callback for baseband spur frequency */
539 void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
540 struct ath9k_channel *chan);
541
e68a060b 542 /* Used to program the radio on non single-chip devices */
2660b81a
S		 543 u32 *analogBank0Data;
544 u32 *analogBank1Data;
545 u32 *analogBank2Data;
546 u32 *analogBank3Data;
547 u32 *analogBank6Data;
548 u32 *analogBank6TPCData;
549 u32 *analogBank7Data;
550 u32 *addac5416_21;
551 u32 *bank6Temp;
552
553 int16_t txpower_indexoffset;
554 u32 beacon_interval;
555 u32 slottime;
556 u32 acktimeout;
557 u32 ctstimeout;
558 u32 globaltxtimeout;
6a2b9e8c
S		 559
560 /* ANI */
2660b81a 561 u32 proc_phyerr;
2660b81a
S		 562 u32 aniperiod;
563 struct ar5416AniState *curani;
564 struct ar5416AniState ani[255];
565 int totalSizeDesired[5];
566 int coarse_high[5];
567 int coarse_low[5];
568 int firpwr[5];
569 enum ath9k_ani_cmd ani_function;
570
af03abec 571 /* Bluetooth coexistance */
766ec4a9 572 struct ath_btcoex_hw btcoex_hw;
af03abec 573
2660b81a 574 u32 intr_txqs;
2660b81a
S		 575 u8 txchainmask;
576 u8 rxchainmask;
577
8bd1d07f
SB		 578 u32 originalGain[22];
579 int initPDADC;
580 int PDADCdelta;
08fc5c1b 581 u8 led_pin;
8bd1d07f 582
2660b81a
S		 583 struct ar5416IniArray iniModes;
584 struct ar5416IniArray iniCommon;
585 struct ar5416IniArray iniBank0;
586 struct ar5416IniArray iniBB_RfGain;
587 struct ar5416IniArray iniBank1;
588 struct ar5416IniArray iniBank2;
589 struct ar5416IniArray iniBank3;
590 struct ar5416IniArray iniBank6;
591 struct ar5416IniArray iniBank6TPC;
592 struct ar5416IniArray iniBank7;
593 struct ar5416IniArray iniAddac;
594 struct ar5416IniArray iniPcieSerdes;
595 struct ar5416IniArray iniModesAdditional;
596 struct ar5416IniArray iniModesRxGain;
597 struct ar5416IniArray iniModesTxGain;
8564328d 598 struct ar5416IniArray iniModes_9271_1_0_only;
193cd458
S		 599 struct ar5416IniArray iniCckfirNormal;
600 struct ar5416IniArray iniCckfirJapan2484;
ff155a45
VT		 601
602 u32 intr_gen_timer_trigger;
603 u32 intr_gen_timer_thresh;
604 struct ath_gen_timer_table hw_gen_timers;
f078f209 605};
f078f209 606
9e4bffd2
LR		 607static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
608{
609 return &ah->common;
610}
611
612static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
613{
614 return &(ath9k_hw_common(ah)->regulatory);
615}
616
f637cfd6 617/* Initialization, Detach, Reset */
394cf0a1 618const char *ath9k_hw_probe(u16 vendorid, u16 devid);
cbe61d8a 619void ath9k_hw_detach(struct ath_hw *ah);
f637cfd6 620int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 621int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
394cf0a1 622 bool bChannelChange);
a9a29ce6 623int ath9k_hw_fill_cap_info(struct ath_hw *ah);
cbe61d8a 624bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 625 u32 capability, u32 *result);
cbe61d8a 626bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1
S		 627 u32 capability, u32 setting, int *status);
628
629/* Key Cache Management */
cbe61d8a
S		 630bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
631bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
632bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
394cf0a1 633 const struct ath9k_keyval *k,
e0caf9ea 634 const u8 *mac);
cbe61d8a 635bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
394cf0a1
S		 636
637/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 638void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
639u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
640void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 641 u32 ah_signal_type);
cbe61d8a 642void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 643u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
644void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
394cf0a1
S		 645
646/* General Operation */
0caa7b14 647bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 648u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 649bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3 650u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 651 u8 phy, int kbps,
394cf0a1 652 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 653void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 654 struct ath9k_channel *chan,
655 struct chan_centers *centers);
cbe61d8a
S		 656u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
657void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
658bool ath9k_hw_phy_disable(struct ath_hw *ah);
659bool ath9k_hw_disable(struct ath_hw *ah);
8fbff4b8 660void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
cbe61d8a
S		 661void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
662void ath9k_hw_setopmode(struct ath_hw *ah);
663void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 664void ath9k_hw_setbssidmask(struct ath_hw *ah);
665void ath9k_hw_write_associd(struct ath_hw *ah);
cbe61d8a
S		 666u64 ath9k_hw_gettsf64(struct ath_hw *ah);
667void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
668void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 669void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
30cbd422 670u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
cbe61d8a 671bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
25c56eec 672void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 673void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
674void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 675 const struct ath9k_beacon_state *bs);
a91d75ae 676
9ecdef4b 677bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 678
93b1b37f 679void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
394cf0a1
S		 680
681/* Interrupt Handling */
cbe61d8a
S		 682bool ath9k_hw_intrpend(struct ath_hw *ah);
683bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
cbe61d8a 684enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
394cf0a1 685
ff155a45
VT		 686/* Generic hw timer primitives */
687struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
688 void (*trigger)(void *),
689 void (*overflow)(void *),
690 void *arg,
691 u8 timer_index);
cd9bf689
LR		 692void ath9k_hw_gen_timer_start(struct ath_hw *ah,
693 struct ath_gen_timer *timer,
694 u32 timer_next,
695 u32 timer_period);
696void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
697
ff155a45
VT		 698void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
699void ath_gen_timer_isr(struct ath_hw *hw);
1773912b 700u32 ath9k_hw_gettsf32(struct ath_hw *ah);
ff155a45 701
f934c4d9 702void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 703
7b6840ab
VT		 704#define ATH_PCIE_CAP_LINK_CTRL 0x70
705#define ATH_PCIE_CAP_LINK_L0S 1
706#define ATH_PCIE_CAP_LINK_L1 2
707
f078f209 708#endif
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