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[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
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f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
3a702e49 33
394cf0a1 34#define ATHEROS_VENDOR_ID 0x168c
7976b426 35
394cf0a1
S		 36#define AR5416_DEVID_PCI 0x0023
37#define AR5416_DEVID_PCIE 0x0024
38#define AR9160_DEVID_PCI 0x0027
39#define AR9280_DEVID_PCI 0x0029
40#define AR9280_DEVID_PCIE 0x002a
41#define AR9285_DEVID_PCIE 0x002b
5ffaf8a3 42#define AR2427_DEVID_PCIE 0x002c
db3cc53a
SB		 43#define AR9287_DEVID_PCI 0x002d
44#define AR9287_DEVID_PCIE 0x002e
45#define AR9300_DEVID_PCIE 0x0030
b99a7be4 46#define AR9300_DEVID_AR9340 0x0031
3050c914 47#define AR9300_DEVID_AR9485_PCIE 0x0032
5a63ef0f 48#define AR9300_DEVID_AR9580 0x0033
423e38e8 49#define AR9300_DEVID_AR9462 0x0034
03689301 50#define AR9300_DEVID_AR9330 0x0035
7976b426 51
394cf0a1 52#define AR5416_AR9100_DEVID 0x000b
7976b426 53
394cf0a1
S		 54#define AR_SUBVENDOR_ID_NOG 0x0e11
55#define AR_SUBVENDOR_ID_NEW_A 0x7065
56#define AR5416_MAGIC 0x19641014
57
fe12946e
VT		 58#define AR9280_COEX2WIRE_SUBSYSID 0x309b
59#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
60#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
61
e3d01bfc
LR		 62#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
63
cfe8cba9
LR		 64#define ATH_DEFAULT_NOISE_FLOOR -95
65
04658fba 66#define ATH9K_RSSI_BAD -128
990b70ab 67
cac4220b
FF		 68#define ATH9K_NUM_CHANNELS 38
69
394cf0a1 70/* Register read/write primitives */
9e4bffd2 71#define REG_WRITE(_ah, _reg, _val) \
f9f84e96 72 (_ah)->reg_ops.write((_ah), (_val), (_reg))
9e4bffd2
LR		 73
74#define REG_READ(_ah, _reg) \
f9f84e96 75 (_ah)->reg_ops.read((_ah), (_reg))
394cf0a1 76
09a525d3 77#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
f9f84e96 78 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
09a525d3 79
845e03c9
FF		 80#define REG_RMW(_ah, _reg, _set, _clr) \
81 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
82
20b3efd9
S		 83#define ENABLE_REGWRITE_BUFFER(_ah) \
84 do { \
f9f84e96
FF		 85 if ((_ah)->reg_ops.enable_write_buffer) \
86 (_ah)->reg_ops.enable_write_buffer((_ah)); \
20b3efd9
S		 87 } while (0)
88
20b3efd9
S		 89#define REGWRITE_BUFFER_FLUSH(_ah) \
90 do { \
f9f84e96
FF		 91 if ((_ah)->reg_ops.write_flush) \
92 (_ah)->reg_ops.write_flush((_ah)); \
20b3efd9
S		 93 } while (0)
94
26526202
RM		 95#define PR_EEP(_s, _val) \
96 do { \
97 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
98 _s, (_val)); \
99 } while (0)
100
394cf0a1
S		 101#define SM(_v, _f) (((_v) << _f##_S) & _f)
102#define MS(_v, _f) (((_v) & _f) >> _f##_S)
394cf0a1 103#define REG_RMW_FIELD(_a, _r, _f, _v) \
845e03c9 104 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
1547da37
LR		 105#define REG_READ_FIELD(_a, _r, _f) \
106 (((REG_READ(_a, _r) & _f) >> _f##_S))
394cf0a1 107#define REG_SET_BIT(_a, _r, _f) \
845e03c9 108 REG_RMW(_a, _r, (_f), 0)
394cf0a1 109#define REG_CLR_BIT(_a, _r, _f) \
845e03c9 110 REG_RMW(_a, _r, 0, (_f))
f078f209 111
e7fc6338
RM		 112#define DO_DELAY(x) do { \
113 if (((++(x) % 64) == 0) && \
114 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
115 != ATH_USB)) \
116 udelay(1); \
394cf0a1 117 } while (0)
f078f209 118
a9b6b256
FF		 119#define REG_WRITE_ARRAY(iniarray, column, regWr) \
120 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
f078f209 121
394cf0a1
S		 122#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
123#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
124#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
125#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 126#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 127#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
128#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 129
394cf0a1
S		 130#define AR_GPIOD_MASK 0x00001FFF
131#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 132
394cf0a1 133#define BASE_ACTIVATE_DELAY 100
0b488ac6 134#define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
394cf0a1
S		 135#define COEF_SCALE_S 24
136#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 137
394cf0a1
S		 138#define ATH9K_ANTENNA0_CHAINMASK 0x1
139#define ATH9K_ANTENNA1_CHAINMASK 0x2
140
141#define ATH9K_NUM_DMA_DEBUG_REGS 8
142#define ATH9K_NUM_QUEUES 10
143
144#define MAX_RATE_POWER 63
0caa7b14 145#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 146#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 147#define AH_TIME_QUANTUM 10
148#define AR_KEYTABLE_SIZE 128
d8caa839 149#define POWER_UP_TIME 10000
394cf0a1 150#define SPUR_RSSI_THRESH 40
331c5ea2
MSS		 151#define UPPER_5G_SUB_BAND_START 5700
152#define MID_5G_SUB_BAND_START 5400
394cf0a1
S		 153
154#define CAB_TIMEOUT_VAL 10
155#define BEACON_TIMEOUT_VAL 10
156#define MIN_BEACON_TIMEOUT_VAL 1
157#define SLEEP_SLOP 3
158
159#define INIT_CONFIG_STATUS 0x00000000
160#define INIT_RSSI_THR 0x00000700
161#define INIT_BCON_CNTRL_REG 0x00000000
162
163#define TU_TO_USEC(_tu) ((_tu) << 10)
164
ceb26445
VT		 165#define ATH9K_HW_RX_HP_QDEPTH 16
166#define ATH9K_HW_RX_LP_QDEPTH 128
167
0e44d48c
MSS		 168#define PAPRD_GAIN_TABLE_ENTRIES 32
169#define PAPRD_TABLE_SZ 24
170#define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
717f6bed 171
066dae93
FF		 172enum ath_hw_txq_subtype {
173 ATH_TXQ_AC_BE = 0,
174 ATH_TXQ_AC_BK = 1,
175 ATH_TXQ_AC_VI = 2,
176 ATH_TXQ_AC_VO = 3,
177};
178
13ce3e99
LR		 179enum ath_ini_subsys {
180 ATH_INI_PRE = 0,
181 ATH_INI_CORE,
182 ATH_INI_POST,
183 ATH_INI_NUM_SPLIT,
184};
185
394cf0a1 186enum ath9k_hw_caps {
364734fa
FF		 187 ATH9K_HW_CAP_HT = BIT(0),
188 ATH9K_HW_CAP_RFSILENT = BIT(1),
189 ATH9K_HW_CAP_CST = BIT(2),
364734fa
FF		 190 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
191 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
192 ATH9K_HW_CAP_EDMA = BIT(6),
193 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
194 ATH9K_HW_CAP_LDPC = BIT(8),
195 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
196 ATH9K_HW_CAP_SGI_20 = BIT(10),
197 ATH9K_HW_CAP_PAPRD = BIT(11),
198 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
d4659912
FF		 199 ATH9K_HW_CAP_2GHZ = BIT(13),
200 ATH9K_HW_CAP_5GHZ = BIT(14),
ea066d5a 201 ATH9K_HW_CAP_APM = BIT(15),
324c74ad 202 ATH9K_HW_CAP_RTT = BIT(16),
7dc181c2 203 ATH9K_HW_CAP_MCI = BIT(17),
394cf0a1 204};
f078f209 205
394cf0a1
S		 206struct ath9k_hw_capabilities {
207 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
394cf0a1
S		 208 u16 rts_aggr_limit;
209 u8 tx_chainmask;
210 u8 rx_chainmask;
47c80de6
VT		 211 u8 max_txchains;
212 u8 max_rxchains;
394cf0a1 213 u8 num_gpio_pins;
ceb26445
VT		 214 u8 rx_hp_qdepth;
215 u8 rx_lp_qdepth;
216 u8 rx_status_len;
162c3be3 217 u8 tx_desc_len;
5088c2f1 218 u8 txs_len;
8060e169
VT		 219 u16 pcie_lcr_offset;
220 bool pcie_lcr_extsync_en;
394cf0a1 221};
f078f209 222
394cf0a1
S		 223struct ath9k_ops_config {
224 int dma_beacon_response_time;
225 int sw_beacon_response_time;
226 int additional_swba_backoff;
227 int ack_6mb;
41f3e54d 228 u32 cwm_ignore_extcca;
6a0ec30a 229 bool pcieSerDesWrite;
394cf0a1
S		 230 u8 pcie_clock_req;
231 u32 pcie_waen;
394cf0a1 232 u8 analog_shiftreg;
6f481010 233 u8 paprd_disable;
394cf0a1
S		 234 u32 ofdm_trig_low;
235 u32 ofdm_trig_high;
236 u32 cck_trig_high;
237 u32 cck_trig_low;
238 u32 enable_ani;
394cf0a1 239 int serialize_regmode;
0ce024cb 240 bool rx_intr_mitigation;
55e82df4 241 bool tx_intr_mitigation;
394cf0a1
S		 242#define SPUR_DISABLE 0
243#define SPUR_ENABLE_IOCTL 1
244#define SPUR_ENABLE_EEPROM 2
394cf0a1
S		 245#define AR_SPUR_5413_1 1640
246#define AR_SPUR_5413_2 1200
247#define AR_NO_SPUR 0x8000
248#define AR_BASE_FREQ_2GHZ 2300
249#define AR_BASE_FREQ_5GHZ 4900
250#define AR_SPUR_FEEQ_BOUND_HT40 19
251#define AR_SPUR_FEEQ_BOUND_HT20 10
252 int spurmode;
253 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 254 u8 max_txtrig_level;
e36b27af 255 u16 ani_poll_interval; /* ANI poll interval in ms */
394cf0a1 256};
f078f209 257
394cf0a1
S		 258enum ath9k_int {
259 ATH9K_INT_RX = 0x00000001,
260 ATH9K_INT_RXDESC = 0x00000002,
b5c80475
FF		 261 ATH9K_INT_RXHP = 0x00000001,
262 ATH9K_INT_RXLP = 0x00000002,
394cf0a1
S		 263 ATH9K_INT_RXNOFRM = 0x00000008,
264 ATH9K_INT_RXEOL = 0x00000010,
265 ATH9K_INT_RXORN = 0x00000020,
266 ATH9K_INT_TX = 0x00000040,
267 ATH9K_INT_TXDESC = 0x00000080,
268 ATH9K_INT_TIM_TIMER = 0x00000100,
aea702b7 269 ATH9K_INT_BB_WATCHDOG = 0x00000400,
394cf0a1
S		 270 ATH9K_INT_TXURN = 0x00000800,
271 ATH9K_INT_MIB = 0x00001000,
272 ATH9K_INT_RXPHY = 0x00004000,
273 ATH9K_INT_RXKCM = 0x00008000,
274 ATH9K_INT_SWBA = 0x00010000,
275 ATH9K_INT_BMISS = 0x00040000,
276 ATH9K_INT_BNR = 0x00100000,
277 ATH9K_INT_TIM = 0x00200000,
278 ATH9K_INT_DTIM = 0x00400000,
279 ATH9K_INT_DTIMSYNC = 0x00800000,
280 ATH9K_INT_GPIO = 0x01000000,
281 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 282 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 283 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 284 ATH9K_INT_CST = 0x10000000,
285 ATH9K_INT_GTT = 0x20000000,
286 ATH9K_INT_FATAL = 0x40000000,
287 ATH9K_INT_GLOBAL = 0x80000000,
288 ATH9K_INT_BMISC = ATH9K_INT_TIM |
289 ATH9K_INT_DTIM |
290 ATH9K_INT_DTIMSYNC |
4af9cf4f 291 ATH9K_INT_TSFOOR |
394cf0a1
S		 292 ATH9K_INT_CABEND,
293 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
294 ATH9K_INT_RXDESC |
295 ATH9K_INT_RXEOL |
296 ATH9K_INT_RXORN |
297 ATH9K_INT_TXURN |
298 ATH9K_INT_TXDESC |
299 ATH9K_INT_MIB |
300 ATH9K_INT_RXPHY |
301 ATH9K_INT_RXKCM |
302 ATH9K_INT_SWBA |
303 ATH9K_INT_BMISS |
304 ATH9K_INT_GPIO,
305 ATH9K_INT_NOCARD = 0xffffffff
306};
f078f209 307
394cf0a1
S		 308#define CHANNEL_CW_INT 0x00002
309#define CHANNEL_CCK 0x00020
310#define CHANNEL_OFDM 0x00040
311#define CHANNEL_2GHZ 0x00080
312#define CHANNEL_5GHZ 0x00100
313#define CHANNEL_PASSIVE 0x00200
314#define CHANNEL_DYN 0x00400
315#define CHANNEL_HALF 0x04000
316#define CHANNEL_QUARTER 0x08000
317#define CHANNEL_HT20 0x10000
318#define CHANNEL_HT40PLUS 0x20000
319#define CHANNEL_HT40MINUS 0x40000
320
394cf0a1
S		 321#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
322#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
323#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
324#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
325#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
326#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
327#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
328#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
329#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
330#define CHANNEL_ALL \
331 (CHANNEL_OFDM| \
332 CHANNEL_CCK| \
333 CHANNEL_2GHZ | \
334 CHANNEL_5GHZ | \
335 CHANNEL_HT20 | \
336 CHANNEL_HT40PLUS | \
337 CHANNEL_HT40MINUS)
338
324c74ad
RM		 339#define MAX_RTT_TABLE_ENTRY 6
340#define RTT_HIST_MAX 3
341struct ath9k_rtt_hist {
342 u32 table[AR9300_MAX_CHAINS][RTT_HIST_MAX][MAX_RTT_TABLE_ENTRY];
343 u8 num_readings;
344};
345
5f0c04ea 346#define MAX_IQCAL_MEASUREMENT 8
77a5a664 347#define MAX_CL_TAB_ENTRY 16
5f0c04ea 348
20bd2a09 349struct ath9k_hw_cal_data {
394cf0a1
S		 350 u16 channel;
351 u32 channelFlags;
394cf0a1 352 int32_t CalValid;
394cf0a1
S		 353 int8_t iCoff;
354 int8_t qCoff;
717f6bed 355 bool paprd_done;
4254bc1c 356 bool nfcal_pending;
70cf1533 357 bool nfcal_interference;
5f0c04ea 358 bool done_txiqcal_once;
77a5a664 359 bool done_txclcal_once;
717f6bed
FF		 360 u16 small_signal_gain[AR9300_MAX_CHAINS];
361 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
5f0c04ea
RM		 362 u32 num_measures[AR9300_MAX_CHAINS];
363 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
77a5a664 364 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
20bd2a09 365 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
324c74ad 366 struct ath9k_rtt_hist rtt_hist;
20bd2a09
FF		 367};
368
369struct ath9k_channel {
370 struct ieee80211_channel *chan;
093115b7 371 struct ar5416AniState ani;
20bd2a09
FF		 372 u16 channel;
373 u32 channelFlags;
374 u32 chanmode;
d9891c78 375 s16 noisefloor;
394cf0a1 376};
f078f209 377
394cf0a1
S		 378#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
379 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
380 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
381 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
382#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
383#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
384#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 385#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
386#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
6b42e8d0 387#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
394cf0a1 388 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
6b42e8d0 389 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
394cf0a1
S		 390
391/* These macros check chanmode and not channelFlags */
392#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
393#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
394 ((_c)->chanmode == CHANNEL_G_HT20))
395#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
396 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
397 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
398 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
399#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
400
401enum ath9k_power_mode {
402 ATH9K_PM_AWAKE = 0,
403 ATH9K_PM_FULL_SLEEP,
404 ATH9K_PM_NETWORK_SLEEP,
405 ATH9K_PM_UNDEFINED
406};
f078f209 407
394cf0a1
S		 408enum ser_reg_mode {
409 SER_REG_MODE_OFF = 0,
410 SER_REG_MODE_ON = 1,
411 SER_REG_MODE_AUTO = 2,
412};
f078f209 413
ad7b8060
VT		 414enum ath9k_rx_qtype {
415 ATH9K_RX_QUEUE_HP,
416 ATH9K_RX_QUEUE_LP,
417 ATH9K_RX_QUEUE_MAX,
418};
419
7dc181c2
RM		 420enum ath_mci_gpm_coex_profile_type {
421 MCI_GPM_COEX_PROFILE_UNKNOWN,
422 MCI_GPM_COEX_PROFILE_RFCOMM,
423 MCI_GPM_COEX_PROFILE_A2DP,
424 MCI_GPM_COEX_PROFILE_HID,
425 MCI_GPM_COEX_PROFILE_BNEP,
426 MCI_GPM_COEX_PROFILE_VOICE,
427 MCI_GPM_COEX_PROFILE_MAX
428};
429
394cf0a1
S		 430struct ath9k_beacon_state {
431 u32 bs_nexttbtt;
432 u32 bs_nextdtim;
433 u32 bs_intval;
4af9cf4f 434#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 435 u32 bs_dtimperiod;
436 u16 bs_cfpperiod;
437 u16 bs_cfpmaxduration;
438 u32 bs_cfpnext;
439 u16 bs_timoffset;
440 u16 bs_bmissthreshold;
441 u32 bs_sleepduration;
4af9cf4f 442 u32 bs_tsfoor_threshold;
394cf0a1 443};
f078f209 444
394cf0a1
S		 445struct chan_centers {
446 u16 synth_center;
447 u16 ctl_center;
448 u16 ext_center;
449};
f078f209 450
394cf0a1
S		 451enum {
452 ATH9K_RESET_POWER_ON,
453 ATH9K_RESET_WARM,
454 ATH9K_RESET_COLD,
455};
f078f209 456
d535a42a
S		 457struct ath9k_hw_version {
458 u32 magic;
459 u16 devid;
460 u16 subvendorid;
461 u32 macVersion;
462 u16 macRev;
463 u16 phyRev;
464 u16 analog5GhzRev;
465 u16 analog2GhzRev;
0b5ead91 466 enum ath_usb_dev usbdev;
d535a42a 467};
394cf0a1 468
ff155a45
VT		 469/* Generic TSF timer definitions */
470
471#define ATH_MAX_GEN_TIMER 16
472
473#define AR_GENTMR_BIT(_index) (1 << (_index))
474
475/*
77c2061d 476 * Using de Bruijin sequence to look up 1's index in a 32 bit number
ff155a45
VT		 477 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
478 */
c90017dd 479#define debruijn32 0x077CB531U
ff155a45
VT		 480
481struct ath_gen_timer_configuration {
482 u32 next_addr;
483 u32 period_addr;
484 u32 mode_addr;
485 u32 mode_mask;
486};
487
488struct ath_gen_timer {
489 void (*trigger)(void *arg);
490 void (*overflow)(void *arg);
491 void *arg;
492 u8 index;
493};
494
495struct ath_gen_timer_table {
496 u32 gen_timer_index[32];
497 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
498 union {
499 unsigned long timer_bits;
500 u16 val;
501 } timer_mask;
502};
503
21cc630f
VT		 504struct ath_hw_antcomb_conf {
505 u8 main_lna_conf;
506 u8 alt_lna_conf;
507 u8 fast_div_bias;
c6ba9feb
MSS		 508 u8 main_gaintb;
509 u8 alt_gaintb;
510 int lna1_lna2_delta;
8afbcc8b 511 u8 div_group;
21cc630f
VT		 512};
513
4e8c14e9
FF		 514/**
515 * struct ath_hw_radar_conf - radar detection initialization parameters
516 *
517 * @pulse_inband: threshold for checking the ratio of in-band power
518 * to total power for short radar pulses (half dB steps)
519 * @pulse_inband_step: threshold for checking an in-band power to total
520 * power ratio increase for short radar pulses (half dB steps)
521 * @pulse_height: threshold for detecting the beginning of a short
522 * radar pulse (dB step)
523 * @pulse_rssi: threshold for detecting if a short radar pulse is
524 * gone (dB step)
525 * @pulse_maxlen: maximum pulse length (0.8 us steps)
526 *
527 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
528 * @radar_inband: threshold for checking the ratio of in-band power
529 * to total power for long radar pulses (half dB steps)
530 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
531 *
532 * @ext_channel: enable extension channel radar detection
533 */
534struct ath_hw_radar_conf {
535 unsigned int pulse_inband;
536 unsigned int pulse_inband_step;
537 unsigned int pulse_height;
538 unsigned int pulse_rssi;
539 unsigned int pulse_maxlen;
540
541 unsigned int radar_rssi;
542 unsigned int radar_inband;
543 int fir_power;
544
545 bool ext_channel;
546};
547
d70357d5
LR		 548/**
549 * struct ath_hw_private_ops - callbacks used internally by hardware code
550 *
551 * This structure contains private callbacks designed to only be used internally
552 * by the hardware core.
553 *
795f5e2c
LR		 554 * @init_cal_settings: setup types of calibrations supported
555 * @init_cal: starts actual calibration
556 *
d70357d5 557 * @init_mode_regs: Initializes mode registers
991312d8 558 * @init_mode_gain_regs: Initialize TX/RX gain registers
8fe65368
LR		 559 *
560 * @rf_set_freq: change frequency
561 * @spur_mitigate_freq: spur mitigation
562 * @rf_alloc_ext_banks:
563 * @rf_free_ext_banks:
564 * @set_rf_regs:
64773964
LR		 565 * @compute_pll_control: compute the PLL control value to use for
566 * AR_RTC_PLL_CONTROL for a given channel
795f5e2c
LR		 567 * @setup_calibration: set up calibration
568 * @iscal_supported: used to query if a type of calibration is supported
ac0bb767 569 *
e36b27af
LR		 570 * @ani_cache_ini_regs: cache the values for ANI from the initial
571 * register settings through the register initialization.
d70357d5
LR		 572 */
573struct ath_hw_private_ops {
795f5e2c 574 /* Calibration ops */
d70357d5 575 void (*init_cal_settings)(struct ath_hw *ah);
795f5e2c
LR		 576 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
577
d70357d5 578 void (*init_mode_regs)(struct ath_hw *ah);
991312d8 579 void (*init_mode_gain_regs)(struct ath_hw *ah);
795f5e2c
LR		 580 void (*setup_calibration)(struct ath_hw *ah,
581 struct ath9k_cal_list *currCal);
8fe65368
LR		 582
583 /* PHY ops */
584 int (*rf_set_freq)(struct ath_hw *ah,
585 struct ath9k_channel *chan);
586 void (*spur_mitigate_freq)(struct ath_hw *ah,
587 struct ath9k_channel *chan);
588 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
589 void (*rf_free_ext_banks)(struct ath_hw *ah);
590 bool (*set_rf_regs)(struct ath_hw *ah,
591 struct ath9k_channel *chan,
592 u16 modesIndex);
593 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
594 void (*init_bb)(struct ath_hw *ah,
595 struct ath9k_channel *chan);
596 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
597 void (*olc_init)(struct ath_hw *ah);
598 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
599 void (*mark_phy_inactive)(struct ath_hw *ah);
600 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
601 bool (*rfbus_req)(struct ath_hw *ah);
602 void (*rfbus_done)(struct ath_hw *ah);
8fe65368 603 void (*restore_chainmask)(struct ath_hw *ah);
64773964
LR		 604 u32 (*compute_pll_control)(struct ath_hw *ah,
605 struct ath9k_channel *chan);
c16fcb49
FF		 606 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
607 int param);
641d9921 608 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
4e8c14e9
FF		 609 void (*set_radar_params)(struct ath_hw *ah,
610 struct ath_hw_radar_conf *conf);
5f0c04ea
RM		 611 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
612 u8 *ini_reloaded);
ac0bb767
LR		 613
614 /* ANI */
e36b27af 615 void (*ani_cache_ini_regs)(struct ath_hw *ah);
d70357d5
LR		 616};
617
618/**
619 * struct ath_hw_ops - callbacks used by hardware code and driver code
620 *
621 * This structure contains callbacks designed to to be used internally by
622 * hardware code and also by the lower level driver.
623 *
624 * @config_pci_powersave:
795f5e2c 625 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
d70357d5
LR		 626 */
627struct ath_hw_ops {
628 void (*config_pci_powersave)(struct ath_hw *ah,
84c87dc8 629 bool power_off);
cee1f625 630 void (*rx_enable)(struct ath_hw *ah);
87d5efbb 631 void (*set_desc_link)(void *ds, u32 link);
795f5e2c
LR		 632 bool (*calibrate)(struct ath_hw *ah,
633 struct ath9k_channel *chan,
634 u8 rxchainmask,
635 bool longcal);
55e82df4 636 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
2b63a41d
FF		 637 void (*set_txdesc)(struct ath_hw *ah, void *ds,
638 struct ath_tx_info *i);
cc610ac0
VT		 639 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
640 struct ath_tx_status *ts);
69de3721
MSS		 641 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
642 struct ath_hw_antcomb_conf *antconf);
643 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
644 struct ath_hw_antcomb_conf *antconf);
645
d70357d5
LR		 646};
647
f2552e28
FF		 648struct ath_nf_limits {
649 s16 max;
650 s16 min;
651 s16 nominal;
652};
653
8ad74c4d
RM		 654enum ath_cal_list {
655 TX_IQ_CAL = BIT(0),
656 TX_IQ_ON_AGC_CAL = BIT(1),
657 TX_CL_CAL = BIT(2),
658};
659
97dcec57
SM		 660/* ah_flags */
661#define AH_USE_EEPROM 0x1
662#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
a126ff51 663#define AH_FASTCC 0x4
97dcec57 664
cbe61d8a 665struct ath_hw {
f9f84e96
FF		 666 struct ath_ops reg_ops;
667
b002a4a9 668 struct ieee80211_hw *hw;
27c51f1a 669 struct ath_common common;
cbe61d8a 670 struct ath9k_hw_version hw_version;
2660b81a
S		 671 struct ath9k_ops_config config;
672 struct ath9k_hw_capabilities caps;
cac4220b 673 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
2660b81a 674 struct ath9k_channel *curchan;
394cf0a1 675
cbe61d8a
S		 676 union {
677 struct ar5416_eeprom_def def;
678 struct ar5416_eeprom_4k map4k;
475f5989 679 struct ar9287_eeprom map9287;
15c9ee7a 680 struct ar9300_eeprom ar9300_eep;
2660b81a 681 } eeprom;
f74df6fb 682 const struct eeprom_ops *eep_ops;
cbe61d8a
S		 683
684 bool sw_mgmt_crypto;
2660b81a 685 bool is_pciexpress;
d4930086 686 bool aspm_enabled;
5f841b41 687 bool is_monitoring;
2eb46d9b 688 bool need_an_top2_fixup;
2660b81a 689 u16 tx_trig_level;
f2552e28 690
bbacee13 691 u32 nf_regs[6];
f2552e28
FF		 692 struct ath_nf_limits nf_2g;
693 struct ath_nf_limits nf_5g;
2660b81a
S		 694 u16 rfsilent;
695 u32 rfkill_gpio;
696 u32 rfkill_polarity;
cbe61d8a 697 u32 ah_flags;
394cf0a1 698
d7e7d229
LR		 699 bool htc_reset_init;
700
2660b81a
S		 701 enum nl80211_iftype opmode;
702 enum ath9k_power_mode power_mode;
f078f209 703
f23fba49 704 s8 noise;
20bd2a09 705 struct ath9k_hw_cal_data *caldata;
a13883b0 706 struct ath9k_pacal_info pacal_info;
2660b81a
S		 707 struct ar5416Stats stats;
708 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
709
710 int16_t curchan_rad_index;
3069168c 711 enum ath9k_int imask;
74bad5cb 712 u32 imrs2_reg;
2660b81a
S		 713 u32 txok_interrupt_mask;
714 u32 txerr_interrupt_mask;
715 u32 txdesc_interrupt_mask;
716 u32 txeol_interrupt_mask;
717 u32 txurn_interrupt_mask;
e8fe7336 718 atomic_t intr_ref_cnt;
2660b81a
S		 719 bool chip_fullsleep;
720 u32 atim_window;
5f0c04ea 721 u32 modes_index;
6a2b9e8c
S		 722
723 /* Calibration */
6497827f 724 u32 supp_cals;
cbfe9468
S		 725 struct ath9k_cal_list iq_caldata;
726 struct ath9k_cal_list adcgain_caldata;
cbfe9468 727 struct ath9k_cal_list adcdc_caldata;
df23acaa 728 struct ath9k_cal_list tempCompCalData;
cbfe9468
S		 729 struct ath9k_cal_list *cal_list;
730 struct ath9k_cal_list *cal_list_last;
731 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 732#define totalPowerMeasI meas0.unsign
733#define totalPowerMeasQ meas1.unsign
734#define totalIqCorrMeas meas2.sign
735#define totalAdcIOddPhase meas0.unsign
736#define totalAdcIEvenPhase meas1.unsign
737#define totalAdcQOddPhase meas2.unsign
738#define totalAdcQEvenPhase meas3.unsign
739#define totalAdcDcOffsetIOddPhase meas0.sign
740#define totalAdcDcOffsetIEvenPhase meas1.sign
741#define totalAdcDcOffsetQOddPhase meas2.sign
742#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 743 union {
744 u32 unsign[AR5416_MAX_CHAINS];
745 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 746 } meas0;
f078f209
LR		 747 union {
748 u32 unsign[AR5416_MAX_CHAINS];
749 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 750 } meas1;
f078f209
LR		 751 union {
752 u32 unsign[AR5416_MAX_CHAINS];
753 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 754 } meas2;
f078f209
LR		 755 union {
756 u32 unsign[AR5416_MAX_CHAINS];
757 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 758 } meas3;
759 u16 cal_samples;
8ad74c4d 760 u8 enabled_cals;
6a2b9e8c 761
2660b81a
S		 762 u32 sta_id1_defaults;
763 u32 misc_mode;
f078f209
LR		 764 enum {
765 AUTO_32KHZ,
766 USE_32KHZ,
767 DONT_USE_32KHZ,
2660b81a 768 } enable_32kHz_clock;
6a2b9e8c 769
d70357d5
LR		 770 /* Private to hardware code */
771 struct ath_hw_private_ops private_ops;
772 /* Accessed by the lower level driver */
773 struct ath_hw_ops ops;
774
e68a060b 775 /* Used to program the radio on non single-chip devices */
2660b81a
S		 776 u32 *analogBank0Data;
777 u32 *analogBank1Data;
778 u32 *analogBank2Data;
779 u32 *analogBank3Data;
780 u32 *analogBank6Data;
781 u32 *analogBank6TPCData;
782 u32 *analogBank7Data;
783 u32 *addac5416_21;
784 u32 *bank6Temp;
785
597a94b3 786 u8 txpower_limit;
e239d859 787 int coverage_class;
2660b81a 788 u32 slottime;
2660b81a 789 u32 globaltxtimeout;
6a2b9e8c
S		 790
791 /* ANI */
2660b81a 792 u32 proc_phyerr;
2660b81a 793 u32 aniperiod;
2660b81a
S		 794 int totalSizeDesired[5];
795 int coarse_high[5];
796 int coarse_low[5];
797 int firpwr[5];
798 enum ath9k_ani_cmd ani_function;
799
af03abec 800 /* Bluetooth coexistance */
766ec4a9 801 struct ath_btcoex_hw btcoex_hw;
af03abec 802
2660b81a 803 u32 intr_txqs;
2660b81a
S		 804 u8 txchainmask;
805 u8 rxchainmask;
806
c5d0855a
FF		 807 struct ath_hw_radar_conf radar_conf;
808
8bd1d07f
SB		 809 u32 originalGain[22];
810 int initPDADC;
811 int PDADCdelta;
6de66dd9 812 int led_pin;
691680b8
FF		 813 u32 gpio_mask;
814 u32 gpio_val;
8bd1d07f 815
2660b81a
S		 816 struct ar5416IniArray iniModes;
817 struct ar5416IniArray iniCommon;
818 struct ar5416IniArray iniBank0;
819 struct ar5416IniArray iniBB_RfGain;
820 struct ar5416IniArray iniBank1;
821 struct ar5416IniArray iniBank2;
822 struct ar5416IniArray iniBank3;
823 struct ar5416IniArray iniBank6;
824 struct ar5416IniArray iniBank6TPC;
825 struct ar5416IniArray iniBank7;
826 struct ar5416IniArray iniAddac;
827 struct ar5416IniArray iniPcieSerdes;
13ce3e99 828 struct ar5416IniArray iniPcieSerdesLowPower;
2660b81a 829 struct ar5416IniArray iniModesAdditional;
d89baac8 830 struct ar5416IniArray iniModesAdditional_40M;
2660b81a
S		 831 struct ar5416IniArray iniModesRxGain;
832 struct ar5416IniArray iniModesTxGain;
8564328d 833 struct ar5416IniArray iniModes_9271_1_0_only;
193cd458
S		 834 struct ar5416IniArray iniCckfirNormal;
835 struct ar5416IniArray iniCckfirJapan2484;
ce407afc 836 struct ar5416IniArray ini_japan2484;
70807e99
S		 837 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
838 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
839 struct ar5416IniArray iniModes_9271_ANI_reg;
840 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
841 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
ce407afc
SB		 842 struct ar5416IniArray ini_radio_post_sys2ant;
843 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR;
ff155a45 844
13ce3e99
LR		 845 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
846 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
847 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
848 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
849
ff155a45
VT		 850 u32 intr_gen_timer_trigger;
851 u32 intr_gen_timer_thresh;
852 struct ath_gen_timer_table hw_gen_timers;
744d4025
VT		 853
854 struct ar9003_txs *ts_ring;
855 void *ts_start;
856 u32 ts_paddr_start;
857 u32 ts_paddr_end;
858 u16 ts_tail;
859 u8 ts_size;
aea702b7
LR		 860
861 u32 bb_watchdog_last_status;
862 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
51ac8cbb 863 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
717f6bed 864
1bf38661
FF		 865 unsigned int paprd_target_power;
866 unsigned int paprd_training_power;
7072bf62 867 unsigned int paprd_ratemask;
f1a8abb0 868 unsigned int paprd_ratemask_ht40;
45ef6a0b 869 bool paprd_table_write_done;
717f6bed
FF		 870 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
871 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
9a658d2b
LR		 872 /*
873 * Store the permanent value of Reg 0x4004in WARegVal
874 * so we dont have to R/M/W. We should not be reading
875 * this register when in sleep states.
876 */
877 u32 WARegVal;
6ee63f55
SB		 878
879 /* Enterprise mode cap */
880 u32 ent_mode;
f2f5f2a1
VT		 881
882 bool is_clk_25mhz;
3762561a 883 int (*get_mac_revision)(void);
7d95847c 884 int (*external_reset)(void);
f078f209 885};
f078f209 886
0cb9e06b
FF		 887struct ath_bus_ops {
888 enum ath_bus_type ath_bus_type;
889 void (*read_cachesize)(struct ath_common *common, int *csz);
890 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
891 void (*bt_coex_prep)(struct ath_common *common);
892 void (*extn_synch_en)(struct ath_common *common);
d4930086 893 void (*aspm_init)(struct ath_common *common);
0cb9e06b
FF		 894};
895
9e4bffd2
LR		 896static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
897{
898 return &ah->common;
899}
900
901static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
902{
903 return &(ath9k_hw_common(ah)->regulatory);
904}
905
d70357d5
LR		 906static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
907{
908 return &ah->private_ops;
909}
910
911static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
912{
913 return &ah->ops;
914}
915
895ad7eb
VT		 916static inline u8 get_streams(int mask)
917{
918 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
919}
920
f637cfd6 921/* Initialization, Detach, Reset */
394cf0a1 922const char *ath9k_hw_probe(u16 vendorid, u16 devid);
285f2dda 923void ath9k_hw_deinit(struct ath_hw *ah);
f637cfd6 924int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 925int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 926 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
a9a29ce6 927int ath9k_hw_fill_cap_info(struct ath_hw *ah);
8fe65368 928u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
394cf0a1 929
394cf0a1 930/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 931void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
932u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
933void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 934 u32 ah_signal_type);
cbe61d8a 935void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 936u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
937void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
394cf0a1
S		 938
939/* General Operation */
0caa7b14 940bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
a9b6b256
FF		 941void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
942 int column, unsigned int *writecnt);
394cf0a1 943u32 ath9k_hw_reverse_bits(u32 val, u32 n);
4f0fc7c3 944u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 945 u8 phy, int kbps,
394cf0a1 946 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 947void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 948 struct ath9k_channel *chan,
949 struct chan_centers *centers);
cbe61d8a
S		 950u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
951void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
952bool ath9k_hw_phy_disable(struct ath_hw *ah);
953bool ath9k_hw_disable(struct ath_hw *ah);
de40f316 954void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
cbe61d8a
S		 955void ath9k_hw_setopmode(struct ath_hw *ah);
956void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 957void ath9k_hw_setbssidmask(struct ath_hw *ah);
958void ath9k_hw_write_associd(struct ath_hw *ah);
dd347f2f 959u32 ath9k_hw_gettsf32(struct ath_hw *ah);
cbe61d8a
S		 960u64 ath9k_hw_gettsf64(struct ath_hw *ah);
961void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
962void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 963void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
0005baf4 964void ath9k_hw_init_global_settings(struct ath_hw *ah);
b84628eb 965u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
25c56eec 966void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 967void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
968void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 969 const struct ath9k_beacon_state *bs);
c9c99e5e 970bool ath9k_hw_check_alive(struct ath_hw *ah);
a91d75ae 971
9ecdef4b 972bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 973
ff155a45
VT		 974/* Generic hw timer primitives */
975struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
976 void (*trigger)(void *),
977 void (*overflow)(void *),
978 void *arg,
979 u8 timer_index);
cd9bf689
LR		 980void ath9k_hw_gen_timer_start(struct ath_hw *ah,
981 struct ath_gen_timer *timer,
982 u32 timer_next,
983 u32 timer_period);
984void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
985
ff155a45
VT		 986void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
987void ath_gen_timer_isr(struct ath_hw *hw);
988
f934c4d9 989void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 990
05020d23
S		 991/* HTC */
992void ath9k_hw_htc_resetinit(struct ath_hw *ah);
993
8fe65368
LR		 994/* PHY */
995void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
996 u32 *coef_mantissa, u32 *coef_exponent);
ca2c68cc 997void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan);
8fe65368 998
ebd5a14a
LR		 999/*
1000 * Code Specific to AR5008, AR9001 or AR9002,
1001 * we stuff these here to avoid callbacks for AR9003.
1002 */
d8f492b7 1003void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
ebd5a14a 1004int ar9002_hw_rf_claim(struct ath_hw *ah);
78ec2677 1005void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
d8f492b7 1006
641d9921 1007/*
aea702b7 1008 * Code specific to AR9003, we stuff these here to avoid callbacks
641d9921
FF		 1009 * for older families
1010 */
aea702b7
LR		 1011void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1012void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1013void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
51ac8cbb 1014void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
717f6bed
FF		 1015void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1016void ar9003_paprd_populate_single_table(struct ath_hw *ah,
20bd2a09
FF		 1017 struct ath9k_hw_cal_data *caldata,
1018 int chain);
1019int ar9003_paprd_create_curve(struct ath_hw *ah,
1020 struct ath9k_hw_cal_data *caldata, int chain);
717f6bed
FF		 1021int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1022int ar9003_paprd_init_table(struct ath_hw *ah);
1023bool ar9003_paprd_is_done(struct ath_hw *ah);
1024void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
641d9921
FF		 1025
1026/* Hardware family op attach helpers */
8fe65368 1027void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
8525f280
LR		 1028void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1029void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
8fe65368 1030
795f5e2c
LR		 1031void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1032void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1033
b3950e6a
LR		 1034void ar9002_hw_attach_ops(struct ath_hw *ah);
1035void ar9003_hw_attach_ops(struct ath_hw *ah);
1036
c2ba3342 1037void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767
LR		 1038/*
1039 * ANI work can be shared between all families but a next
1040 * generation implementation of ANI will be used only for AR9003 only
1041 * for now as the other families still need to be tested with the same
e36b27af
LR		 1042 * next generation ANI. Feel free to start testing it though for the
1043 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
ac0bb767 1044 */
e36b27af 1045extern int modparam_force_new_ani;
8eb4980c 1046void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
bfc472bb 1047void ath9k_hw_proc_mib_event(struct ath_hw *ah);
95792178 1048void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767 1049
73377256
LR		 1050#define ATH9K_CLOCK_RATE_CCK 22
1051#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1052#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1053#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1054
f078f209 1055#endif
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