]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/net/wireless/ath/ath9k/hw.h
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath9k: remove ath9k_ht_macmode
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
c46917bb 33#include "../debug.h"
3a702e49 34
394cf0a1
S		 35#define ATHEROS_VENDOR_ID 0x168c
36#define AR5416_DEVID_PCI 0x0023
37#define AR5416_DEVID_PCIE 0x0024
38#define AR9160_DEVID_PCI 0x0027
39#define AR9280_DEVID_PCI 0x0029
40#define AR9280_DEVID_PCIE 0x002a
41#define AR9285_DEVID_PCIE 0x002b
42#define AR5416_AR9100_DEVID 0x000b
43#define AR_SUBVENDOR_ID_NOG 0x0e11
44#define AR_SUBVENDOR_ID_NEW_A 0x7065
45#define AR5416_MAGIC 0x19641014
46
ac88b6ec
VN		 47#define AR5416_DEVID_AR9287_PCI 0x002D
48#define AR5416_DEVID_AR9287_PCIE 0x002E
49
fe12946e
VT		 50#define AR9280_COEX2WIRE_SUBSYSID 0x309b
51#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
52#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
53
394cf0a1 54/* Register read/write primitives */
9e4bffd2
LR		 55#define REG_WRITE(_ah, _reg, _val) \
56 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
57
58#define REG_READ(_ah, _reg) \
59 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
394cf0a1
S		 60
61#define SM(_v, _f) (((_v) << _f##_S) & _f)
62#define MS(_v, _f) (((_v) & _f) >> _f##_S)
63#define REG_RMW(_a, _r, _set, _clr) \
64 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
65#define REG_RMW_FIELD(_a, _r, _f, _v) \
66 REG_WRITE(_a, _r, \
67 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
68#define REG_SET_BIT(_a, _r, _f) \
69 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
70#define REG_CLR_BIT(_a, _r, _f) \
71 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 72
394cf0a1
S		 73#define DO_DELAY(x) do { \
74 if ((++(x) % 64) == 0) \
75 udelay(1); \
76 } while (0)
f078f209 77
394cf0a1
S		 78#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
79 int r; \
80 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
81 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
82 INI_RA((iniarray), r, (column))); \
83 DO_DELAY(regWr); \
84 } \
85 } while (0)
f078f209 86
394cf0a1
S		 87#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
88#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
89#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
90#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 91#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 92#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
93#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 94
394cf0a1
S		 95#define AR_GPIOD_MASK 0x00001FFF
96#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 97
394cf0a1
S		 98#define BASE_ACTIVATE_DELAY 100
99#define RTC_PLL_SETTLE_DELAY 1000
100#define COEF_SCALE_S 24
101#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 102
394cf0a1
S		 103#define ATH9K_ANTENNA0_CHAINMASK 0x1
104#define ATH9K_ANTENNA1_CHAINMASK 0x2
105
106#define ATH9K_NUM_DMA_DEBUG_REGS 8
107#define ATH9K_NUM_QUEUES 10
108
109#define MAX_RATE_POWER 63
0caa7b14 110#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 111#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 112#define AH_TIME_QUANTUM 10
113#define AR_KEYTABLE_SIZE 128
d8caa839 114#define POWER_UP_TIME 10000
394cf0a1
S		 115#define SPUR_RSSI_THRESH 40
116
117#define CAB_TIMEOUT_VAL 10
118#define BEACON_TIMEOUT_VAL 10
119#define MIN_BEACON_TIMEOUT_VAL 1
120#define SLEEP_SLOP 3
121
122#define INIT_CONFIG_STATUS 0x00000000
123#define INIT_RSSI_THR 0x00000700
124#define INIT_BCON_CNTRL_REG 0x00000000
125
126#define TU_TO_USEC(_tu) ((_tu) << 10)
127
128enum wireless_mode {
129 ATH9K_MODE_11A = 0,
b9b6e15a
LR		 130 ATH9K_MODE_11G,
131 ATH9K_MODE_11NA_HT20,
132 ATH9K_MODE_11NG_HT20,
133 ATH9K_MODE_11NA_HT40PLUS,
134 ATH9K_MODE_11NA_HT40MINUS,
135 ATH9K_MODE_11NG_HT40PLUS,
136 ATH9K_MODE_11NG_HT40MINUS,
137 ATH9K_MODE_MAX,
394cf0a1 138};
f078f209 139
1cf6873a
S		 140enum ath9k_ant_setting {
141 ATH9K_ANT_VARIABLE = 0,
142 ATH9K_ANT_FIXED_A,
143 ATH9K_ANT_FIXED_B
144};
145
394cf0a1 146enum ath9k_hw_caps {
bdbdf46d
S		 147 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
148 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
149 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
150 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
151 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
152 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
153 ATH9K_HW_CAP_VEOL = BIT(6),
154 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
155 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
156 ATH9K_HW_CAP_HT = BIT(9),
157 ATH9K_HW_CAP_GTT = BIT(10),
158 ATH9K_HW_CAP_FASTCC = BIT(11),
159 ATH9K_HW_CAP_RFSILENT = BIT(12),
160 ATH9K_HW_CAP_CST = BIT(13),
161 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
162 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
163 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
394cf0a1 164};
f078f209 165
394cf0a1
S		 166enum ath9k_capability_type {
167 ATH9K_CAP_CIPHER = 0,
168 ATH9K_CAP_TKIP_MIC,
169 ATH9K_CAP_TKIP_SPLIT,
394cf0a1
S		 170 ATH9K_CAP_DIVERSITY,
171 ATH9K_CAP_TXPOW,
394cf0a1 172 ATH9K_CAP_MCAST_KEYSRCH,
8bd1d07f 173 ATH9K_CAP_DS
394cf0a1 174};
f078f209 175
394cf0a1
S		 176struct ath9k_hw_capabilities {
177 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
178 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
179 u16 total_queues;
180 u16 keycache_size;
181 u16 low_5ghz_chan, high_5ghz_chan;
182 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 183 u16 rts_aggr_limit;
184 u8 tx_chainmask;
185 u8 rx_chainmask;
186 u16 tx_triglevel_max;
187 u16 reg_cap;
188 u8 num_gpio_pins;
189 u8 num_antcfg_2ghz;
190 u8 num_antcfg_5ghz;
191};
f078f209 192
394cf0a1
S		 193struct ath9k_ops_config {
194 int dma_beacon_response_time;
195 int sw_beacon_response_time;
196 int additional_swba_backoff;
197 int ack_6mb;
198 int cwm_ignore_extcca;
199 u8 pcie_powersave_enable;
394cf0a1
S		 200 u8 pcie_clock_req;
201 u32 pcie_waen;
394cf0a1
S		 202 u8 analog_shiftreg;
203 u8 ht_enable;
204 u32 ofdm_trig_low;
205 u32 ofdm_trig_high;
206 u32 cck_trig_high;
207 u32 cck_trig_low;
208 u32 enable_ani;
1cf6873a 209 enum ath9k_ant_setting diversity_control;
394cf0a1
S		 210 u16 antenna_switch_swap;
211 int serialize_regmode;
0ef1f168 212 bool intr_mitigation;
394cf0a1
S		 213#define SPUR_DISABLE 0
214#define SPUR_ENABLE_IOCTL 1
215#define SPUR_ENABLE_EEPROM 2
216#define AR_EEPROM_MODAL_SPURS 5
217#define AR_SPUR_5413_1 1640
218#define AR_SPUR_5413_2 1200
219#define AR_NO_SPUR 0x8000
220#define AR_BASE_FREQ_2GHZ 2300
221#define AR_BASE_FREQ_5GHZ 4900
222#define AR_SPUR_FEEQ_BOUND_HT40 19
223#define AR_SPUR_FEEQ_BOUND_HT20 10
224 int spurmode;
225 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
226};
f078f209 227
394cf0a1
S		 228enum ath9k_int {
229 ATH9K_INT_RX = 0x00000001,
230 ATH9K_INT_RXDESC = 0x00000002,
231 ATH9K_INT_RXNOFRM = 0x00000008,
232 ATH9K_INT_RXEOL = 0x00000010,
233 ATH9K_INT_RXORN = 0x00000020,
234 ATH9K_INT_TX = 0x00000040,
235 ATH9K_INT_TXDESC = 0x00000080,
236 ATH9K_INT_TIM_TIMER = 0x00000100,
237 ATH9K_INT_TXURN = 0x00000800,
238 ATH9K_INT_MIB = 0x00001000,
239 ATH9K_INT_RXPHY = 0x00004000,
240 ATH9K_INT_RXKCM = 0x00008000,
241 ATH9K_INT_SWBA = 0x00010000,
242 ATH9K_INT_BMISS = 0x00040000,
243 ATH9K_INT_BNR = 0x00100000,
244 ATH9K_INT_TIM = 0x00200000,
245 ATH9K_INT_DTIM = 0x00400000,
246 ATH9K_INT_DTIMSYNC = 0x00800000,
247 ATH9K_INT_GPIO = 0x01000000,
248 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 249 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 250 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 251 ATH9K_INT_CST = 0x10000000,
252 ATH9K_INT_GTT = 0x20000000,
253 ATH9K_INT_FATAL = 0x40000000,
254 ATH9K_INT_GLOBAL = 0x80000000,
255 ATH9K_INT_BMISC = ATH9K_INT_TIM |
256 ATH9K_INT_DTIM |
257 ATH9K_INT_DTIMSYNC |
4af9cf4f 258 ATH9K_INT_TSFOOR |
394cf0a1
S		 259 ATH9K_INT_CABEND,
260 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
261 ATH9K_INT_RXDESC |
262 ATH9K_INT_RXEOL |
263 ATH9K_INT_RXORN |
264 ATH9K_INT_TXURN |
265 ATH9K_INT_TXDESC |
266 ATH9K_INT_MIB |
267 ATH9K_INT_RXPHY |
268 ATH9K_INT_RXKCM |
269 ATH9K_INT_SWBA |
270 ATH9K_INT_BMISS |
271 ATH9K_INT_GPIO,
272 ATH9K_INT_NOCARD = 0xffffffff
273};
f078f209 274
394cf0a1
S		 275#define CHANNEL_CW_INT 0x00002
276#define CHANNEL_CCK 0x00020
277#define CHANNEL_OFDM 0x00040
278#define CHANNEL_2GHZ 0x00080
279#define CHANNEL_5GHZ 0x00100
280#define CHANNEL_PASSIVE 0x00200
281#define CHANNEL_DYN 0x00400
282#define CHANNEL_HALF 0x04000
283#define CHANNEL_QUARTER 0x08000
284#define CHANNEL_HT20 0x10000
285#define CHANNEL_HT40PLUS 0x20000
286#define CHANNEL_HT40MINUS 0x40000
287
394cf0a1
S		 288#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
289#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
290#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
291#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
292#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
293#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
294#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
295#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
296#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
297#define CHANNEL_ALL \
298 (CHANNEL_OFDM| \
299 CHANNEL_CCK| \
300 CHANNEL_2GHZ | \
301 CHANNEL_5GHZ | \
302 CHANNEL_HT20 | \
303 CHANNEL_HT40PLUS | \
304 CHANNEL_HT40MINUS)
305
306struct ath9k_channel {
307 struct ieee80211_channel *chan;
308 u16 channel;
309 u32 channelFlags;
310 u32 chanmode;
311 int32_t CalValid;
312 bool oneTimeCalsDone;
313 int8_t iCoff;
314 int8_t qCoff;
315 int16_t rawNoiseFloor;
316};
f078f209 317
394cf0a1
S		 318#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
319 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
320 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
321 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
322#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
323#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
324#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 325#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
326#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
327#define IS_CHAN_A_5MHZ_SPACED(_c) \
328 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
329 (((_c)->channel % 20) != 0) && \
330 (((_c)->channel % 10) != 0))
331
332/* These macros check chanmode and not channelFlags */
333#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
334#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
335 ((_c)->chanmode == CHANNEL_G_HT20))
336#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
337 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
338 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
339 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
340#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
341
342enum ath9k_power_mode {
343 ATH9K_PM_AWAKE = 0,
344 ATH9K_PM_FULL_SLEEP,
345 ATH9K_PM_NETWORK_SLEEP,
346 ATH9K_PM_UNDEFINED
347};
f078f209 348
394cf0a1
S		 349enum ath9k_tp_scale {
350 ATH9K_TP_SCALE_MAX = 0,
351 ATH9K_TP_SCALE_50,
352 ATH9K_TP_SCALE_25,
353 ATH9K_TP_SCALE_12,
354 ATH9K_TP_SCALE_MIN
355};
f078f209 356
394cf0a1
S		 357enum ser_reg_mode {
358 SER_REG_MODE_OFF = 0,
359 SER_REG_MODE_ON = 1,
360 SER_REG_MODE_AUTO = 2,
361};
f078f209 362
394cf0a1
S		 363struct ath9k_beacon_state {
364 u32 bs_nexttbtt;
365 u32 bs_nextdtim;
366 u32 bs_intval;
367#define ATH9K_BEACON_PERIOD 0x0000ffff
368#define ATH9K_BEACON_ENA 0x00800000
369#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 370#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 371 u32 bs_dtimperiod;
372 u16 bs_cfpperiod;
373 u16 bs_cfpmaxduration;
374 u32 bs_cfpnext;
375 u16 bs_timoffset;
376 u16 bs_bmissthreshold;
377 u32 bs_sleepduration;
4af9cf4f 378 u32 bs_tsfoor_threshold;
394cf0a1 379};
f078f209 380
394cf0a1
S		 381struct chan_centers {
382 u16 synth_center;
383 u16 ctl_center;
384 u16 ext_center;
385};
f078f209 386
394cf0a1
S		 387enum {
388 ATH9K_RESET_POWER_ON,
389 ATH9K_RESET_WARM,
390 ATH9K_RESET_COLD,
391};
f078f209 392
d535a42a
S		 393struct ath9k_hw_version {
394 u32 magic;
395 u16 devid;
396 u16 subvendorid;
397 u32 macVersion;
398 u16 macRev;
399 u16 phyRev;
400 u16 analog5GhzRev;
401 u16 analog2GhzRev;
aeac355d 402 u16 subsysid;
d535a42a 403};
394cf0a1 404
ff155a45
VT		 405/* Generic TSF timer definitions */
406
407#define ATH_MAX_GEN_TIMER 16
408
409#define AR_GENTMR_BIT(_index) (1 << (_index))
410
411/*
412 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
413 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
414 */
415#define debruijn32 0x077CB531UL
416
417struct ath_gen_timer_configuration {
418 u32 next_addr;
419 u32 period_addr;
420 u32 mode_addr;
421 u32 mode_mask;
422};
423
424struct ath_gen_timer {
425 void (*trigger)(void *arg);
426 void (*overflow)(void *arg);
427 void *arg;
428 u8 index;
429};
430
431struct ath_gen_timer_table {
432 u32 gen_timer_index[32];
433 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
434 union {
435 unsigned long timer_bits;
436 u16 val;
437 } timer_mask;
438};
439
cbe61d8a 440struct ath_hw {
b002a4a9 441 struct ieee80211_hw *hw;
394cf0a1 442 struct ath_softc *ah_sc;
27c51f1a 443 struct ath_common common;
cbe61d8a 444 struct ath9k_hw_version hw_version;
2660b81a
S		 445 struct ath9k_ops_config config;
446 struct ath9k_hw_capabilities caps;
2660b81a
S		 447 struct ath9k_channel channels[38];
448 struct ath9k_channel *curchan;
394cf0a1 449
cbe61d8a
S		 450 union {
451 struct ar5416_eeprom_def def;
452 struct ar5416_eeprom_4k map4k;
475f5989 453 struct ar9287_eeprom map9287;
2660b81a 454 } eeprom;
f74df6fb 455 const struct eeprom_ops *eep_ops;
2660b81a 456 enum ath9k_eep_map eep_map;
cbe61d8a
S		 457
458 bool sw_mgmt_crypto;
2660b81a 459 bool is_pciexpress;
2660b81a
S		 460 u16 tx_trig_level;
461 u16 rfsilent;
462 u32 rfkill_gpio;
463 u32 rfkill_polarity;
cbe61d8a 464 u32 ah_flags;
394cf0a1 465
d7e7d229
LR		 466 bool htc_reset_init;
467
2660b81a
S		 468 enum nl80211_iftype opmode;
469 enum ath9k_power_mode power_mode;
f078f209 470
cbe61d8a 471 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
a13883b0 472 struct ath9k_pacal_info pacal_info;
2660b81a
S		 473 struct ar5416Stats stats;
474 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
475
476 int16_t curchan_rad_index;
477 u32 mask_reg;
478 u32 txok_interrupt_mask;
479 u32 txerr_interrupt_mask;
480 u32 txdesc_interrupt_mask;
481 u32 txeol_interrupt_mask;
482 u32 txurn_interrupt_mask;
483 bool chip_fullsleep;
484 u32 atim_window;
6a2b9e8c
S		 485
486 /* Calibration */
cbfe9468
S		 487 enum ath9k_cal_types supp_cals;
488 struct ath9k_cal_list iq_caldata;
489 struct ath9k_cal_list adcgain_caldata;
490 struct ath9k_cal_list adcdc_calinitdata;
491 struct ath9k_cal_list adcdc_caldata;
492 struct ath9k_cal_list *cal_list;
493 struct ath9k_cal_list *cal_list_last;
494 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 495#define totalPowerMeasI meas0.unsign
496#define totalPowerMeasQ meas1.unsign
497#define totalIqCorrMeas meas2.sign
498#define totalAdcIOddPhase meas0.unsign
499#define totalAdcIEvenPhase meas1.unsign
500#define totalAdcQOddPhase meas2.unsign
501#define totalAdcQEvenPhase meas3.unsign
502#define totalAdcDcOffsetIOddPhase meas0.sign
503#define totalAdcDcOffsetIEvenPhase meas1.sign
504#define totalAdcDcOffsetQOddPhase meas2.sign
505#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 506 union {
507 u32 unsign[AR5416_MAX_CHAINS];
508 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 509 } meas0;
f078f209
LR		 510 union {
511 u32 unsign[AR5416_MAX_CHAINS];
512 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 513 } meas1;
f078f209
LR		 514 union {
515 u32 unsign[AR5416_MAX_CHAINS];
516 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 517 } meas2;
f078f209
LR		 518 union {
519 u32 unsign[AR5416_MAX_CHAINS];
520 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 521 } meas3;
522 u16 cal_samples;
6a2b9e8c 523
2660b81a
S		 524 u32 sta_id1_defaults;
525 u32 misc_mode;
f078f209
LR		 526 enum {
527 AUTO_32KHZ,
528 USE_32KHZ,
529 DONT_USE_32KHZ,
2660b81a 530 } enable_32kHz_clock;
6a2b9e8c
S		 531
532 /* RF */
2660b81a
S		 533 u32 *analogBank0Data;
534 u32 *analogBank1Data;
535 u32 *analogBank2Data;
536 u32 *analogBank3Data;
537 u32 *analogBank6Data;
538 u32 *analogBank6TPCData;
539 u32 *analogBank7Data;
540 u32 *addac5416_21;
541 u32 *bank6Temp;
542
543 int16_t txpower_indexoffset;
544 u32 beacon_interval;
545 u32 slottime;
546 u32 acktimeout;
547 u32 ctstimeout;
548 u32 globaltxtimeout;
549 u8 gbeacon_rate;
6a2b9e8c
S		 550
551 /* ANI */
2660b81a 552 u32 proc_phyerr;
2660b81a
S		 553 u32 aniperiod;
554 struct ar5416AniState *curani;
555 struct ar5416AniState ani[255];
556 int totalSizeDesired[5];
557 int coarse_high[5];
558 int coarse_low[5];
559 int firpwr[5];
560 enum ath9k_ani_cmd ani_function;
561
af03abec 562 /* Bluetooth coexistance */
766ec4a9 563 struct ath_btcoex_hw btcoex_hw;
af03abec 564
2660b81a 565 u32 intr_txqs;
2660b81a
S		 566 u8 txchainmask;
567 u8 rxchainmask;
568
8bd1d07f
SB		 569 u32 originalGain[22];
570 int initPDADC;
571 int PDADCdelta;
08fc5c1b 572 u8 led_pin;
8bd1d07f 573
2660b81a
S		 574 struct ar5416IniArray iniModes;
575 struct ar5416IniArray iniCommon;
576 struct ar5416IniArray iniBank0;
577 struct ar5416IniArray iniBB_RfGain;
578 struct ar5416IniArray iniBank1;
579 struct ar5416IniArray iniBank2;
580 struct ar5416IniArray iniBank3;
581 struct ar5416IniArray iniBank6;
582 struct ar5416IniArray iniBank6TPC;
583 struct ar5416IniArray iniBank7;
584 struct ar5416IniArray iniAddac;
585 struct ar5416IniArray iniPcieSerdes;
586 struct ar5416IniArray iniModesAdditional;
587 struct ar5416IniArray iniModesRxGain;
588 struct ar5416IniArray iniModesTxGain;
ff155a45
VT		 589
590 u32 intr_gen_timer_trigger;
591 u32 intr_gen_timer_thresh;
592 struct ath_gen_timer_table hw_gen_timers;
f078f209 593};
f078f209 594
9e4bffd2
LR		 595static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
596{
597 return &ah->common;
598}
599
600static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
601{
602 return &(ath9k_hw_common(ah)->regulatory);
603}
604
f637cfd6 605/* Initialization, Detach, Reset */
394cf0a1 606const char *ath9k_hw_probe(u16 vendorid, u16 devid);
cbe61d8a 607void ath9k_hw_detach(struct ath_hw *ah);
f637cfd6 608int ath9k_hw_init(struct ath_hw *ah);
081b35ab 609void ath9k_hw_rf_free(struct ath_hw *ah);
cbe61d8a 610int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
394cf0a1 611 bool bChannelChange);
eef7a574 612void ath9k_hw_fill_cap_info(struct ath_hw *ah);
cbe61d8a 613bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 614 u32 capability, u32 *result);
cbe61d8a 615bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1
S		 616 u32 capability, u32 setting, int *status);
617
618/* Key Cache Management */
cbe61d8a
S		 619bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
620bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
621bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
394cf0a1 622 const struct ath9k_keyval *k,
e0caf9ea 623 const u8 *mac);
cbe61d8a 624bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
394cf0a1
S		 625
626/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 627void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
628u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
629void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 630 u32 ah_signal_type);
cbe61d8a 631void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 632u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
633void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
634bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
394cf0a1
S		 635 enum ath9k_ant_setting settings,
636 struct ath9k_channel *chan,
637 u8 *tx_chainmask, u8 *rx_chainmask,
638 u8 *antenna_cfgd);
639
640/* General Operation */
0caa7b14 641bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 642u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 643bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3
LR		 644u16 ath9k_hw_computetxtime(struct ath_hw *ah,
645 const struct ath_rate_table *rates,
394cf0a1 646 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 647void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 648 struct ath9k_channel *chan,
649 struct chan_centers *centers);
cbe61d8a
S		 650u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
651void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
652bool ath9k_hw_phy_disable(struct ath_hw *ah);
653bool ath9k_hw_disable(struct ath_hw *ah);
8fbff4b8 654void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
cbe61d8a
S		 655void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
656void ath9k_hw_setopmode(struct ath_hw *ah);
657void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 658void ath9k_hw_setbssidmask(struct ath_hw *ah);
659void ath9k_hw_write_associd(struct ath_hw *ah);
cbe61d8a
S		 660u64 ath9k_hw_gettsf64(struct ath_hw *ah);
661void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
662void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 663void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
cbe61d8a 664bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
25c56eec 665void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 666void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
667void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 668 const struct ath9k_beacon_state *bs);
a91d75ae 669
9ecdef4b 670bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 671
93b1b37f 672void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
394cf0a1
S		 673
674/* Interrupt Handling */
cbe61d8a
S		 675bool ath9k_hw_intrpend(struct ath_hw *ah);
676bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
cbe61d8a 677enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
394cf0a1 678
ff155a45
VT		 679/* Generic hw timer primitives */
680struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
681 void (*trigger)(void *),
682 void (*overflow)(void *),
683 void *arg,
684 u8 timer_index);
cd9bf689
LR		 685void ath9k_hw_gen_timer_start(struct ath_hw *ah,
686 struct ath_gen_timer *timer,
687 u32 timer_next,
688 u32 timer_period);
689void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
690
ff155a45
VT		 691void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
692void ath_gen_timer_isr(struct ath_hw *hw);
1773912b 693u32 ath9k_hw_gettsf32(struct ath_hw *ah);
ff155a45 694
7b6840ab
VT		 695#define ATH_PCIE_CAP_LINK_CTRL 0x70
696#define ATH_PCIE_CAP_LINK_L0S 1
697#define ATH_PCIE_CAP_LINK_L1 2
698
f078f209 699#endif
Ubuntu Jammy Linux kernel mirror