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ath9k_hw: Take care of few host interface register changes for AR9340
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
3a702e49 33
394cf0a1 34#define ATHEROS_VENDOR_ID 0x168c
7976b426 35
394cf0a1
S		 36#define AR5416_DEVID_PCI 0x0023
37#define AR5416_DEVID_PCIE 0x0024
38#define AR9160_DEVID_PCI 0x0027
39#define AR9280_DEVID_PCI 0x0029
40#define AR9280_DEVID_PCIE 0x002a
41#define AR9285_DEVID_PCIE 0x002b
5ffaf8a3 42#define AR2427_DEVID_PCIE 0x002c
db3cc53a
SB		 43#define AR9287_DEVID_PCI 0x002d
44#define AR9287_DEVID_PCIE 0x002e
45#define AR9300_DEVID_PCIE 0x0030
b99a7be4 46#define AR9300_DEVID_AR9340 0x0031
3050c914 47#define AR9300_DEVID_AR9485_PCIE 0x0032
7976b426 48
394cf0a1 49#define AR5416_AR9100_DEVID 0x000b
7976b426 50
394cf0a1
S		 51#define AR_SUBVENDOR_ID_NOG 0x0e11
52#define AR_SUBVENDOR_ID_NEW_A 0x7065
53#define AR5416_MAGIC 0x19641014
54
fe12946e
VT		 55#define AR9280_COEX2WIRE_SUBSYSID 0x309b
56#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
57#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58
e3d01bfc
LR		 59#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
60
cfe8cba9
LR		 61#define ATH_DEFAULT_NOISE_FLOOR -95
62
04658fba 63#define ATH9K_RSSI_BAD -128
990b70ab 64
cac4220b
FF		 65#define ATH9K_NUM_CHANNELS 38
66
394cf0a1 67/* Register read/write primitives */
9e4bffd2 68#define REG_WRITE(_ah, _reg, _val) \
f9f84e96 69 (_ah)->reg_ops.write((_ah), (_val), (_reg))
9e4bffd2
LR		 70
71#define REG_READ(_ah, _reg) \
f9f84e96 72 (_ah)->reg_ops.read((_ah), (_reg))
394cf0a1 73
09a525d3 74#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
f9f84e96 75 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
09a525d3 76
845e03c9
FF		 77#define REG_RMW(_ah, _reg, _set, _clr) \
78 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
79
20b3efd9
S		 80#define ENABLE_REGWRITE_BUFFER(_ah) \
81 do { \
f9f84e96
FF		 82 if ((_ah)->reg_ops.enable_write_buffer) \
83 (_ah)->reg_ops.enable_write_buffer((_ah)); \
20b3efd9
S		 84 } while (0)
85
20b3efd9
S		 86#define REGWRITE_BUFFER_FLUSH(_ah) \
87 do { \
f9f84e96
FF		 88 if ((_ah)->reg_ops.write_flush) \
89 (_ah)->reg_ops.write_flush((_ah)); \
20b3efd9
S		 90 } while (0)
91
394cf0a1
S		 92#define SM(_v, _f) (((_v) << _f##_S) & _f)
93#define MS(_v, _f) (((_v) & _f) >> _f##_S)
394cf0a1 94#define REG_RMW_FIELD(_a, _r, _f, _v) \
845e03c9 95 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
1547da37
LR		 96#define REG_READ_FIELD(_a, _r, _f) \
97 (((REG_READ(_a, _r) & _f) >> _f##_S))
394cf0a1 98#define REG_SET_BIT(_a, _r, _f) \
845e03c9 99 REG_RMW(_a, _r, (_f), 0)
394cf0a1 100#define REG_CLR_BIT(_a, _r, _f) \
845e03c9 101 REG_RMW(_a, _r, 0, (_f))
f078f209 102
e7fc6338
RM		 103#define DO_DELAY(x) do { \
104 if (((++(x) % 64) == 0) && \
105 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
106 != ATH_USB)) \
107 udelay(1); \
394cf0a1 108 } while (0)
f078f209 109
a9b6b256
FF		 110#define REG_WRITE_ARRAY(iniarray, column, regWr) \
111 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
f078f209 112
394cf0a1
S		 113#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
114#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
115#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
116#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 117#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 118#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
119#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 120
394cf0a1
S		 121#define AR_GPIOD_MASK 0x00001FFF
122#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 123
394cf0a1 124#define BASE_ACTIVATE_DELAY 100
63a75b91 125#define RTC_PLL_SETTLE_DELAY 100
394cf0a1
S		 126#define COEF_SCALE_S 24
127#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 128
394cf0a1
S		 129#define ATH9K_ANTENNA0_CHAINMASK 0x1
130#define ATH9K_ANTENNA1_CHAINMASK 0x2
131
132#define ATH9K_NUM_DMA_DEBUG_REGS 8
133#define ATH9K_NUM_QUEUES 10
134
135#define MAX_RATE_POWER 63
0caa7b14 136#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 137#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 138#define AH_TIME_QUANTUM 10
139#define AR_KEYTABLE_SIZE 128
d8caa839 140#define POWER_UP_TIME 10000
394cf0a1
S		 141#define SPUR_RSSI_THRESH 40
142
143#define CAB_TIMEOUT_VAL 10
144#define BEACON_TIMEOUT_VAL 10
145#define MIN_BEACON_TIMEOUT_VAL 1
146#define SLEEP_SLOP 3
147
148#define INIT_CONFIG_STATUS 0x00000000
149#define INIT_RSSI_THR 0x00000700
150#define INIT_BCON_CNTRL_REG 0x00000000
151
152#define TU_TO_USEC(_tu) ((_tu) << 10)
153
ceb26445
VT		 154#define ATH9K_HW_RX_HP_QDEPTH 16
155#define ATH9K_HW_RX_LP_QDEPTH 128
156
717f6bed
FF		 157#define PAPRD_GAIN_TABLE_ENTRIES 32
158#define PAPRD_TABLE_SZ 24
159
066dae93
FF		 160enum ath_hw_txq_subtype {
161 ATH_TXQ_AC_BE = 0,
162 ATH_TXQ_AC_BK = 1,
163 ATH_TXQ_AC_VI = 2,
164 ATH_TXQ_AC_VO = 3,
165};
166
13ce3e99
LR		 167enum ath_ini_subsys {
168 ATH_INI_PRE = 0,
169 ATH_INI_CORE,
170 ATH_INI_POST,
171 ATH_INI_NUM_SPLIT,
172};
173
394cf0a1 174enum ath9k_hw_caps {
364734fa
FF		 175 ATH9K_HW_CAP_HT = BIT(0),
176 ATH9K_HW_CAP_RFSILENT = BIT(1),
177 ATH9K_HW_CAP_CST = BIT(2),
364734fa
FF		 178 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
179 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
180 ATH9K_HW_CAP_EDMA = BIT(6),
181 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
182 ATH9K_HW_CAP_LDPC = BIT(8),
183 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
184 ATH9K_HW_CAP_SGI_20 = BIT(10),
185 ATH9K_HW_CAP_PAPRD = BIT(11),
186 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
d4659912
FF		 187 ATH9K_HW_CAP_2GHZ = BIT(13),
188 ATH9K_HW_CAP_5GHZ = BIT(14),
ea066d5a 189 ATH9K_HW_CAP_APM = BIT(15),
394cf0a1 190};
f078f209 191
394cf0a1
S		 192struct ath9k_hw_capabilities {
193 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
394cf0a1
S		 194 u16 rts_aggr_limit;
195 u8 tx_chainmask;
196 u8 rx_chainmask;
47c80de6
VT		 197 u8 max_txchains;
198 u8 max_rxchains;
394cf0a1 199 u8 num_gpio_pins;
ceb26445
VT		 200 u8 rx_hp_qdepth;
201 u8 rx_lp_qdepth;
202 u8 rx_status_len;
162c3be3 203 u8 tx_desc_len;
5088c2f1 204 u8 txs_len;
8060e169
VT		 205 u16 pcie_lcr_offset;
206 bool pcie_lcr_extsync_en;
394cf0a1 207};
f078f209 208
394cf0a1
S		 209struct ath9k_ops_config {
210 int dma_beacon_response_time;
211 int sw_beacon_response_time;
212 int additional_swba_backoff;
213 int ack_6mb;
41f3e54d 214 u32 cwm_ignore_extcca;
394cf0a1 215 u8 pcie_powersave_enable;
6a0ec30a 216 bool pcieSerDesWrite;
394cf0a1
S		 217 u8 pcie_clock_req;
218 u32 pcie_waen;
394cf0a1 219 u8 analog_shiftreg;
6f481010 220 u8 paprd_disable;
394cf0a1
S		 221 u32 ofdm_trig_low;
222 u32 ofdm_trig_high;
223 u32 cck_trig_high;
224 u32 cck_trig_low;
225 u32 enable_ani;
394cf0a1 226 int serialize_regmode;
0ce024cb 227 bool rx_intr_mitigation;
55e82df4 228 bool tx_intr_mitigation;
394cf0a1
S		 229#define SPUR_DISABLE 0
230#define SPUR_ENABLE_IOCTL 1
231#define SPUR_ENABLE_EEPROM 2
394cf0a1
S		 232#define AR_SPUR_5413_1 1640
233#define AR_SPUR_5413_2 1200
234#define AR_NO_SPUR 0x8000
235#define AR_BASE_FREQ_2GHZ 2300
236#define AR_BASE_FREQ_5GHZ 4900
237#define AR_SPUR_FEEQ_BOUND_HT40 19
238#define AR_SPUR_FEEQ_BOUND_HT20 10
239 int spurmode;
240 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 241 u8 max_txtrig_level;
e36b27af 242 u16 ani_poll_interval; /* ANI poll interval in ms */
394cf0a1 243};
f078f209 244
394cf0a1
S		 245enum ath9k_int {
246 ATH9K_INT_RX = 0x00000001,
247 ATH9K_INT_RXDESC = 0x00000002,
b5c80475
FF		 248 ATH9K_INT_RXHP = 0x00000001,
249 ATH9K_INT_RXLP = 0x00000002,
394cf0a1
S		 250 ATH9K_INT_RXNOFRM = 0x00000008,
251 ATH9K_INT_RXEOL = 0x00000010,
252 ATH9K_INT_RXORN = 0x00000020,
253 ATH9K_INT_TX = 0x00000040,
254 ATH9K_INT_TXDESC = 0x00000080,
255 ATH9K_INT_TIM_TIMER = 0x00000100,
aea702b7 256 ATH9K_INT_BB_WATCHDOG = 0x00000400,
394cf0a1
S		 257 ATH9K_INT_TXURN = 0x00000800,
258 ATH9K_INT_MIB = 0x00001000,
259 ATH9K_INT_RXPHY = 0x00004000,
260 ATH9K_INT_RXKCM = 0x00008000,
261 ATH9K_INT_SWBA = 0x00010000,
262 ATH9K_INT_BMISS = 0x00040000,
263 ATH9K_INT_BNR = 0x00100000,
264 ATH9K_INT_TIM = 0x00200000,
265 ATH9K_INT_DTIM = 0x00400000,
266 ATH9K_INT_DTIMSYNC = 0x00800000,
267 ATH9K_INT_GPIO = 0x01000000,
268 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 269 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 270 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 271 ATH9K_INT_CST = 0x10000000,
272 ATH9K_INT_GTT = 0x20000000,
273 ATH9K_INT_FATAL = 0x40000000,
274 ATH9K_INT_GLOBAL = 0x80000000,
275 ATH9K_INT_BMISC = ATH9K_INT_TIM |
276 ATH9K_INT_DTIM |
277 ATH9K_INT_DTIMSYNC |
4af9cf4f 278 ATH9K_INT_TSFOOR |
394cf0a1
S		 279 ATH9K_INT_CABEND,
280 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
281 ATH9K_INT_RXDESC |
282 ATH9K_INT_RXEOL |
283 ATH9K_INT_RXORN |
284 ATH9K_INT_TXURN |
285 ATH9K_INT_TXDESC |
286 ATH9K_INT_MIB |
287 ATH9K_INT_RXPHY |
288 ATH9K_INT_RXKCM |
289 ATH9K_INT_SWBA |
290 ATH9K_INT_BMISS |
291 ATH9K_INT_GPIO,
292 ATH9K_INT_NOCARD = 0xffffffff
293};
f078f209 294
394cf0a1
S		 295#define CHANNEL_CW_INT 0x00002
296#define CHANNEL_CCK 0x00020
297#define CHANNEL_OFDM 0x00040
298#define CHANNEL_2GHZ 0x00080
299#define CHANNEL_5GHZ 0x00100
300#define CHANNEL_PASSIVE 0x00200
301#define CHANNEL_DYN 0x00400
302#define CHANNEL_HALF 0x04000
303#define CHANNEL_QUARTER 0x08000
304#define CHANNEL_HT20 0x10000
305#define CHANNEL_HT40PLUS 0x20000
306#define CHANNEL_HT40MINUS 0x40000
307
394cf0a1
S		 308#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
309#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
310#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
311#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
312#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
313#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
314#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
315#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
316#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
317#define CHANNEL_ALL \
318 (CHANNEL_OFDM| \
319 CHANNEL_CCK| \
320 CHANNEL_2GHZ | \
321 CHANNEL_5GHZ | \
322 CHANNEL_HT20 | \
323 CHANNEL_HT40PLUS | \
324 CHANNEL_HT40MINUS)
325
20bd2a09 326struct ath9k_hw_cal_data {
394cf0a1
S		 327 u16 channel;
328 u32 channelFlags;
394cf0a1 329 int32_t CalValid;
394cf0a1
S		 330 int8_t iCoff;
331 int8_t qCoff;
717f6bed 332 bool paprd_done;
4254bc1c 333 bool nfcal_pending;
70cf1533 334 bool nfcal_interference;
717f6bed
FF		 335 u16 small_signal_gain[AR9300_MAX_CHAINS];
336 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
20bd2a09
FF		 337 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
338};
339
340struct ath9k_channel {
341 struct ieee80211_channel *chan;
093115b7 342 struct ar5416AniState ani;
20bd2a09
FF		 343 u16 channel;
344 u32 channelFlags;
345 u32 chanmode;
d9891c78 346 s16 noisefloor;
394cf0a1 347};
f078f209 348
394cf0a1
S		 349#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
350 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
351 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
352 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
353#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
354#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
355#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 356#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
357#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
6b42e8d0 358#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
394cf0a1 359 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
6b42e8d0 360 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
394cf0a1
S		 361
362/* These macros check chanmode and not channelFlags */
363#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
364#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
365 ((_c)->chanmode == CHANNEL_G_HT20))
366#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
367 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
368 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
369 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
370#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
371
372enum ath9k_power_mode {
373 ATH9K_PM_AWAKE = 0,
374 ATH9K_PM_FULL_SLEEP,
375 ATH9K_PM_NETWORK_SLEEP,
376 ATH9K_PM_UNDEFINED
377};
f078f209 378
394cf0a1
S		 379enum ath9k_tp_scale {
380 ATH9K_TP_SCALE_MAX = 0,
381 ATH9K_TP_SCALE_50,
382 ATH9K_TP_SCALE_25,
383 ATH9K_TP_SCALE_12,
384 ATH9K_TP_SCALE_MIN
385};
f078f209 386
394cf0a1
S		 387enum ser_reg_mode {
388 SER_REG_MODE_OFF = 0,
389 SER_REG_MODE_ON = 1,
390 SER_REG_MODE_AUTO = 2,
391};
f078f209 392
ad7b8060
VT		 393enum ath9k_rx_qtype {
394 ATH9K_RX_QUEUE_HP,
395 ATH9K_RX_QUEUE_LP,
396 ATH9K_RX_QUEUE_MAX,
397};
398
394cf0a1
S		 399struct ath9k_beacon_state {
400 u32 bs_nexttbtt;
401 u32 bs_nextdtim;
402 u32 bs_intval;
403#define ATH9K_BEACON_PERIOD 0x0000ffff
4af9cf4f 404#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 405 u32 bs_dtimperiod;
406 u16 bs_cfpperiod;
407 u16 bs_cfpmaxduration;
408 u32 bs_cfpnext;
409 u16 bs_timoffset;
410 u16 bs_bmissthreshold;
411 u32 bs_sleepduration;
4af9cf4f 412 u32 bs_tsfoor_threshold;
394cf0a1 413};
f078f209 414
394cf0a1
S		 415struct chan_centers {
416 u16 synth_center;
417 u16 ctl_center;
418 u16 ext_center;
419};
f078f209 420
394cf0a1
S		 421enum {
422 ATH9K_RESET_POWER_ON,
423 ATH9K_RESET_WARM,
424 ATH9K_RESET_COLD,
425};
f078f209 426
d535a42a
S		 427struct ath9k_hw_version {
428 u32 magic;
429 u16 devid;
430 u16 subvendorid;
431 u32 macVersion;
432 u16 macRev;
433 u16 phyRev;
434 u16 analog5GhzRev;
435 u16 analog2GhzRev;
aeac355d 436 u16 subsysid;
0b5ead91 437 enum ath_usb_dev usbdev;
d535a42a 438};
394cf0a1 439
ff155a45
VT		 440/* Generic TSF timer definitions */
441
442#define ATH_MAX_GEN_TIMER 16
443
444#define AR_GENTMR_BIT(_index) (1 << (_index))
445
446/*
77c2061d 447 * Using de Bruijin sequence to look up 1's index in a 32 bit number
ff155a45
VT		 448 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
449 */
c90017dd 450#define debruijn32 0x077CB531U
ff155a45
VT		 451
452struct ath_gen_timer_configuration {
453 u32 next_addr;
454 u32 period_addr;
455 u32 mode_addr;
456 u32 mode_mask;
457};
458
459struct ath_gen_timer {
460 void (*trigger)(void *arg);
461 void (*overflow)(void *arg);
462 void *arg;
463 u8 index;
464};
465
466struct ath_gen_timer_table {
467 u32 gen_timer_index[32];
468 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
469 union {
470 unsigned long timer_bits;
471 u16 val;
472 } timer_mask;
473};
474
21cc630f
VT		 475struct ath_hw_antcomb_conf {
476 u8 main_lna_conf;
477 u8 alt_lna_conf;
478 u8 fast_div_bias;
479};
480
4e8c14e9
FF		 481/**
482 * struct ath_hw_radar_conf - radar detection initialization parameters
483 *
484 * @pulse_inband: threshold for checking the ratio of in-band power
485 * to total power for short radar pulses (half dB steps)
486 * @pulse_inband_step: threshold for checking an in-band power to total
487 * power ratio increase for short radar pulses (half dB steps)
488 * @pulse_height: threshold for detecting the beginning of a short
489 * radar pulse (dB step)
490 * @pulse_rssi: threshold for detecting if a short radar pulse is
491 * gone (dB step)
492 * @pulse_maxlen: maximum pulse length (0.8 us steps)
493 *
494 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
495 * @radar_inband: threshold for checking the ratio of in-band power
496 * to total power for long radar pulses (half dB steps)
497 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
498 *
499 * @ext_channel: enable extension channel radar detection
500 */
501struct ath_hw_radar_conf {
502 unsigned int pulse_inband;
503 unsigned int pulse_inband_step;
504 unsigned int pulse_height;
505 unsigned int pulse_rssi;
506 unsigned int pulse_maxlen;
507
508 unsigned int radar_rssi;
509 unsigned int radar_inband;
510 int fir_power;
511
512 bool ext_channel;
513};
514
d70357d5
LR		 515/**
516 * struct ath_hw_private_ops - callbacks used internally by hardware code
517 *
518 * This structure contains private callbacks designed to only be used internally
519 * by the hardware core.
520 *
795f5e2c
LR		 521 * @init_cal_settings: setup types of calibrations supported
522 * @init_cal: starts actual calibration
523 *
d70357d5 524 * @init_mode_regs: Initializes mode registers
991312d8 525 * @init_mode_gain_regs: Initialize TX/RX gain registers
8fe65368
LR		 526 *
527 * @rf_set_freq: change frequency
528 * @spur_mitigate_freq: spur mitigation
529 * @rf_alloc_ext_banks:
530 * @rf_free_ext_banks:
531 * @set_rf_regs:
64773964
LR		 532 * @compute_pll_control: compute the PLL control value to use for
533 * AR_RTC_PLL_CONTROL for a given channel
795f5e2c
LR		 534 * @setup_calibration: set up calibration
535 * @iscal_supported: used to query if a type of calibration is supported
ac0bb767 536 *
e36b27af
LR		 537 * @ani_cache_ini_regs: cache the values for ANI from the initial
538 * register settings through the register initialization.
d70357d5
LR		 539 */
540struct ath_hw_private_ops {
795f5e2c 541 /* Calibration ops */
d70357d5 542 void (*init_cal_settings)(struct ath_hw *ah);
795f5e2c
LR		 543 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
544
d70357d5 545 void (*init_mode_regs)(struct ath_hw *ah);
991312d8 546 void (*init_mode_gain_regs)(struct ath_hw *ah);
795f5e2c
LR		 547 void (*setup_calibration)(struct ath_hw *ah,
548 struct ath9k_cal_list *currCal);
8fe65368
LR		 549
550 /* PHY ops */
551 int (*rf_set_freq)(struct ath_hw *ah,
552 struct ath9k_channel *chan);
553 void (*spur_mitigate_freq)(struct ath_hw *ah,
554 struct ath9k_channel *chan);
555 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
556 void (*rf_free_ext_banks)(struct ath_hw *ah);
557 bool (*set_rf_regs)(struct ath_hw *ah,
558 struct ath9k_channel *chan,
559 u16 modesIndex);
560 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
561 void (*init_bb)(struct ath_hw *ah,
562 struct ath9k_channel *chan);
563 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
564 void (*olc_init)(struct ath_hw *ah);
565 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
566 void (*mark_phy_inactive)(struct ath_hw *ah);
567 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
568 bool (*rfbus_req)(struct ath_hw *ah);
569 void (*rfbus_done)(struct ath_hw *ah);
8fe65368
LR		 570 void (*restore_chainmask)(struct ath_hw *ah);
571 void (*set_diversity)(struct ath_hw *ah, bool value);
64773964
LR		 572 u32 (*compute_pll_control)(struct ath_hw *ah,
573 struct ath9k_channel *chan);
c16fcb49
FF		 574 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
575 int param);
641d9921 576 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
4e8c14e9
FF		 577 void (*set_radar_params)(struct ath_hw *ah,
578 struct ath_hw_radar_conf *conf);
ac0bb767
LR		 579
580 /* ANI */
e36b27af 581 void (*ani_cache_ini_regs)(struct ath_hw *ah);
d70357d5
LR		 582};
583
584/**
585 * struct ath_hw_ops - callbacks used by hardware code and driver code
586 *
587 * This structure contains callbacks designed to to be used internally by
588 * hardware code and also by the lower level driver.
589 *
590 * @config_pci_powersave:
795f5e2c 591 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
d70357d5
LR		 592 */
593struct ath_hw_ops {
594 void (*config_pci_powersave)(struct ath_hw *ah,
595 int restore,
596 int power_off);
cee1f625 597 void (*rx_enable)(struct ath_hw *ah);
87d5efbb
VT		 598 void (*set_desc_link)(void *ds, u32 link);
599 void (*get_desc_link)(void *ds, u32 **link);
795f5e2c
LR		 600 bool (*calibrate)(struct ath_hw *ah,
601 struct ath9k_channel *chan,
602 u8 rxchainmask,
603 bool longcal);
55e82df4 604 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
cc610ac0
VT		 605 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
606 bool is_firstseg, bool is_is_lastseg,
607 const void *ds0, dma_addr_t buf_addr,
608 unsigned int qcu);
609 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
610 struct ath_tx_status *ts);
611 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
612 u32 pktLen, enum ath9k_pkt_type type,
613 u32 txPower, u32 keyIx,
614 enum ath9k_key_type keyType,
615 u32 flags);
616 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
617 void *lastds,
618 u32 durUpdateEn, u32 rtsctsRate,
619 u32 rtsctsDuration,
620 struct ath9k_11n_rate_series series[],
621 u32 nseries, u32 flags);
622 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
623 u32 aggrLen);
624 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
625 u32 numDelims);
626 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
627 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
628 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
629 u32 burstDuration);
5519541d 630 void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
d70357d5
LR		 631};
632
f2552e28
FF		 633struct ath_nf_limits {
634 s16 max;
635 s16 min;
636 s16 nominal;
637};
638
97dcec57
SM		 639/* ah_flags */
640#define AH_USE_EEPROM 0x1
641#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
642
cbe61d8a 643struct ath_hw {
f9f84e96
FF		 644 struct ath_ops reg_ops;
645
b002a4a9 646 struct ieee80211_hw *hw;
27c51f1a 647 struct ath_common common;
cbe61d8a 648 struct ath9k_hw_version hw_version;
2660b81a
S		 649 struct ath9k_ops_config config;
650 struct ath9k_hw_capabilities caps;
cac4220b 651 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
2660b81a 652 struct ath9k_channel *curchan;
394cf0a1 653
cbe61d8a
S		 654 union {
655 struct ar5416_eeprom_def def;
656 struct ar5416_eeprom_4k map4k;
475f5989 657 struct ar9287_eeprom map9287;
15c9ee7a 658 struct ar9300_eeprom ar9300_eep;
2660b81a 659 } eeprom;
f74df6fb 660 const struct eeprom_ops *eep_ops;
cbe61d8a
S		 661
662 bool sw_mgmt_crypto;
2660b81a 663 bool is_pciexpress;
5f841b41 664 bool is_monitoring;
2eb46d9b 665 bool need_an_top2_fixup;
2660b81a 666 u16 tx_trig_level;
f2552e28 667
bbacee13 668 u32 nf_regs[6];
f2552e28
FF		 669 struct ath_nf_limits nf_2g;
670 struct ath_nf_limits nf_5g;
2660b81a
S		 671 u16 rfsilent;
672 u32 rfkill_gpio;
673 u32 rfkill_polarity;
cbe61d8a 674 u32 ah_flags;
394cf0a1 675
d7e7d229
LR		 676 bool htc_reset_init;
677
2660b81a
S		 678 enum nl80211_iftype opmode;
679 enum ath9k_power_mode power_mode;
f078f209 680
20bd2a09 681 struct ath9k_hw_cal_data *caldata;
a13883b0 682 struct ath9k_pacal_info pacal_info;
2660b81a
S		 683 struct ar5416Stats stats;
684 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
685
686 int16_t curchan_rad_index;
3069168c 687 enum ath9k_int imask;
74bad5cb 688 u32 imrs2_reg;
2660b81a
S		 689 u32 txok_interrupt_mask;
690 u32 txerr_interrupt_mask;
691 u32 txdesc_interrupt_mask;
692 u32 txeol_interrupt_mask;
693 u32 txurn_interrupt_mask;
694 bool chip_fullsleep;
695 u32 atim_window;
6a2b9e8c
S		 696
697 /* Calibration */
6497827f 698 u32 supp_cals;
cbfe9468
S		 699 struct ath9k_cal_list iq_caldata;
700 struct ath9k_cal_list adcgain_caldata;
cbfe9468 701 struct ath9k_cal_list adcdc_caldata;
df23acaa 702 struct ath9k_cal_list tempCompCalData;
cbfe9468
S		 703 struct ath9k_cal_list *cal_list;
704 struct ath9k_cal_list *cal_list_last;
705 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 706#define totalPowerMeasI meas0.unsign
707#define totalPowerMeasQ meas1.unsign
708#define totalIqCorrMeas meas2.sign
709#define totalAdcIOddPhase meas0.unsign
710#define totalAdcIEvenPhase meas1.unsign
711#define totalAdcQOddPhase meas2.unsign
712#define totalAdcQEvenPhase meas3.unsign
713#define totalAdcDcOffsetIOddPhase meas0.sign
714#define totalAdcDcOffsetIEvenPhase meas1.sign
715#define totalAdcDcOffsetQOddPhase meas2.sign
716#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 717 union {
718 u32 unsign[AR5416_MAX_CHAINS];
719 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 720 } meas0;
f078f209
LR		 721 union {
722 u32 unsign[AR5416_MAX_CHAINS];
723 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 724 } meas1;
f078f209
LR		 725 union {
726 u32 unsign[AR5416_MAX_CHAINS];
727 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 728 } meas2;
f078f209
LR		 729 union {
730 u32 unsign[AR5416_MAX_CHAINS];
731 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 732 } meas3;
733 u16 cal_samples;
6a2b9e8c 734
2660b81a
S		 735 u32 sta_id1_defaults;
736 u32 misc_mode;
f078f209
LR		 737 enum {
738 AUTO_32KHZ,
739 USE_32KHZ,
740 DONT_USE_32KHZ,
2660b81a 741 } enable_32kHz_clock;
6a2b9e8c 742
d70357d5
LR		 743 /* Private to hardware code */
744 struct ath_hw_private_ops private_ops;
745 /* Accessed by the lower level driver */
746 struct ath_hw_ops ops;
747
e68a060b 748 /* Used to program the radio on non single-chip devices */
2660b81a
S		 749 u32 *analogBank0Data;
750 u32 *analogBank1Data;
751 u32 *analogBank2Data;
752 u32 *analogBank3Data;
753 u32 *analogBank6Data;
754 u32 *analogBank6TPCData;
755 u32 *analogBank7Data;
756 u32 *addac5416_21;
757 u32 *bank6Temp;
758
597a94b3 759 u8 txpower_limit;
e239d859 760 int coverage_class;
2660b81a 761 u32 slottime;
2660b81a 762 u32 globaltxtimeout;
6a2b9e8c
S		 763
764 /* ANI */
2660b81a 765 u32 proc_phyerr;
2660b81a 766 u32 aniperiod;
2660b81a
S		 767 int totalSizeDesired[5];
768 int coarse_high[5];
769 int coarse_low[5];
770 int firpwr[5];
771 enum ath9k_ani_cmd ani_function;
772
af03abec 773 /* Bluetooth coexistance */
766ec4a9 774 struct ath_btcoex_hw btcoex_hw;
af03abec 775
2660b81a 776 u32 intr_txqs;
2660b81a
S		 777 u8 txchainmask;
778 u8 rxchainmask;
779
c5d0855a
FF		 780 struct ath_hw_radar_conf radar_conf;
781
8bd1d07f
SB		 782 u32 originalGain[22];
783 int initPDADC;
784 int PDADCdelta;
6de66dd9 785 int led_pin;
691680b8
FF		 786 u32 gpio_mask;
787 u32 gpio_val;
8bd1d07f 788
2660b81a
S		 789 struct ar5416IniArray iniModes;
790 struct ar5416IniArray iniCommon;
791 struct ar5416IniArray iniBank0;
792 struct ar5416IniArray iniBB_RfGain;
793 struct ar5416IniArray iniBank1;
794 struct ar5416IniArray iniBank2;
795 struct ar5416IniArray iniBank3;
796 struct ar5416IniArray iniBank6;
797 struct ar5416IniArray iniBank6TPC;
798 struct ar5416IniArray iniBank7;
799 struct ar5416IniArray iniAddac;
800 struct ar5416IniArray iniPcieSerdes;
13ce3e99 801 struct ar5416IniArray iniPcieSerdesLowPower;
2660b81a
S		 802 struct ar5416IniArray iniModesAdditional;
803 struct ar5416IniArray iniModesRxGain;
804 struct ar5416IniArray iniModesTxGain;
8564328d 805 struct ar5416IniArray iniModes_9271_1_0_only;
193cd458
S		 806 struct ar5416IniArray iniCckfirNormal;
807 struct ar5416IniArray iniCckfirJapan2484;
70807e99
S		 808 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
809 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
810 struct ar5416IniArray iniModes_9271_ANI_reg;
811 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
812 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
ff155a45 813
13ce3e99
LR		 814 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
815 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
816 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
817 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
818
ff155a45
VT		 819 u32 intr_gen_timer_trigger;
820 u32 intr_gen_timer_thresh;
821 struct ath_gen_timer_table hw_gen_timers;
744d4025
VT		 822
823 struct ar9003_txs *ts_ring;
824 void *ts_start;
825 u32 ts_paddr_start;
826 u32 ts_paddr_end;
827 u16 ts_tail;
828 u8 ts_size;
aea702b7
LR		 829
830 u32 bb_watchdog_last_status;
831 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
717f6bed 832
1bf38661
FF		 833 unsigned int paprd_target_power;
834 unsigned int paprd_training_power;
7072bf62 835 unsigned int paprd_ratemask;
f1a8abb0 836 unsigned int paprd_ratemask_ht40;
45ef6a0b 837 bool paprd_table_write_done;
717f6bed
FF		 838 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
839 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
9a658d2b
LR		 840 /*
841 * Store the permanent value of Reg 0x4004in WARegVal
842 * so we dont have to R/M/W. We should not be reading
843 * this register when in sleep states.
844 */
845 u32 WARegVal;
6ee63f55
SB		 846
847 /* Enterprise mode cap */
848 u32 ent_mode;
f078f209 849};
f078f209 850
0cb9e06b
FF		 851struct ath_bus_ops {
852 enum ath_bus_type ath_bus_type;
853 void (*read_cachesize)(struct ath_common *common, int *csz);
854 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
855 void (*bt_coex_prep)(struct ath_common *common);
856 void (*extn_synch_en)(struct ath_common *common);
857};
858
9e4bffd2
LR		 859static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
860{
861 return &ah->common;
862}
863
864static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
865{
866 return &(ath9k_hw_common(ah)->regulatory);
867}
868
d70357d5
LR		 869static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
870{
871 return &ah->private_ops;
872}
873
874static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
875{
876 return &ah->ops;
877}
878
895ad7eb
VT		 879static inline u8 get_streams(int mask)
880{
881 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
882}
883
f637cfd6 884/* Initialization, Detach, Reset */
394cf0a1 885const char *ath9k_hw_probe(u16 vendorid, u16 devid);
285f2dda 886void ath9k_hw_deinit(struct ath_hw *ah);
f637cfd6 887int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 888int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 889 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
a9a29ce6 890int ath9k_hw_fill_cap_info(struct ath_hw *ah);
8fe65368 891u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
394cf0a1 892
394cf0a1 893/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 894void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
895u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
896void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 897 u32 ah_signal_type);
cbe61d8a 898void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 899u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
900void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
21cc630f
VT		 901void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
902 struct ath_hw_antcomb_conf *antconf);
903void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
904 struct ath_hw_antcomb_conf *antconf);
394cf0a1
S		 905
906/* General Operation */
0caa7b14 907bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
a9b6b256
FF		 908void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
909 int column, unsigned int *writecnt);
394cf0a1 910u32 ath9k_hw_reverse_bits(u32 val, u32 n);
4f0fc7c3 911u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 912 u8 phy, int kbps,
394cf0a1 913 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 914void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 915 struct ath9k_channel *chan,
916 struct chan_centers *centers);
cbe61d8a
S		 917u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
918void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
919bool ath9k_hw_phy_disable(struct ath_hw *ah);
920bool ath9k_hw_disable(struct ath_hw *ah);
de40f316 921void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
cbe61d8a
S		 922void ath9k_hw_setopmode(struct ath_hw *ah);
923void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 924void ath9k_hw_setbssidmask(struct ath_hw *ah);
925void ath9k_hw_write_associd(struct ath_hw *ah);
dd347f2f 926u32 ath9k_hw_gettsf32(struct ath_hw *ah);
cbe61d8a
S		 927u64 ath9k_hw_gettsf64(struct ath_hw *ah);
928void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
929void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 930void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
0005baf4 931void ath9k_hw_init_global_settings(struct ath_hw *ah);
b1415819 932unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
25c56eec 933void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 934void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
935void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 936 const struct ath9k_beacon_state *bs);
c9c99e5e 937bool ath9k_hw_check_alive(struct ath_hw *ah);
a91d75ae 938
9ecdef4b 939bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 940
ff155a45
VT		 941/* Generic hw timer primitives */
942struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
943 void (*trigger)(void *),
944 void (*overflow)(void *),
945 void *arg,
946 u8 timer_index);
cd9bf689
LR		 947void ath9k_hw_gen_timer_start(struct ath_hw *ah,
948 struct ath_gen_timer *timer,
949 u32 timer_next,
950 u32 timer_period);
951void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
952
ff155a45
VT		 953void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
954void ath_gen_timer_isr(struct ath_hw *hw);
955
f934c4d9 956void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 957
05020d23
S		 958/* HTC */
959void ath9k_hw_htc_resetinit(struct ath_hw *ah);
960
8fe65368
LR		 961/* PHY */
962void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
963 u32 *coef_mantissa, u32 *coef_exponent);
964
ebd5a14a
LR		 965/*
966 * Code Specific to AR5008, AR9001 or AR9002,
967 * we stuff these here to avoid callbacks for AR9003.
968 */
d8f492b7 969void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
ebd5a14a 970int ar9002_hw_rf_claim(struct ath_hw *ah);
78ec2677 971void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
e9141f71 972void ar9002_hw_update_async_fifo(struct ath_hw *ah);
6c94fdc9 973void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
d8f492b7 974
641d9921 975/*
aea702b7 976 * Code specific to AR9003, we stuff these here to avoid callbacks
641d9921
FF		 977 * for older families
978 */
aea702b7
LR		 979void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
980void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
981void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
717f6bed
FF		 982void ar9003_paprd_enable(struct ath_hw *ah, bool val);
983void ar9003_paprd_populate_single_table(struct ath_hw *ah,
20bd2a09
FF		 984 struct ath9k_hw_cal_data *caldata,
985 int chain);
986int ar9003_paprd_create_curve(struct ath_hw *ah,
987 struct ath9k_hw_cal_data *caldata, int chain);
717f6bed
FF		 988int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
989int ar9003_paprd_init_table(struct ath_hw *ah);
990bool ar9003_paprd_is_done(struct ath_hw *ah);
991void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
641d9921
FF		 992
993/* Hardware family op attach helpers */
8fe65368 994void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
8525f280
LR		 995void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
996void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
8fe65368 997
795f5e2c
LR		 998void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
999void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1000
b3950e6a
LR		 1001void ar9002_hw_attach_ops(struct ath_hw *ah);
1002void ar9003_hw_attach_ops(struct ath_hw *ah);
1003
c2ba3342 1004void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767
LR		 1005/*
1006 * ANI work can be shared between all families but a next
1007 * generation implementation of ANI will be used only for AR9003 only
1008 * for now as the other families still need to be tested with the same
e36b27af
LR		 1009 * next generation ANI. Feel free to start testing it though for the
1010 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
ac0bb767 1011 */
e36b27af 1012extern int modparam_force_new_ani;
8eb4980c 1013void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
bfc472bb 1014void ath9k_hw_proc_mib_event(struct ath_hw *ah);
95792178 1015void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767 1016
7b6840ab
VT		 1017#define ATH_PCIE_CAP_LINK_CTRL 0x70
1018#define ATH_PCIE_CAP_LINK_L0S 1
1019#define ATH_PCIE_CAP_LINK_L1 2
1020
73377256
LR		 1021#define ATH9K_CLOCK_RATE_CCK 22
1022#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1023#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1024#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1025
f078f209 1026#endif
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