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mac80211: bracket driver tracing
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
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f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
c46917bb 33#include "../debug.h"
3a702e49 34
394cf0a1 35#define ATHEROS_VENDOR_ID 0x168c
7976b426 36
394cf0a1
S		 37#define AR5416_DEVID_PCI 0x0023
38#define AR5416_DEVID_PCIE 0x0024
39#define AR9160_DEVID_PCI 0x0027
40#define AR9280_DEVID_PCI 0x0029
41#define AR9280_DEVID_PCIE 0x002a
42#define AR9285_DEVID_PCIE 0x002b
5ffaf8a3 43#define AR2427_DEVID_PCIE 0x002c
db3cc53a
SB		 44#define AR9287_DEVID_PCI 0x002d
45#define AR9287_DEVID_PCIE 0x002e
46#define AR9300_DEVID_PCIE 0x0030
7976b426 47
394cf0a1 48#define AR5416_AR9100_DEVID 0x000b
7976b426 49
394cf0a1
S		 50#define AR_SUBVENDOR_ID_NOG 0x0e11
51#define AR_SUBVENDOR_ID_NEW_A 0x7065
52#define AR5416_MAGIC 0x19641014
53
fe12946e
VT		 54#define AR9280_COEX2WIRE_SUBSYSID 0x309b
55#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
57
e3d01bfc
LR		 58#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
59
cfe8cba9
LR		 60#define ATH_DEFAULT_NOISE_FLOOR -95
61
04658fba 62#define ATH9K_RSSI_BAD -128
990b70ab 63
394cf0a1 64/* Register read/write primitives */
9e4bffd2
LR		 65#define REG_WRITE(_ah, _reg, _val) \
66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
67
68#define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
394cf0a1 70
20b3efd9
S		 71#define ENABLE_REGWRITE_BUFFER(_ah) \
72 do { \
73 if (AR_SREV_9271(_ah)) \
74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
75 } while (0)
76
77#define DISABLE_REGWRITE_BUFFER(_ah) \
78 do { \
79 if (AR_SREV_9271(_ah)) \
80 ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
81 } while (0)
82
83#define REGWRITE_BUFFER_FLUSH(_ah) \
84 do { \
85 if (AR_SREV_9271(_ah)) \
86 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
87 } while (0)
88
394cf0a1
S		 89#define SM(_v, _f) (((_v) << _f##_S) & _f)
90#define MS(_v, _f) (((_v) & _f) >> _f##_S)
91#define REG_RMW(_a, _r, _set, _clr) \
92 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
93#define REG_RMW_FIELD(_a, _r, _f, _v) \
94 REG_WRITE(_a, _r, \
95 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
1547da37
LR		 96#define REG_READ_FIELD(_a, _r, _f) \
97 (((REG_READ(_a, _r) & _f) >> _f##_S))
394cf0a1
S		 98#define REG_SET_BIT(_a, _r, _f) \
99 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
100#define REG_CLR_BIT(_a, _r, _f) \
101 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 102
394cf0a1
S		 103#define DO_DELAY(x) do { \
104 if ((++(x) % 64) == 0) \
105 udelay(1); \
106 } while (0)
f078f209 107
394cf0a1
S		 108#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
109 int r; \
110 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
111 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
112 INI_RA((iniarray), r, (column))); \
113 DO_DELAY(regWr); \
114 } \
115 } while (0)
f078f209 116
394cf0a1
S		 117#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
118#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
119#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
120#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 121#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 122#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
123#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 124
394cf0a1
S		 125#define AR_GPIOD_MASK 0x00001FFF
126#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 127
394cf0a1 128#define BASE_ACTIVATE_DELAY 100
63a75b91 129#define RTC_PLL_SETTLE_DELAY 100
394cf0a1
S		 130#define COEF_SCALE_S 24
131#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 132
394cf0a1
S		 133#define ATH9K_ANTENNA0_CHAINMASK 0x1
134#define ATH9K_ANTENNA1_CHAINMASK 0x2
135
136#define ATH9K_NUM_DMA_DEBUG_REGS 8
137#define ATH9K_NUM_QUEUES 10
138
139#define MAX_RATE_POWER 63
0caa7b14 140#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 141#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 142#define AH_TIME_QUANTUM 10
143#define AR_KEYTABLE_SIZE 128
d8caa839 144#define POWER_UP_TIME 10000
394cf0a1
S		 145#define SPUR_RSSI_THRESH 40
146
147#define CAB_TIMEOUT_VAL 10
148#define BEACON_TIMEOUT_VAL 10
149#define MIN_BEACON_TIMEOUT_VAL 1
150#define SLEEP_SLOP 3
151
152#define INIT_CONFIG_STATUS 0x00000000
153#define INIT_RSSI_THR 0x00000700
154#define INIT_BCON_CNTRL_REG 0x00000000
155
156#define TU_TO_USEC(_tu) ((_tu) << 10)
157
ceb26445
VT		 158#define ATH9K_HW_RX_HP_QDEPTH 16
159#define ATH9K_HW_RX_LP_QDEPTH 128
160
13ce3e99
LR		 161enum ath_ini_subsys {
162 ATH_INI_PRE = 0,
163 ATH_INI_CORE,
164 ATH_INI_POST,
165 ATH_INI_NUM_SPLIT,
166};
167
394cf0a1
S		 168enum wireless_mode {
169 ATH9K_MODE_11A = 0,
b9b6e15a
LR		 170 ATH9K_MODE_11G,
171 ATH9K_MODE_11NA_HT20,
172 ATH9K_MODE_11NG_HT20,
173 ATH9K_MODE_11NA_HT40PLUS,
174 ATH9K_MODE_11NA_HT40MINUS,
175 ATH9K_MODE_11NG_HT40PLUS,
176 ATH9K_MODE_11NG_HT40MINUS,
177 ATH9K_MODE_MAX,
394cf0a1 178};
f078f209 179
394cf0a1 180enum ath9k_hw_caps {
bdbdf46d
S		 181 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
182 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
183 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
184 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
185 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
186 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
187 ATH9K_HW_CAP_VEOL = BIT(6),
188 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
189 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
190 ATH9K_HW_CAP_HT = BIT(9),
191 ATH9K_HW_CAP_GTT = BIT(10),
192 ATH9K_HW_CAP_FASTCC = BIT(11),
193 ATH9K_HW_CAP_RFSILENT = BIT(12),
194 ATH9K_HW_CAP_CST = BIT(13),
195 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
196 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
197 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
1adf02ff 198 ATH9K_HW_CAP_EDMA = BIT(17),
6c84ce08 199 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
ce01805a 200 ATH9K_HW_CAP_LDPC = BIT(19),
e5553724 201 ATH9K_HW_CAP_FASTCLOCK = BIT(20),
6473d24d 202 ATH9K_HW_CAP_SGI_20 = BIT(21),
394cf0a1 203};
f078f209 204
394cf0a1
S		 205enum ath9k_capability_type {
206 ATH9K_CAP_CIPHER = 0,
207 ATH9K_CAP_TKIP_MIC,
208 ATH9K_CAP_TKIP_SPLIT,
394cf0a1 209 ATH9K_CAP_TXPOW,
394cf0a1 210 ATH9K_CAP_MCAST_KEYSRCH,
8bd1d07f 211 ATH9K_CAP_DS
394cf0a1 212};
f078f209 213
394cf0a1
S		 214struct ath9k_hw_capabilities {
215 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
216 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
217 u16 total_queues;
218 u16 keycache_size;
219 u16 low_5ghz_chan, high_5ghz_chan;
220 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 221 u16 rts_aggr_limit;
222 u8 tx_chainmask;
223 u8 rx_chainmask;
224 u16 tx_triglevel_max;
225 u16 reg_cap;
226 u8 num_gpio_pins;
227 u8 num_antcfg_2ghz;
228 u8 num_antcfg_5ghz;
ceb26445
VT		 229 u8 rx_hp_qdepth;
230 u8 rx_lp_qdepth;
231 u8 rx_status_len;
162c3be3 232 u8 tx_desc_len;
5088c2f1 233 u8 txs_len;
394cf0a1 234};
f078f209 235
394cf0a1
S		 236struct ath9k_ops_config {
237 int dma_beacon_response_time;
238 int sw_beacon_response_time;
239 int additional_swba_backoff;
240 int ack_6mb;
241 int cwm_ignore_extcca;
242 u8 pcie_powersave_enable;
394cf0a1
S		 243 u8 pcie_clock_req;
244 u32 pcie_waen;
394cf0a1
S		 245 u8 analog_shiftreg;
246 u8 ht_enable;
247 u32 ofdm_trig_low;
248 u32 ofdm_trig_high;
249 u32 cck_trig_high;
250 u32 cck_trig_low;
251 u32 enable_ani;
394cf0a1 252 int serialize_regmode;
0ce024cb 253 bool rx_intr_mitigation;
55e82df4 254 bool tx_intr_mitigation;
394cf0a1
S		 255#define SPUR_DISABLE 0
256#define SPUR_ENABLE_IOCTL 1
257#define SPUR_ENABLE_EEPROM 2
258#define AR_EEPROM_MODAL_SPURS 5
259#define AR_SPUR_5413_1 1640
260#define AR_SPUR_5413_2 1200
261#define AR_NO_SPUR 0x8000
262#define AR_BASE_FREQ_2GHZ 2300
263#define AR_BASE_FREQ_5GHZ 4900
264#define AR_SPUR_FEEQ_BOUND_HT40 19
265#define AR_SPUR_FEEQ_BOUND_HT20 10
266 int spurmode;
267 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 268 u8 max_txtrig_level;
394cf0a1 269};
f078f209 270
394cf0a1
S		 271enum ath9k_int {
272 ATH9K_INT_RX = 0x00000001,
273 ATH9K_INT_RXDESC = 0x00000002,
b5c80475
FF		 274 ATH9K_INT_RXHP = 0x00000001,
275 ATH9K_INT_RXLP = 0x00000002,
394cf0a1
S		 276 ATH9K_INT_RXNOFRM = 0x00000008,
277 ATH9K_INT_RXEOL = 0x00000010,
278 ATH9K_INT_RXORN = 0x00000020,
279 ATH9K_INT_TX = 0x00000040,
280 ATH9K_INT_TXDESC = 0x00000080,
281 ATH9K_INT_TIM_TIMER = 0x00000100,
aea702b7 282 ATH9K_INT_BB_WATCHDOG = 0x00000400,
394cf0a1
S		 283 ATH9K_INT_TXURN = 0x00000800,
284 ATH9K_INT_MIB = 0x00001000,
285 ATH9K_INT_RXPHY = 0x00004000,
286 ATH9K_INT_RXKCM = 0x00008000,
287 ATH9K_INT_SWBA = 0x00010000,
288 ATH9K_INT_BMISS = 0x00040000,
289 ATH9K_INT_BNR = 0x00100000,
290 ATH9K_INT_TIM = 0x00200000,
291 ATH9K_INT_DTIM = 0x00400000,
292 ATH9K_INT_DTIMSYNC = 0x00800000,
293 ATH9K_INT_GPIO = 0x01000000,
294 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 295 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 296 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 297 ATH9K_INT_CST = 0x10000000,
298 ATH9K_INT_GTT = 0x20000000,
299 ATH9K_INT_FATAL = 0x40000000,
300 ATH9K_INT_GLOBAL = 0x80000000,
301 ATH9K_INT_BMISC = ATH9K_INT_TIM |
302 ATH9K_INT_DTIM |
303 ATH9K_INT_DTIMSYNC |
4af9cf4f 304 ATH9K_INT_TSFOOR |
394cf0a1
S		 305 ATH9K_INT_CABEND,
306 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
307 ATH9K_INT_RXDESC |
308 ATH9K_INT_RXEOL |
309 ATH9K_INT_RXORN |
310 ATH9K_INT_TXURN |
311 ATH9K_INT_TXDESC |
312 ATH9K_INT_MIB |
313 ATH9K_INT_RXPHY |
314 ATH9K_INT_RXKCM |
315 ATH9K_INT_SWBA |
316 ATH9K_INT_BMISS |
317 ATH9K_INT_GPIO,
318 ATH9K_INT_NOCARD = 0xffffffff
319};
f078f209 320
394cf0a1
S		 321#define CHANNEL_CW_INT 0x00002
322#define CHANNEL_CCK 0x00020
323#define CHANNEL_OFDM 0x00040
324#define CHANNEL_2GHZ 0x00080
325#define CHANNEL_5GHZ 0x00100
326#define CHANNEL_PASSIVE 0x00200
327#define CHANNEL_DYN 0x00400
328#define CHANNEL_HALF 0x04000
329#define CHANNEL_QUARTER 0x08000
330#define CHANNEL_HT20 0x10000
331#define CHANNEL_HT40PLUS 0x20000
332#define CHANNEL_HT40MINUS 0x40000
333
394cf0a1
S		 334#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
335#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
336#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
337#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
338#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
339#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
340#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
341#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
342#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
343#define CHANNEL_ALL \
344 (CHANNEL_OFDM| \
345 CHANNEL_CCK| \
346 CHANNEL_2GHZ | \
347 CHANNEL_5GHZ | \
348 CHANNEL_HT20 | \
349 CHANNEL_HT40PLUS | \
350 CHANNEL_HT40MINUS)
351
352struct ath9k_channel {
353 struct ieee80211_channel *chan;
354 u16 channel;
355 u32 channelFlags;
356 u32 chanmode;
357 int32_t CalValid;
358 bool oneTimeCalsDone;
359 int8_t iCoff;
360 int8_t qCoff;
361 int16_t rawNoiseFloor;
362};
f078f209 363
394cf0a1
S		 364#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
365 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
366 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
367 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
368#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
369#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
370#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 371#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
372#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
6b42e8d0 373#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
394cf0a1 374 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
6b42e8d0 375 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
394cf0a1
S		 376
377/* These macros check chanmode and not channelFlags */
378#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
379#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
380 ((_c)->chanmode == CHANNEL_G_HT20))
381#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
382 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
383 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
384 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
385#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
386
387enum ath9k_power_mode {
388 ATH9K_PM_AWAKE = 0,
389 ATH9K_PM_FULL_SLEEP,
390 ATH9K_PM_NETWORK_SLEEP,
391 ATH9K_PM_UNDEFINED
392};
f078f209 393
394cf0a1
S		 394enum ath9k_tp_scale {
395 ATH9K_TP_SCALE_MAX = 0,
396 ATH9K_TP_SCALE_50,
397 ATH9K_TP_SCALE_25,
398 ATH9K_TP_SCALE_12,
399 ATH9K_TP_SCALE_MIN
400};
f078f209 401
394cf0a1
S		 402enum ser_reg_mode {
403 SER_REG_MODE_OFF = 0,
404 SER_REG_MODE_ON = 1,
405 SER_REG_MODE_AUTO = 2,
406};
f078f209 407
ad7b8060
VT		 408enum ath9k_rx_qtype {
409 ATH9K_RX_QUEUE_HP,
410 ATH9K_RX_QUEUE_LP,
411 ATH9K_RX_QUEUE_MAX,
412};
413
394cf0a1
S		 414struct ath9k_beacon_state {
415 u32 bs_nexttbtt;
416 u32 bs_nextdtim;
417 u32 bs_intval;
418#define ATH9K_BEACON_PERIOD 0x0000ffff
419#define ATH9K_BEACON_ENA 0x00800000
420#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 421#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 422 u32 bs_dtimperiod;
423 u16 bs_cfpperiod;
424 u16 bs_cfpmaxduration;
425 u32 bs_cfpnext;
426 u16 bs_timoffset;
427 u16 bs_bmissthreshold;
428 u32 bs_sleepduration;
4af9cf4f 429 u32 bs_tsfoor_threshold;
394cf0a1 430};
f078f209 431
394cf0a1
S		 432struct chan_centers {
433 u16 synth_center;
434 u16 ctl_center;
435 u16 ext_center;
436};
f078f209 437
394cf0a1
S		 438enum {
439 ATH9K_RESET_POWER_ON,
440 ATH9K_RESET_WARM,
441 ATH9K_RESET_COLD,
442};
f078f209 443
d535a42a
S		 444struct ath9k_hw_version {
445 u32 magic;
446 u16 devid;
447 u16 subvendorid;
448 u32 macVersion;
449 u16 macRev;
450 u16 phyRev;
451 u16 analog5GhzRev;
452 u16 analog2GhzRev;
aeac355d 453 u16 subsysid;
d535a42a 454};
394cf0a1 455
ff155a45
VT		 456/* Generic TSF timer definitions */
457
458#define ATH_MAX_GEN_TIMER 16
459
460#define AR_GENTMR_BIT(_index) (1 << (_index))
461
462/*
77c2061d 463 * Using de Bruijin sequence to look up 1's index in a 32 bit number
ff155a45
VT		 464 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
465 */
c90017dd 466#define debruijn32 0x077CB531U
ff155a45
VT		 467
468struct ath_gen_timer_configuration {
469 u32 next_addr;
470 u32 period_addr;
471 u32 mode_addr;
472 u32 mode_mask;
473};
474
475struct ath_gen_timer {
476 void (*trigger)(void *arg);
477 void (*overflow)(void *arg);
478 void *arg;
479 u8 index;
480};
481
482struct ath_gen_timer_table {
483 u32 gen_timer_index[32];
484 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
485 union {
486 unsigned long timer_bits;
487 u16 val;
488 } timer_mask;
489};
490
d70357d5
LR		 491/**
492 * struct ath_hw_private_ops - callbacks used internally by hardware code
493 *
494 * This structure contains private callbacks designed to only be used internally
495 * by the hardware core.
496 *
795f5e2c
LR		 497 * @init_cal_settings: setup types of calibrations supported
498 * @init_cal: starts actual calibration
499 *
d70357d5 500 * @init_mode_regs: Initializes mode registers
991312d8 501 * @init_mode_gain_regs: Initialize TX/RX gain registers
d70357d5 502 * @macversion_supported: If this specific mac revision is supported
8fe65368
LR		 503 *
504 * @rf_set_freq: change frequency
505 * @spur_mitigate_freq: spur mitigation
506 * @rf_alloc_ext_banks:
507 * @rf_free_ext_banks:
508 * @set_rf_regs:
64773964
LR		 509 * @compute_pll_control: compute the PLL control value to use for
510 * AR_RTC_PLL_CONTROL for a given channel
795f5e2c
LR		 511 * @setup_calibration: set up calibration
512 * @iscal_supported: used to query if a type of calibration is supported
77d6d39a 513 * @loadnf: load noise floor read from each chain on the CCA registers
d70357d5
LR		 514 */
515struct ath_hw_private_ops {
795f5e2c 516 /* Calibration ops */
d70357d5 517 void (*init_cal_settings)(struct ath_hw *ah);
795f5e2c
LR		 518 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
519
d70357d5 520 void (*init_mode_regs)(struct ath_hw *ah);
991312d8 521 void (*init_mode_gain_regs)(struct ath_hw *ah);
d70357d5 522 bool (*macversion_supported)(u32 macversion);
795f5e2c
LR		 523 void (*setup_calibration)(struct ath_hw *ah,
524 struct ath9k_cal_list *currCal);
525 bool (*iscal_supported)(struct ath_hw *ah,
526 enum ath9k_cal_types calType);
8fe65368
LR		 527
528 /* PHY ops */
529 int (*rf_set_freq)(struct ath_hw *ah,
530 struct ath9k_channel *chan);
531 void (*spur_mitigate_freq)(struct ath_hw *ah,
532 struct ath9k_channel *chan);
533 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
534 void (*rf_free_ext_banks)(struct ath_hw *ah);
535 bool (*set_rf_regs)(struct ath_hw *ah,
536 struct ath9k_channel *chan,
537 u16 modesIndex);
538 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
539 void (*init_bb)(struct ath_hw *ah,
540 struct ath9k_channel *chan);
541 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
542 void (*olc_init)(struct ath_hw *ah);
543 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
544 void (*mark_phy_inactive)(struct ath_hw *ah);
545 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
546 bool (*rfbus_req)(struct ath_hw *ah);
547 void (*rfbus_done)(struct ath_hw *ah);
548 void (*enable_rfkill)(struct ath_hw *ah);
549 void (*restore_chainmask)(struct ath_hw *ah);
550 void (*set_diversity)(struct ath_hw *ah, bool value);
64773964
LR		 551 u32 (*compute_pll_control)(struct ath_hw *ah,
552 struct ath9k_channel *chan);
c16fcb49
FF		 553 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
554 int param);
641d9921 555 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
77d6d39a 556 void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
d70357d5
LR		 557};
558
559/**
560 * struct ath_hw_ops - callbacks used by hardware code and driver code
561 *
562 * This structure contains callbacks designed to to be used internally by
563 * hardware code and also by the lower level driver.
564 *
565 * @config_pci_powersave:
795f5e2c 566 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
d70357d5
LR		 567 */
568struct ath_hw_ops {
569 void (*config_pci_powersave)(struct ath_hw *ah,
570 int restore,
571 int power_off);
cee1f625 572 void (*rx_enable)(struct ath_hw *ah);
87d5efbb
VT		 573 void (*set_desc_link)(void *ds, u32 link);
574 void (*get_desc_link)(void *ds, u32 **link);
795f5e2c
LR		 575 bool (*calibrate)(struct ath_hw *ah,
576 struct ath9k_channel *chan,
577 u8 rxchainmask,
578 bool longcal);
55e82df4 579 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
cc610ac0
VT		 580 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
581 bool is_firstseg, bool is_is_lastseg,
582 const void *ds0, dma_addr_t buf_addr,
583 unsigned int qcu);
584 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
585 struct ath_tx_status *ts);
586 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
587 u32 pktLen, enum ath9k_pkt_type type,
588 u32 txPower, u32 keyIx,
589 enum ath9k_key_type keyType,
590 u32 flags);
591 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
592 void *lastds,
593 u32 durUpdateEn, u32 rtsctsRate,
594 u32 rtsctsDuration,
595 struct ath9k_11n_rate_series series[],
596 u32 nseries, u32 flags);
597 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
598 u32 aggrLen);
599 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
600 u32 numDelims);
601 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
602 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
603 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
604 u32 burstDuration);
605 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
606 u32 vmf);
d70357d5
LR		 607};
608
cbe61d8a 609struct ath_hw {
b002a4a9 610 struct ieee80211_hw *hw;
27c51f1a 611 struct ath_common common;
cbe61d8a 612 struct ath9k_hw_version hw_version;
2660b81a
S		 613 struct ath9k_ops_config config;
614 struct ath9k_hw_capabilities caps;
2660b81a
S		 615 struct ath9k_channel channels[38];
616 struct ath9k_channel *curchan;
394cf0a1 617
cbe61d8a
S		 618 union {
619 struct ar5416_eeprom_def def;
620 struct ar5416_eeprom_4k map4k;
475f5989 621 struct ar9287_eeprom map9287;
15c9ee7a 622 struct ar9300_eeprom ar9300_eep;
2660b81a 623 } eeprom;
f74df6fb 624 const struct eeprom_ops *eep_ops;
cbe61d8a
S		 625
626 bool sw_mgmt_crypto;
2660b81a 627 bool is_pciexpress;
2eb46d9b 628 bool need_an_top2_fixup;
2660b81a 629 u16 tx_trig_level;
641d9921
FF		 630 s16 nf_2g_max;
631 s16 nf_2g_min;
632 s16 nf_5g_max;
633 s16 nf_5g_min;
2660b81a
S		 634 u16 rfsilent;
635 u32 rfkill_gpio;
636 u32 rfkill_polarity;
cbe61d8a 637 u32 ah_flags;
394cf0a1 638
d7e7d229
LR		 639 bool htc_reset_init;
640
2660b81a
S		 641 enum nl80211_iftype opmode;
642 enum ath9k_power_mode power_mode;
f078f209 643
cbe61d8a 644 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
a13883b0 645 struct ath9k_pacal_info pacal_info;
2660b81a
S		 646 struct ar5416Stats stats;
647 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
648
649 int16_t curchan_rad_index;
3069168c 650 enum ath9k_int imask;
74bad5cb 651 u32 imrs2_reg;
2660b81a
S		 652 u32 txok_interrupt_mask;
653 u32 txerr_interrupt_mask;
654 u32 txdesc_interrupt_mask;
655 u32 txeol_interrupt_mask;
656 u32 txurn_interrupt_mask;
657 bool chip_fullsleep;
658 u32 atim_window;
6a2b9e8c
S		 659
660 /* Calibration */
cbfe9468
S		 661 enum ath9k_cal_types supp_cals;
662 struct ath9k_cal_list iq_caldata;
663 struct ath9k_cal_list adcgain_caldata;
664 struct ath9k_cal_list adcdc_calinitdata;
665 struct ath9k_cal_list adcdc_caldata;
df23acaa 666 struct ath9k_cal_list tempCompCalData;
cbfe9468
S		 667 struct ath9k_cal_list *cal_list;
668 struct ath9k_cal_list *cal_list_last;
669 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 670#define totalPowerMeasI meas0.unsign
671#define totalPowerMeasQ meas1.unsign
672#define totalIqCorrMeas meas2.sign
673#define totalAdcIOddPhase meas0.unsign
674#define totalAdcIEvenPhase meas1.unsign
675#define totalAdcQOddPhase meas2.unsign
676#define totalAdcQEvenPhase meas3.unsign
677#define totalAdcDcOffsetIOddPhase meas0.sign
678#define totalAdcDcOffsetIEvenPhase meas1.sign
679#define totalAdcDcOffsetQOddPhase meas2.sign
680#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 681 union {
682 u32 unsign[AR5416_MAX_CHAINS];
683 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 684 } meas0;
f078f209
LR		 685 union {
686 u32 unsign[AR5416_MAX_CHAINS];
687 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 688 } meas1;
f078f209
LR		 689 union {
690 u32 unsign[AR5416_MAX_CHAINS];
691 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 692 } meas2;
f078f209
LR		 693 union {
694 u32 unsign[AR5416_MAX_CHAINS];
695 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 696 } meas3;
697 u16 cal_samples;
6a2b9e8c 698
2660b81a
S		 699 u32 sta_id1_defaults;
700 u32 misc_mode;
f078f209
LR		 701 enum {
702 AUTO_32KHZ,
703 USE_32KHZ,
704 DONT_USE_32KHZ,
2660b81a 705 } enable_32kHz_clock;
6a2b9e8c 706
d70357d5
LR		 707 /* Private to hardware code */
708 struct ath_hw_private_ops private_ops;
709 /* Accessed by the lower level driver */
710 struct ath_hw_ops ops;
711
e68a060b 712 /* Used to program the radio on non single-chip devices */
2660b81a
S		 713 u32 *analogBank0Data;
714 u32 *analogBank1Data;
715 u32 *analogBank2Data;
716 u32 *analogBank3Data;
717 u32 *analogBank6Data;
718 u32 *analogBank6TPCData;
719 u32 *analogBank7Data;
720 u32 *addac5416_21;
721 u32 *bank6Temp;
722
597a94b3 723 u8 txpower_limit;
2660b81a 724 int16_t txpower_indexoffset;
e239d859 725 int coverage_class;
2660b81a
S		 726 u32 beacon_interval;
727 u32 slottime;
2660b81a 728 u32 globaltxtimeout;
6a2b9e8c
S		 729
730 /* ANI */
2660b81a 731 u32 proc_phyerr;
2660b81a
S		 732 u32 aniperiod;
733 struct ar5416AniState *curani;
734 struct ar5416AniState ani[255];
735 int totalSizeDesired[5];
736 int coarse_high[5];
737 int coarse_low[5];
738 int firpwr[5];
739 enum ath9k_ani_cmd ani_function;
740
af03abec 741 /* Bluetooth coexistance */
766ec4a9 742 struct ath_btcoex_hw btcoex_hw;
af03abec 743
2660b81a 744 u32 intr_txqs;
2660b81a
S		 745 u8 txchainmask;
746 u8 rxchainmask;
747
8bd1d07f
SB		 748 u32 originalGain[22];
749 int initPDADC;
750 int PDADCdelta;
08fc5c1b 751 u8 led_pin;
8bd1d07f 752
2660b81a
S		 753 struct ar5416IniArray iniModes;
754 struct ar5416IniArray iniCommon;
755 struct ar5416IniArray iniBank0;
756 struct ar5416IniArray iniBB_RfGain;
757 struct ar5416IniArray iniBank1;
758 struct ar5416IniArray iniBank2;
759 struct ar5416IniArray iniBank3;
760 struct ar5416IniArray iniBank6;
761 struct ar5416IniArray iniBank6TPC;
762 struct ar5416IniArray iniBank7;
763 struct ar5416IniArray iniAddac;
764 struct ar5416IniArray iniPcieSerdes;
13ce3e99 765 struct ar5416IniArray iniPcieSerdesLowPower;
2660b81a
S		 766 struct ar5416IniArray iniModesAdditional;
767 struct ar5416IniArray iniModesRxGain;
768 struct ar5416IniArray iniModesTxGain;
8564328d 769 struct ar5416IniArray iniModes_9271_1_0_only;
193cd458
S		 770 struct ar5416IniArray iniCckfirNormal;
771 struct ar5416IniArray iniCckfirJapan2484;
70807e99
S		 772 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
773 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
774 struct ar5416IniArray iniModes_9271_ANI_reg;
775 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
776 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
ff155a45 777
13ce3e99
LR		 778 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
779 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
780 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
781 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
782
ff155a45
VT		 783 u32 intr_gen_timer_trigger;
784 u32 intr_gen_timer_thresh;
785 struct ath_gen_timer_table hw_gen_timers;
744d4025
VT		 786
787 struct ar9003_txs *ts_ring;
788 void *ts_start;
789 u32 ts_paddr_start;
790 u32 ts_paddr_end;
791 u16 ts_tail;
792 u8 ts_size;
aea702b7
LR		 793
794 u32 bb_watchdog_last_status;
795 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
f078f209 796};
f078f209 797
9e4bffd2
LR		 798static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
799{
800 return &ah->common;
801}
802
803static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
804{
805 return &(ath9k_hw_common(ah)->regulatory);
806}
807
d70357d5
LR		 808static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
809{
810 return &ah->private_ops;
811}
812
813static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
814{
815 return &ah->ops;
816}
817
f637cfd6 818/* Initialization, Detach, Reset */
394cf0a1 819const char *ath9k_hw_probe(u16 vendorid, u16 devid);
285f2dda 820void ath9k_hw_deinit(struct ath_hw *ah);
f637cfd6 821int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 822int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
394cf0a1 823 bool bChannelChange);
a9a29ce6 824int ath9k_hw_fill_cap_info(struct ath_hw *ah);
cbe61d8a 825bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 826 u32 capability, u32 *result);
cbe61d8a 827bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 828 u32 capability, u32 setting, int *status);
8fe65368 829u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
394cf0a1
S		 830
831/* Key Cache Management */
cbe61d8a
S		 832bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
833bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
834bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
394cf0a1 835 const struct ath9k_keyval *k,
e0caf9ea 836 const u8 *mac);
cbe61d8a 837bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
394cf0a1
S		 838
839/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 840void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
841u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
842void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 843 u32 ah_signal_type);
cbe61d8a 844void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 845u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
846void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
394cf0a1
S		 847
848/* General Operation */
0caa7b14 849bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 850u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 851bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3 852u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 853 u8 phy, int kbps,
394cf0a1 854 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 855void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 856 struct ath9k_channel *chan,
857 struct chan_centers *centers);
cbe61d8a
S		 858u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
859void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
860bool ath9k_hw_phy_disable(struct ath_hw *ah);
861bool ath9k_hw_disable(struct ath_hw *ah);
8fbff4b8 862void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
cbe61d8a
S		 863void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
864void ath9k_hw_setopmode(struct ath_hw *ah);
865void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 866void ath9k_hw_setbssidmask(struct ath_hw *ah);
867void ath9k_hw_write_associd(struct ath_hw *ah);
cbe61d8a
S		 868u64 ath9k_hw_gettsf64(struct ath_hw *ah);
869void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
870void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 871void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
30cbd422 872u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
0005baf4 873void ath9k_hw_init_global_settings(struct ath_hw *ah);
25c56eec 874void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 875void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
876void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 877 const struct ath9k_beacon_state *bs);
c9c99e5e 878bool ath9k_hw_check_alive(struct ath_hw *ah);
a91d75ae 879
9ecdef4b 880bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 881
ff155a45
VT		 882/* Generic hw timer primitives */
883struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
884 void (*trigger)(void *),
885 void (*overflow)(void *),
886 void *arg,
887 u8 timer_index);
cd9bf689
LR		 888void ath9k_hw_gen_timer_start(struct ath_hw *ah,
889 struct ath_gen_timer *timer,
890 u32 timer_next,
891 u32 timer_period);
892void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
893
ff155a45
VT		 894void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
895void ath_gen_timer_isr(struct ath_hw *hw);
1773912b 896u32 ath9k_hw_gettsf32(struct ath_hw *ah);
ff155a45 897
f934c4d9 898void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 899
05020d23
S		 900/* HTC */
901void ath9k_hw_htc_resetinit(struct ath_hw *ah);
902
8fe65368
LR		 903/* PHY */
904void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
905 u32 *coef_mantissa, u32 *coef_exponent);
906
ebd5a14a
LR		 907/*
908 * Code Specific to AR5008, AR9001 or AR9002,
909 * we stuff these here to avoid callbacks for AR9003.
910 */
d8f492b7 911void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
ebd5a14a 912int ar9002_hw_rf_claim(struct ath_hw *ah);
78ec2677 913void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
e9141f71 914void ar9002_hw_update_async_fifo(struct ath_hw *ah);
6c94fdc9 915void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
d8f492b7 916
641d9921 917/*
aea702b7 918 * Code specific to AR9003, we stuff these here to avoid callbacks
641d9921
FF		 919 * for older families
920 */
921void ar9003_hw_set_nf_limits(struct ath_hw *ah);
aea702b7
LR		 922void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
923void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
924void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
641d9921
FF		 925
926/* Hardware family op attach helpers */
8fe65368 927void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
8525f280
LR		 928void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
929void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
8fe65368 930
795f5e2c
LR		 931void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
932void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
933
b3950e6a
LR		 934void ar9002_hw_attach_ops(struct ath_hw *ah);
935void ar9003_hw_attach_ops(struct ath_hw *ah);
936
7b6840ab
VT		 937#define ATH_PCIE_CAP_LINK_CTRL 0x70
938#define ATH_PCIE_CAP_LINK_L0S 1
939#define ATH_PCIE_CAP_LINK_L1 2
940
f078f209 941#endif
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