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ath9k_hw: define modules to get/set Antenna diversity paramaters
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
3a702e49 33
394cf0a1 34#define ATHEROS_VENDOR_ID 0x168c
7976b426 35
394cf0a1
S		 36#define AR5416_DEVID_PCI 0x0023
37#define AR5416_DEVID_PCIE 0x0024
38#define AR9160_DEVID_PCI 0x0027
39#define AR9280_DEVID_PCI 0x0029
40#define AR9280_DEVID_PCIE 0x002a
41#define AR9285_DEVID_PCIE 0x002b
5ffaf8a3 42#define AR2427_DEVID_PCIE 0x002c
db3cc53a
SB		 43#define AR9287_DEVID_PCI 0x002d
44#define AR9287_DEVID_PCIE 0x002e
45#define AR9300_DEVID_PCIE 0x0030
b99a7be4 46#define AR9300_DEVID_AR9340 0x0031
3050c914 47#define AR9300_DEVID_AR9485_PCIE 0x0032
7976b426 48
394cf0a1 49#define AR5416_AR9100_DEVID 0x000b
7976b426 50
394cf0a1
S		 51#define AR_SUBVENDOR_ID_NOG 0x0e11
52#define AR_SUBVENDOR_ID_NEW_A 0x7065
53#define AR5416_MAGIC 0x19641014
54
fe12946e
VT		 55#define AR9280_COEX2WIRE_SUBSYSID 0x309b
56#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
57#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
58
a6ef530f
VN		 59#define AR9300_NUM_BT_WEIGHTS 4
60#define AR9300_NUM_WLAN_WEIGHTS 4
61
e3d01bfc
LR		 62#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
63
cfe8cba9
LR		 64#define ATH_DEFAULT_NOISE_FLOOR -95
65
04658fba 66#define ATH9K_RSSI_BAD -128
990b70ab 67
cac4220b
FF		 68#define ATH9K_NUM_CHANNELS 38
69
394cf0a1 70/* Register read/write primitives */
9e4bffd2 71#define REG_WRITE(_ah, _reg, _val) \
f9f84e96 72 (_ah)->reg_ops.write((_ah), (_val), (_reg))
9e4bffd2
LR		 73
74#define REG_READ(_ah, _reg) \
f9f84e96 75 (_ah)->reg_ops.read((_ah), (_reg))
394cf0a1 76
09a525d3 77#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
f9f84e96 78 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
09a525d3 79
845e03c9
FF		 80#define REG_RMW(_ah, _reg, _set, _clr) \
81 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
82
20b3efd9
S		 83#define ENABLE_REGWRITE_BUFFER(_ah) \
84 do { \
f9f84e96
FF		 85 if ((_ah)->reg_ops.enable_write_buffer) \
86 (_ah)->reg_ops.enable_write_buffer((_ah)); \
20b3efd9
S		 87 } while (0)
88
20b3efd9
S		 89#define REGWRITE_BUFFER_FLUSH(_ah) \
90 do { \
f9f84e96
FF		 91 if ((_ah)->reg_ops.write_flush) \
92 (_ah)->reg_ops.write_flush((_ah)); \
20b3efd9
S		 93 } while (0)
94
394cf0a1
S		 95#define SM(_v, _f) (((_v) << _f##_S) & _f)
96#define MS(_v, _f) (((_v) & _f) >> _f##_S)
394cf0a1 97#define REG_RMW_FIELD(_a, _r, _f, _v) \
845e03c9 98 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
1547da37
LR		 99#define REG_READ_FIELD(_a, _r, _f) \
100 (((REG_READ(_a, _r) & _f) >> _f##_S))
394cf0a1 101#define REG_SET_BIT(_a, _r, _f) \
845e03c9 102 REG_RMW(_a, _r, (_f), 0)
394cf0a1 103#define REG_CLR_BIT(_a, _r, _f) \
845e03c9 104 REG_RMW(_a, _r, 0, (_f))
f078f209 105
e7fc6338
RM		 106#define DO_DELAY(x) do { \
107 if (((++(x) % 64) == 0) && \
108 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
109 != ATH_USB)) \
110 udelay(1); \
394cf0a1 111 } while (0)
f078f209 112
a9b6b256
FF		 113#define REG_WRITE_ARRAY(iniarray, column, regWr) \
114 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
f078f209 115
394cf0a1
S		 116#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
117#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
118#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
119#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 120#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 121#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
122#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 123
394cf0a1
S		 124#define AR_GPIOD_MASK 0x00001FFF
125#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 126
394cf0a1 127#define BASE_ACTIVATE_DELAY 100
0b488ac6 128#define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
394cf0a1
S		 129#define COEF_SCALE_S 24
130#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 131
394cf0a1
S		 132#define ATH9K_ANTENNA0_CHAINMASK 0x1
133#define ATH9K_ANTENNA1_CHAINMASK 0x2
134
135#define ATH9K_NUM_DMA_DEBUG_REGS 8
136#define ATH9K_NUM_QUEUES 10
137
138#define MAX_RATE_POWER 63
0caa7b14 139#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 140#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 141#define AH_TIME_QUANTUM 10
142#define AR_KEYTABLE_SIZE 128
d8caa839 143#define POWER_UP_TIME 10000
394cf0a1
S		 144#define SPUR_RSSI_THRESH 40
145
146#define CAB_TIMEOUT_VAL 10
147#define BEACON_TIMEOUT_VAL 10
148#define MIN_BEACON_TIMEOUT_VAL 1
149#define SLEEP_SLOP 3
150
151#define INIT_CONFIG_STATUS 0x00000000
152#define INIT_RSSI_THR 0x00000700
153#define INIT_BCON_CNTRL_REG 0x00000000
154
155#define TU_TO_USEC(_tu) ((_tu) << 10)
156
ceb26445
VT		 157#define ATH9K_HW_RX_HP_QDEPTH 16
158#define ATH9K_HW_RX_LP_QDEPTH 128
159
717f6bed
FF		 160#define PAPRD_GAIN_TABLE_ENTRIES 32
161#define PAPRD_TABLE_SZ 24
162
066dae93
FF		 163enum ath_hw_txq_subtype {
164 ATH_TXQ_AC_BE = 0,
165 ATH_TXQ_AC_BK = 1,
166 ATH_TXQ_AC_VI = 2,
167 ATH_TXQ_AC_VO = 3,
168};
169
13ce3e99
LR		 170enum ath_ini_subsys {
171 ATH_INI_PRE = 0,
172 ATH_INI_CORE,
173 ATH_INI_POST,
174 ATH_INI_NUM_SPLIT,
175};
176
394cf0a1 177enum ath9k_hw_caps {
364734fa
FF		 178 ATH9K_HW_CAP_HT = BIT(0),
179 ATH9K_HW_CAP_RFSILENT = BIT(1),
180 ATH9K_HW_CAP_CST = BIT(2),
364734fa
FF		 181 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
182 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
183 ATH9K_HW_CAP_EDMA = BIT(6),
184 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
185 ATH9K_HW_CAP_LDPC = BIT(8),
186 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
187 ATH9K_HW_CAP_SGI_20 = BIT(10),
188 ATH9K_HW_CAP_PAPRD = BIT(11),
189 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
d4659912
FF		 190 ATH9K_HW_CAP_2GHZ = BIT(13),
191 ATH9K_HW_CAP_5GHZ = BIT(14),
ea066d5a 192 ATH9K_HW_CAP_APM = BIT(15),
394cf0a1 193};
f078f209 194
394cf0a1
S		 195struct ath9k_hw_capabilities {
196 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
394cf0a1
S		 197 u16 rts_aggr_limit;
198 u8 tx_chainmask;
199 u8 rx_chainmask;
47c80de6
VT		 200 u8 max_txchains;
201 u8 max_rxchains;
394cf0a1 202 u8 num_gpio_pins;
ceb26445
VT		 203 u8 rx_hp_qdepth;
204 u8 rx_lp_qdepth;
205 u8 rx_status_len;
162c3be3 206 u8 tx_desc_len;
5088c2f1 207 u8 txs_len;
8060e169
VT		 208 u16 pcie_lcr_offset;
209 bool pcie_lcr_extsync_en;
394cf0a1 210};
f078f209 211
394cf0a1
S		 212struct ath9k_ops_config {
213 int dma_beacon_response_time;
214 int sw_beacon_response_time;
215 int additional_swba_backoff;
216 int ack_6mb;
41f3e54d 217 u32 cwm_ignore_extcca;
394cf0a1 218 u8 pcie_powersave_enable;
6a0ec30a 219 bool pcieSerDesWrite;
394cf0a1
S		 220 u8 pcie_clock_req;
221 u32 pcie_waen;
394cf0a1 222 u8 analog_shiftreg;
6f481010 223 u8 paprd_disable;
394cf0a1
S		 224 u32 ofdm_trig_low;
225 u32 ofdm_trig_high;
226 u32 cck_trig_high;
227 u32 cck_trig_low;
228 u32 enable_ani;
394cf0a1 229 int serialize_regmode;
0ce024cb 230 bool rx_intr_mitigation;
55e82df4 231 bool tx_intr_mitigation;
394cf0a1
S		 232#define SPUR_DISABLE 0
233#define SPUR_ENABLE_IOCTL 1
234#define SPUR_ENABLE_EEPROM 2
394cf0a1
S		 235#define AR_SPUR_5413_1 1640
236#define AR_SPUR_5413_2 1200
237#define AR_NO_SPUR 0x8000
238#define AR_BASE_FREQ_2GHZ 2300
239#define AR_BASE_FREQ_5GHZ 4900
240#define AR_SPUR_FEEQ_BOUND_HT40 19
241#define AR_SPUR_FEEQ_BOUND_HT20 10
242 int spurmode;
243 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 244 u8 max_txtrig_level;
e36b27af 245 u16 ani_poll_interval; /* ANI poll interval in ms */
394cf0a1 246};
f078f209 247
394cf0a1
S		 248enum ath9k_int {
249 ATH9K_INT_RX = 0x00000001,
250 ATH9K_INT_RXDESC = 0x00000002,
b5c80475
FF		 251 ATH9K_INT_RXHP = 0x00000001,
252 ATH9K_INT_RXLP = 0x00000002,
394cf0a1
S		 253 ATH9K_INT_RXNOFRM = 0x00000008,
254 ATH9K_INT_RXEOL = 0x00000010,
255 ATH9K_INT_RXORN = 0x00000020,
256 ATH9K_INT_TX = 0x00000040,
257 ATH9K_INT_TXDESC = 0x00000080,
258 ATH9K_INT_TIM_TIMER = 0x00000100,
aea702b7 259 ATH9K_INT_BB_WATCHDOG = 0x00000400,
394cf0a1
S		 260 ATH9K_INT_TXURN = 0x00000800,
261 ATH9K_INT_MIB = 0x00001000,
262 ATH9K_INT_RXPHY = 0x00004000,
263 ATH9K_INT_RXKCM = 0x00008000,
264 ATH9K_INT_SWBA = 0x00010000,
265 ATH9K_INT_BMISS = 0x00040000,
266 ATH9K_INT_BNR = 0x00100000,
267 ATH9K_INT_TIM = 0x00200000,
268 ATH9K_INT_DTIM = 0x00400000,
269 ATH9K_INT_DTIMSYNC = 0x00800000,
270 ATH9K_INT_GPIO = 0x01000000,
271 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 272 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 273 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 274 ATH9K_INT_CST = 0x10000000,
275 ATH9K_INT_GTT = 0x20000000,
276 ATH9K_INT_FATAL = 0x40000000,
277 ATH9K_INT_GLOBAL = 0x80000000,
278 ATH9K_INT_BMISC = ATH9K_INT_TIM |
279 ATH9K_INT_DTIM |
280 ATH9K_INT_DTIMSYNC |
4af9cf4f 281 ATH9K_INT_TSFOOR |
394cf0a1
S		 282 ATH9K_INT_CABEND,
283 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
284 ATH9K_INT_RXDESC |
285 ATH9K_INT_RXEOL |
286 ATH9K_INT_RXORN |
287 ATH9K_INT_TXURN |
288 ATH9K_INT_TXDESC |
289 ATH9K_INT_MIB |
290 ATH9K_INT_RXPHY |
291 ATH9K_INT_RXKCM |
292 ATH9K_INT_SWBA |
293 ATH9K_INT_BMISS |
294 ATH9K_INT_GPIO,
295 ATH9K_INT_NOCARD = 0xffffffff
296};
f078f209 297
394cf0a1
S		 298#define CHANNEL_CW_INT 0x00002
299#define CHANNEL_CCK 0x00020
300#define CHANNEL_OFDM 0x00040
301#define CHANNEL_2GHZ 0x00080
302#define CHANNEL_5GHZ 0x00100
303#define CHANNEL_PASSIVE 0x00200
304#define CHANNEL_DYN 0x00400
305#define CHANNEL_HALF 0x04000
306#define CHANNEL_QUARTER 0x08000
307#define CHANNEL_HT20 0x10000
308#define CHANNEL_HT40PLUS 0x20000
309#define CHANNEL_HT40MINUS 0x40000
310
394cf0a1
S		 311#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
312#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
313#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
314#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
315#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
316#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
317#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
318#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
319#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
320#define CHANNEL_ALL \
321 (CHANNEL_OFDM| \
322 CHANNEL_CCK| \
323 CHANNEL_2GHZ | \
324 CHANNEL_5GHZ | \
325 CHANNEL_HT20 | \
326 CHANNEL_HT40PLUS | \
327 CHANNEL_HT40MINUS)
328
20bd2a09 329struct ath9k_hw_cal_data {
394cf0a1
S		 330 u16 channel;
331 u32 channelFlags;
394cf0a1 332 int32_t CalValid;
394cf0a1
S		 333 int8_t iCoff;
334 int8_t qCoff;
717f6bed 335 bool paprd_done;
4254bc1c 336 bool nfcal_pending;
70cf1533 337 bool nfcal_interference;
717f6bed
FF		 338 u16 small_signal_gain[AR9300_MAX_CHAINS];
339 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
20bd2a09
FF		 340 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
341};
342
343struct ath9k_channel {
344 struct ieee80211_channel *chan;
093115b7 345 struct ar5416AniState ani;
20bd2a09
FF		 346 u16 channel;
347 u32 channelFlags;
348 u32 chanmode;
d9891c78 349 s16 noisefloor;
394cf0a1 350};
f078f209 351
394cf0a1
S		 352#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
353 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
354 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
355 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
356#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
357#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
358#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 359#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
360#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
6b42e8d0 361#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
394cf0a1 362 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
6b42e8d0 363 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
394cf0a1
S		 364
365/* These macros check chanmode and not channelFlags */
366#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
367#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
368 ((_c)->chanmode == CHANNEL_G_HT20))
369#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
370 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
371 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
372 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
373#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
374
375enum ath9k_power_mode {
376 ATH9K_PM_AWAKE = 0,
377 ATH9K_PM_FULL_SLEEP,
378 ATH9K_PM_NETWORK_SLEEP,
379 ATH9K_PM_UNDEFINED
380};
f078f209 381
394cf0a1
S		 382enum ath9k_tp_scale {
383 ATH9K_TP_SCALE_MAX = 0,
384 ATH9K_TP_SCALE_50,
385 ATH9K_TP_SCALE_25,
386 ATH9K_TP_SCALE_12,
387 ATH9K_TP_SCALE_MIN
388};
f078f209 389
394cf0a1
S		 390enum ser_reg_mode {
391 SER_REG_MODE_OFF = 0,
392 SER_REG_MODE_ON = 1,
393 SER_REG_MODE_AUTO = 2,
394};
f078f209 395
ad7b8060
VT		 396enum ath9k_rx_qtype {
397 ATH9K_RX_QUEUE_HP,
398 ATH9K_RX_QUEUE_LP,
399 ATH9K_RX_QUEUE_MAX,
400};
401
394cf0a1
S		 402struct ath9k_beacon_state {
403 u32 bs_nexttbtt;
404 u32 bs_nextdtim;
405 u32 bs_intval;
406#define ATH9K_BEACON_PERIOD 0x0000ffff
4af9cf4f 407#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 408 u32 bs_dtimperiod;
409 u16 bs_cfpperiod;
410 u16 bs_cfpmaxduration;
411 u32 bs_cfpnext;
412 u16 bs_timoffset;
413 u16 bs_bmissthreshold;
414 u32 bs_sleepduration;
4af9cf4f 415 u32 bs_tsfoor_threshold;
394cf0a1 416};
f078f209 417
394cf0a1
S		 418struct chan_centers {
419 u16 synth_center;
420 u16 ctl_center;
421 u16 ext_center;
422};
f078f209 423
394cf0a1
S		 424enum {
425 ATH9K_RESET_POWER_ON,
426 ATH9K_RESET_WARM,
427 ATH9K_RESET_COLD,
428};
f078f209 429
d535a42a
S		 430struct ath9k_hw_version {
431 u32 magic;
432 u16 devid;
433 u16 subvendorid;
434 u32 macVersion;
435 u16 macRev;
436 u16 phyRev;
437 u16 analog5GhzRev;
438 u16 analog2GhzRev;
aeac355d 439 u16 subsysid;
0b5ead91 440 enum ath_usb_dev usbdev;
d535a42a 441};
394cf0a1 442
ff155a45
VT		 443/* Generic TSF timer definitions */
444
445#define ATH_MAX_GEN_TIMER 16
446
447#define AR_GENTMR_BIT(_index) (1 << (_index))
448
449/*
77c2061d 450 * Using de Bruijin sequence to look up 1's index in a 32 bit number
ff155a45
VT		 451 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
452 */
c90017dd 453#define debruijn32 0x077CB531U
ff155a45
VT		 454
455struct ath_gen_timer_configuration {
456 u32 next_addr;
457 u32 period_addr;
458 u32 mode_addr;
459 u32 mode_mask;
460};
461
462struct ath_gen_timer {
463 void (*trigger)(void *arg);
464 void (*overflow)(void *arg);
465 void *arg;
466 u8 index;
467};
468
469struct ath_gen_timer_table {
470 u32 gen_timer_index[32];
471 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
472 union {
473 unsigned long timer_bits;
474 u16 val;
475 } timer_mask;
476};
477
21cc630f
VT		 478struct ath_hw_antcomb_conf {
479 u8 main_lna_conf;
480 u8 alt_lna_conf;
481 u8 fast_div_bias;
c6ba9feb
MSS		 482 u8 main_gaintb;
483 u8 alt_gaintb;
484 int lna1_lna2_delta;
21cc630f
VT		 485};
486
4e8c14e9
FF		 487/**
488 * struct ath_hw_radar_conf - radar detection initialization parameters
489 *
490 * @pulse_inband: threshold for checking the ratio of in-band power
491 * to total power for short radar pulses (half dB steps)
492 * @pulse_inband_step: threshold for checking an in-band power to total
493 * power ratio increase for short radar pulses (half dB steps)
494 * @pulse_height: threshold for detecting the beginning of a short
495 * radar pulse (dB step)
496 * @pulse_rssi: threshold for detecting if a short radar pulse is
497 * gone (dB step)
498 * @pulse_maxlen: maximum pulse length (0.8 us steps)
499 *
500 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
501 * @radar_inband: threshold for checking the ratio of in-band power
502 * to total power for long radar pulses (half dB steps)
503 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
504 *
505 * @ext_channel: enable extension channel radar detection
506 */
507struct ath_hw_radar_conf {
508 unsigned int pulse_inband;
509 unsigned int pulse_inband_step;
510 unsigned int pulse_height;
511 unsigned int pulse_rssi;
512 unsigned int pulse_maxlen;
513
514 unsigned int radar_rssi;
515 unsigned int radar_inband;
516 int fir_power;
517
518 bool ext_channel;
519};
520
d70357d5
LR		 521/**
522 * struct ath_hw_private_ops - callbacks used internally by hardware code
523 *
524 * This structure contains private callbacks designed to only be used internally
525 * by the hardware core.
526 *
795f5e2c
LR		 527 * @init_cal_settings: setup types of calibrations supported
528 * @init_cal: starts actual calibration
529 *
d70357d5 530 * @init_mode_regs: Initializes mode registers
991312d8 531 * @init_mode_gain_regs: Initialize TX/RX gain registers
8fe65368
LR		 532 *
533 * @rf_set_freq: change frequency
534 * @spur_mitigate_freq: spur mitigation
535 * @rf_alloc_ext_banks:
536 * @rf_free_ext_banks:
537 * @set_rf_regs:
64773964
LR		 538 * @compute_pll_control: compute the PLL control value to use for
539 * AR_RTC_PLL_CONTROL for a given channel
795f5e2c
LR		 540 * @setup_calibration: set up calibration
541 * @iscal_supported: used to query if a type of calibration is supported
ac0bb767 542 *
e36b27af
LR		 543 * @ani_cache_ini_regs: cache the values for ANI from the initial
544 * register settings through the register initialization.
d70357d5
LR		 545 */
546struct ath_hw_private_ops {
795f5e2c 547 /* Calibration ops */
d70357d5 548 void (*init_cal_settings)(struct ath_hw *ah);
795f5e2c
LR		 549 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
550
d70357d5 551 void (*init_mode_regs)(struct ath_hw *ah);
991312d8 552 void (*init_mode_gain_regs)(struct ath_hw *ah);
795f5e2c
LR		 553 void (*setup_calibration)(struct ath_hw *ah,
554 struct ath9k_cal_list *currCal);
8fe65368
LR		 555
556 /* PHY ops */
557 int (*rf_set_freq)(struct ath_hw *ah,
558 struct ath9k_channel *chan);
559 void (*spur_mitigate_freq)(struct ath_hw *ah,
560 struct ath9k_channel *chan);
561 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
562 void (*rf_free_ext_banks)(struct ath_hw *ah);
563 bool (*set_rf_regs)(struct ath_hw *ah,
564 struct ath9k_channel *chan,
565 u16 modesIndex);
566 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
567 void (*init_bb)(struct ath_hw *ah,
568 struct ath9k_channel *chan);
569 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
570 void (*olc_init)(struct ath_hw *ah);
571 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
572 void (*mark_phy_inactive)(struct ath_hw *ah);
573 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
574 bool (*rfbus_req)(struct ath_hw *ah);
575 void (*rfbus_done)(struct ath_hw *ah);
8fe65368
LR		 576 void (*restore_chainmask)(struct ath_hw *ah);
577 void (*set_diversity)(struct ath_hw *ah, bool value);
64773964
LR		 578 u32 (*compute_pll_control)(struct ath_hw *ah,
579 struct ath9k_channel *chan);
c16fcb49
FF		 580 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
581 int param);
641d9921 582 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
4e8c14e9
FF		 583 void (*set_radar_params)(struct ath_hw *ah,
584 struct ath_hw_radar_conf *conf);
ac0bb767
LR		 585
586 /* ANI */
e36b27af 587 void (*ani_cache_ini_regs)(struct ath_hw *ah);
d70357d5
LR		 588};
589
590/**
591 * struct ath_hw_ops - callbacks used by hardware code and driver code
592 *
593 * This structure contains callbacks designed to to be used internally by
594 * hardware code and also by the lower level driver.
595 *
596 * @config_pci_powersave:
795f5e2c 597 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
d70357d5
LR		 598 */
599struct ath_hw_ops {
600 void (*config_pci_powersave)(struct ath_hw *ah,
601 int restore,
602 int power_off);
cee1f625 603 void (*rx_enable)(struct ath_hw *ah);
87d5efbb
VT		 604 void (*set_desc_link)(void *ds, u32 link);
605 void (*get_desc_link)(void *ds, u32 **link);
795f5e2c
LR		 606 bool (*calibrate)(struct ath_hw *ah,
607 struct ath9k_channel *chan,
608 u8 rxchainmask,
609 bool longcal);
55e82df4 610 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
cc610ac0
VT		 611 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
612 bool is_firstseg, bool is_is_lastseg,
613 const void *ds0, dma_addr_t buf_addr,
614 unsigned int qcu);
615 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
616 struct ath_tx_status *ts);
617 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
618 u32 pktLen, enum ath9k_pkt_type type,
619 u32 txPower, u32 keyIx,
620 enum ath9k_key_type keyType,
621 u32 flags);
622 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
623 void *lastds,
624 u32 durUpdateEn, u32 rtsctsRate,
625 u32 rtsctsDuration,
626 struct ath9k_11n_rate_series series[],
627 u32 nseries, u32 flags);
628 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
629 u32 aggrLen);
630 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
631 u32 numDelims);
632 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
633 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
5519541d 634 void (*set_clrdmask)(struct ath_hw *ah, void *ds, bool val);
69de3721
MSS		 635 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
636 struct ath_hw_antcomb_conf *antconf);
637 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
638 struct ath_hw_antcomb_conf *antconf);
639
d70357d5
LR		 640};
641
f2552e28
FF		 642struct ath_nf_limits {
643 s16 max;
644 s16 min;
645 s16 nominal;
646};
647
97dcec57
SM		 648/* ah_flags */
649#define AH_USE_EEPROM 0x1
650#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
651
cbe61d8a 652struct ath_hw {
f9f84e96
FF		 653 struct ath_ops reg_ops;
654
b002a4a9 655 struct ieee80211_hw *hw;
27c51f1a 656 struct ath_common common;
cbe61d8a 657 struct ath9k_hw_version hw_version;
2660b81a
S		 658 struct ath9k_ops_config config;
659 struct ath9k_hw_capabilities caps;
cac4220b 660 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
2660b81a 661 struct ath9k_channel *curchan;
394cf0a1 662
cbe61d8a
S		 663 union {
664 struct ar5416_eeprom_def def;
665 struct ar5416_eeprom_4k map4k;
475f5989 666 struct ar9287_eeprom map9287;
15c9ee7a 667 struct ar9300_eeprom ar9300_eep;
2660b81a 668 } eeprom;
f74df6fb 669 const struct eeprom_ops *eep_ops;
cbe61d8a
S		 670
671 bool sw_mgmt_crypto;
2660b81a 672 bool is_pciexpress;
5f841b41 673 bool is_monitoring;
2eb46d9b 674 bool need_an_top2_fixup;
2660b81a 675 u16 tx_trig_level;
f2552e28 676
bbacee13 677 u32 nf_regs[6];
f2552e28
FF		 678 struct ath_nf_limits nf_2g;
679 struct ath_nf_limits nf_5g;
2660b81a
S		 680 u16 rfsilent;
681 u32 rfkill_gpio;
682 u32 rfkill_polarity;
cbe61d8a 683 u32 ah_flags;
394cf0a1 684
d7e7d229
LR		 685 bool htc_reset_init;
686
2660b81a
S		 687 enum nl80211_iftype opmode;
688 enum ath9k_power_mode power_mode;
f078f209 689
20bd2a09 690 struct ath9k_hw_cal_data *caldata;
a13883b0 691 struct ath9k_pacal_info pacal_info;
2660b81a
S		 692 struct ar5416Stats stats;
693 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
694
695 int16_t curchan_rad_index;
3069168c 696 enum ath9k_int imask;
74bad5cb 697 u32 imrs2_reg;
2660b81a
S		 698 u32 txok_interrupt_mask;
699 u32 txerr_interrupt_mask;
700 u32 txdesc_interrupt_mask;
701 u32 txeol_interrupt_mask;
702 u32 txurn_interrupt_mask;
703 bool chip_fullsleep;
704 u32 atim_window;
6a2b9e8c
S		 705
706 /* Calibration */
6497827f 707 u32 supp_cals;
cbfe9468
S		 708 struct ath9k_cal_list iq_caldata;
709 struct ath9k_cal_list adcgain_caldata;
cbfe9468 710 struct ath9k_cal_list adcdc_caldata;
df23acaa 711 struct ath9k_cal_list tempCompCalData;
cbfe9468
S		 712 struct ath9k_cal_list *cal_list;
713 struct ath9k_cal_list *cal_list_last;
714 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 715#define totalPowerMeasI meas0.unsign
716#define totalPowerMeasQ meas1.unsign
717#define totalIqCorrMeas meas2.sign
718#define totalAdcIOddPhase meas0.unsign
719#define totalAdcIEvenPhase meas1.unsign
720#define totalAdcQOddPhase meas2.unsign
721#define totalAdcQEvenPhase meas3.unsign
722#define totalAdcDcOffsetIOddPhase meas0.sign
723#define totalAdcDcOffsetIEvenPhase meas1.sign
724#define totalAdcDcOffsetQOddPhase meas2.sign
725#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 726 union {
727 u32 unsign[AR5416_MAX_CHAINS];
728 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 729 } meas0;
f078f209
LR		 730 union {
731 u32 unsign[AR5416_MAX_CHAINS];
732 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 733 } meas1;
f078f209
LR		 734 union {
735 u32 unsign[AR5416_MAX_CHAINS];
736 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 737 } meas2;
f078f209
LR		 738 union {
739 u32 unsign[AR5416_MAX_CHAINS];
740 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 741 } meas3;
742 u16 cal_samples;
6a2b9e8c 743
2660b81a
S		 744 u32 sta_id1_defaults;
745 u32 misc_mode;
f078f209
LR		 746 enum {
747 AUTO_32KHZ,
748 USE_32KHZ,
749 DONT_USE_32KHZ,
2660b81a 750 } enable_32kHz_clock;
6a2b9e8c 751
d70357d5
LR		 752 /* Private to hardware code */
753 struct ath_hw_private_ops private_ops;
754 /* Accessed by the lower level driver */
755 struct ath_hw_ops ops;
756
e68a060b 757 /* Used to program the radio on non single-chip devices */
2660b81a
S		 758 u32 *analogBank0Data;
759 u32 *analogBank1Data;
760 u32 *analogBank2Data;
761 u32 *analogBank3Data;
762 u32 *analogBank6Data;
763 u32 *analogBank6TPCData;
764 u32 *analogBank7Data;
765 u32 *addac5416_21;
766 u32 *bank6Temp;
767
597a94b3 768 u8 txpower_limit;
e239d859 769 int coverage_class;
2660b81a 770 u32 slottime;
2660b81a 771 u32 globaltxtimeout;
6a2b9e8c
S		 772
773 /* ANI */
2660b81a 774 u32 proc_phyerr;
2660b81a 775 u32 aniperiod;
2660b81a
S		 776 int totalSizeDesired[5];
777 int coarse_high[5];
778 int coarse_low[5];
779 int firpwr[5];
780 enum ath9k_ani_cmd ani_function;
781
af03abec 782 /* Bluetooth coexistance */
766ec4a9 783 struct ath_btcoex_hw btcoex_hw;
a6ef530f
VN		 784 u32 bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS];
785 u32 bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS];
af03abec 786
2660b81a 787 u32 intr_txqs;
2660b81a
S		 788 u8 txchainmask;
789 u8 rxchainmask;
790
c5d0855a
FF		 791 struct ath_hw_radar_conf radar_conf;
792
8bd1d07f
SB		 793 u32 originalGain[22];
794 int initPDADC;
795 int PDADCdelta;
6de66dd9 796 int led_pin;
691680b8
FF		 797 u32 gpio_mask;
798 u32 gpio_val;
8bd1d07f 799
2660b81a
S		 800 struct ar5416IniArray iniModes;
801 struct ar5416IniArray iniCommon;
802 struct ar5416IniArray iniBank0;
803 struct ar5416IniArray iniBB_RfGain;
804 struct ar5416IniArray iniBank1;
805 struct ar5416IniArray iniBank2;
806 struct ar5416IniArray iniBank3;
807 struct ar5416IniArray iniBank6;
808 struct ar5416IniArray iniBank6TPC;
809 struct ar5416IniArray iniBank7;
810 struct ar5416IniArray iniAddac;
811 struct ar5416IniArray iniPcieSerdes;
13ce3e99 812 struct ar5416IniArray iniPcieSerdesLowPower;
2660b81a 813 struct ar5416IniArray iniModesAdditional;
d89baac8 814 struct ar5416IniArray iniModesAdditional_40M;
2660b81a
S		 815 struct ar5416IniArray iniModesRxGain;
816 struct ar5416IniArray iniModesTxGain;
8564328d 817 struct ar5416IniArray iniModes_9271_1_0_only;
193cd458
S		 818 struct ar5416IniArray iniCckfirNormal;
819 struct ar5416IniArray iniCckfirJapan2484;
70807e99
S		 820 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
821 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
822 struct ar5416IniArray iniModes_9271_ANI_reg;
823 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
824 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
ff155a45 825
13ce3e99
LR		 826 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
827 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
828 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
829 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
830
ff155a45
VT		 831 u32 intr_gen_timer_trigger;
832 u32 intr_gen_timer_thresh;
833 struct ath_gen_timer_table hw_gen_timers;
744d4025
VT		 834
835 struct ar9003_txs *ts_ring;
836 void *ts_start;
837 u32 ts_paddr_start;
838 u32 ts_paddr_end;
839 u16 ts_tail;
840 u8 ts_size;
aea702b7
LR		 841
842 u32 bb_watchdog_last_status;
843 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
717f6bed 844
1bf38661
FF		 845 unsigned int paprd_target_power;
846 unsigned int paprd_training_power;
7072bf62 847 unsigned int paprd_ratemask;
f1a8abb0 848 unsigned int paprd_ratemask_ht40;
45ef6a0b 849 bool paprd_table_write_done;
717f6bed
FF		 850 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
851 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
9a658d2b
LR		 852 /*
853 * Store the permanent value of Reg 0x4004in WARegVal
854 * so we dont have to R/M/W. We should not be reading
855 * this register when in sleep states.
856 */
857 u32 WARegVal;
6ee63f55
SB		 858
859 /* Enterprise mode cap */
860 u32 ent_mode;
f2f5f2a1
VT		 861
862 bool is_clk_25mhz;
f078f209 863};
f078f209 864
0cb9e06b
FF		 865struct ath_bus_ops {
866 enum ath_bus_type ath_bus_type;
867 void (*read_cachesize)(struct ath_common *common, int *csz);
868 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
869 void (*bt_coex_prep)(struct ath_common *common);
870 void (*extn_synch_en)(struct ath_common *common);
871};
872
9e4bffd2
LR		 873static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
874{
875 return &ah->common;
876}
877
878static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
879{
880 return &(ath9k_hw_common(ah)->regulatory);
881}
882
d70357d5
LR		 883static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
884{
885 return &ah->private_ops;
886}
887
888static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
889{
890 return &ah->ops;
891}
892
895ad7eb
VT		 893static inline u8 get_streams(int mask)
894{
895 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
896}
897
f637cfd6 898/* Initialization, Detach, Reset */
394cf0a1 899const char *ath9k_hw_probe(u16 vendorid, u16 devid);
285f2dda 900void ath9k_hw_deinit(struct ath_hw *ah);
f637cfd6 901int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 902int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 903 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
a9a29ce6 904int ath9k_hw_fill_cap_info(struct ath_hw *ah);
8fe65368 905u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
394cf0a1 906
394cf0a1 907/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 908void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
909u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
910void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 911 u32 ah_signal_type);
cbe61d8a 912void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 913u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
914void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
394cf0a1
S		 915
916/* General Operation */
0caa7b14 917bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
a9b6b256
FF		 918void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
919 int column, unsigned int *writecnt);
394cf0a1 920u32 ath9k_hw_reverse_bits(u32 val, u32 n);
4f0fc7c3 921u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 922 u8 phy, int kbps,
394cf0a1 923 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 924void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 925 struct ath9k_channel *chan,
926 struct chan_centers *centers);
cbe61d8a
S		 927u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
928void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
929bool ath9k_hw_phy_disable(struct ath_hw *ah);
930bool ath9k_hw_disable(struct ath_hw *ah);
de40f316 931void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
cbe61d8a
S		 932void ath9k_hw_setopmode(struct ath_hw *ah);
933void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 934void ath9k_hw_setbssidmask(struct ath_hw *ah);
935void ath9k_hw_write_associd(struct ath_hw *ah);
dd347f2f 936u32 ath9k_hw_gettsf32(struct ath_hw *ah);
cbe61d8a
S		 937u64 ath9k_hw_gettsf64(struct ath_hw *ah);
938void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
939void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 940void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
0005baf4 941void ath9k_hw_init_global_settings(struct ath_hw *ah);
b84628eb 942u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
25c56eec 943void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 944void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
945void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 946 const struct ath9k_beacon_state *bs);
c9c99e5e 947bool ath9k_hw_check_alive(struct ath_hw *ah);
a91d75ae 948
9ecdef4b 949bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 950
ff155a45
VT		 951/* Generic hw timer primitives */
952struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
953 void (*trigger)(void *),
954 void (*overflow)(void *),
955 void *arg,
956 u8 timer_index);
cd9bf689
LR		 957void ath9k_hw_gen_timer_start(struct ath_hw *ah,
958 struct ath_gen_timer *timer,
959 u32 timer_next,
960 u32 timer_period);
961void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
962
ff155a45
VT		 963void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
964void ath_gen_timer_isr(struct ath_hw *hw);
965
f934c4d9 966void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 967
05020d23
S		 968/* HTC */
969void ath9k_hw_htc_resetinit(struct ath_hw *ah);
970
8fe65368
LR		 971/* PHY */
972void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
973 u32 *coef_mantissa, u32 *coef_exponent);
974
ebd5a14a
LR		 975/*
976 * Code Specific to AR5008, AR9001 or AR9002,
977 * we stuff these here to avoid callbacks for AR9003.
978 */
d8f492b7 979void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
ebd5a14a 980int ar9002_hw_rf_claim(struct ath_hw *ah);
78ec2677 981void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
e9141f71 982void ar9002_hw_update_async_fifo(struct ath_hw *ah);
6c94fdc9 983void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
d8f492b7 984
641d9921 985/*
aea702b7 986 * Code specific to AR9003, we stuff these here to avoid callbacks
641d9921
FF		 987 * for older families
988 */
aea702b7
LR		 989void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
990void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
991void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
717f6bed
FF		 992void ar9003_paprd_enable(struct ath_hw *ah, bool val);
993void ar9003_paprd_populate_single_table(struct ath_hw *ah,
20bd2a09
FF		 994 struct ath9k_hw_cal_data *caldata,
995 int chain);
996int ar9003_paprd_create_curve(struct ath_hw *ah,
997 struct ath9k_hw_cal_data *caldata, int chain);
717f6bed
FF		 998int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
999int ar9003_paprd_init_table(struct ath_hw *ah);
1000bool ar9003_paprd_is_done(struct ath_hw *ah);
1001void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
641d9921
FF		 1002
1003/* Hardware family op attach helpers */
8fe65368 1004void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
8525f280
LR		 1005void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1006void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
8fe65368 1007
795f5e2c
LR		 1008void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1009void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1010
b3950e6a
LR		 1011void ar9002_hw_attach_ops(struct ath_hw *ah);
1012void ar9003_hw_attach_ops(struct ath_hw *ah);
1013
c2ba3342 1014void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767
LR		 1015/*
1016 * ANI work can be shared between all families but a next
1017 * generation implementation of ANI will be used only for AR9003 only
1018 * for now as the other families still need to be tested with the same
e36b27af
LR		 1019 * next generation ANI. Feel free to start testing it though for the
1020 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
ac0bb767 1021 */
e36b27af 1022extern int modparam_force_new_ani;
8eb4980c 1023void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
bfc472bb 1024void ath9k_hw_proc_mib_event(struct ath_hw *ah);
95792178 1025void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767 1026
7b6840ab
VT		 1027#define ATH_PCIE_CAP_LINK_CTRL 0x70
1028#define ATH_PCIE_CAP_LINK_L0S 1
1029#define ATH_PCIE_CAP_LINK_L1 2
1030
73377256
LR		 1031#define ATH9K_CLOCK_RATE_CCK 22
1032#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1033#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1034#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1035
f078f209 1036#endif
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