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Commit | Line | Data |
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f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef HW_H | |
18 | #define HW_H | |
19 | ||
20 | #include <linux/if_ether.h> | |
21 | #include <linux/delay.h> | |
394cf0a1 | 22 | #include <linux/io.h> |
ab5c4f71 | 23 | #include <linux/firmware.h> |
394cf0a1 S |
24 | |
25 | #include "mac.h" | |
26 | #include "ani.h" | |
27 | #include "eeprom.h" | |
28 | #include "calib.h" | |
394cf0a1 S |
29 | #include "reg.h" |
30 | #include "phy.h" | |
af03abec | 31 | #include "btcoex.h" |
c774d57f | 32 | #include "dynack.h" |
394cf0a1 | 33 | |
203c4805 | 34 | #include "../regd.h" |
3a702e49 | 35 | |
394cf0a1 | 36 | #define ATHEROS_VENDOR_ID 0x168c |
7976b426 | 37 | |
394cf0a1 S |
38 | #define AR5416_DEVID_PCI 0x0023 |
39 | #define AR5416_DEVID_PCIE 0x0024 | |
40 | #define AR9160_DEVID_PCI 0x0027 | |
41 | #define AR9280_DEVID_PCI 0x0029 | |
42 | #define AR9280_DEVID_PCIE 0x002a | |
43 | #define AR9285_DEVID_PCIE 0x002b | |
5ffaf8a3 | 44 | #define AR2427_DEVID_PCIE 0x002c |
db3cc53a SB |
45 | #define AR9287_DEVID_PCI 0x002d |
46 | #define AR9287_DEVID_PCIE 0x002e | |
47 | #define AR9300_DEVID_PCIE 0x0030 | |
b99a7be4 | 48 | #define AR9300_DEVID_AR9340 0x0031 |
3050c914 | 49 | #define AR9300_DEVID_AR9485_PCIE 0x0032 |
5a63ef0f | 50 | #define AR9300_DEVID_AR9580 0x0033 |
423e38e8 | 51 | #define AR9300_DEVID_AR9462 0x0034 |
03689301 | 52 | #define AR9300_DEVID_AR9330 0x0035 |
b1233779 | 53 | #define AR9300_DEVID_QCA955X 0x0038 |
d4e5979c | 54 | #define AR9485_DEVID_AR1111 0x0037 |
77fac465 | 55 | #define AR9300_DEVID_AR9565 0x0036 |
e6b1e46e | 56 | #define AR9300_DEVID_AR953X 0x003d |
7976b426 | 57 | |
394cf0a1 | 58 | #define AR5416_AR9100_DEVID 0x000b |
7976b426 | 59 | |
394cf0a1 S |
60 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
61 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | |
62 | #define AR5416_MAGIC 0x19641014 | |
63 | ||
fe12946e VT |
64 | #define AR9280_COEX2WIRE_SUBSYSID 0x309b |
65 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa | |
66 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab | |
67 | ||
e3d01bfc LR |
68 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
69 | ||
cfe8cba9 LR |
70 | #define ATH_DEFAULT_NOISE_FLOOR -95 |
71 | ||
04658fba | 72 | #define ATH9K_RSSI_BAD -128 |
990b70ab | 73 | |
cac4220b FF |
74 | #define ATH9K_NUM_CHANNELS 38 |
75 | ||
394cf0a1 | 76 | /* Register read/write primitives */ |
9e4bffd2 | 77 | #define REG_WRITE(_ah, _reg, _val) \ |
f9f84e96 | 78 | (_ah)->reg_ops.write((_ah), (_val), (_reg)) |
9e4bffd2 LR |
79 | |
80 | #define REG_READ(_ah, _reg) \ | |
f9f84e96 | 81 | (_ah)->reg_ops.read((_ah), (_reg)) |
394cf0a1 | 82 | |
09a525d3 | 83 | #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ |
f9f84e96 | 84 | (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) |
09a525d3 | 85 | |
845e03c9 FF |
86 | #define REG_RMW(_ah, _reg, _set, _clr) \ |
87 | (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) | |
88 | ||
20b3efd9 S |
89 | #define ENABLE_REGWRITE_BUFFER(_ah) \ |
90 | do { \ | |
f9f84e96 FF |
91 | if ((_ah)->reg_ops.enable_write_buffer) \ |
92 | (_ah)->reg_ops.enable_write_buffer((_ah)); \ | |
20b3efd9 S |
93 | } while (0) |
94 | ||
20b3efd9 S |
95 | #define REGWRITE_BUFFER_FLUSH(_ah) \ |
96 | do { \ | |
f9f84e96 FF |
97 | if ((_ah)->reg_ops.write_flush) \ |
98 | (_ah)->reg_ops.write_flush((_ah)); \ | |
20b3efd9 S |
99 | } while (0) |
100 | ||
26526202 RM |
101 | #define PR_EEP(_s, _val) \ |
102 | do { \ | |
5e88ba62 ZK |
103 | len += scnprintf(buf + len, size - len, "%20s : %10d\n",\ |
104 | _s, (_val)); \ | |
26526202 RM |
105 | } while (0) |
106 | ||
394cf0a1 S |
107 | #define SM(_v, _f) (((_v) << _f##_S) & _f) |
108 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | |
394cf0a1 | 109 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ |
845e03c9 | 110 | REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) |
1547da37 LR |
111 | #define REG_READ_FIELD(_a, _r, _f) \ |
112 | (((REG_READ(_a, _r) & _f) >> _f##_S)) | |
394cf0a1 | 113 | #define REG_SET_BIT(_a, _r, _f) \ |
845e03c9 | 114 | REG_RMW(_a, _r, (_f), 0) |
394cf0a1 | 115 | #define REG_CLR_BIT(_a, _r, _f) \ |
845e03c9 | 116 | REG_RMW(_a, _r, 0, (_f)) |
f078f209 | 117 | |
e7fc6338 RM |
118 | #define DO_DELAY(x) do { \ |
119 | if (((++(x) % 64) == 0) && \ | |
120 | (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ | |
121 | != ATH_USB)) \ | |
122 | udelay(1); \ | |
394cf0a1 | 123 | } while (0) |
f078f209 | 124 | |
a9b6b256 FF |
125 | #define REG_WRITE_ARRAY(iniarray, column, regWr) \ |
126 | ath9k_hw_write_array(ah, iniarray, column, &(regWr)) | |
f078f209 | 127 | |
394cf0a1 S |
128 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
129 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | |
130 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | |
131 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 | |
1773912b | 132 | #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 |
394cf0a1 S |
133 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
134 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | |
93d36e99 MSS |
135 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16 |
136 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17 | |
137 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18 | |
138 | #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19 | |
139 | #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14 | |
140 | #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13 | |
141 | #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9 | |
142 | #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8 | |
143 | #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d | |
144 | #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e | |
f078f209 | 145 | |
394cf0a1 S |
146 | #define AR_GPIOD_MASK 0x00001FFF |
147 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | |
f078f209 | 148 | |
394cf0a1 | 149 | #define BASE_ACTIVATE_DELAY 100 |
0b488ac6 | 150 | #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100) |
394cf0a1 S |
151 | #define COEF_SCALE_S 24 |
152 | #define HT40_CHANNEL_CENTER_SHIFT 10 | |
f078f209 | 153 | |
394cf0a1 S |
154 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
155 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 | |
156 | ||
157 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 | |
158 | #define ATH9K_NUM_QUEUES 10 | |
159 | ||
160 | #define MAX_RATE_POWER 63 | |
0caa7b14 | 161 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
f9b604f6 | 162 | #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ |
394cf0a1 S |
163 | #define AH_TIME_QUANTUM 10 |
164 | #define AR_KEYTABLE_SIZE 128 | |
d8caa839 | 165 | #define POWER_UP_TIME 10000 |
394cf0a1 | 166 | #define SPUR_RSSI_THRESH 40 |
331c5ea2 MSS |
167 | #define UPPER_5G_SUB_BAND_START 5700 |
168 | #define MID_5G_SUB_BAND_START 5400 | |
394cf0a1 S |
169 | |
170 | #define CAB_TIMEOUT_VAL 10 | |
171 | #define BEACON_TIMEOUT_VAL 10 | |
172 | #define MIN_BEACON_TIMEOUT_VAL 1 | |
4ed15762 | 173 | #define SLEEP_SLOP TU_TO_USEC(3) |
394cf0a1 S |
174 | |
175 | #define INIT_CONFIG_STATUS 0x00000000 | |
176 | #define INIT_RSSI_THR 0x00000700 | |
177 | #define INIT_BCON_CNTRL_REG 0x00000000 | |
178 | ||
179 | #define TU_TO_USEC(_tu) ((_tu) << 10) | |
180 | ||
ceb26445 VT |
181 | #define ATH9K_HW_RX_HP_QDEPTH 16 |
182 | #define ATH9K_HW_RX_LP_QDEPTH 128 | |
183 | ||
0e44d48c MSS |
184 | #define PAPRD_GAIN_TABLE_ENTRIES 32 |
185 | #define PAPRD_TABLE_SZ 24 | |
186 | #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0 | |
717f6bed | 187 | |
01c78533 MSS |
188 | /* |
189 | * Wake on Wireless | |
190 | */ | |
191 | ||
192 | /* Keep Alive Frame */ | |
193 | #define KAL_FRAME_LEN 28 | |
194 | #define KAL_FRAME_TYPE 0x2 /* data frame */ | |
195 | #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */ | |
196 | #define KAL_DURATION_ID 0x3d | |
197 | #define KAL_NUM_DATA_WORDS 6 | |
198 | #define KAL_NUM_DESC_WORDS 12 | |
199 | #define KAL_ANTENNA_MODE 1 | |
200 | #define KAL_TO_DS 1 | |
201 | #define KAL_DELAY 4 /*delay of 4ms between 2 KAL frames */ | |
202 | #define KAL_TIMEOUT 900 | |
203 | ||
204 | #define MAX_PATTERN_SIZE 256 | |
205 | #define MAX_PATTERN_MASK_SIZE 32 | |
206 | #define MAX_NUM_PATTERN 8 | |
207 | #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and | |
208 | deauthenticate packets */ | |
209 | ||
210 | /* | |
211 | * WoW trigger mapping to hardware code | |
212 | */ | |
213 | ||
214 | #define AH_WOW_USER_PATTERN_EN BIT(0) | |
215 | #define AH_WOW_MAGIC_PATTERN_EN BIT(1) | |
216 | #define AH_WOW_LINK_CHANGE BIT(2) | |
217 | #define AH_WOW_BEACON_MISS BIT(3) | |
218 | ||
066dae93 FF |
219 | enum ath_hw_txq_subtype { |
220 | ATH_TXQ_AC_BE = 0, | |
221 | ATH_TXQ_AC_BK = 1, | |
222 | ATH_TXQ_AC_VI = 2, | |
223 | ATH_TXQ_AC_VO = 3, | |
224 | }; | |
225 | ||
13ce3e99 LR |
226 | enum ath_ini_subsys { |
227 | ATH_INI_PRE = 0, | |
228 | ATH_INI_CORE, | |
229 | ATH_INI_POST, | |
230 | ATH_INI_NUM_SPLIT, | |
231 | }; | |
232 | ||
394cf0a1 | 233 | enum ath9k_hw_caps { |
364734fa FF |
234 | ATH9K_HW_CAP_HT = BIT(0), |
235 | ATH9K_HW_CAP_RFSILENT = BIT(1), | |
1b2538b2 MSS |
236 | ATH9K_HW_CAP_AUTOSLEEP = BIT(2), |
237 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3), | |
238 | ATH9K_HW_CAP_EDMA = BIT(4), | |
239 | ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5), | |
240 | ATH9K_HW_CAP_LDPC = BIT(6), | |
241 | ATH9K_HW_CAP_FASTCLOCK = BIT(7), | |
242 | ATH9K_HW_CAP_SGI_20 = BIT(8), | |
1b2538b2 MSS |
243 | ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10), |
244 | ATH9K_HW_CAP_2GHZ = BIT(11), | |
245 | ATH9K_HW_CAP_5GHZ = BIT(12), | |
246 | ATH9K_HW_CAP_APM = BIT(13), | |
935477ed | 247 | #ifdef CONFIG_ATH9K_PCOEM |
1b2538b2 MSS |
248 | ATH9K_HW_CAP_RTT = BIT(14), |
249 | ATH9K_HW_CAP_MCI = BIT(15), | |
935477ed FF |
250 | ATH9K_HW_WOW_DEVICE_CAPABLE = BIT(16), |
251 | ATH9K_HW_CAP_BT_ANT_DIV = BIT(17), | |
252 | #else | |
253 | ATH9K_HW_CAP_RTT = 0, | |
254 | ATH9K_HW_CAP_MCI = 0, | |
255 | ATH9K_HW_WOW_DEVICE_CAPABLE = 0, | |
256 | ATH9K_HW_CAP_BT_ANT_DIV = 0, | |
257 | #endif | |
258 | ATH9K_HW_CAP_DFS = BIT(18), | |
259 | ATH9K_HW_CAP_PAPRD = BIT(19), | |
260 | ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20), | |
394cf0a1 | 261 | }; |
f078f209 | 262 | |
8e981389 MSS |
263 | /* |
264 | * WoW device capabilities | |
265 | * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW. | |
266 | * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching | |
267 | * an exact user defined pattern or de-authentication/disassoc pattern. | |
268 | * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four | |
269 | * bytes of the pattern for user defined pattern, de-authentication and | |
270 | * disassociation patterns for all types of possible frames recieved | |
271 | * of those types. | |
272 | */ | |
273 | ||
394cf0a1 S |
274 | struct ath9k_hw_capabilities { |
275 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | |
394cf0a1 S |
276 | u16 rts_aggr_limit; |
277 | u8 tx_chainmask; | |
278 | u8 rx_chainmask; | |
47c80de6 VT |
279 | u8 max_txchains; |
280 | u8 max_rxchains; | |
394cf0a1 | 281 | u8 num_gpio_pins; |
ceb26445 VT |
282 | u8 rx_hp_qdepth; |
283 | u8 rx_lp_qdepth; | |
284 | u8 rx_status_len; | |
162c3be3 | 285 | u8 tx_desc_len; |
5088c2f1 | 286 | u8 txs_len; |
394cf0a1 | 287 | }; |
f078f209 | 288 | |
4598702d SM |
289 | #define AR_NO_SPUR 0x8000 |
290 | #define AR_BASE_FREQ_2GHZ 2300 | |
291 | #define AR_BASE_FREQ_5GHZ 4900 | |
292 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | |
293 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | |
294 | ||
295 | enum ath9k_hw_hang_checks { | |
296 | HW_BB_WATCHDOG = BIT(0), | |
297 | HW_PHYRESTART_CLC_WAR = BIT(1), | |
298 | HW_BB_RIFS_HANG = BIT(2), | |
299 | HW_BB_DFS_HANG = BIT(3), | |
300 | HW_BB_RX_CLEAR_STUCK_HANG = BIT(4), | |
301 | HW_MAC_HANG = BIT(5), | |
302 | }; | |
303 | ||
394cf0a1 S |
304 | struct ath9k_ops_config { |
305 | int dma_beacon_response_time; | |
306 | int sw_beacon_response_time; | |
41f3e54d | 307 | u32 cwm_ignore_extcca; |
394cf0a1 | 308 | u32 pcie_waen; |
394cf0a1 | 309 | u8 analog_shiftreg; |
394cf0a1 S |
310 | u32 ofdm_trig_low; |
311 | u32 ofdm_trig_high; | |
312 | u32 cck_trig_high; | |
313 | u32 cck_trig_low; | |
74673db9 | 314 | u32 enable_paprd; |
394cf0a1 | 315 | int serialize_regmode; |
0ce024cb | 316 | bool rx_intr_mitigation; |
55e82df4 | 317 | bool tx_intr_mitigation; |
f4709fdf | 318 | u8 max_txtrig_level; |
e36b27af | 319 | u16 ani_poll_interval; /* ANI poll interval in ms */ |
4598702d | 320 | u16 hw_hang_checks; |
a64e1a45 SM |
321 | u16 rimt_first; |
322 | u16 rimt_last; | |
9b60b64b SM |
323 | |
324 | /* Platform specific config */ | |
b380a43b | 325 | u32 aspm_l1_fix; |
9b60b64b | 326 | u32 xlna_gpio; |
31fd216d | 327 | u32 ant_ctrl_comm2g_switch_enable; |
9b60b64b | 328 | bool xatten_margin_cfg; |
e083a42e | 329 | bool alt_mingainidx; |
2d22c7dd | 330 | bool no_pll_pwrsave; |
0f978bfa | 331 | bool tx_gain_buffalo; |
394cf0a1 | 332 | }; |
f078f209 | 333 | |
394cf0a1 S |
334 | enum ath9k_int { |
335 | ATH9K_INT_RX = 0x00000001, | |
336 | ATH9K_INT_RXDESC = 0x00000002, | |
b5c80475 FF |
337 | ATH9K_INT_RXHP = 0x00000001, |
338 | ATH9K_INT_RXLP = 0x00000002, | |
394cf0a1 S |
339 | ATH9K_INT_RXNOFRM = 0x00000008, |
340 | ATH9K_INT_RXEOL = 0x00000010, | |
341 | ATH9K_INT_RXORN = 0x00000020, | |
342 | ATH9K_INT_TX = 0x00000040, | |
343 | ATH9K_INT_TXDESC = 0x00000080, | |
344 | ATH9K_INT_TIM_TIMER = 0x00000100, | |
2ee4bd1e | 345 | ATH9K_INT_MCI = 0x00000200, |
aea702b7 | 346 | ATH9K_INT_BB_WATCHDOG = 0x00000400, |
394cf0a1 S |
347 | ATH9K_INT_TXURN = 0x00000800, |
348 | ATH9K_INT_MIB = 0x00001000, | |
349 | ATH9K_INT_RXPHY = 0x00004000, | |
350 | ATH9K_INT_RXKCM = 0x00008000, | |
351 | ATH9K_INT_SWBA = 0x00010000, | |
352 | ATH9K_INT_BMISS = 0x00040000, | |
353 | ATH9K_INT_BNR = 0x00100000, | |
354 | ATH9K_INT_TIM = 0x00200000, | |
355 | ATH9K_INT_DTIM = 0x00400000, | |
356 | ATH9K_INT_DTIMSYNC = 0x00800000, | |
357 | ATH9K_INT_GPIO = 0x01000000, | |
358 | ATH9K_INT_CABEND = 0x02000000, | |
4af9cf4f | 359 | ATH9K_INT_TSFOOR = 0x04000000, |
ff155a45 | 360 | ATH9K_INT_GENTIMER = 0x08000000, |
394cf0a1 S |
361 | ATH9K_INT_CST = 0x10000000, |
362 | ATH9K_INT_GTT = 0x20000000, | |
363 | ATH9K_INT_FATAL = 0x40000000, | |
364 | ATH9K_INT_GLOBAL = 0x80000000, | |
365 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | |
366 | ATH9K_INT_DTIM | | |
367 | ATH9K_INT_DTIMSYNC | | |
4af9cf4f | 368 | ATH9K_INT_TSFOOR | |
394cf0a1 S |
369 | ATH9K_INT_CABEND, |
370 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | |
371 | ATH9K_INT_RXDESC | | |
372 | ATH9K_INT_RXEOL | | |
373 | ATH9K_INT_RXORN | | |
374 | ATH9K_INT_TXURN | | |
375 | ATH9K_INT_TXDESC | | |
376 | ATH9K_INT_MIB | | |
377 | ATH9K_INT_RXPHY | | |
378 | ATH9K_INT_RXKCM | | |
379 | ATH9K_INT_SWBA | | |
380 | ATH9K_INT_BMISS | | |
381 | ATH9K_INT_GPIO, | |
382 | ATH9K_INT_NOCARD = 0xffffffff | |
383 | }; | |
f078f209 | 384 | |
324c74ad | 385 | #define MAX_RTT_TABLE_ENTRY 6 |
5f0c04ea | 386 | #define MAX_IQCAL_MEASUREMENT 8 |
77a5a664 | 387 | #define MAX_CL_TAB_ENTRY 16 |
96da6fdd | 388 | #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j)) |
5f0c04ea | 389 | |
4b9b42bf SM |
390 | enum ath9k_cal_flags { |
391 | RTT_DONE, | |
392 | PAPRD_PACKET_SENT, | |
393 | PAPRD_DONE, | |
394 | NFCAL_PENDING, | |
395 | NFCAL_INTF, | |
396 | TXIQCAL_DONE, | |
397 | TXCLCAL_DONE, | |
3001f0d0 | 398 | SW_PKDET_DONE, |
4b9b42bf SM |
399 | }; |
400 | ||
20bd2a09 | 401 | struct ath9k_hw_cal_data { |
394cf0a1 | 402 | u16 channel; |
6b21fd20 | 403 | u16 channelFlags; |
4b9b42bf | 404 | unsigned long cal_flags; |
394cf0a1 | 405 | int32_t CalValid; |
394cf0a1 S |
406 | int8_t iCoff; |
407 | int8_t qCoff; | |
3001f0d0 | 408 | u8 caldac[2]; |
717f6bed FF |
409 | u16 small_signal_gain[AR9300_MAX_CHAINS]; |
410 | u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; | |
5f0c04ea RM |
411 | u32 num_measures[AR9300_MAX_CHAINS]; |
412 | int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS]; | |
77a5a664 | 413 | u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY]; |
8a90555f | 414 | u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY]; |
20bd2a09 FF |
415 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
416 | }; | |
417 | ||
418 | struct ath9k_channel { | |
419 | struct ieee80211_channel *chan; | |
420 | u16 channel; | |
6b21fd20 | 421 | u16 channelFlags; |
d9891c78 | 422 | s16 noisefloor; |
394cf0a1 | 423 | }; |
f078f209 | 424 | |
6b21fd20 FF |
425 | #define CHANNEL_5GHZ BIT(0) |
426 | #define CHANNEL_HALF BIT(1) | |
427 | #define CHANNEL_QUARTER BIT(2) | |
428 | #define CHANNEL_HT BIT(3) | |
429 | #define CHANNEL_HT40PLUS BIT(4) | |
430 | #define CHANNEL_HT40MINUS BIT(5) | |
431 | ||
432 | #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ)) | |
433 | #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c)) | |
434 | ||
435 | #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF)) | |
436 | #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER)) | |
6b42e8d0 | 437 | #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ |
6b21fd20 FF |
438 | (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) |
439 | ||
440 | #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT) | |
441 | ||
442 | #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c)) | |
443 | ||
444 | #define IS_CHAN_HT40(_c) \ | |
445 | (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS))) | |
446 | ||
447 | #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS) | |
448 | #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS) | |
394cf0a1 S |
449 | |
450 | enum ath9k_power_mode { | |
451 | ATH9K_PM_AWAKE = 0, | |
452 | ATH9K_PM_FULL_SLEEP, | |
453 | ATH9K_PM_NETWORK_SLEEP, | |
454 | ATH9K_PM_UNDEFINED | |
455 | }; | |
f078f209 | 456 | |
394cf0a1 S |
457 | enum ser_reg_mode { |
458 | SER_REG_MODE_OFF = 0, | |
459 | SER_REG_MODE_ON = 1, | |
460 | SER_REG_MODE_AUTO = 2, | |
461 | }; | |
f078f209 | 462 | |
ad7b8060 VT |
463 | enum ath9k_rx_qtype { |
464 | ATH9K_RX_QUEUE_HP, | |
465 | ATH9K_RX_QUEUE_LP, | |
466 | ATH9K_RX_QUEUE_MAX, | |
467 | }; | |
468 | ||
394cf0a1 S |
469 | struct ath9k_beacon_state { |
470 | u32 bs_nexttbtt; | |
471 | u32 bs_nextdtim; | |
472 | u32 bs_intval; | |
4af9cf4f | 473 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
394cf0a1 | 474 | u32 bs_dtimperiod; |
394cf0a1 S |
475 | u16 bs_bmissthreshold; |
476 | u32 bs_sleepduration; | |
4af9cf4f | 477 | u32 bs_tsfoor_threshold; |
394cf0a1 | 478 | }; |
f078f209 | 479 | |
394cf0a1 S |
480 | struct chan_centers { |
481 | u16 synth_center; | |
482 | u16 ctl_center; | |
483 | u16 ext_center; | |
484 | }; | |
f078f209 | 485 | |
394cf0a1 S |
486 | enum { |
487 | ATH9K_RESET_POWER_ON, | |
488 | ATH9K_RESET_WARM, | |
489 | ATH9K_RESET_COLD, | |
490 | }; | |
f078f209 | 491 | |
d535a42a S |
492 | struct ath9k_hw_version { |
493 | u32 magic; | |
494 | u16 devid; | |
495 | u16 subvendorid; | |
496 | u32 macVersion; | |
497 | u16 macRev; | |
498 | u16 phyRev; | |
499 | u16 analog5GhzRev; | |
500 | u16 analog2GhzRev; | |
0b5ead91 | 501 | enum ath_usb_dev usbdev; |
d535a42a | 502 | }; |
394cf0a1 | 503 | |
ff155a45 VT |
504 | /* Generic TSF timer definitions */ |
505 | ||
506 | #define ATH_MAX_GEN_TIMER 16 | |
507 | ||
508 | #define AR_GENTMR_BIT(_index) (1 << (_index)) | |
509 | ||
ff155a45 VT |
510 | struct ath_gen_timer_configuration { |
511 | u32 next_addr; | |
512 | u32 period_addr; | |
513 | u32 mode_addr; | |
514 | u32 mode_mask; | |
515 | }; | |
516 | ||
517 | struct ath_gen_timer { | |
518 | void (*trigger)(void *arg); | |
519 | void (*overflow)(void *arg); | |
520 | void *arg; | |
521 | u8 index; | |
522 | }; | |
523 | ||
524 | struct ath_gen_timer_table { | |
ff155a45 | 525 | struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; |
c67ce339 | 526 | u16 timer_mask; |
ff155a45 VT |
527 | }; |
528 | ||
21cc630f VT |
529 | struct ath_hw_antcomb_conf { |
530 | u8 main_lna_conf; | |
531 | u8 alt_lna_conf; | |
532 | u8 fast_div_bias; | |
c6ba9feb MSS |
533 | u8 main_gaintb; |
534 | u8 alt_gaintb; | |
535 | int lna1_lna2_delta; | |
f96bd2ad | 536 | int lna1_lna2_switch_delta; |
8afbcc8b | 537 | u8 div_group; |
21cc630f VT |
538 | }; |
539 | ||
4e8c14e9 FF |
540 | /** |
541 | * struct ath_hw_radar_conf - radar detection initialization parameters | |
542 | * | |
543 | * @pulse_inband: threshold for checking the ratio of in-band power | |
544 | * to total power for short radar pulses (half dB steps) | |
545 | * @pulse_inband_step: threshold for checking an in-band power to total | |
546 | * power ratio increase for short radar pulses (half dB steps) | |
547 | * @pulse_height: threshold for detecting the beginning of a short | |
548 | * radar pulse (dB step) | |
549 | * @pulse_rssi: threshold for detecting if a short radar pulse is | |
550 | * gone (dB step) | |
551 | * @pulse_maxlen: maximum pulse length (0.8 us steps) | |
552 | * | |
553 | * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) | |
554 | * @radar_inband: threshold for checking the ratio of in-band power | |
555 | * to total power for long radar pulses (half dB steps) | |
556 | * @fir_power: threshold for detecting the end of a long radar pulse (dB) | |
557 | * | |
558 | * @ext_channel: enable extension channel radar detection | |
559 | */ | |
560 | struct ath_hw_radar_conf { | |
561 | unsigned int pulse_inband; | |
562 | unsigned int pulse_inband_step; | |
563 | unsigned int pulse_height; | |
564 | unsigned int pulse_rssi; | |
565 | unsigned int pulse_maxlen; | |
566 | ||
567 | unsigned int radar_rssi; | |
568 | unsigned int radar_inband; | |
569 | int fir_power; | |
570 | ||
571 | bool ext_channel; | |
572 | }; | |
573 | ||
d70357d5 LR |
574 | /** |
575 | * struct ath_hw_private_ops - callbacks used internally by hardware code | |
576 | * | |
577 | * This structure contains private callbacks designed to only be used internally | |
578 | * by the hardware core. | |
579 | * | |
795f5e2c LR |
580 | * @init_cal_settings: setup types of calibrations supported |
581 | * @init_cal: starts actual calibration | |
582 | * | |
991312d8 | 583 | * @init_mode_gain_regs: Initialize TX/RX gain registers |
8fe65368 LR |
584 | * |
585 | * @rf_set_freq: change frequency | |
586 | * @spur_mitigate_freq: spur mitigation | |
8fe65368 | 587 | * @set_rf_regs: |
64773964 LR |
588 | * @compute_pll_control: compute the PLL control value to use for |
589 | * AR_RTC_PLL_CONTROL for a given channel | |
795f5e2c LR |
590 | * @setup_calibration: set up calibration |
591 | * @iscal_supported: used to query if a type of calibration is supported | |
ac0bb767 | 592 | * |
e36b27af LR |
593 | * @ani_cache_ini_regs: cache the values for ANI from the initial |
594 | * register settings through the register initialization. | |
d70357d5 LR |
595 | */ |
596 | struct ath_hw_private_ops { | |
4598702d | 597 | void (*init_hang_checks)(struct ath_hw *ah); |
990de2b2 SM |
598 | bool (*detect_mac_hang)(struct ath_hw *ah); |
599 | bool (*detect_bb_hang)(struct ath_hw *ah); | |
600 | ||
795f5e2c | 601 | /* Calibration ops */ |
d70357d5 | 602 | void (*init_cal_settings)(struct ath_hw *ah); |
795f5e2c LR |
603 | bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); |
604 | ||
991312d8 | 605 | void (*init_mode_gain_regs)(struct ath_hw *ah); |
795f5e2c LR |
606 | void (*setup_calibration)(struct ath_hw *ah, |
607 | struct ath9k_cal_list *currCal); | |
8fe65368 LR |
608 | |
609 | /* PHY ops */ | |
610 | int (*rf_set_freq)(struct ath_hw *ah, | |
611 | struct ath9k_channel *chan); | |
612 | void (*spur_mitigate_freq)(struct ath_hw *ah, | |
613 | struct ath9k_channel *chan); | |
8fe65368 LR |
614 | bool (*set_rf_regs)(struct ath_hw *ah, |
615 | struct ath9k_channel *chan, | |
616 | u16 modesIndex); | |
617 | void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); | |
618 | void (*init_bb)(struct ath_hw *ah, | |
619 | struct ath9k_channel *chan); | |
620 | int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); | |
621 | void (*olc_init)(struct ath_hw *ah); | |
622 | void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); | |
623 | void (*mark_phy_inactive)(struct ath_hw *ah); | |
624 | void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); | |
625 | bool (*rfbus_req)(struct ath_hw *ah); | |
626 | void (*rfbus_done)(struct ath_hw *ah); | |
8fe65368 | 627 | void (*restore_chainmask)(struct ath_hw *ah); |
64773964 LR |
628 | u32 (*compute_pll_control)(struct ath_hw *ah, |
629 | struct ath9k_channel *chan); | |
c16fcb49 FF |
630 | bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, |
631 | int param); | |
641d9921 | 632 | void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); |
4e8c14e9 FF |
633 | void (*set_radar_params)(struct ath_hw *ah, |
634 | struct ath_hw_radar_conf *conf); | |
5f0c04ea RM |
635 | int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, |
636 | u8 *ini_reloaded); | |
ac0bb767 LR |
637 | |
638 | /* ANI */ | |
e36b27af | 639 | void (*ani_cache_ini_regs)(struct ath_hw *ah); |
d70357d5 LR |
640 | }; |
641 | ||
e93d083f SW |
642 | /** |
643 | * struct ath_spec_scan - parameters for Atheros spectral scan | |
644 | * | |
645 | * @enabled: enable/disable spectral scan | |
646 | * @short_repeat: controls whether the chip is in spectral scan mode | |
647 | * for 4 usec (enabled) or 204 usec (disabled) | |
648 | * @count: number of scan results requested. There are special meanings | |
649 | * in some chip revisions: | |
650 | * AR92xx: highest bit set (>=128) for endless mode | |
651 | * (spectral scan won't stopped until explicitly disabled) | |
652 | * AR9300 and newer: 0 for endless mode | |
653 | * @endless: true if endless mode is intended. Otherwise, count value is | |
654 | * corrected to the next possible value. | |
655 | * @period: time duration between successive spectral scan entry points | |
656 | * (period*256*Tclk). Tclk = ath_common->clockrate | |
657 | * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS | |
658 | * | |
659 | * Note: Tclk = 40MHz or 44MHz depending upon operating mode. | |
660 | * Typically it's 44MHz in 2/5GHz on later chips, but there's | |
661 | * a "fast clock" check for this in 5GHz. | |
662 | * | |
663 | */ | |
664 | struct ath_spec_scan { | |
665 | bool enabled; | |
666 | bool short_repeat; | |
667 | bool endless; | |
668 | u8 count; | |
669 | u8 period; | |
670 | u8 fft_period; | |
671 | }; | |
672 | ||
d70357d5 LR |
673 | /** |
674 | * struct ath_hw_ops - callbacks used by hardware code and driver code | |
675 | * | |
676 | * This structure contains callbacks designed to to be used internally by | |
677 | * hardware code and also by the lower level driver. | |
678 | * | |
679 | * @config_pci_powersave: | |
795f5e2c | 680 | * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC |
e93d083f SW |
681 | * |
682 | * @spectral_scan_config: set parameters for spectral scan and enable/disable it | |
683 | * @spectral_scan_trigger: trigger a spectral scan run | |
684 | * @spectral_scan_wait: wait for a spectral scan run to finish | |
d70357d5 LR |
685 | */ |
686 | struct ath_hw_ops { | |
687 | void (*config_pci_powersave)(struct ath_hw *ah, | |
84c87dc8 | 688 | bool power_off); |
cee1f625 | 689 | void (*rx_enable)(struct ath_hw *ah); |
87d5efbb | 690 | void (*set_desc_link)(void *ds, u32 link); |
7b8aaead FF |
691 | int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan, |
692 | u8 rxchainmask, bool longcal); | |
6a4d05dc FF |
693 | bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked, |
694 | u32 *sync_cause_p); | |
2b63a41d FF |
695 | void (*set_txdesc)(struct ath_hw *ah, void *ds, |
696 | struct ath_tx_info *i); | |
cc610ac0 VT |
697 | int (*proc_txdesc)(struct ath_hw *ah, void *ds, |
698 | struct ath_tx_status *ts); | |
315dd114 | 699 | int (*get_duration)(struct ath_hw *ah, const void *ds, int index); |
69de3721 MSS |
700 | void (*antdiv_comb_conf_get)(struct ath_hw *ah, |
701 | struct ath_hw_antcomb_conf *antconf); | |
702 | void (*antdiv_comb_conf_set)(struct ath_hw *ah, | |
703 | struct ath_hw_antcomb_conf *antconf); | |
e93d083f SW |
704 | void (*spectral_scan_config)(struct ath_hw *ah, |
705 | struct ath_spec_scan *param); | |
706 | void (*spectral_scan_trigger)(struct ath_hw *ah); | |
707 | void (*spectral_scan_wait)(struct ath_hw *ah); | |
36e8825e | 708 | |
89f927af LR |
709 | void (*tx99_start)(struct ath_hw *ah, u32 qnum); |
710 | void (*tx99_stop)(struct ath_hw *ah); | |
711 | void (*tx99_set_txpower)(struct ath_hw *ah, u8 power); | |
712 | ||
36e8825e SM |
713 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
714 | void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable); | |
715 | #endif | |
d70357d5 LR |
716 | }; |
717 | ||
f2552e28 FF |
718 | struct ath_nf_limits { |
719 | s16 max; | |
720 | s16 min; | |
721 | s16 nominal; | |
722 | }; | |
723 | ||
8ad74c4d RM |
724 | enum ath_cal_list { |
725 | TX_IQ_CAL = BIT(0), | |
726 | TX_IQ_ON_AGC_CAL = BIT(1), | |
727 | TX_CL_CAL = BIT(2), | |
728 | }; | |
729 | ||
97dcec57 SM |
730 | /* ah_flags */ |
731 | #define AH_USE_EEPROM 0x1 | |
732 | #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ | |
a126ff51 | 733 | #define AH_FASTCC 0x4 |
97dcec57 | 734 | |
cbe61d8a | 735 | struct ath_hw { |
f9f84e96 FF |
736 | struct ath_ops reg_ops; |
737 | ||
c1b976d2 | 738 | struct device *dev; |
b002a4a9 | 739 | struct ieee80211_hw *hw; |
27c51f1a | 740 | struct ath_common common; |
cbe61d8a | 741 | struct ath9k_hw_version hw_version; |
2660b81a S |
742 | struct ath9k_ops_config config; |
743 | struct ath9k_hw_capabilities caps; | |
cac4220b | 744 | struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; |
2660b81a | 745 | struct ath9k_channel *curchan; |
394cf0a1 | 746 | |
cbe61d8a S |
747 | union { |
748 | struct ar5416_eeprom_def def; | |
749 | struct ar5416_eeprom_4k map4k; | |
475f5989 | 750 | struct ar9287_eeprom map9287; |
15c9ee7a | 751 | struct ar9300_eeprom ar9300_eep; |
2660b81a | 752 | } eeprom; |
f74df6fb | 753 | const struct eeprom_ops *eep_ops; |
cbe61d8a S |
754 | |
755 | bool sw_mgmt_crypto; | |
2660b81a | 756 | bool is_pciexpress; |
d4930086 | 757 | bool aspm_enabled; |
5f841b41 | 758 | bool is_monitoring; |
2eb46d9b | 759 | bool need_an_top2_fixup; |
2660b81a | 760 | u16 tx_trig_level; |
f2552e28 | 761 | |
bbacee13 | 762 | u32 nf_regs[6]; |
f2552e28 FF |
763 | struct ath_nf_limits nf_2g; |
764 | struct ath_nf_limits nf_5g; | |
2660b81a S |
765 | u16 rfsilent; |
766 | u32 rfkill_gpio; | |
767 | u32 rfkill_polarity; | |
cbe61d8a | 768 | u32 ah_flags; |
394cf0a1 | 769 | |
ceb26a60 | 770 | bool reset_power_on; |
d7e7d229 LR |
771 | bool htc_reset_init; |
772 | ||
2660b81a S |
773 | enum nl80211_iftype opmode; |
774 | enum ath9k_power_mode power_mode; | |
f078f209 | 775 | |
f23fba49 | 776 | s8 noise; |
20bd2a09 | 777 | struct ath9k_hw_cal_data *caldata; |
a13883b0 | 778 | struct ath9k_pacal_info pacal_info; |
2660b81a S |
779 | struct ar5416Stats stats; |
780 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; | |
781 | ||
3069168c | 782 | enum ath9k_int imask; |
74bad5cb | 783 | u32 imrs2_reg; |
2660b81a S |
784 | u32 txok_interrupt_mask; |
785 | u32 txerr_interrupt_mask; | |
786 | u32 txdesc_interrupt_mask; | |
787 | u32 txeol_interrupt_mask; | |
788 | u32 txurn_interrupt_mask; | |
e8fe7336 | 789 | atomic_t intr_ref_cnt; |
2660b81a | 790 | bool chip_fullsleep; |
5f0c04ea | 791 | u32 modes_index; |
6a2b9e8c S |
792 | |
793 | /* Calibration */ | |
6497827f | 794 | u32 supp_cals; |
cbfe9468 S |
795 | struct ath9k_cal_list iq_caldata; |
796 | struct ath9k_cal_list adcgain_caldata; | |
cbfe9468 S |
797 | struct ath9k_cal_list adcdc_caldata; |
798 | struct ath9k_cal_list *cal_list; | |
799 | struct ath9k_cal_list *cal_list_last; | |
800 | struct ath9k_cal_list *cal_list_curr; | |
2660b81a S |
801 | #define totalPowerMeasI meas0.unsign |
802 | #define totalPowerMeasQ meas1.unsign | |
803 | #define totalIqCorrMeas meas2.sign | |
804 | #define totalAdcIOddPhase meas0.unsign | |
805 | #define totalAdcIEvenPhase meas1.unsign | |
806 | #define totalAdcQOddPhase meas2.unsign | |
807 | #define totalAdcQEvenPhase meas3.unsign | |
808 | #define totalAdcDcOffsetIOddPhase meas0.sign | |
809 | #define totalAdcDcOffsetIEvenPhase meas1.sign | |
810 | #define totalAdcDcOffsetQOddPhase meas2.sign | |
811 | #define totalAdcDcOffsetQEvenPhase meas3.sign | |
f078f209 LR |
812 | union { |
813 | u32 unsign[AR5416_MAX_CHAINS]; | |
814 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 815 | } meas0; |
f078f209 LR |
816 | union { |
817 | u32 unsign[AR5416_MAX_CHAINS]; | |
818 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 819 | } meas1; |
f078f209 LR |
820 | union { |
821 | u32 unsign[AR5416_MAX_CHAINS]; | |
822 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 823 | } meas2; |
f078f209 LR |
824 | union { |
825 | u32 unsign[AR5416_MAX_CHAINS]; | |
826 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a S |
827 | } meas3; |
828 | u16 cal_samples; | |
8ad74c4d | 829 | u8 enabled_cals; |
6a2b9e8c | 830 | |
2660b81a S |
831 | u32 sta_id1_defaults; |
832 | u32 misc_mode; | |
6a2b9e8c | 833 | |
d70357d5 LR |
834 | /* Private to hardware code */ |
835 | struct ath_hw_private_ops private_ops; | |
836 | /* Accessed by the lower level driver */ | |
837 | struct ath_hw_ops ops; | |
838 | ||
e68a060b | 839 | /* Used to program the radio on non single-chip devices */ |
2660b81a | 840 | u32 *analogBank6Data; |
2660b81a | 841 | |
e239d859 | 842 | int coverage_class; |
2660b81a | 843 | u32 slottime; |
2660b81a | 844 | u32 globaltxtimeout; |
6a2b9e8c S |
845 | |
846 | /* ANI */ | |
2660b81a | 847 | u32 aniperiod; |
2660b81a | 848 | enum ath9k_ani_cmd ani_function; |
424749c7 | 849 | u32 ani_skip_count; |
c24bd362 | 850 | struct ar5416AniState ani; |
2660b81a | 851 | |
dbccdd1d | 852 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
766ec4a9 | 853 | struct ath_btcoex_hw btcoex_hw; |
dbccdd1d | 854 | #endif |
af03abec | 855 | |
2660b81a | 856 | u32 intr_txqs; |
2660b81a S |
857 | u8 txchainmask; |
858 | u8 rxchainmask; | |
859 | ||
c5d0855a FF |
860 | struct ath_hw_radar_conf radar_conf; |
861 | ||
8bd1d07f SB |
862 | u32 originalGain[22]; |
863 | int initPDADC; | |
864 | int PDADCdelta; | |
6de66dd9 | 865 | int led_pin; |
691680b8 FF |
866 | u32 gpio_mask; |
867 | u32 gpio_val; | |
8bd1d07f | 868 | |
4a878b9f | 869 | struct ar5416IniArray ini_dfs; |
2660b81a S |
870 | struct ar5416IniArray iniModes; |
871 | struct ar5416IniArray iniCommon; | |
2660b81a | 872 | struct ar5416IniArray iniBB_RfGain; |
2660b81a | 873 | struct ar5416IniArray iniBank6; |
2660b81a S |
874 | struct ar5416IniArray iniAddac; |
875 | struct ar5416IniArray iniPcieSerdes; | |
13ce3e99 | 876 | struct ar5416IniArray iniPcieSerdesLowPower; |
c7d36f9f FF |
877 | struct ar5416IniArray iniModesFastClock; |
878 | struct ar5416IniArray iniAdditional; | |
2660b81a | 879 | struct ar5416IniArray iniModesRxGain; |
8bc45c6b | 880 | struct ar5416IniArray ini_modes_rx_gain_bounds; |
2660b81a | 881 | struct ar5416IniArray iniModesTxGain; |
193cd458 S |
882 | struct ar5416IniArray iniCckfirNormal; |
883 | struct ar5416IniArray iniCckfirJapan2484; | |
70807e99 | 884 | struct ar5416IniArray iniModes_9271_ANI_reg; |
ce407afc | 885 | struct ar5416IniArray ini_radio_post_sys2ant; |
51dbd0a8 | 886 | struct ar5416IniArray ini_modes_rxgain_5g_xlna; |
c177fabe SM |
887 | struct ar5416IniArray ini_modes_rxgain_bb_core; |
888 | struct ar5416IniArray ini_modes_rxgain_bb_postamble; | |
ff155a45 | 889 | |
13ce3e99 LR |
890 | struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; |
891 | struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; | |
892 | struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; | |
893 | struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; | |
894 | ||
ff155a45 VT |
895 | u32 intr_gen_timer_trigger; |
896 | u32 intr_gen_timer_thresh; | |
897 | struct ath_gen_timer_table hw_gen_timers; | |
744d4025 VT |
898 | |
899 | struct ar9003_txs *ts_ring; | |
744d4025 VT |
900 | u32 ts_paddr_start; |
901 | u32 ts_paddr_end; | |
902 | u16 ts_tail; | |
016c2177 | 903 | u16 ts_size; |
aea702b7 LR |
904 | |
905 | u32 bb_watchdog_last_status; | |
906 | u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ | |
51ac8cbb | 907 | u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */ |
717f6bed | 908 | |
1bf38661 FF |
909 | unsigned int paprd_target_power; |
910 | unsigned int paprd_training_power; | |
7072bf62 | 911 | unsigned int paprd_ratemask; |
f1a8abb0 | 912 | unsigned int paprd_ratemask_ht40; |
45ef6a0b | 913 | bool paprd_table_write_done; |
717f6bed FF |
914 | u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; |
915 | u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; | |
9a658d2b LR |
916 | /* |
917 | * Store the permanent value of Reg 0x4004in WARegVal | |
918 | * so we dont have to R/M/W. We should not be reading | |
919 | * this register when in sleep states. | |
920 | */ | |
921 | u32 WARegVal; | |
6ee63f55 SB |
922 | |
923 | /* Enterprise mode cap */ | |
924 | u32 ent_mode; | |
f2f5f2a1 | 925 | |
e60001e7 | 926 | #ifdef CONFIG_ATH9K_WOW |
01c78533 MSS |
927 | u32 wow_event_mask; |
928 | #endif | |
f2f5f2a1 | 929 | bool is_clk_25mhz; |
3762561a | 930 | int (*get_mac_revision)(void); |
7d95847c | 931 | int (*external_reset)(void); |
ab5c4f71 GJ |
932 | |
933 | const struct firmware *eeprom_blob; | |
c774d57f LB |
934 | |
935 | struct ath_dynack dynack; | |
f078f209 | 936 | }; |
f078f209 | 937 | |
0cb9e06b FF |
938 | struct ath_bus_ops { |
939 | enum ath_bus_type ath_bus_type; | |
940 | void (*read_cachesize)(struct ath_common *common, int *csz); | |
941 | bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data); | |
942 | void (*bt_coex_prep)(struct ath_common *common); | |
d4930086 | 943 | void (*aspm_init)(struct ath_common *common); |
0cb9e06b FF |
944 | }; |
945 | ||
9e4bffd2 LR |
946 | static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) |
947 | { | |
948 | return &ah->common; | |
949 | } | |
950 | ||
951 | static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) | |
952 | { | |
953 | return &(ath9k_hw_common(ah)->regulatory); | |
954 | } | |
955 | ||
d70357d5 LR |
956 | static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) |
957 | { | |
958 | return &ah->private_ops; | |
959 | } | |
960 | ||
961 | static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) | |
962 | { | |
963 | return &ah->ops; | |
964 | } | |
965 | ||
895ad7eb VT |
966 | static inline u8 get_streams(int mask) |
967 | { | |
968 | return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); | |
969 | } | |
970 | ||
f637cfd6 | 971 | /* Initialization, Detach, Reset */ |
285f2dda | 972 | void ath9k_hw_deinit(struct ath_hw *ah); |
f637cfd6 | 973 | int ath9k_hw_init(struct ath_hw *ah); |
cbe61d8a | 974 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
caed6579 | 975 | struct ath9k_hw_cal_data *caldata, bool fastcc); |
a9a29ce6 | 976 | int ath9k_hw_fill_cap_info(struct ath_hw *ah); |
8fe65368 | 977 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); |
394cf0a1 | 978 | |
394cf0a1 | 979 | /* GPIO / RFKILL / Antennae */ |
cbe61d8a S |
980 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); |
981 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); | |
982 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, | |
394cf0a1 | 983 | u32 ah_signal_type); |
cbe61d8a | 984 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
cbe61d8a | 985 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); |
394cf0a1 S |
986 | |
987 | /* General Operation */ | |
7c5adc8d FF |
988 | void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, |
989 | int hw_delay); | |
0caa7b14 | 990 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
0166b4be | 991 | void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, |
a9b6b256 | 992 | int column, unsigned int *writecnt); |
394cf0a1 | 993 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
4f0fc7c3 | 994 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 995 | u8 phy, int kbps, |
394cf0a1 | 996 | u32 frameLen, u16 rateix, bool shortPreamble); |
cbe61d8a | 997 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
394cf0a1 S |
998 | struct ath9k_channel *chan, |
999 | struct chan_centers *centers); | |
cbe61d8a S |
1000 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
1001 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); | |
1002 | bool ath9k_hw_phy_disable(struct ath_hw *ah); | |
1003 | bool ath9k_hw_disable(struct ath_hw *ah); | |
de40f316 | 1004 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); |
cbe61d8a S |
1005 | void ath9k_hw_setopmode(struct ath_hw *ah); |
1006 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); | |
f2b2143e | 1007 | void ath9k_hw_write_associd(struct ath_hw *ah); |
dd347f2f | 1008 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); |
cbe61d8a S |
1009 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
1010 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); | |
1011 | void ath9k_hw_reset_tsf(struct ath_hw *ah); | |
8d7e09dd | 1012 | u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur); |
60ca9f87 | 1013 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set); |
0005baf4 | 1014 | void ath9k_hw_init_global_settings(struct ath_hw *ah); |
b84628eb | 1015 | u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); |
e4744ec7 | 1016 | void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan); |
cbe61d8a S |
1017 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); |
1018 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |
394cf0a1 | 1019 | const struct ath9k_beacon_state *bs); |
1e516ca7 | 1020 | void ath9k_hw_check_nav(struct ath_hw *ah); |
c9c99e5e | 1021 | bool ath9k_hw_check_alive(struct ath_hw *ah); |
a91d75ae | 1022 | |
9ecdef4b | 1023 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); |
a91d75ae | 1024 | |
ff155a45 VT |
1025 | /* Generic hw timer primitives */ |
1026 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
1027 | void (*trigger)(void *), | |
1028 | void (*overflow)(void *), | |
1029 | void *arg, | |
1030 | u8 timer_index); | |
cd9bf689 LR |
1031 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
1032 | struct ath_gen_timer *timer, | |
1033 | u32 timer_next, | |
1034 | u32 timer_period); | |
1035 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); | |
1036 | ||
ff155a45 VT |
1037 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); |
1038 | void ath_gen_timer_isr(struct ath_hw *hw); | |
1039 | ||
f934c4d9 | 1040 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); |
2da4f01a | 1041 | |
8fe65368 LR |
1042 | /* PHY */ |
1043 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, | |
1044 | u32 *coef_mantissa, u32 *coef_exponent); | |
64ea57d0 GJ |
1045 | void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, |
1046 | bool test); | |
8fe65368 | 1047 | |
ebd5a14a LR |
1048 | /* |
1049 | * Code Specific to AR5008, AR9001 or AR9002, | |
1050 | * we stuff these here to avoid callbacks for AR9003. | |
1051 | */ | |
ebd5a14a | 1052 | int ar9002_hw_rf_claim(struct ath_hw *ah); |
78ec2677 | 1053 | void ar9002_hw_enable_async_fifo(struct ath_hw *ah); |
d8f492b7 | 1054 | |
641d9921 | 1055 | /* |
aea702b7 | 1056 | * Code specific to AR9003, we stuff these here to avoid callbacks |
641d9921 FF |
1057 | * for older families |
1058 | */ | |
d88527d3 | 1059 | bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah); |
aea702b7 LR |
1060 | void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); |
1061 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); | |
1062 | void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); | |
51ac8cbb | 1063 | void ar9003_hw_disable_phy_restart(struct ath_hw *ah); |
717f6bed FF |
1064 | void ar9003_paprd_enable(struct ath_hw *ah, bool val); |
1065 | void ar9003_paprd_populate_single_table(struct ath_hw *ah, | |
20bd2a09 FF |
1066 | struct ath9k_hw_cal_data *caldata, |
1067 | int chain); | |
1068 | int ar9003_paprd_create_curve(struct ath_hw *ah, | |
1069 | struct ath9k_hw_cal_data *caldata, int chain); | |
36d2943b | 1070 | void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); |
717f6bed FF |
1071 | int ar9003_paprd_init_table(struct ath_hw *ah); |
1072 | bool ar9003_paprd_is_done(struct ath_hw *ah); | |
0f21ee8d | 1073 | bool ar9003_is_paprd_enabled(struct ath_hw *ah); |
4a8f1995 | 1074 | void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx); |
641d9921 FF |
1075 | |
1076 | /* Hardware family op attach helpers */ | |
c1b976d2 | 1077 | int ar5008_hw_attach_phy_ops(struct ath_hw *ah); |
8525f280 LR |
1078 | void ar9002_hw_attach_phy_ops(struct ath_hw *ah); |
1079 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah); | |
8fe65368 | 1080 | |
795f5e2c LR |
1081 | void ar9002_hw_attach_calib_ops(struct ath_hw *ah); |
1082 | void ar9003_hw_attach_calib_ops(struct ath_hw *ah); | |
1083 | ||
c1b976d2 | 1084 | int ar9002_hw_attach_ops(struct ath_hw *ah); |
b3950e6a LR |
1085 | void ar9003_hw_attach_ops(struct ath_hw *ah); |
1086 | ||
c2ba3342 | 1087 | void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); |
6790ae7a | 1088 | |
8eb4980c | 1089 | void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); |
95792178 | 1090 | void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); |
ac0bb767 | 1091 | |
8e15e094 LB |
1092 | void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us); |
1093 | void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us); | |
1094 | void ath9k_hw_setslottime(struct ath_hw *ah, u32 us); | |
1095 | ||
8a309305 | 1096 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
dbccdd1d SM |
1097 | static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) |
1098 | { | |
1099 | return ah->btcoex_hw.enabled; | |
1100 | } | |
5955b2b0 SM |
1101 | static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) |
1102 | { | |
e1ecad78 RM |
1103 | return ah->common.btcoex_enabled && |
1104 | (ah->caps.hw_caps & ATH9K_HW_CAP_MCI); | |
5955b2b0 SM |
1105 | |
1106 | } | |
dbccdd1d | 1107 | void ath9k_hw_btcoex_enable(struct ath_hw *ah); |
8a309305 FF |
1108 | static inline enum ath_btcoex_scheme |
1109 | ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) | |
1110 | { | |
1111 | return ah->btcoex_hw.scheme; | |
1112 | } | |
1113 | #else | |
dbccdd1d SM |
1114 | static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah) |
1115 | { | |
1116 | return false; | |
1117 | } | |
5955b2b0 SM |
1118 | static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah) |
1119 | { | |
1120 | return false; | |
1121 | } | |
dbccdd1d SM |
1122 | static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah) |
1123 | { | |
1124 | } | |
1125 | static inline enum ath_btcoex_scheme | |
1126 | ath9k_hw_get_btcoex_scheme(struct ath_hw *ah) | |
1127 | { | |
1128 | return ATH_BTCOEX_CFG_NONE; | |
1129 | } | |
64ab38df | 1130 | #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */ |
8a309305 | 1131 | |
64875c63 | 1132 | |
e60001e7 | 1133 | #ifdef CONFIG_ATH9K_WOW |
64875c63 MSS |
1134 | const char *ath9k_hw_wow_event_to_string(u32 wow_event); |
1135 | void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern, | |
1136 | u8 *user_mask, int pattern_count, | |
1137 | int pattern_len); | |
1138 | u32 ath9k_hw_wow_wakeup(struct ath_hw *ah); | |
1139 | void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable); | |
1140 | #else | |
1141 | static inline const char *ath9k_hw_wow_event_to_string(u32 wow_event) | |
1142 | { | |
1143 | return NULL; | |
1144 | } | |
1145 | static inline void ath9k_hw_wow_apply_pattern(struct ath_hw *ah, | |
1146 | u8 *user_pattern, | |
1147 | u8 *user_mask, | |
1148 | int pattern_count, | |
1149 | int pattern_len) | |
1150 | { | |
1151 | } | |
1152 | static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah) | |
1153 | { | |
1154 | return 0; | |
1155 | } | |
1156 | static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable) | |
1157 | { | |
1158 | } | |
1159 | #endif | |
1160 | ||
73377256 LR |
1161 | #define ATH9K_CLOCK_RATE_CCK 22 |
1162 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 | |
1163 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 | |
1164 | #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 | |
1165 | ||
f078f209 | 1166 | #endif |