]>
Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
b3950e6a | 2 | * Copyright (c) 2008-2010 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef HW_H | |
18 | #define HW_H | |
19 | ||
20 | #include <linux/if_ether.h> | |
21 | #include <linux/delay.h> | |
394cf0a1 S |
22 | #include <linux/io.h> |
23 | ||
24 | #include "mac.h" | |
25 | #include "ani.h" | |
26 | #include "eeprom.h" | |
27 | #include "calib.h" | |
394cf0a1 S |
28 | #include "reg.h" |
29 | #include "phy.h" | |
af03abec | 30 | #include "btcoex.h" |
394cf0a1 | 31 | |
203c4805 | 32 | #include "../regd.h" |
3a702e49 | 33 | |
394cf0a1 | 34 | #define ATHEROS_VENDOR_ID 0x168c |
7976b426 | 35 | |
394cf0a1 S |
36 | #define AR5416_DEVID_PCI 0x0023 |
37 | #define AR5416_DEVID_PCIE 0x0024 | |
38 | #define AR9160_DEVID_PCI 0x0027 | |
39 | #define AR9280_DEVID_PCI 0x0029 | |
40 | #define AR9280_DEVID_PCIE 0x002a | |
41 | #define AR9285_DEVID_PCIE 0x002b | |
5ffaf8a3 | 42 | #define AR2427_DEVID_PCIE 0x002c |
db3cc53a SB |
43 | #define AR9287_DEVID_PCI 0x002d |
44 | #define AR9287_DEVID_PCIE 0x002e | |
45 | #define AR9300_DEVID_PCIE 0x0030 | |
3050c914 | 46 | #define AR9300_DEVID_AR9485_PCIE 0x0032 |
7976b426 | 47 | |
394cf0a1 | 48 | #define AR5416_AR9100_DEVID 0x000b |
7976b426 | 49 | |
394cf0a1 S |
50 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
51 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | |
52 | #define AR5416_MAGIC 0x19641014 | |
53 | ||
fe12946e VT |
54 | #define AR9280_COEX2WIRE_SUBSYSID 0x309b |
55 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa | |
56 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab | |
57 | ||
e3d01bfc LR |
58 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
59 | ||
cfe8cba9 LR |
60 | #define ATH_DEFAULT_NOISE_FLOOR -95 |
61 | ||
04658fba | 62 | #define ATH9K_RSSI_BAD -128 |
990b70ab | 63 | |
cac4220b FF |
64 | #define ATH9K_NUM_CHANNELS 38 |
65 | ||
394cf0a1 | 66 | /* Register read/write primitives */ |
9e4bffd2 | 67 | #define REG_WRITE(_ah, _reg, _val) \ |
f9f84e96 | 68 | (_ah)->reg_ops.write((_ah), (_val), (_reg)) |
9e4bffd2 LR |
69 | |
70 | #define REG_READ(_ah, _reg) \ | |
f9f84e96 | 71 | (_ah)->reg_ops.read((_ah), (_reg)) |
394cf0a1 | 72 | |
09a525d3 | 73 | #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \ |
f9f84e96 | 74 | (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt)) |
09a525d3 | 75 | |
845e03c9 FF |
76 | #define REG_RMW(_ah, _reg, _set, _clr) \ |
77 | (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr)) | |
78 | ||
20b3efd9 S |
79 | #define ENABLE_REGWRITE_BUFFER(_ah) \ |
80 | do { \ | |
f9f84e96 FF |
81 | if ((_ah)->reg_ops.enable_write_buffer) \ |
82 | (_ah)->reg_ops.enable_write_buffer((_ah)); \ | |
20b3efd9 S |
83 | } while (0) |
84 | ||
20b3efd9 S |
85 | #define REGWRITE_BUFFER_FLUSH(_ah) \ |
86 | do { \ | |
f9f84e96 FF |
87 | if ((_ah)->reg_ops.write_flush) \ |
88 | (_ah)->reg_ops.write_flush((_ah)); \ | |
20b3efd9 S |
89 | } while (0) |
90 | ||
394cf0a1 S |
91 | #define SM(_v, _f) (((_v) << _f##_S) & _f) |
92 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | |
394cf0a1 | 93 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ |
845e03c9 | 94 | REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f)) |
1547da37 LR |
95 | #define REG_READ_FIELD(_a, _r, _f) \ |
96 | (((REG_READ(_a, _r) & _f) >> _f##_S)) | |
394cf0a1 | 97 | #define REG_SET_BIT(_a, _r, _f) \ |
845e03c9 | 98 | REG_RMW(_a, _r, (_f), 0) |
394cf0a1 | 99 | #define REG_CLR_BIT(_a, _r, _f) \ |
845e03c9 | 100 | REG_RMW(_a, _r, 0, (_f)) |
f078f209 | 101 | |
e7fc6338 RM |
102 | #define DO_DELAY(x) do { \ |
103 | if (((++(x) % 64) == 0) && \ | |
104 | (ath9k_hw_common(ah)->bus_ops->ath_bus_type \ | |
105 | != ATH_USB)) \ | |
106 | udelay(1); \ | |
394cf0a1 | 107 | } while (0) |
f078f209 | 108 | |
a9b6b256 FF |
109 | #define REG_WRITE_ARRAY(iniarray, column, regWr) \ |
110 | ath9k_hw_write_array(ah, iniarray, column, &(regWr)) | |
f078f209 | 111 | |
394cf0a1 S |
112 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
113 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | |
114 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | |
115 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 | |
1773912b | 116 | #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 |
394cf0a1 S |
117 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
118 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | |
f078f209 | 119 | |
394cf0a1 S |
120 | #define AR_GPIOD_MASK 0x00001FFF |
121 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | |
f078f209 | 122 | |
394cf0a1 | 123 | #define BASE_ACTIVATE_DELAY 100 |
63a75b91 | 124 | #define RTC_PLL_SETTLE_DELAY 100 |
394cf0a1 S |
125 | #define COEF_SCALE_S 24 |
126 | #define HT40_CHANNEL_CENTER_SHIFT 10 | |
f078f209 | 127 | |
394cf0a1 S |
128 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
129 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 | |
130 | ||
131 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 | |
132 | #define ATH9K_NUM_QUEUES 10 | |
133 | ||
134 | #define MAX_RATE_POWER 63 | |
0caa7b14 | 135 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
f9b604f6 | 136 | #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ |
394cf0a1 S |
137 | #define AH_TIME_QUANTUM 10 |
138 | #define AR_KEYTABLE_SIZE 128 | |
d8caa839 | 139 | #define POWER_UP_TIME 10000 |
394cf0a1 S |
140 | #define SPUR_RSSI_THRESH 40 |
141 | ||
142 | #define CAB_TIMEOUT_VAL 10 | |
143 | #define BEACON_TIMEOUT_VAL 10 | |
144 | #define MIN_BEACON_TIMEOUT_VAL 1 | |
145 | #define SLEEP_SLOP 3 | |
146 | ||
147 | #define INIT_CONFIG_STATUS 0x00000000 | |
148 | #define INIT_RSSI_THR 0x00000700 | |
149 | #define INIT_BCON_CNTRL_REG 0x00000000 | |
150 | ||
151 | #define TU_TO_USEC(_tu) ((_tu) << 10) | |
152 | ||
ceb26445 VT |
153 | #define ATH9K_HW_RX_HP_QDEPTH 16 |
154 | #define ATH9K_HW_RX_LP_QDEPTH 128 | |
155 | ||
717f6bed FF |
156 | #define PAPRD_GAIN_TABLE_ENTRIES 32 |
157 | #define PAPRD_TABLE_SZ 24 | |
158 | ||
066dae93 FF |
159 | enum ath_hw_txq_subtype { |
160 | ATH_TXQ_AC_BE = 0, | |
161 | ATH_TXQ_AC_BK = 1, | |
162 | ATH_TXQ_AC_VI = 2, | |
163 | ATH_TXQ_AC_VO = 3, | |
164 | }; | |
165 | ||
13ce3e99 LR |
166 | enum ath_ini_subsys { |
167 | ATH_INI_PRE = 0, | |
168 | ATH_INI_CORE, | |
169 | ATH_INI_POST, | |
170 | ATH_INI_NUM_SPLIT, | |
171 | }; | |
172 | ||
394cf0a1 | 173 | enum ath9k_hw_caps { |
364734fa FF |
174 | ATH9K_HW_CAP_HT = BIT(0), |
175 | ATH9K_HW_CAP_RFSILENT = BIT(1), | |
176 | ATH9K_HW_CAP_CST = BIT(2), | |
364734fa FF |
177 | ATH9K_HW_CAP_AUTOSLEEP = BIT(4), |
178 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5), | |
179 | ATH9K_HW_CAP_EDMA = BIT(6), | |
180 | ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7), | |
181 | ATH9K_HW_CAP_LDPC = BIT(8), | |
182 | ATH9K_HW_CAP_FASTCLOCK = BIT(9), | |
183 | ATH9K_HW_CAP_SGI_20 = BIT(10), | |
184 | ATH9K_HW_CAP_PAPRD = BIT(11), | |
185 | ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12), | |
d4659912 FF |
186 | ATH9K_HW_CAP_2GHZ = BIT(13), |
187 | ATH9K_HW_CAP_5GHZ = BIT(14), | |
ea066d5a | 188 | ATH9K_HW_CAP_APM = BIT(15), |
394cf0a1 | 189 | }; |
f078f209 | 190 | |
394cf0a1 S |
191 | struct ath9k_hw_capabilities { |
192 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | |
394cf0a1 S |
193 | u16 rts_aggr_limit; |
194 | u8 tx_chainmask; | |
195 | u8 rx_chainmask; | |
47c80de6 VT |
196 | u8 max_txchains; |
197 | u8 max_rxchains; | |
394cf0a1 | 198 | u8 num_gpio_pins; |
ceb26445 VT |
199 | u8 rx_hp_qdepth; |
200 | u8 rx_lp_qdepth; | |
201 | u8 rx_status_len; | |
162c3be3 | 202 | u8 tx_desc_len; |
5088c2f1 | 203 | u8 txs_len; |
8060e169 VT |
204 | u16 pcie_lcr_offset; |
205 | bool pcie_lcr_extsync_en; | |
394cf0a1 | 206 | }; |
f078f209 | 207 | |
394cf0a1 S |
208 | struct ath9k_ops_config { |
209 | int dma_beacon_response_time; | |
210 | int sw_beacon_response_time; | |
211 | int additional_swba_backoff; | |
212 | int ack_6mb; | |
41f3e54d | 213 | u32 cwm_ignore_extcca; |
394cf0a1 | 214 | u8 pcie_powersave_enable; |
6a0ec30a | 215 | bool pcieSerDesWrite; |
394cf0a1 S |
216 | u8 pcie_clock_req; |
217 | u32 pcie_waen; | |
394cf0a1 | 218 | u8 analog_shiftreg; |
6f481010 | 219 | u8 paprd_disable; |
394cf0a1 S |
220 | u32 ofdm_trig_low; |
221 | u32 ofdm_trig_high; | |
222 | u32 cck_trig_high; | |
223 | u32 cck_trig_low; | |
224 | u32 enable_ani; | |
394cf0a1 | 225 | int serialize_regmode; |
0ce024cb | 226 | bool rx_intr_mitigation; |
55e82df4 | 227 | bool tx_intr_mitigation; |
394cf0a1 S |
228 | #define SPUR_DISABLE 0 |
229 | #define SPUR_ENABLE_IOCTL 1 | |
230 | #define SPUR_ENABLE_EEPROM 2 | |
394cf0a1 S |
231 | #define AR_SPUR_5413_1 1640 |
232 | #define AR_SPUR_5413_2 1200 | |
233 | #define AR_NO_SPUR 0x8000 | |
234 | #define AR_BASE_FREQ_2GHZ 2300 | |
235 | #define AR_BASE_FREQ_5GHZ 4900 | |
236 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | |
237 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | |
238 | int spurmode; | |
239 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; | |
f4709fdf | 240 | u8 max_txtrig_level; |
e36b27af | 241 | u16 ani_poll_interval; /* ANI poll interval in ms */ |
394cf0a1 | 242 | }; |
f078f209 | 243 | |
394cf0a1 S |
244 | enum ath9k_int { |
245 | ATH9K_INT_RX = 0x00000001, | |
246 | ATH9K_INT_RXDESC = 0x00000002, | |
b5c80475 FF |
247 | ATH9K_INT_RXHP = 0x00000001, |
248 | ATH9K_INT_RXLP = 0x00000002, | |
394cf0a1 S |
249 | ATH9K_INT_RXNOFRM = 0x00000008, |
250 | ATH9K_INT_RXEOL = 0x00000010, | |
251 | ATH9K_INT_RXORN = 0x00000020, | |
252 | ATH9K_INT_TX = 0x00000040, | |
253 | ATH9K_INT_TXDESC = 0x00000080, | |
254 | ATH9K_INT_TIM_TIMER = 0x00000100, | |
aea702b7 | 255 | ATH9K_INT_BB_WATCHDOG = 0x00000400, |
394cf0a1 S |
256 | ATH9K_INT_TXURN = 0x00000800, |
257 | ATH9K_INT_MIB = 0x00001000, | |
258 | ATH9K_INT_RXPHY = 0x00004000, | |
259 | ATH9K_INT_RXKCM = 0x00008000, | |
260 | ATH9K_INT_SWBA = 0x00010000, | |
261 | ATH9K_INT_BMISS = 0x00040000, | |
262 | ATH9K_INT_BNR = 0x00100000, | |
263 | ATH9K_INT_TIM = 0x00200000, | |
264 | ATH9K_INT_DTIM = 0x00400000, | |
265 | ATH9K_INT_DTIMSYNC = 0x00800000, | |
266 | ATH9K_INT_GPIO = 0x01000000, | |
267 | ATH9K_INT_CABEND = 0x02000000, | |
4af9cf4f | 268 | ATH9K_INT_TSFOOR = 0x04000000, |
ff155a45 | 269 | ATH9K_INT_GENTIMER = 0x08000000, |
394cf0a1 S |
270 | ATH9K_INT_CST = 0x10000000, |
271 | ATH9K_INT_GTT = 0x20000000, | |
272 | ATH9K_INT_FATAL = 0x40000000, | |
273 | ATH9K_INT_GLOBAL = 0x80000000, | |
274 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | |
275 | ATH9K_INT_DTIM | | |
276 | ATH9K_INT_DTIMSYNC | | |
4af9cf4f | 277 | ATH9K_INT_TSFOOR | |
394cf0a1 S |
278 | ATH9K_INT_CABEND, |
279 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | |
280 | ATH9K_INT_RXDESC | | |
281 | ATH9K_INT_RXEOL | | |
282 | ATH9K_INT_RXORN | | |
283 | ATH9K_INT_TXURN | | |
284 | ATH9K_INT_TXDESC | | |
285 | ATH9K_INT_MIB | | |
286 | ATH9K_INT_RXPHY | | |
287 | ATH9K_INT_RXKCM | | |
288 | ATH9K_INT_SWBA | | |
289 | ATH9K_INT_BMISS | | |
290 | ATH9K_INT_GPIO, | |
291 | ATH9K_INT_NOCARD = 0xffffffff | |
292 | }; | |
f078f209 | 293 | |
394cf0a1 S |
294 | #define CHANNEL_CW_INT 0x00002 |
295 | #define CHANNEL_CCK 0x00020 | |
296 | #define CHANNEL_OFDM 0x00040 | |
297 | #define CHANNEL_2GHZ 0x00080 | |
298 | #define CHANNEL_5GHZ 0x00100 | |
299 | #define CHANNEL_PASSIVE 0x00200 | |
300 | #define CHANNEL_DYN 0x00400 | |
301 | #define CHANNEL_HALF 0x04000 | |
302 | #define CHANNEL_QUARTER 0x08000 | |
303 | #define CHANNEL_HT20 0x10000 | |
304 | #define CHANNEL_HT40PLUS 0x20000 | |
305 | #define CHANNEL_HT40MINUS 0x40000 | |
306 | ||
394cf0a1 S |
307 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
308 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) | |
309 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) | |
310 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) | |
311 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) | |
312 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) | |
313 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) | |
314 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) | |
315 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) | |
316 | #define CHANNEL_ALL \ | |
317 | (CHANNEL_OFDM| \ | |
318 | CHANNEL_CCK| \ | |
319 | CHANNEL_2GHZ | \ | |
320 | CHANNEL_5GHZ | \ | |
321 | CHANNEL_HT20 | \ | |
322 | CHANNEL_HT40PLUS | \ | |
323 | CHANNEL_HT40MINUS) | |
324 | ||
20bd2a09 | 325 | struct ath9k_hw_cal_data { |
394cf0a1 S |
326 | u16 channel; |
327 | u32 channelFlags; | |
394cf0a1 | 328 | int32_t CalValid; |
394cf0a1 S |
329 | int8_t iCoff; |
330 | int8_t qCoff; | |
717f6bed | 331 | bool paprd_done; |
4254bc1c | 332 | bool nfcal_pending; |
70cf1533 | 333 | bool nfcal_interference; |
717f6bed FF |
334 | u16 small_signal_gain[AR9300_MAX_CHAINS]; |
335 | u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; | |
20bd2a09 FF |
336 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
337 | }; | |
338 | ||
339 | struct ath9k_channel { | |
340 | struct ieee80211_channel *chan; | |
093115b7 | 341 | struct ar5416AniState ani; |
20bd2a09 FF |
342 | u16 channel; |
343 | u32 channelFlags; | |
344 | u32 chanmode; | |
d9891c78 | 345 | s16 noisefloor; |
394cf0a1 | 346 | }; |
f078f209 | 347 | |
394cf0a1 S |
348 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ |
349 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ | |
350 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ | |
351 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) | |
352 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) | |
353 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) | |
354 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) | |
394cf0a1 S |
355 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) |
356 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) | |
6b42e8d0 | 357 | #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ |
394cf0a1 | 358 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ |
6b42e8d0 | 359 | ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) |
394cf0a1 S |
360 | |
361 | /* These macros check chanmode and not channelFlags */ | |
362 | #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) | |
363 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ | |
364 | ((_c)->chanmode == CHANNEL_G_HT20)) | |
365 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ | |
366 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ | |
367 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ | |
368 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) | |
369 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) | |
370 | ||
371 | enum ath9k_power_mode { | |
372 | ATH9K_PM_AWAKE = 0, | |
373 | ATH9K_PM_FULL_SLEEP, | |
374 | ATH9K_PM_NETWORK_SLEEP, | |
375 | ATH9K_PM_UNDEFINED | |
376 | }; | |
f078f209 | 377 | |
394cf0a1 S |
378 | enum ath9k_tp_scale { |
379 | ATH9K_TP_SCALE_MAX = 0, | |
380 | ATH9K_TP_SCALE_50, | |
381 | ATH9K_TP_SCALE_25, | |
382 | ATH9K_TP_SCALE_12, | |
383 | ATH9K_TP_SCALE_MIN | |
384 | }; | |
f078f209 | 385 | |
394cf0a1 S |
386 | enum ser_reg_mode { |
387 | SER_REG_MODE_OFF = 0, | |
388 | SER_REG_MODE_ON = 1, | |
389 | SER_REG_MODE_AUTO = 2, | |
390 | }; | |
f078f209 | 391 | |
ad7b8060 VT |
392 | enum ath9k_rx_qtype { |
393 | ATH9K_RX_QUEUE_HP, | |
394 | ATH9K_RX_QUEUE_LP, | |
395 | ATH9K_RX_QUEUE_MAX, | |
396 | }; | |
397 | ||
394cf0a1 S |
398 | struct ath9k_beacon_state { |
399 | u32 bs_nexttbtt; | |
400 | u32 bs_nextdtim; | |
401 | u32 bs_intval; | |
402 | #define ATH9K_BEACON_PERIOD 0x0000ffff | |
4af9cf4f | 403 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
394cf0a1 S |
404 | u32 bs_dtimperiod; |
405 | u16 bs_cfpperiod; | |
406 | u16 bs_cfpmaxduration; | |
407 | u32 bs_cfpnext; | |
408 | u16 bs_timoffset; | |
409 | u16 bs_bmissthreshold; | |
410 | u32 bs_sleepduration; | |
4af9cf4f | 411 | u32 bs_tsfoor_threshold; |
394cf0a1 | 412 | }; |
f078f209 | 413 | |
394cf0a1 S |
414 | struct chan_centers { |
415 | u16 synth_center; | |
416 | u16 ctl_center; | |
417 | u16 ext_center; | |
418 | }; | |
f078f209 | 419 | |
394cf0a1 S |
420 | enum { |
421 | ATH9K_RESET_POWER_ON, | |
422 | ATH9K_RESET_WARM, | |
423 | ATH9K_RESET_COLD, | |
424 | }; | |
f078f209 | 425 | |
d535a42a S |
426 | struct ath9k_hw_version { |
427 | u32 magic; | |
428 | u16 devid; | |
429 | u16 subvendorid; | |
430 | u32 macVersion; | |
431 | u16 macRev; | |
432 | u16 phyRev; | |
433 | u16 analog5GhzRev; | |
434 | u16 analog2GhzRev; | |
aeac355d | 435 | u16 subsysid; |
0b5ead91 | 436 | enum ath_usb_dev usbdev; |
d535a42a | 437 | }; |
394cf0a1 | 438 | |
ff155a45 VT |
439 | /* Generic TSF timer definitions */ |
440 | ||
441 | #define ATH_MAX_GEN_TIMER 16 | |
442 | ||
443 | #define AR_GENTMR_BIT(_index) (1 << (_index)) | |
444 | ||
445 | /* | |
77c2061d | 446 | * Using de Bruijin sequence to look up 1's index in a 32 bit number |
ff155a45 VT |
447 | * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 |
448 | */ | |
c90017dd | 449 | #define debruijn32 0x077CB531U |
ff155a45 VT |
450 | |
451 | struct ath_gen_timer_configuration { | |
452 | u32 next_addr; | |
453 | u32 period_addr; | |
454 | u32 mode_addr; | |
455 | u32 mode_mask; | |
456 | }; | |
457 | ||
458 | struct ath_gen_timer { | |
459 | void (*trigger)(void *arg); | |
460 | void (*overflow)(void *arg); | |
461 | void *arg; | |
462 | u8 index; | |
463 | }; | |
464 | ||
465 | struct ath_gen_timer_table { | |
466 | u32 gen_timer_index[32]; | |
467 | struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; | |
468 | union { | |
469 | unsigned long timer_bits; | |
470 | u16 val; | |
471 | } timer_mask; | |
472 | }; | |
473 | ||
21cc630f VT |
474 | struct ath_hw_antcomb_conf { |
475 | u8 main_lna_conf; | |
476 | u8 alt_lna_conf; | |
477 | u8 fast_div_bias; | |
478 | }; | |
479 | ||
4e8c14e9 FF |
480 | /** |
481 | * struct ath_hw_radar_conf - radar detection initialization parameters | |
482 | * | |
483 | * @pulse_inband: threshold for checking the ratio of in-band power | |
484 | * to total power for short radar pulses (half dB steps) | |
485 | * @pulse_inband_step: threshold for checking an in-band power to total | |
486 | * power ratio increase for short radar pulses (half dB steps) | |
487 | * @pulse_height: threshold for detecting the beginning of a short | |
488 | * radar pulse (dB step) | |
489 | * @pulse_rssi: threshold for detecting if a short radar pulse is | |
490 | * gone (dB step) | |
491 | * @pulse_maxlen: maximum pulse length (0.8 us steps) | |
492 | * | |
493 | * @radar_rssi: RSSI threshold for starting long radar detection (dB steps) | |
494 | * @radar_inband: threshold for checking the ratio of in-band power | |
495 | * to total power for long radar pulses (half dB steps) | |
496 | * @fir_power: threshold for detecting the end of a long radar pulse (dB) | |
497 | * | |
498 | * @ext_channel: enable extension channel radar detection | |
499 | */ | |
500 | struct ath_hw_radar_conf { | |
501 | unsigned int pulse_inband; | |
502 | unsigned int pulse_inband_step; | |
503 | unsigned int pulse_height; | |
504 | unsigned int pulse_rssi; | |
505 | unsigned int pulse_maxlen; | |
506 | ||
507 | unsigned int radar_rssi; | |
508 | unsigned int radar_inband; | |
509 | int fir_power; | |
510 | ||
511 | bool ext_channel; | |
512 | }; | |
513 | ||
d70357d5 LR |
514 | /** |
515 | * struct ath_hw_private_ops - callbacks used internally by hardware code | |
516 | * | |
517 | * This structure contains private callbacks designed to only be used internally | |
518 | * by the hardware core. | |
519 | * | |
795f5e2c LR |
520 | * @init_cal_settings: setup types of calibrations supported |
521 | * @init_cal: starts actual calibration | |
522 | * | |
d70357d5 | 523 | * @init_mode_regs: Initializes mode registers |
991312d8 | 524 | * @init_mode_gain_regs: Initialize TX/RX gain registers |
8fe65368 LR |
525 | * |
526 | * @rf_set_freq: change frequency | |
527 | * @spur_mitigate_freq: spur mitigation | |
528 | * @rf_alloc_ext_banks: | |
529 | * @rf_free_ext_banks: | |
530 | * @set_rf_regs: | |
64773964 LR |
531 | * @compute_pll_control: compute the PLL control value to use for |
532 | * AR_RTC_PLL_CONTROL for a given channel | |
795f5e2c LR |
533 | * @setup_calibration: set up calibration |
534 | * @iscal_supported: used to query if a type of calibration is supported | |
ac0bb767 | 535 | * |
e36b27af LR |
536 | * @ani_cache_ini_regs: cache the values for ANI from the initial |
537 | * register settings through the register initialization. | |
d70357d5 LR |
538 | */ |
539 | struct ath_hw_private_ops { | |
795f5e2c | 540 | /* Calibration ops */ |
d70357d5 | 541 | void (*init_cal_settings)(struct ath_hw *ah); |
795f5e2c LR |
542 | bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); |
543 | ||
d70357d5 | 544 | void (*init_mode_regs)(struct ath_hw *ah); |
991312d8 | 545 | void (*init_mode_gain_regs)(struct ath_hw *ah); |
795f5e2c LR |
546 | void (*setup_calibration)(struct ath_hw *ah, |
547 | struct ath9k_cal_list *currCal); | |
8fe65368 LR |
548 | |
549 | /* PHY ops */ | |
550 | int (*rf_set_freq)(struct ath_hw *ah, | |
551 | struct ath9k_channel *chan); | |
552 | void (*spur_mitigate_freq)(struct ath_hw *ah, | |
553 | struct ath9k_channel *chan); | |
554 | int (*rf_alloc_ext_banks)(struct ath_hw *ah); | |
555 | void (*rf_free_ext_banks)(struct ath_hw *ah); | |
556 | bool (*set_rf_regs)(struct ath_hw *ah, | |
557 | struct ath9k_channel *chan, | |
558 | u16 modesIndex); | |
559 | void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); | |
560 | void (*init_bb)(struct ath_hw *ah, | |
561 | struct ath9k_channel *chan); | |
562 | int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); | |
563 | void (*olc_init)(struct ath_hw *ah); | |
564 | void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); | |
565 | void (*mark_phy_inactive)(struct ath_hw *ah); | |
566 | void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); | |
567 | bool (*rfbus_req)(struct ath_hw *ah); | |
568 | void (*rfbus_done)(struct ath_hw *ah); | |
8fe65368 LR |
569 | void (*restore_chainmask)(struct ath_hw *ah); |
570 | void (*set_diversity)(struct ath_hw *ah, bool value); | |
64773964 LR |
571 | u32 (*compute_pll_control)(struct ath_hw *ah, |
572 | struct ath9k_channel *chan); | |
c16fcb49 FF |
573 | bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, |
574 | int param); | |
641d9921 | 575 | void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); |
4e8c14e9 FF |
576 | void (*set_radar_params)(struct ath_hw *ah, |
577 | struct ath_hw_radar_conf *conf); | |
ac0bb767 LR |
578 | |
579 | /* ANI */ | |
e36b27af | 580 | void (*ani_cache_ini_regs)(struct ath_hw *ah); |
d70357d5 LR |
581 | }; |
582 | ||
583 | /** | |
584 | * struct ath_hw_ops - callbacks used by hardware code and driver code | |
585 | * | |
586 | * This structure contains callbacks designed to to be used internally by | |
587 | * hardware code and also by the lower level driver. | |
588 | * | |
589 | * @config_pci_powersave: | |
795f5e2c | 590 | * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC |
d70357d5 LR |
591 | */ |
592 | struct ath_hw_ops { | |
593 | void (*config_pci_powersave)(struct ath_hw *ah, | |
594 | int restore, | |
595 | int power_off); | |
cee1f625 | 596 | void (*rx_enable)(struct ath_hw *ah); |
87d5efbb VT |
597 | void (*set_desc_link)(void *ds, u32 link); |
598 | void (*get_desc_link)(void *ds, u32 **link); | |
795f5e2c LR |
599 | bool (*calibrate)(struct ath_hw *ah, |
600 | struct ath9k_channel *chan, | |
601 | u8 rxchainmask, | |
602 | bool longcal); | |
55e82df4 | 603 | bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); |
cc610ac0 VT |
604 | void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen, |
605 | bool is_firstseg, bool is_is_lastseg, | |
606 | const void *ds0, dma_addr_t buf_addr, | |
607 | unsigned int qcu); | |
608 | int (*proc_txdesc)(struct ath_hw *ah, void *ds, | |
609 | struct ath_tx_status *ts); | |
610 | void (*set11n_txdesc)(struct ath_hw *ah, void *ds, | |
611 | u32 pktLen, enum ath9k_pkt_type type, | |
612 | u32 txPower, u32 keyIx, | |
613 | enum ath9k_key_type keyType, | |
614 | u32 flags); | |
615 | void (*set11n_ratescenario)(struct ath_hw *ah, void *ds, | |
616 | void *lastds, | |
617 | u32 durUpdateEn, u32 rtsctsRate, | |
618 | u32 rtsctsDuration, | |
619 | struct ath9k_11n_rate_series series[], | |
620 | u32 nseries, u32 flags); | |
621 | void (*set11n_aggr_first)(struct ath_hw *ah, void *ds, | |
622 | u32 aggrLen); | |
623 | void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds, | |
624 | u32 numDelims); | |
625 | void (*set11n_aggr_last)(struct ath_hw *ah, void *ds); | |
626 | void (*clr11n_aggr)(struct ath_hw *ah, void *ds); | |
627 | void (*set11n_burstduration)(struct ath_hw *ah, void *ds, | |
628 | u32 burstDuration); | |
d70357d5 LR |
629 | }; |
630 | ||
f2552e28 FF |
631 | struct ath_nf_limits { |
632 | s16 max; | |
633 | s16 min; | |
634 | s16 nominal; | |
635 | }; | |
636 | ||
97dcec57 SM |
637 | /* ah_flags */ |
638 | #define AH_USE_EEPROM 0x1 | |
639 | #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */ | |
640 | ||
cbe61d8a | 641 | struct ath_hw { |
f9f84e96 FF |
642 | struct ath_ops reg_ops; |
643 | ||
b002a4a9 | 644 | struct ieee80211_hw *hw; |
27c51f1a | 645 | struct ath_common common; |
cbe61d8a | 646 | struct ath9k_hw_version hw_version; |
2660b81a S |
647 | struct ath9k_ops_config config; |
648 | struct ath9k_hw_capabilities caps; | |
cac4220b | 649 | struct ath9k_channel channels[ATH9K_NUM_CHANNELS]; |
2660b81a | 650 | struct ath9k_channel *curchan; |
394cf0a1 | 651 | |
cbe61d8a S |
652 | union { |
653 | struct ar5416_eeprom_def def; | |
654 | struct ar5416_eeprom_4k map4k; | |
475f5989 | 655 | struct ar9287_eeprom map9287; |
15c9ee7a | 656 | struct ar9300_eeprom ar9300_eep; |
2660b81a | 657 | } eeprom; |
f74df6fb | 658 | const struct eeprom_ops *eep_ops; |
cbe61d8a S |
659 | |
660 | bool sw_mgmt_crypto; | |
2660b81a | 661 | bool is_pciexpress; |
5f841b41 | 662 | bool is_monitoring; |
2eb46d9b | 663 | bool need_an_top2_fixup; |
2660b81a | 664 | u16 tx_trig_level; |
f2552e28 | 665 | |
bbacee13 | 666 | u32 nf_regs[6]; |
f2552e28 FF |
667 | struct ath_nf_limits nf_2g; |
668 | struct ath_nf_limits nf_5g; | |
2660b81a S |
669 | u16 rfsilent; |
670 | u32 rfkill_gpio; | |
671 | u32 rfkill_polarity; | |
cbe61d8a | 672 | u32 ah_flags; |
394cf0a1 | 673 | |
d7e7d229 LR |
674 | bool htc_reset_init; |
675 | ||
2660b81a S |
676 | enum nl80211_iftype opmode; |
677 | enum ath9k_power_mode power_mode; | |
f078f209 | 678 | |
20bd2a09 | 679 | struct ath9k_hw_cal_data *caldata; |
a13883b0 | 680 | struct ath9k_pacal_info pacal_info; |
2660b81a S |
681 | struct ar5416Stats stats; |
682 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; | |
683 | ||
684 | int16_t curchan_rad_index; | |
3069168c | 685 | enum ath9k_int imask; |
74bad5cb | 686 | u32 imrs2_reg; |
2660b81a S |
687 | u32 txok_interrupt_mask; |
688 | u32 txerr_interrupt_mask; | |
689 | u32 txdesc_interrupt_mask; | |
690 | u32 txeol_interrupt_mask; | |
691 | u32 txurn_interrupt_mask; | |
692 | bool chip_fullsleep; | |
693 | u32 atim_window; | |
6a2b9e8c S |
694 | |
695 | /* Calibration */ | |
6497827f | 696 | u32 supp_cals; |
cbfe9468 S |
697 | struct ath9k_cal_list iq_caldata; |
698 | struct ath9k_cal_list adcgain_caldata; | |
cbfe9468 | 699 | struct ath9k_cal_list adcdc_caldata; |
df23acaa | 700 | struct ath9k_cal_list tempCompCalData; |
cbfe9468 S |
701 | struct ath9k_cal_list *cal_list; |
702 | struct ath9k_cal_list *cal_list_last; | |
703 | struct ath9k_cal_list *cal_list_curr; | |
2660b81a S |
704 | #define totalPowerMeasI meas0.unsign |
705 | #define totalPowerMeasQ meas1.unsign | |
706 | #define totalIqCorrMeas meas2.sign | |
707 | #define totalAdcIOddPhase meas0.unsign | |
708 | #define totalAdcIEvenPhase meas1.unsign | |
709 | #define totalAdcQOddPhase meas2.unsign | |
710 | #define totalAdcQEvenPhase meas3.unsign | |
711 | #define totalAdcDcOffsetIOddPhase meas0.sign | |
712 | #define totalAdcDcOffsetIEvenPhase meas1.sign | |
713 | #define totalAdcDcOffsetQOddPhase meas2.sign | |
714 | #define totalAdcDcOffsetQEvenPhase meas3.sign | |
f078f209 LR |
715 | union { |
716 | u32 unsign[AR5416_MAX_CHAINS]; | |
717 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 718 | } meas0; |
f078f209 LR |
719 | union { |
720 | u32 unsign[AR5416_MAX_CHAINS]; | |
721 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 722 | } meas1; |
f078f209 LR |
723 | union { |
724 | u32 unsign[AR5416_MAX_CHAINS]; | |
725 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 726 | } meas2; |
f078f209 LR |
727 | union { |
728 | u32 unsign[AR5416_MAX_CHAINS]; | |
729 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a S |
730 | } meas3; |
731 | u16 cal_samples; | |
6a2b9e8c | 732 | |
2660b81a S |
733 | u32 sta_id1_defaults; |
734 | u32 misc_mode; | |
f078f209 LR |
735 | enum { |
736 | AUTO_32KHZ, | |
737 | USE_32KHZ, | |
738 | DONT_USE_32KHZ, | |
2660b81a | 739 | } enable_32kHz_clock; |
6a2b9e8c | 740 | |
d70357d5 LR |
741 | /* Private to hardware code */ |
742 | struct ath_hw_private_ops private_ops; | |
743 | /* Accessed by the lower level driver */ | |
744 | struct ath_hw_ops ops; | |
745 | ||
e68a060b | 746 | /* Used to program the radio on non single-chip devices */ |
2660b81a S |
747 | u32 *analogBank0Data; |
748 | u32 *analogBank1Data; | |
749 | u32 *analogBank2Data; | |
750 | u32 *analogBank3Data; | |
751 | u32 *analogBank6Data; | |
752 | u32 *analogBank6TPCData; | |
753 | u32 *analogBank7Data; | |
754 | u32 *addac5416_21; | |
755 | u32 *bank6Temp; | |
756 | ||
597a94b3 | 757 | u8 txpower_limit; |
e239d859 | 758 | int coverage_class; |
2660b81a | 759 | u32 slottime; |
2660b81a | 760 | u32 globaltxtimeout; |
6a2b9e8c S |
761 | |
762 | /* ANI */ | |
2660b81a | 763 | u32 proc_phyerr; |
2660b81a | 764 | u32 aniperiod; |
2660b81a S |
765 | int totalSizeDesired[5]; |
766 | int coarse_high[5]; | |
767 | int coarse_low[5]; | |
768 | int firpwr[5]; | |
769 | enum ath9k_ani_cmd ani_function; | |
770 | ||
af03abec | 771 | /* Bluetooth coexistance */ |
766ec4a9 | 772 | struct ath_btcoex_hw btcoex_hw; |
af03abec | 773 | |
2660b81a | 774 | u32 intr_txqs; |
2660b81a S |
775 | u8 txchainmask; |
776 | u8 rxchainmask; | |
777 | ||
c5d0855a FF |
778 | struct ath_hw_radar_conf radar_conf; |
779 | ||
8bd1d07f SB |
780 | u32 originalGain[22]; |
781 | int initPDADC; | |
782 | int PDADCdelta; | |
6de66dd9 | 783 | int led_pin; |
691680b8 FF |
784 | u32 gpio_mask; |
785 | u32 gpio_val; | |
8bd1d07f | 786 | |
2660b81a S |
787 | struct ar5416IniArray iniModes; |
788 | struct ar5416IniArray iniCommon; | |
789 | struct ar5416IniArray iniBank0; | |
790 | struct ar5416IniArray iniBB_RfGain; | |
791 | struct ar5416IniArray iniBank1; | |
792 | struct ar5416IniArray iniBank2; | |
793 | struct ar5416IniArray iniBank3; | |
794 | struct ar5416IniArray iniBank6; | |
795 | struct ar5416IniArray iniBank6TPC; | |
796 | struct ar5416IniArray iniBank7; | |
797 | struct ar5416IniArray iniAddac; | |
798 | struct ar5416IniArray iniPcieSerdes; | |
13ce3e99 | 799 | struct ar5416IniArray iniPcieSerdesLowPower; |
2660b81a S |
800 | struct ar5416IniArray iniModesAdditional; |
801 | struct ar5416IniArray iniModesRxGain; | |
802 | struct ar5416IniArray iniModesTxGain; | |
8564328d | 803 | struct ar5416IniArray iniModes_9271_1_0_only; |
193cd458 S |
804 | struct ar5416IniArray iniCckfirNormal; |
805 | struct ar5416IniArray iniCckfirJapan2484; | |
70807e99 S |
806 | struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; |
807 | struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; | |
808 | struct ar5416IniArray iniModes_9271_ANI_reg; | |
809 | struct ar5416IniArray iniModes_high_power_tx_gain_9271; | |
810 | struct ar5416IniArray iniModes_normal_power_tx_gain_9271; | |
ff155a45 | 811 | |
13ce3e99 LR |
812 | struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; |
813 | struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; | |
814 | struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; | |
815 | struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; | |
816 | ||
ff155a45 VT |
817 | u32 intr_gen_timer_trigger; |
818 | u32 intr_gen_timer_thresh; | |
819 | struct ath_gen_timer_table hw_gen_timers; | |
744d4025 VT |
820 | |
821 | struct ar9003_txs *ts_ring; | |
822 | void *ts_start; | |
823 | u32 ts_paddr_start; | |
824 | u32 ts_paddr_end; | |
825 | u16 ts_tail; | |
826 | u8 ts_size; | |
aea702b7 LR |
827 | |
828 | u32 bb_watchdog_last_status; | |
829 | u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ | |
717f6bed | 830 | |
1bf38661 FF |
831 | unsigned int paprd_target_power; |
832 | unsigned int paprd_training_power; | |
7072bf62 | 833 | unsigned int paprd_ratemask; |
f1a8abb0 | 834 | unsigned int paprd_ratemask_ht40; |
45ef6a0b | 835 | bool paprd_table_write_done; |
717f6bed FF |
836 | u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; |
837 | u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; | |
9a658d2b LR |
838 | /* |
839 | * Store the permanent value of Reg 0x4004in WARegVal | |
840 | * so we dont have to R/M/W. We should not be reading | |
841 | * this register when in sleep states. | |
842 | */ | |
843 | u32 WARegVal; | |
6ee63f55 SB |
844 | |
845 | /* Enterprise mode cap */ | |
846 | u32 ent_mode; | |
f078f209 | 847 | }; |
f078f209 | 848 | |
9e4bffd2 LR |
849 | static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) |
850 | { | |
851 | return &ah->common; | |
852 | } | |
853 | ||
854 | static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) | |
855 | { | |
856 | return &(ath9k_hw_common(ah)->regulatory); | |
857 | } | |
858 | ||
d70357d5 LR |
859 | static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) |
860 | { | |
861 | return &ah->private_ops; | |
862 | } | |
863 | ||
864 | static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) | |
865 | { | |
866 | return &ah->ops; | |
867 | } | |
868 | ||
895ad7eb VT |
869 | static inline u8 get_streams(int mask) |
870 | { | |
871 | return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2)); | |
872 | } | |
873 | ||
f637cfd6 | 874 | /* Initialization, Detach, Reset */ |
394cf0a1 | 875 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); |
285f2dda | 876 | void ath9k_hw_deinit(struct ath_hw *ah); |
f637cfd6 | 877 | int ath9k_hw_init(struct ath_hw *ah); |
cbe61d8a | 878 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
20bd2a09 | 879 | struct ath9k_hw_cal_data *caldata, bool bChannelChange); |
a9a29ce6 | 880 | int ath9k_hw_fill_cap_info(struct ath_hw *ah); |
8fe65368 | 881 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); |
394cf0a1 | 882 | |
394cf0a1 | 883 | /* GPIO / RFKILL / Antennae */ |
cbe61d8a S |
884 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); |
885 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); | |
886 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, | |
394cf0a1 | 887 | u32 ah_signal_type); |
cbe61d8a | 888 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
cbe61d8a S |
889 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah); |
890 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); | |
21cc630f VT |
891 | void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah, |
892 | struct ath_hw_antcomb_conf *antconf); | |
893 | void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah, | |
894 | struct ath_hw_antcomb_conf *antconf); | |
394cf0a1 S |
895 | |
896 | /* General Operation */ | |
0caa7b14 | 897 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
a9b6b256 FF |
898 | void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, |
899 | int column, unsigned int *writecnt); | |
394cf0a1 | 900 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
4f0fc7c3 | 901 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 902 | u8 phy, int kbps, |
394cf0a1 | 903 | u32 frameLen, u16 rateix, bool shortPreamble); |
cbe61d8a | 904 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
394cf0a1 S |
905 | struct ath9k_channel *chan, |
906 | struct chan_centers *centers); | |
cbe61d8a S |
907 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
908 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); | |
909 | bool ath9k_hw_phy_disable(struct ath_hw *ah); | |
910 | bool ath9k_hw_disable(struct ath_hw *ah); | |
de40f316 | 911 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test); |
cbe61d8a S |
912 | void ath9k_hw_setopmode(struct ath_hw *ah); |
913 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); | |
f2b2143e LR |
914 | void ath9k_hw_setbssidmask(struct ath_hw *ah); |
915 | void ath9k_hw_write_associd(struct ath_hw *ah); | |
dd347f2f | 916 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); |
cbe61d8a S |
917 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
918 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); | |
919 | void ath9k_hw_reset_tsf(struct ath_hw *ah); | |
54e4cec6 | 920 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); |
0005baf4 | 921 | void ath9k_hw_init_global_settings(struct ath_hw *ah); |
b1415819 | 922 | unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah); |
25c56eec | 923 | void ath9k_hw_set11nmac2040(struct ath_hw *ah); |
cbe61d8a S |
924 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); |
925 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |
394cf0a1 | 926 | const struct ath9k_beacon_state *bs); |
c9c99e5e | 927 | bool ath9k_hw_check_alive(struct ath_hw *ah); |
a91d75ae | 928 | |
9ecdef4b | 929 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); |
a91d75ae | 930 | |
ff155a45 VT |
931 | /* Generic hw timer primitives */ |
932 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
933 | void (*trigger)(void *), | |
934 | void (*overflow)(void *), | |
935 | void *arg, | |
936 | u8 timer_index); | |
cd9bf689 LR |
937 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
938 | struct ath_gen_timer *timer, | |
939 | u32 timer_next, | |
940 | u32 timer_period); | |
941 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); | |
942 | ||
ff155a45 VT |
943 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); |
944 | void ath_gen_timer_isr(struct ath_hw *hw); | |
945 | ||
f934c4d9 | 946 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); |
2da4f01a | 947 | |
05020d23 S |
948 | /* HTC */ |
949 | void ath9k_hw_htc_resetinit(struct ath_hw *ah); | |
950 | ||
8fe65368 LR |
951 | /* PHY */ |
952 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, | |
953 | u32 *coef_mantissa, u32 *coef_exponent); | |
954 | ||
ebd5a14a LR |
955 | /* |
956 | * Code Specific to AR5008, AR9001 or AR9002, | |
957 | * we stuff these here to avoid callbacks for AR9003. | |
958 | */ | |
d8f492b7 | 959 | void ar9002_hw_cck_chan14_spread(struct ath_hw *ah); |
ebd5a14a | 960 | int ar9002_hw_rf_claim(struct ath_hw *ah); |
78ec2677 | 961 | void ar9002_hw_enable_async_fifo(struct ath_hw *ah); |
e9141f71 | 962 | void ar9002_hw_update_async_fifo(struct ath_hw *ah); |
6c94fdc9 | 963 | void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah); |
d8f492b7 | 964 | |
641d9921 | 965 | /* |
aea702b7 | 966 | * Code specific to AR9003, we stuff these here to avoid callbacks |
641d9921 FF |
967 | * for older families |
968 | */ | |
aea702b7 LR |
969 | void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); |
970 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); | |
971 | void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); | |
717f6bed FF |
972 | void ar9003_paprd_enable(struct ath_hw *ah, bool val); |
973 | void ar9003_paprd_populate_single_table(struct ath_hw *ah, | |
20bd2a09 FF |
974 | struct ath9k_hw_cal_data *caldata, |
975 | int chain); | |
976 | int ar9003_paprd_create_curve(struct ath_hw *ah, | |
977 | struct ath9k_hw_cal_data *caldata, int chain); | |
717f6bed FF |
978 | int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); |
979 | int ar9003_paprd_init_table(struct ath_hw *ah); | |
980 | bool ar9003_paprd_is_done(struct ath_hw *ah); | |
981 | void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains); | |
641d9921 FF |
982 | |
983 | /* Hardware family op attach helpers */ | |
8fe65368 | 984 | void ar5008_hw_attach_phy_ops(struct ath_hw *ah); |
8525f280 LR |
985 | void ar9002_hw_attach_phy_ops(struct ath_hw *ah); |
986 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah); | |
8fe65368 | 987 | |
795f5e2c LR |
988 | void ar9002_hw_attach_calib_ops(struct ath_hw *ah); |
989 | void ar9003_hw_attach_calib_ops(struct ath_hw *ah); | |
990 | ||
b3950e6a LR |
991 | void ar9002_hw_attach_ops(struct ath_hw *ah); |
992 | void ar9003_hw_attach_ops(struct ath_hw *ah); | |
993 | ||
c2ba3342 | 994 | void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan); |
ac0bb767 LR |
995 | /* |
996 | * ANI work can be shared between all families but a next | |
997 | * generation implementation of ANI will be used only for AR9003 only | |
998 | * for now as the other families still need to be tested with the same | |
e36b27af LR |
999 | * next generation ANI. Feel free to start testing it though for the |
1000 | * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani. | |
ac0bb767 | 1001 | */ |
e36b27af | 1002 | extern int modparam_force_new_ani; |
8eb4980c | 1003 | void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning); |
bfc472bb | 1004 | void ath9k_hw_proc_mib_event(struct ath_hw *ah); |
95792178 | 1005 | void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan); |
ac0bb767 | 1006 | |
7b6840ab VT |
1007 | #define ATH_PCIE_CAP_LINK_CTRL 0x70 |
1008 | #define ATH_PCIE_CAP_LINK_L0S 1 | |
1009 | #define ATH_PCIE_CAP_LINK_L1 2 | |
1010 | ||
73377256 LR |
1011 | #define ATH9K_CLOCK_RATE_CCK 22 |
1012 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 | |
1013 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 | |
1014 | #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 | |
1015 | ||
f078f209 | 1016 | #endif |