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cfg80211: add channel utilization stats to the survey command
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
c46917bb 33#include "../debug.h"
3a702e49 34
394cf0a1 35#define ATHEROS_VENDOR_ID 0x168c
7976b426 36
394cf0a1
S		 37#define AR5416_DEVID_PCI 0x0023
38#define AR5416_DEVID_PCIE 0x0024
39#define AR9160_DEVID_PCI 0x0027
40#define AR9280_DEVID_PCI 0x0029
41#define AR9280_DEVID_PCIE 0x002a
42#define AR9285_DEVID_PCIE 0x002b
5ffaf8a3 43#define AR2427_DEVID_PCIE 0x002c
db3cc53a
SB		 44#define AR9287_DEVID_PCI 0x002d
45#define AR9287_DEVID_PCIE 0x002e
46#define AR9300_DEVID_PCIE 0x0030
7976b426 47
394cf0a1 48#define AR5416_AR9100_DEVID 0x000b
7976b426 49
394cf0a1
S		 50#define AR_SUBVENDOR_ID_NOG 0x0e11
51#define AR_SUBVENDOR_ID_NEW_A 0x7065
52#define AR5416_MAGIC 0x19641014
53
fe12946e
VT		 54#define AR9280_COEX2WIRE_SUBSYSID 0x309b
55#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
57
e3d01bfc
LR		 58#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
59
cfe8cba9
LR		 60#define ATH_DEFAULT_NOISE_FLOOR -95
61
04658fba 62#define ATH9K_RSSI_BAD -128
990b70ab 63
394cf0a1 64/* Register read/write primitives */
9e4bffd2
LR		 65#define REG_WRITE(_ah, _reg, _val) \
66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
67
68#define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
394cf0a1 70
20b3efd9
S		 71#define ENABLE_REGWRITE_BUFFER(_ah) \
72 do { \
435c1610 73 if (ath9k_hw_common(_ah)->ops->enable_write_buffer) \
20b3efd9
S		 74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
75 } while (0)
76
20b3efd9
S		 77#define REGWRITE_BUFFER_FLUSH(_ah) \
78 do { \
435c1610 79 if (ath9k_hw_common(_ah)->ops->write_flush) \
20b3efd9
S		 80 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
81 } while (0)
82
394cf0a1
S		 83#define SM(_v, _f) (((_v) << _f##_S) & _f)
84#define MS(_v, _f) (((_v) & _f) >> _f##_S)
85#define REG_RMW(_a, _r, _set, _clr) \
86 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
87#define REG_RMW_FIELD(_a, _r, _f, _v) \
88 REG_WRITE(_a, _r, \
89 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
1547da37
LR		 90#define REG_READ_FIELD(_a, _r, _f) \
91 (((REG_READ(_a, _r) & _f) >> _f##_S))
394cf0a1
S		 92#define REG_SET_BIT(_a, _r, _f) \
93 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
94#define REG_CLR_BIT(_a, _r, _f) \
95 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 96
394cf0a1
S		 97#define DO_DELAY(x) do { \
98 if ((++(x) % 64) == 0) \
99 udelay(1); \
100 } while (0)
f078f209 101
394cf0a1
S		 102#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
103 int r; \
104 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
105 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
106 INI_RA((iniarray), r, (column))); \
107 DO_DELAY(regWr); \
108 } \
109 } while (0)
f078f209 110
394cf0a1
S		 111#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
112#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
113#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
114#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 115#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 116#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
117#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 118
394cf0a1
S		 119#define AR_GPIOD_MASK 0x00001FFF
120#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 121
394cf0a1 122#define BASE_ACTIVATE_DELAY 100
63a75b91 123#define RTC_PLL_SETTLE_DELAY 100
394cf0a1
S		 124#define COEF_SCALE_S 24
125#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 126
394cf0a1
S		 127#define ATH9K_ANTENNA0_CHAINMASK 0x1
128#define ATH9K_ANTENNA1_CHAINMASK 0x2
129
130#define ATH9K_NUM_DMA_DEBUG_REGS 8
131#define ATH9K_NUM_QUEUES 10
132
133#define MAX_RATE_POWER 63
0caa7b14 134#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 135#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 136#define AH_TIME_QUANTUM 10
137#define AR_KEYTABLE_SIZE 128
d8caa839 138#define POWER_UP_TIME 10000
394cf0a1
S		 139#define SPUR_RSSI_THRESH 40
140
141#define CAB_TIMEOUT_VAL 10
142#define BEACON_TIMEOUT_VAL 10
143#define MIN_BEACON_TIMEOUT_VAL 1
144#define SLEEP_SLOP 3
145
146#define INIT_CONFIG_STATUS 0x00000000
147#define INIT_RSSI_THR 0x00000700
148#define INIT_BCON_CNTRL_REG 0x00000000
149
150#define TU_TO_USEC(_tu) ((_tu) << 10)
151
ceb26445
VT		 152#define ATH9K_HW_RX_HP_QDEPTH 16
153#define ATH9K_HW_RX_LP_QDEPTH 128
154
717f6bed
FF		 155#define PAPRD_GAIN_TABLE_ENTRIES 32
156#define PAPRD_TABLE_SZ 24
157
13ce3e99
LR		 158enum ath_ini_subsys {
159 ATH_INI_PRE = 0,
160 ATH_INI_CORE,
161 ATH_INI_POST,
162 ATH_INI_NUM_SPLIT,
163};
164
394cf0a1
S		 165enum wireless_mode {
166 ATH9K_MODE_11A = 0,
b9b6e15a
LR		 167 ATH9K_MODE_11G,
168 ATH9K_MODE_11NA_HT20,
169 ATH9K_MODE_11NG_HT20,
170 ATH9K_MODE_11NA_HT40PLUS,
171 ATH9K_MODE_11NA_HT40MINUS,
172 ATH9K_MODE_11NG_HT40PLUS,
173 ATH9K_MODE_11NG_HT40MINUS,
174 ATH9K_MODE_MAX,
394cf0a1 175};
f078f209 176
394cf0a1 177enum ath9k_hw_caps {
364734fa
FF		 178 ATH9K_HW_CAP_HT = BIT(0),
179 ATH9K_HW_CAP_RFSILENT = BIT(1),
180 ATH9K_HW_CAP_CST = BIT(2),
181 ATH9K_HW_CAP_ENHANCEDPM = BIT(3),
182 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
183 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
184 ATH9K_HW_CAP_EDMA = BIT(6),
185 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
186 ATH9K_HW_CAP_LDPC = BIT(8),
187 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
188 ATH9K_HW_CAP_SGI_20 = BIT(10),
189 ATH9K_HW_CAP_PAPRD = BIT(11),
190 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
394cf0a1 191};
f078f209 192
394cf0a1
S		 193struct ath9k_hw_capabilities {
194 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
195 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
196 u16 total_queues;
197 u16 keycache_size;
198 u16 low_5ghz_chan, high_5ghz_chan;
199 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 200 u16 rts_aggr_limit;
201 u8 tx_chainmask;
202 u8 rx_chainmask;
203 u16 tx_triglevel_max;
204 u16 reg_cap;
205 u8 num_gpio_pins;
206 u8 num_antcfg_2ghz;
207 u8 num_antcfg_5ghz;
ceb26445
VT		 208 u8 rx_hp_qdepth;
209 u8 rx_lp_qdepth;
210 u8 rx_status_len;
162c3be3 211 u8 tx_desc_len;
5088c2f1 212 u8 txs_len;
394cf0a1 213};
f078f209 214
394cf0a1
S		 215struct ath9k_ops_config {
216 int dma_beacon_response_time;
217 int sw_beacon_response_time;
218 int additional_swba_backoff;
219 int ack_6mb;
41f3e54d 220 u32 cwm_ignore_extcca;
394cf0a1 221 u8 pcie_powersave_enable;
6a0ec30a 222 bool pcieSerDesWrite;
394cf0a1
S		 223 u8 pcie_clock_req;
224 u32 pcie_waen;
394cf0a1
S		 225 u8 analog_shiftreg;
226 u8 ht_enable;
227 u32 ofdm_trig_low;
228 u32 ofdm_trig_high;
229 u32 cck_trig_high;
230 u32 cck_trig_low;
231 u32 enable_ani;
394cf0a1 232 int serialize_regmode;
0ce024cb 233 bool rx_intr_mitigation;
55e82df4 234 bool tx_intr_mitigation;
394cf0a1
S		 235#define SPUR_DISABLE 0
236#define SPUR_ENABLE_IOCTL 1
237#define SPUR_ENABLE_EEPROM 2
238#define AR_EEPROM_MODAL_SPURS 5
239#define AR_SPUR_5413_1 1640
240#define AR_SPUR_5413_2 1200
241#define AR_NO_SPUR 0x8000
242#define AR_BASE_FREQ_2GHZ 2300
243#define AR_BASE_FREQ_5GHZ 4900
244#define AR_SPUR_FEEQ_BOUND_HT40 19
245#define AR_SPUR_FEEQ_BOUND_HT20 10
246 int spurmode;
247 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 248 u8 max_txtrig_level;
e36b27af 249 u16 ani_poll_interval; /* ANI poll interval in ms */
394cf0a1 250};
f078f209 251
394cf0a1
S		 252enum ath9k_int {
253 ATH9K_INT_RX = 0x00000001,
254 ATH9K_INT_RXDESC = 0x00000002,
b5c80475
FF		 255 ATH9K_INT_RXHP = 0x00000001,
256 ATH9K_INT_RXLP = 0x00000002,
394cf0a1
S		 257 ATH9K_INT_RXNOFRM = 0x00000008,
258 ATH9K_INT_RXEOL = 0x00000010,
259 ATH9K_INT_RXORN = 0x00000020,
260 ATH9K_INT_TX = 0x00000040,
261 ATH9K_INT_TXDESC = 0x00000080,
262 ATH9K_INT_TIM_TIMER = 0x00000100,
aea702b7 263 ATH9K_INT_BB_WATCHDOG = 0x00000400,
394cf0a1
S		 264 ATH9K_INT_TXURN = 0x00000800,
265 ATH9K_INT_MIB = 0x00001000,
266 ATH9K_INT_RXPHY = 0x00004000,
267 ATH9K_INT_RXKCM = 0x00008000,
268 ATH9K_INT_SWBA = 0x00010000,
269 ATH9K_INT_BMISS = 0x00040000,
270 ATH9K_INT_BNR = 0x00100000,
271 ATH9K_INT_TIM = 0x00200000,
272 ATH9K_INT_DTIM = 0x00400000,
273 ATH9K_INT_DTIMSYNC = 0x00800000,
274 ATH9K_INT_GPIO = 0x01000000,
275 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 276 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 277 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 278 ATH9K_INT_CST = 0x10000000,
279 ATH9K_INT_GTT = 0x20000000,
280 ATH9K_INT_FATAL = 0x40000000,
281 ATH9K_INT_GLOBAL = 0x80000000,
282 ATH9K_INT_BMISC = ATH9K_INT_TIM |
283 ATH9K_INT_DTIM |
284 ATH9K_INT_DTIMSYNC |
4af9cf4f 285 ATH9K_INT_TSFOOR |
394cf0a1
S		 286 ATH9K_INT_CABEND,
287 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
288 ATH9K_INT_RXDESC |
289 ATH9K_INT_RXEOL |
290 ATH9K_INT_RXORN |
291 ATH9K_INT_TXURN |
292 ATH9K_INT_TXDESC |
293 ATH9K_INT_MIB |
294 ATH9K_INT_RXPHY |
295 ATH9K_INT_RXKCM |
296 ATH9K_INT_SWBA |
297 ATH9K_INT_BMISS |
298 ATH9K_INT_GPIO,
299 ATH9K_INT_NOCARD = 0xffffffff
300};
f078f209 301
394cf0a1
S		 302#define CHANNEL_CW_INT 0x00002
303#define CHANNEL_CCK 0x00020
304#define CHANNEL_OFDM 0x00040
305#define CHANNEL_2GHZ 0x00080
306#define CHANNEL_5GHZ 0x00100
307#define CHANNEL_PASSIVE 0x00200
308#define CHANNEL_DYN 0x00400
309#define CHANNEL_HALF 0x04000
310#define CHANNEL_QUARTER 0x08000
311#define CHANNEL_HT20 0x10000
312#define CHANNEL_HT40PLUS 0x20000
313#define CHANNEL_HT40MINUS 0x40000
314
394cf0a1
S		 315#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
316#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
317#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
318#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
319#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
320#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
321#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
322#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
323#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
324#define CHANNEL_ALL \
325 (CHANNEL_OFDM| \
326 CHANNEL_CCK| \
327 CHANNEL_2GHZ | \
328 CHANNEL_5GHZ | \
329 CHANNEL_HT20 | \
330 CHANNEL_HT40PLUS | \
331 CHANNEL_HT40MINUS)
332
20bd2a09 333struct ath9k_hw_cal_data {
394cf0a1
S		 334 u16 channel;
335 u32 channelFlags;
394cf0a1 336 int32_t CalValid;
394cf0a1
S		 337 int8_t iCoff;
338 int8_t qCoff;
717f6bed 339 bool paprd_done;
4254bc1c 340 bool nfcal_pending;
70cf1533 341 bool nfcal_interference;
717f6bed
FF		 342 u16 small_signal_gain[AR9300_MAX_CHAINS];
343 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
20bd2a09
FF		 344 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
345};
346
347struct ath9k_channel {
348 struct ieee80211_channel *chan;
093115b7 349 struct ar5416AniState ani;
20bd2a09
FF		 350 u16 channel;
351 u32 channelFlags;
352 u32 chanmode;
d9891c78 353 s16 noisefloor;
394cf0a1 354};
f078f209 355
394cf0a1
S		 356#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
357 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
358 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
359 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
360#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
361#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
362#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 363#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
364#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
6b42e8d0 365#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
394cf0a1 366 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
6b42e8d0 367 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
394cf0a1
S		 368
369/* These macros check chanmode and not channelFlags */
370#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
371#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
372 ((_c)->chanmode == CHANNEL_G_HT20))
373#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
374 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
375 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
376 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
377#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
378
379enum ath9k_power_mode {
380 ATH9K_PM_AWAKE = 0,
381 ATH9K_PM_FULL_SLEEP,
382 ATH9K_PM_NETWORK_SLEEP,
383 ATH9K_PM_UNDEFINED
384};
f078f209 385
394cf0a1
S		 386enum ath9k_tp_scale {
387 ATH9K_TP_SCALE_MAX = 0,
388 ATH9K_TP_SCALE_50,
389 ATH9K_TP_SCALE_25,
390 ATH9K_TP_SCALE_12,
391 ATH9K_TP_SCALE_MIN
392};
f078f209 393
394cf0a1
S		 394enum ser_reg_mode {
395 SER_REG_MODE_OFF = 0,
396 SER_REG_MODE_ON = 1,
397 SER_REG_MODE_AUTO = 2,
398};
f078f209 399
ad7b8060
VT		 400enum ath9k_rx_qtype {
401 ATH9K_RX_QUEUE_HP,
402 ATH9K_RX_QUEUE_LP,
403 ATH9K_RX_QUEUE_MAX,
404};
405
394cf0a1
S		 406struct ath9k_beacon_state {
407 u32 bs_nexttbtt;
408 u32 bs_nextdtim;
409 u32 bs_intval;
410#define ATH9K_BEACON_PERIOD 0x0000ffff
411#define ATH9K_BEACON_ENA 0x00800000
412#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 413#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 414 u32 bs_dtimperiod;
415 u16 bs_cfpperiod;
416 u16 bs_cfpmaxduration;
417 u32 bs_cfpnext;
418 u16 bs_timoffset;
419 u16 bs_bmissthreshold;
420 u32 bs_sleepduration;
4af9cf4f 421 u32 bs_tsfoor_threshold;
394cf0a1 422};
f078f209 423
394cf0a1
S		 424struct chan_centers {
425 u16 synth_center;
426 u16 ctl_center;
427 u16 ext_center;
428};
f078f209 429
394cf0a1
S		 430enum {
431 ATH9K_RESET_POWER_ON,
432 ATH9K_RESET_WARM,
433 ATH9K_RESET_COLD,
434};
f078f209 435
d535a42a
S		 436struct ath9k_hw_version {
437 u32 magic;
438 u16 devid;
439 u16 subvendorid;
440 u32 macVersion;
441 u16 macRev;
442 u16 phyRev;
443 u16 analog5GhzRev;
444 u16 analog2GhzRev;
aeac355d 445 u16 subsysid;
d535a42a 446};
394cf0a1 447
ff155a45
VT		 448/* Generic TSF timer definitions */
449
450#define ATH_MAX_GEN_TIMER 16
451
452#define AR_GENTMR_BIT(_index) (1 << (_index))
453
454/*
77c2061d 455 * Using de Bruijin sequence to look up 1's index in a 32 bit number
ff155a45
VT		 456 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
457 */
c90017dd 458#define debruijn32 0x077CB531U
ff155a45
VT		 459
460struct ath_gen_timer_configuration {
461 u32 next_addr;
462 u32 period_addr;
463 u32 mode_addr;
464 u32 mode_mask;
465};
466
467struct ath_gen_timer {
468 void (*trigger)(void *arg);
469 void (*overflow)(void *arg);
470 void *arg;
471 u8 index;
472};
473
474struct ath_gen_timer_table {
475 u32 gen_timer_index[32];
476 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
477 union {
478 unsigned long timer_bits;
479 u16 val;
480 } timer_mask;
481};
482
21cc630f
VT		 483struct ath_hw_antcomb_conf {
484 u8 main_lna_conf;
485 u8 alt_lna_conf;
486 u8 fast_div_bias;
487};
488
d70357d5
LR		 489/**
490 * struct ath_hw_private_ops - callbacks used internally by hardware code
491 *
492 * This structure contains private callbacks designed to only be used internally
493 * by the hardware core.
494 *
795f5e2c
LR		 495 * @init_cal_settings: setup types of calibrations supported
496 * @init_cal: starts actual calibration
497 *
d70357d5 498 * @init_mode_regs: Initializes mode registers
991312d8 499 * @init_mode_gain_regs: Initialize TX/RX gain registers
d70357d5 500 * @macversion_supported: If this specific mac revision is supported
8fe65368
LR		 501 *
502 * @rf_set_freq: change frequency
503 * @spur_mitigate_freq: spur mitigation
504 * @rf_alloc_ext_banks:
505 * @rf_free_ext_banks:
506 * @set_rf_regs:
64773964
LR		 507 * @compute_pll_control: compute the PLL control value to use for
508 * AR_RTC_PLL_CONTROL for a given channel
795f5e2c
LR		 509 * @setup_calibration: set up calibration
510 * @iscal_supported: used to query if a type of calibration is supported
ac0bb767 511 *
e36b27af
LR		 512 * @ani_cache_ini_regs: cache the values for ANI from the initial
513 * register settings through the register initialization.
d70357d5
LR		 514 */
515struct ath_hw_private_ops {
795f5e2c 516 /* Calibration ops */
d70357d5 517 void (*init_cal_settings)(struct ath_hw *ah);
795f5e2c
LR		 518 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
519
d70357d5 520 void (*init_mode_regs)(struct ath_hw *ah);
991312d8 521 void (*init_mode_gain_regs)(struct ath_hw *ah);
d70357d5 522 bool (*macversion_supported)(u32 macversion);
795f5e2c
LR		 523 void (*setup_calibration)(struct ath_hw *ah,
524 struct ath9k_cal_list *currCal);
8fe65368
LR		 525
526 /* PHY ops */
527 int (*rf_set_freq)(struct ath_hw *ah,
528 struct ath9k_channel *chan);
529 void (*spur_mitigate_freq)(struct ath_hw *ah,
530 struct ath9k_channel *chan);
531 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
532 void (*rf_free_ext_banks)(struct ath_hw *ah);
533 bool (*set_rf_regs)(struct ath_hw *ah,
534 struct ath9k_channel *chan,
535 u16 modesIndex);
536 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
537 void (*init_bb)(struct ath_hw *ah,
538 struct ath9k_channel *chan);
539 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
540 void (*olc_init)(struct ath_hw *ah);
541 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
542 void (*mark_phy_inactive)(struct ath_hw *ah);
543 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
544 bool (*rfbus_req)(struct ath_hw *ah);
545 void (*rfbus_done)(struct ath_hw *ah);
546 void (*enable_rfkill)(struct ath_hw *ah);
547 void (*restore_chainmask)(struct ath_hw *ah);
548 void (*set_diversity)(struct ath_hw *ah, bool value);
64773964
LR		 549 u32 (*compute_pll_control)(struct ath_hw *ah,
550 struct ath9k_channel *chan);
c16fcb49
FF		 551 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
552 int param);
641d9921 553 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
ac0bb767
LR		 554
555 /* ANI */
e36b27af 556 void (*ani_cache_ini_regs)(struct ath_hw *ah);
d70357d5
LR		 557};
558
559/**
560 * struct ath_hw_ops - callbacks used by hardware code and driver code
561 *
562 * This structure contains callbacks designed to to be used internally by
563 * hardware code and also by the lower level driver.
564 *
565 * @config_pci_powersave:
795f5e2c 566 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
d70357d5
LR		 567 */
568struct ath_hw_ops {
569 void (*config_pci_powersave)(struct ath_hw *ah,
570 int restore,
571 int power_off);
cee1f625 572 void (*rx_enable)(struct ath_hw *ah);
87d5efbb
VT		 573 void (*set_desc_link)(void *ds, u32 link);
574 void (*get_desc_link)(void *ds, u32 **link);
795f5e2c
LR		 575 bool (*calibrate)(struct ath_hw *ah,
576 struct ath9k_channel *chan,
577 u8 rxchainmask,
578 bool longcal);
55e82df4 579 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
cc610ac0
VT		 580 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
581 bool is_firstseg, bool is_is_lastseg,
582 const void *ds0, dma_addr_t buf_addr,
583 unsigned int qcu);
584 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
585 struct ath_tx_status *ts);
586 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
587 u32 pktLen, enum ath9k_pkt_type type,
588 u32 txPower, u32 keyIx,
589 enum ath9k_key_type keyType,
590 u32 flags);
591 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
592 void *lastds,
593 u32 durUpdateEn, u32 rtsctsRate,
594 u32 rtsctsDuration,
595 struct ath9k_11n_rate_series series[],
596 u32 nseries, u32 flags);
597 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
598 u32 aggrLen);
599 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
600 u32 numDelims);
601 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
602 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
603 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
604 u32 burstDuration);
605 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
606 u32 vmf);
d70357d5
LR		 607};
608
f2552e28
FF		 609struct ath_nf_limits {
610 s16 max;
611 s16 min;
612 s16 nominal;
613};
614
cbe61d8a 615struct ath_hw {
b002a4a9 616 struct ieee80211_hw *hw;
27c51f1a 617 struct ath_common common;
cbe61d8a 618 struct ath9k_hw_version hw_version;
2660b81a
S		 619 struct ath9k_ops_config config;
620 struct ath9k_hw_capabilities caps;
2660b81a
S		 621 struct ath9k_channel channels[38];
622 struct ath9k_channel *curchan;
394cf0a1 623
cbe61d8a
S		 624 union {
625 struct ar5416_eeprom_def def;
626 struct ar5416_eeprom_4k map4k;
475f5989 627 struct ar9287_eeprom map9287;
15c9ee7a 628 struct ar9300_eeprom ar9300_eep;
2660b81a 629 } eeprom;
f74df6fb 630 const struct eeprom_ops *eep_ops;
cbe61d8a
S		 631
632 bool sw_mgmt_crypto;
2660b81a 633 bool is_pciexpress;
2eb46d9b 634 bool need_an_top2_fixup;
2660b81a 635 u16 tx_trig_level;
f2552e28 636
bbacee13 637 u32 nf_regs[6];
f2552e28
FF		 638 struct ath_nf_limits nf_2g;
639 struct ath_nf_limits nf_5g;
2660b81a
S		 640 u16 rfsilent;
641 u32 rfkill_gpio;
642 u32 rfkill_polarity;
cbe61d8a 643 u32 ah_flags;
394cf0a1 644
d7e7d229
LR		 645 bool htc_reset_init;
646
2660b81a
S		 647 enum nl80211_iftype opmode;
648 enum ath9k_power_mode power_mode;
f078f209 649
20bd2a09 650 struct ath9k_hw_cal_data *caldata;
a13883b0 651 struct ath9k_pacal_info pacal_info;
2660b81a
S		 652 struct ar5416Stats stats;
653 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
654
655 int16_t curchan_rad_index;
3069168c 656 enum ath9k_int imask;
74bad5cb 657 u32 imrs2_reg;
2660b81a
S		 658 u32 txok_interrupt_mask;
659 u32 txerr_interrupt_mask;
660 u32 txdesc_interrupt_mask;
661 u32 txeol_interrupt_mask;
662 u32 txurn_interrupt_mask;
663 bool chip_fullsleep;
664 u32 atim_window;
6a2b9e8c
S		 665
666 /* Calibration */
6497827f 667 u32 supp_cals;
cbfe9468
S		 668 struct ath9k_cal_list iq_caldata;
669 struct ath9k_cal_list adcgain_caldata;
cbfe9468 670 struct ath9k_cal_list adcdc_caldata;
df23acaa 671 struct ath9k_cal_list tempCompCalData;
cbfe9468
S		 672 struct ath9k_cal_list *cal_list;
673 struct ath9k_cal_list *cal_list_last;
674 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 675#define totalPowerMeasI meas0.unsign
676#define totalPowerMeasQ meas1.unsign
677#define totalIqCorrMeas meas2.sign
678#define totalAdcIOddPhase meas0.unsign
679#define totalAdcIEvenPhase meas1.unsign
680#define totalAdcQOddPhase meas2.unsign
681#define totalAdcQEvenPhase meas3.unsign
682#define totalAdcDcOffsetIOddPhase meas0.sign
683#define totalAdcDcOffsetIEvenPhase meas1.sign
684#define totalAdcDcOffsetQOddPhase meas2.sign
685#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 686 union {
687 u32 unsign[AR5416_MAX_CHAINS];
688 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 689 } meas0;
f078f209
LR		 690 union {
691 u32 unsign[AR5416_MAX_CHAINS];
692 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 693 } meas1;
f078f209
LR		 694 union {
695 u32 unsign[AR5416_MAX_CHAINS];
696 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 697 } meas2;
f078f209
LR		 698 union {
699 u32 unsign[AR5416_MAX_CHAINS];
700 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 701 } meas3;
702 u16 cal_samples;
6a2b9e8c 703
2660b81a
S		 704 u32 sta_id1_defaults;
705 u32 misc_mode;
f078f209
LR		 706 enum {
707 AUTO_32KHZ,
708 USE_32KHZ,
709 DONT_USE_32KHZ,
2660b81a 710 } enable_32kHz_clock;
6a2b9e8c 711
d70357d5
LR		 712 /* Private to hardware code */
713 struct ath_hw_private_ops private_ops;
714 /* Accessed by the lower level driver */
715 struct ath_hw_ops ops;
716
e68a060b 717 /* Used to program the radio on non single-chip devices */
2660b81a
S		 718 u32 *analogBank0Data;
719 u32 *analogBank1Data;
720 u32 *analogBank2Data;
721 u32 *analogBank3Data;
722 u32 *analogBank6Data;
723 u32 *analogBank6TPCData;
724 u32 *analogBank7Data;
725 u32 *addac5416_21;
726 u32 *bank6Temp;
727
597a94b3 728 u8 txpower_limit;
2660b81a 729 int16_t txpower_indexoffset;
e239d859 730 int coverage_class;
2660b81a
S		 731 u32 beacon_interval;
732 u32 slottime;
2660b81a 733 u32 globaltxtimeout;
6a2b9e8c
S		 734
735 /* ANI */
2660b81a 736 u32 proc_phyerr;
2660b81a 737 u32 aniperiod;
2660b81a
S		 738 int totalSizeDesired[5];
739 int coarse_high[5];
740 int coarse_low[5];
741 int firpwr[5];
742 enum ath9k_ani_cmd ani_function;
743
af03abec 744 /* Bluetooth coexistance */
766ec4a9 745 struct ath_btcoex_hw btcoex_hw;
af03abec 746
2660b81a 747 u32 intr_txqs;
2660b81a
S		 748 u8 txchainmask;
749 u8 rxchainmask;
750
8bd1d07f
SB		 751 u32 originalGain[22];
752 int initPDADC;
753 int PDADCdelta;
08fc5c1b 754 u8 led_pin;
8bd1d07f 755
2660b81a
S		 756 struct ar5416IniArray iniModes;
757 struct ar5416IniArray iniCommon;
758 struct ar5416IniArray iniBank0;
759 struct ar5416IniArray iniBB_RfGain;
760 struct ar5416IniArray iniBank1;
761 struct ar5416IniArray iniBank2;
762 struct ar5416IniArray iniBank3;
763 struct ar5416IniArray iniBank6;
764 struct ar5416IniArray iniBank6TPC;
765 struct ar5416IniArray iniBank7;
766 struct ar5416IniArray iniAddac;
767 struct ar5416IniArray iniPcieSerdes;
13ce3e99 768 struct ar5416IniArray iniPcieSerdesLowPower;
2660b81a
S		 769 struct ar5416IniArray iniModesAdditional;
770 struct ar5416IniArray iniModesRxGain;
771 struct ar5416IniArray iniModesTxGain;
8564328d 772 struct ar5416IniArray iniModes_9271_1_0_only;
193cd458
S		 773 struct ar5416IniArray iniCckfirNormal;
774 struct ar5416IniArray iniCckfirJapan2484;
70807e99
S		 775 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
776 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
777 struct ar5416IniArray iniModes_9271_ANI_reg;
778 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
779 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
ff155a45 780
13ce3e99
LR		 781 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
782 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
783 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
784 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
785
ff155a45
VT		 786 u32 intr_gen_timer_trigger;
787 u32 intr_gen_timer_thresh;
788 struct ath_gen_timer_table hw_gen_timers;
744d4025
VT		 789
790 struct ar9003_txs *ts_ring;
791 void *ts_start;
792 u32 ts_paddr_start;
793 u32 ts_paddr_end;
794 u16 ts_tail;
795 u8 ts_size;
aea702b7
LR		 796
797 u32 bb_watchdog_last_status;
798 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
717f6bed
FF		 799
800 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
801 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
9a658d2b
LR		 802 /*
803 * Store the permanent value of Reg 0x4004in WARegVal
804 * so we dont have to R/M/W. We should not be reading
805 * this register when in sleep states.
806 */
807 u32 WARegVal;
f078f209 808};
f078f209 809
9e4bffd2
LR		 810static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
811{
812 return &ah->common;
813}
814
815static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
816{
817 return &(ath9k_hw_common(ah)->regulatory);
818}
819
d70357d5
LR		 820static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
821{
822 return &ah->private_ops;
823}
824
825static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
826{
827 return &ah->ops;
828}
829
54bd5006
FF		 830static inline int sign_extend(int val, const int nbits)
831{
832 int order = BIT(nbits-1);
833 return (val ^ order) - order;
834}
835
f637cfd6 836/* Initialization, Detach, Reset */
394cf0a1 837const char *ath9k_hw_probe(u16 vendorid, u16 devid);
285f2dda 838void ath9k_hw_deinit(struct ath_hw *ah);
f637cfd6 839int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 840int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 841 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
a9a29ce6 842int ath9k_hw_fill_cap_info(struct ath_hw *ah);
8fe65368 843u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
394cf0a1 844
394cf0a1 845/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 846void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
847u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
848void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 849 u32 ah_signal_type);
cbe61d8a 850void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 851u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
852void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
21cc630f
VT		 853void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
854 struct ath_hw_antcomb_conf *antconf);
855void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
856 struct ath_hw_antcomb_conf *antconf);
394cf0a1
S		 857
858/* General Operation */
0caa7b14 859bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 860u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 861bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3 862u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 863 u8 phy, int kbps,
394cf0a1 864 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 865void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 866 struct ath9k_channel *chan,
867 struct chan_centers *centers);
cbe61d8a
S		 868u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
869void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
870bool ath9k_hw_phy_disable(struct ath_hw *ah);
871bool ath9k_hw_disable(struct ath_hw *ah);
8fbff4b8 872void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
cbe61d8a
S		 873void ath9k_hw_setopmode(struct ath_hw *ah);
874void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 875void ath9k_hw_setbssidmask(struct ath_hw *ah);
876void ath9k_hw_write_associd(struct ath_hw *ah);
cbe61d8a
S		 877u64 ath9k_hw_gettsf64(struct ath_hw *ah);
878void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
879void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 880void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
0005baf4 881void ath9k_hw_init_global_settings(struct ath_hw *ah);
25c56eec 882void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 883void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
884void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 885 const struct ath9k_beacon_state *bs);
c9c99e5e 886bool ath9k_hw_check_alive(struct ath_hw *ah);
a91d75ae 887
9ecdef4b 888bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 889
ff155a45
VT		 890/* Generic hw timer primitives */
891struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
892 void (*trigger)(void *),
893 void (*overflow)(void *),
894 void *arg,
895 u8 timer_index);
cd9bf689
LR		 896void ath9k_hw_gen_timer_start(struct ath_hw *ah,
897 struct ath_gen_timer *timer,
898 u32 timer_next,
899 u32 timer_period);
900void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
901
ff155a45
VT		 902void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
903void ath_gen_timer_isr(struct ath_hw *hw);
1773912b 904u32 ath9k_hw_gettsf32(struct ath_hw *ah);
ff155a45 905
f934c4d9 906void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 907
05020d23
S		 908/* HTC */
909void ath9k_hw_htc_resetinit(struct ath_hw *ah);
910
8fe65368
LR		 911/* PHY */
912void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
913 u32 *coef_mantissa, u32 *coef_exponent);
914
ebd5a14a
LR		 915/*
916 * Code Specific to AR5008, AR9001 or AR9002,
917 * we stuff these here to avoid callbacks for AR9003.
918 */
d8f492b7 919void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
ebd5a14a 920int ar9002_hw_rf_claim(struct ath_hw *ah);
78ec2677 921void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
e9141f71 922void ar9002_hw_update_async_fifo(struct ath_hw *ah);
6c94fdc9 923void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
d8f492b7 924
641d9921 925/*
aea702b7 926 * Code specific to AR9003, we stuff these here to avoid callbacks
641d9921
FF		 927 * for older families
928 */
aea702b7
LR		 929void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
930void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
931void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
717f6bed
FF		 932void ar9003_paprd_enable(struct ath_hw *ah, bool val);
933void ar9003_paprd_populate_single_table(struct ath_hw *ah,
20bd2a09
FF		 934 struct ath9k_hw_cal_data *caldata,
935 int chain);
936int ar9003_paprd_create_curve(struct ath_hw *ah,
937 struct ath9k_hw_cal_data *caldata, int chain);
717f6bed
FF		 938int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
939int ar9003_paprd_init_table(struct ath_hw *ah);
940bool ar9003_paprd_is_done(struct ath_hw *ah);
941void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
641d9921
FF		 942
943/* Hardware family op attach helpers */
8fe65368 944void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
8525f280
LR		 945void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
946void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
8fe65368 947
795f5e2c
LR		 948void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
949void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
950
b3950e6a
LR		 951void ar9002_hw_attach_ops(struct ath_hw *ah);
952void ar9003_hw_attach_ops(struct ath_hw *ah);
953
c2ba3342 954void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767
LR		 955/*
956 * ANI work can be shared between all families but a next
957 * generation implementation of ANI will be used only for AR9003 only
958 * for now as the other families still need to be tested with the same
e36b27af
LR		 959 * next generation ANI. Feel free to start testing it though for the
960 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
ac0bb767 961 */
e36b27af 962extern int modparam_force_new_ani;
8eb4980c 963void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
bfc472bb 964void ath9k_hw_proc_mib_event(struct ath_hw *ah);
95792178 965void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767 966
7b6840ab
VT		 967#define ATH_PCIE_CAP_LINK_CTRL 0x70
968#define ATH_PCIE_CAP_LINK_L0S 1
969#define ATH_PCIE_CAP_LINK_L1 2
970
73377256
LR		 971#define ATH9K_CLOCK_RATE_CCK 22
972#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
973#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
974#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
975
f078f209 976#endif
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