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ath9k: remove driver ASSERT, just use BUG_ON()
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
c46917bb 33#include "../debug.h"
3a702e49 34
394cf0a1
S		 35#define ATHEROS_VENDOR_ID 0x168c
36#define AR5416_DEVID_PCI 0x0023
37#define AR5416_DEVID_PCIE 0x0024
38#define AR9160_DEVID_PCI 0x0027
39#define AR9280_DEVID_PCI 0x0029
40#define AR9280_DEVID_PCIE 0x002a
41#define AR9285_DEVID_PCIE 0x002b
42#define AR5416_AR9100_DEVID 0x000b
43#define AR_SUBVENDOR_ID_NOG 0x0e11
44#define AR_SUBVENDOR_ID_NEW_A 0x7065
45#define AR5416_MAGIC 0x19641014
46
ac88b6ec
VN		 47#define AR5416_DEVID_AR9287_PCI 0x002D
48#define AR5416_DEVID_AR9287_PCIE 0x002E
49
fe12946e
VT		 50#define AR9280_COEX2WIRE_SUBSYSID 0x309b
51#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
52#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
53
e3d01bfc
LR		 54#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
55
394cf0a1 56/* Register read/write primitives */
9e4bffd2
LR		 57#define REG_WRITE(_ah, _reg, _val) \
58 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
59
60#define REG_READ(_ah, _reg) \
61 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
394cf0a1
S		 62
63#define SM(_v, _f) (((_v) << _f##_S) & _f)
64#define MS(_v, _f) (((_v) & _f) >> _f##_S)
65#define REG_RMW(_a, _r, _set, _clr) \
66 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
67#define REG_RMW_FIELD(_a, _r, _f, _v) \
68 REG_WRITE(_a, _r, \
69 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
70#define REG_SET_BIT(_a, _r, _f) \
71 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
72#define REG_CLR_BIT(_a, _r, _f) \
73 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 74
394cf0a1
S		 75#define DO_DELAY(x) do { \
76 if ((++(x) % 64) == 0) \
77 udelay(1); \
78 } while (0)
f078f209 79
394cf0a1
S		 80#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
81 int r; \
82 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
83 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
84 INI_RA((iniarray), r, (column))); \
85 DO_DELAY(regWr); \
86 } \
87 } while (0)
f078f209 88
394cf0a1
S		 89#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
90#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
91#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
92#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 93#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 94#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
95#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 96
394cf0a1
S		 97#define AR_GPIOD_MASK 0x00001FFF
98#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 99
394cf0a1
S		 100#define BASE_ACTIVATE_DELAY 100
101#define RTC_PLL_SETTLE_DELAY 1000
102#define COEF_SCALE_S 24
103#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 104
394cf0a1
S		 105#define ATH9K_ANTENNA0_CHAINMASK 0x1
106#define ATH9K_ANTENNA1_CHAINMASK 0x2
107
108#define ATH9K_NUM_DMA_DEBUG_REGS 8
109#define ATH9K_NUM_QUEUES 10
110
111#define MAX_RATE_POWER 63
0caa7b14 112#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 113#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 114#define AH_TIME_QUANTUM 10
115#define AR_KEYTABLE_SIZE 128
d8caa839 116#define POWER_UP_TIME 10000
394cf0a1
S		 117#define SPUR_RSSI_THRESH 40
118
119#define CAB_TIMEOUT_VAL 10
120#define BEACON_TIMEOUT_VAL 10
121#define MIN_BEACON_TIMEOUT_VAL 1
122#define SLEEP_SLOP 3
123
124#define INIT_CONFIG_STATUS 0x00000000
125#define INIT_RSSI_THR 0x00000700
126#define INIT_BCON_CNTRL_REG 0x00000000
127
128#define TU_TO_USEC(_tu) ((_tu) << 10)
129
130enum wireless_mode {
131 ATH9K_MODE_11A = 0,
b9b6e15a
LR		 132 ATH9K_MODE_11G,
133 ATH9K_MODE_11NA_HT20,
134 ATH9K_MODE_11NG_HT20,
135 ATH9K_MODE_11NA_HT40PLUS,
136 ATH9K_MODE_11NA_HT40MINUS,
137 ATH9K_MODE_11NG_HT40PLUS,
138 ATH9K_MODE_11NG_HT40MINUS,
139 ATH9K_MODE_MAX,
394cf0a1 140};
f078f209 141
1cf6873a
S		 142enum ath9k_ant_setting {
143 ATH9K_ANT_VARIABLE = 0,
144 ATH9K_ANT_FIXED_A,
145 ATH9K_ANT_FIXED_B
146};
147
394cf0a1 148enum ath9k_hw_caps {
bdbdf46d
S		 149 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
150 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
151 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
152 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
153 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
154 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
155 ATH9K_HW_CAP_VEOL = BIT(6),
156 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
157 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
158 ATH9K_HW_CAP_HT = BIT(9),
159 ATH9K_HW_CAP_GTT = BIT(10),
160 ATH9K_HW_CAP_FASTCC = BIT(11),
161 ATH9K_HW_CAP_RFSILENT = BIT(12),
162 ATH9K_HW_CAP_CST = BIT(13),
163 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
164 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
165 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
394cf0a1 166};
f078f209 167
394cf0a1
S		 168enum ath9k_capability_type {
169 ATH9K_CAP_CIPHER = 0,
170 ATH9K_CAP_TKIP_MIC,
171 ATH9K_CAP_TKIP_SPLIT,
394cf0a1
S		 172 ATH9K_CAP_DIVERSITY,
173 ATH9K_CAP_TXPOW,
394cf0a1 174 ATH9K_CAP_MCAST_KEYSRCH,
8bd1d07f 175 ATH9K_CAP_DS
394cf0a1 176};
f078f209 177
394cf0a1
S		 178struct ath9k_hw_capabilities {
179 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
180 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
181 u16 total_queues;
182 u16 keycache_size;
183 u16 low_5ghz_chan, high_5ghz_chan;
184 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 185 u16 rts_aggr_limit;
186 u8 tx_chainmask;
187 u8 rx_chainmask;
188 u16 tx_triglevel_max;
189 u16 reg_cap;
190 u8 num_gpio_pins;
191 u8 num_antcfg_2ghz;
192 u8 num_antcfg_5ghz;
193};
f078f209 194
394cf0a1
S		 195struct ath9k_ops_config {
196 int dma_beacon_response_time;
197 int sw_beacon_response_time;
198 int additional_swba_backoff;
199 int ack_6mb;
200 int cwm_ignore_extcca;
201 u8 pcie_powersave_enable;
394cf0a1
S		 202 u8 pcie_clock_req;
203 u32 pcie_waen;
394cf0a1
S		 204 u8 analog_shiftreg;
205 u8 ht_enable;
206 u32 ofdm_trig_low;
207 u32 ofdm_trig_high;
208 u32 cck_trig_high;
209 u32 cck_trig_low;
210 u32 enable_ani;
1cf6873a 211 enum ath9k_ant_setting diversity_control;
394cf0a1
S		 212 u16 antenna_switch_swap;
213 int serialize_regmode;
0ef1f168 214 bool intr_mitigation;
394cf0a1
S		 215#define SPUR_DISABLE 0
216#define SPUR_ENABLE_IOCTL 1
217#define SPUR_ENABLE_EEPROM 2
218#define AR_EEPROM_MODAL_SPURS 5
219#define AR_SPUR_5413_1 1640
220#define AR_SPUR_5413_2 1200
221#define AR_NO_SPUR 0x8000
222#define AR_BASE_FREQ_2GHZ 2300
223#define AR_BASE_FREQ_5GHZ 4900
224#define AR_SPUR_FEEQ_BOUND_HT40 19
225#define AR_SPUR_FEEQ_BOUND_HT20 10
226 int spurmode;
227 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
228};
f078f209 229
394cf0a1
S		 230enum ath9k_int {
231 ATH9K_INT_RX = 0x00000001,
232 ATH9K_INT_RXDESC = 0x00000002,
233 ATH9K_INT_RXNOFRM = 0x00000008,
234 ATH9K_INT_RXEOL = 0x00000010,
235 ATH9K_INT_RXORN = 0x00000020,
236 ATH9K_INT_TX = 0x00000040,
237 ATH9K_INT_TXDESC = 0x00000080,
238 ATH9K_INT_TIM_TIMER = 0x00000100,
239 ATH9K_INT_TXURN = 0x00000800,
240 ATH9K_INT_MIB = 0x00001000,
241 ATH9K_INT_RXPHY = 0x00004000,
242 ATH9K_INT_RXKCM = 0x00008000,
243 ATH9K_INT_SWBA = 0x00010000,
244 ATH9K_INT_BMISS = 0x00040000,
245 ATH9K_INT_BNR = 0x00100000,
246 ATH9K_INT_TIM = 0x00200000,
247 ATH9K_INT_DTIM = 0x00400000,
248 ATH9K_INT_DTIMSYNC = 0x00800000,
249 ATH9K_INT_GPIO = 0x01000000,
250 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 251 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 252 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 253 ATH9K_INT_CST = 0x10000000,
254 ATH9K_INT_GTT = 0x20000000,
255 ATH9K_INT_FATAL = 0x40000000,
256 ATH9K_INT_GLOBAL = 0x80000000,
257 ATH9K_INT_BMISC = ATH9K_INT_TIM |
258 ATH9K_INT_DTIM |
259 ATH9K_INT_DTIMSYNC |
4af9cf4f 260 ATH9K_INT_TSFOOR |
394cf0a1
S		 261 ATH9K_INT_CABEND,
262 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
263 ATH9K_INT_RXDESC |
264 ATH9K_INT_RXEOL |
265 ATH9K_INT_RXORN |
266 ATH9K_INT_TXURN |
267 ATH9K_INT_TXDESC |
268 ATH9K_INT_MIB |
269 ATH9K_INT_RXPHY |
270 ATH9K_INT_RXKCM |
271 ATH9K_INT_SWBA |
272 ATH9K_INT_BMISS |
273 ATH9K_INT_GPIO,
274 ATH9K_INT_NOCARD = 0xffffffff
275};
f078f209 276
394cf0a1
S		 277#define CHANNEL_CW_INT 0x00002
278#define CHANNEL_CCK 0x00020
279#define CHANNEL_OFDM 0x00040
280#define CHANNEL_2GHZ 0x00080
281#define CHANNEL_5GHZ 0x00100
282#define CHANNEL_PASSIVE 0x00200
283#define CHANNEL_DYN 0x00400
284#define CHANNEL_HALF 0x04000
285#define CHANNEL_QUARTER 0x08000
286#define CHANNEL_HT20 0x10000
287#define CHANNEL_HT40PLUS 0x20000
288#define CHANNEL_HT40MINUS 0x40000
289
394cf0a1
S		 290#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
291#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
292#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
293#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
294#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
295#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
296#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
297#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
298#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
299#define CHANNEL_ALL \
300 (CHANNEL_OFDM| \
301 CHANNEL_CCK| \
302 CHANNEL_2GHZ | \
303 CHANNEL_5GHZ | \
304 CHANNEL_HT20 | \
305 CHANNEL_HT40PLUS | \
306 CHANNEL_HT40MINUS)
307
308struct ath9k_channel {
309 struct ieee80211_channel *chan;
310 u16 channel;
311 u32 channelFlags;
312 u32 chanmode;
313 int32_t CalValid;
314 bool oneTimeCalsDone;
315 int8_t iCoff;
316 int8_t qCoff;
317 int16_t rawNoiseFloor;
318};
f078f209 319
394cf0a1
S		 320#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
321 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
322 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
323 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
324#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
325#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
326#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 327#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
328#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
329#define IS_CHAN_A_5MHZ_SPACED(_c) \
330 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
331 (((_c)->channel % 20) != 0) && \
332 (((_c)->channel % 10) != 0))
333
334/* These macros check chanmode and not channelFlags */
335#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
336#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
337 ((_c)->chanmode == CHANNEL_G_HT20))
338#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
339 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
340 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
341 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
342#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
343
344enum ath9k_power_mode {
345 ATH9K_PM_AWAKE = 0,
346 ATH9K_PM_FULL_SLEEP,
347 ATH9K_PM_NETWORK_SLEEP,
348 ATH9K_PM_UNDEFINED
349};
f078f209 350
394cf0a1
S		 351enum ath9k_tp_scale {
352 ATH9K_TP_SCALE_MAX = 0,
353 ATH9K_TP_SCALE_50,
354 ATH9K_TP_SCALE_25,
355 ATH9K_TP_SCALE_12,
356 ATH9K_TP_SCALE_MIN
357};
f078f209 358
394cf0a1
S		 359enum ser_reg_mode {
360 SER_REG_MODE_OFF = 0,
361 SER_REG_MODE_ON = 1,
362 SER_REG_MODE_AUTO = 2,
363};
f078f209 364
394cf0a1
S		 365struct ath9k_beacon_state {
366 u32 bs_nexttbtt;
367 u32 bs_nextdtim;
368 u32 bs_intval;
369#define ATH9K_BEACON_PERIOD 0x0000ffff
370#define ATH9K_BEACON_ENA 0x00800000
371#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 372#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 373 u32 bs_dtimperiod;
374 u16 bs_cfpperiod;
375 u16 bs_cfpmaxduration;
376 u32 bs_cfpnext;
377 u16 bs_timoffset;
378 u16 bs_bmissthreshold;
379 u32 bs_sleepduration;
4af9cf4f 380 u32 bs_tsfoor_threshold;
394cf0a1 381};
f078f209 382
394cf0a1
S		 383struct chan_centers {
384 u16 synth_center;
385 u16 ctl_center;
386 u16 ext_center;
387};
f078f209 388
394cf0a1
S		 389enum {
390 ATH9K_RESET_POWER_ON,
391 ATH9K_RESET_WARM,
392 ATH9K_RESET_COLD,
393};
f078f209 394
d535a42a
S		 395struct ath9k_hw_version {
396 u32 magic;
397 u16 devid;
398 u16 subvendorid;
399 u32 macVersion;
400 u16 macRev;
401 u16 phyRev;
402 u16 analog5GhzRev;
403 u16 analog2GhzRev;
aeac355d 404 u16 subsysid;
d535a42a 405};
394cf0a1 406
ff155a45
VT		 407/* Generic TSF timer definitions */
408
409#define ATH_MAX_GEN_TIMER 16
410
411#define AR_GENTMR_BIT(_index) (1 << (_index))
412
413/*
414 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
415 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
416 */
417#define debruijn32 0x077CB531UL
418
419struct ath_gen_timer_configuration {
420 u32 next_addr;
421 u32 period_addr;
422 u32 mode_addr;
423 u32 mode_mask;
424};
425
426struct ath_gen_timer {
427 void (*trigger)(void *arg);
428 void (*overflow)(void *arg);
429 void *arg;
430 u8 index;
431};
432
433struct ath_gen_timer_table {
434 u32 gen_timer_index[32];
435 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
436 union {
437 unsigned long timer_bits;
438 u16 val;
439 } timer_mask;
440};
441
cbe61d8a 442struct ath_hw {
b002a4a9 443 struct ieee80211_hw *hw;
394cf0a1 444 struct ath_softc *ah_sc;
27c51f1a 445 struct ath_common common;
cbe61d8a 446 struct ath9k_hw_version hw_version;
2660b81a
S		 447 struct ath9k_ops_config config;
448 struct ath9k_hw_capabilities caps;
2660b81a
S		 449 struct ath9k_channel channels[38];
450 struct ath9k_channel *curchan;
394cf0a1 451
cbe61d8a
S		 452 union {
453 struct ar5416_eeprom_def def;
454 struct ar5416_eeprom_4k map4k;
475f5989 455 struct ar9287_eeprom map9287;
2660b81a 456 } eeprom;
f74df6fb 457 const struct eeprom_ops *eep_ops;
2660b81a 458 enum ath9k_eep_map eep_map;
cbe61d8a
S		 459
460 bool sw_mgmt_crypto;
2660b81a 461 bool is_pciexpress;
2660b81a
S		 462 u16 tx_trig_level;
463 u16 rfsilent;
464 u32 rfkill_gpio;
465 u32 rfkill_polarity;
cbe61d8a 466 u32 ah_flags;
394cf0a1 467
d7e7d229
LR		 468 bool htc_reset_init;
469
2660b81a
S		 470 enum nl80211_iftype opmode;
471 enum ath9k_power_mode power_mode;
f078f209 472
cbe61d8a 473 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
a13883b0 474 struct ath9k_pacal_info pacal_info;
2660b81a
S		 475 struct ar5416Stats stats;
476 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
477
478 int16_t curchan_rad_index;
479 u32 mask_reg;
480 u32 txok_interrupt_mask;
481 u32 txerr_interrupt_mask;
482 u32 txdesc_interrupt_mask;
483 u32 txeol_interrupt_mask;
484 u32 txurn_interrupt_mask;
485 bool chip_fullsleep;
486 u32 atim_window;
6a2b9e8c
S		 487
488 /* Calibration */
cbfe9468
S		 489 enum ath9k_cal_types supp_cals;
490 struct ath9k_cal_list iq_caldata;
491 struct ath9k_cal_list adcgain_caldata;
492 struct ath9k_cal_list adcdc_calinitdata;
493 struct ath9k_cal_list adcdc_caldata;
494 struct ath9k_cal_list *cal_list;
495 struct ath9k_cal_list *cal_list_last;
496 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 497#define totalPowerMeasI meas0.unsign
498#define totalPowerMeasQ meas1.unsign
499#define totalIqCorrMeas meas2.sign
500#define totalAdcIOddPhase meas0.unsign
501#define totalAdcIEvenPhase meas1.unsign
502#define totalAdcQOddPhase meas2.unsign
503#define totalAdcQEvenPhase meas3.unsign
504#define totalAdcDcOffsetIOddPhase meas0.sign
505#define totalAdcDcOffsetIEvenPhase meas1.sign
506#define totalAdcDcOffsetQOddPhase meas2.sign
507#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 508 union {
509 u32 unsign[AR5416_MAX_CHAINS];
510 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 511 } meas0;
f078f209
LR		 512 union {
513 u32 unsign[AR5416_MAX_CHAINS];
514 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 515 } meas1;
f078f209
LR		 516 union {
517 u32 unsign[AR5416_MAX_CHAINS];
518 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 519 } meas2;
f078f209
LR		 520 union {
521 u32 unsign[AR5416_MAX_CHAINS];
522 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 523 } meas3;
524 u16 cal_samples;
6a2b9e8c 525
2660b81a
S		 526 u32 sta_id1_defaults;
527 u32 misc_mode;
f078f209
LR		 528 enum {
529 AUTO_32KHZ,
530 USE_32KHZ,
531 DONT_USE_32KHZ,
2660b81a 532 } enable_32kHz_clock;
6a2b9e8c
S		 533
534 /* RF */
2660b81a
S		 535 u32 *analogBank0Data;
536 u32 *analogBank1Data;
537 u32 *analogBank2Data;
538 u32 *analogBank3Data;
539 u32 *analogBank6Data;
540 u32 *analogBank6TPCData;
541 u32 *analogBank7Data;
542 u32 *addac5416_21;
543 u32 *bank6Temp;
544
545 int16_t txpower_indexoffset;
546 u32 beacon_interval;
547 u32 slottime;
548 u32 acktimeout;
549 u32 ctstimeout;
550 u32 globaltxtimeout;
551 u8 gbeacon_rate;
6a2b9e8c
S		 552
553 /* ANI */
2660b81a 554 u32 proc_phyerr;
2660b81a
S		 555 u32 aniperiod;
556 struct ar5416AniState *curani;
557 struct ar5416AniState ani[255];
558 int totalSizeDesired[5];
559 int coarse_high[5];
560 int coarse_low[5];
561 int firpwr[5];
562 enum ath9k_ani_cmd ani_function;
563
af03abec 564 /* Bluetooth coexistance */
766ec4a9 565 struct ath_btcoex_hw btcoex_hw;
af03abec 566
2660b81a 567 u32 intr_txqs;
2660b81a
S		 568 u8 txchainmask;
569 u8 rxchainmask;
570
8bd1d07f
SB		 571 u32 originalGain[22];
572 int initPDADC;
573 int PDADCdelta;
08fc5c1b 574 u8 led_pin;
8bd1d07f 575
2660b81a
S		 576 struct ar5416IniArray iniModes;
577 struct ar5416IniArray iniCommon;
578 struct ar5416IniArray iniBank0;
579 struct ar5416IniArray iniBB_RfGain;
580 struct ar5416IniArray iniBank1;
581 struct ar5416IniArray iniBank2;
582 struct ar5416IniArray iniBank3;
583 struct ar5416IniArray iniBank6;
584 struct ar5416IniArray iniBank6TPC;
585 struct ar5416IniArray iniBank7;
586 struct ar5416IniArray iniAddac;
587 struct ar5416IniArray iniPcieSerdes;
588 struct ar5416IniArray iniModesAdditional;
589 struct ar5416IniArray iniModesRxGain;
590 struct ar5416IniArray iniModesTxGain;
ff155a45
VT		 591
592 u32 intr_gen_timer_trigger;
593 u32 intr_gen_timer_thresh;
594 struct ath_gen_timer_table hw_gen_timers;
f078f209 595};
f078f209 596
9e4bffd2
LR		 597static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
598{
599 return &ah->common;
600}
601
602static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
603{
604 return &(ath9k_hw_common(ah)->regulatory);
605}
606
f637cfd6 607/* Initialization, Detach, Reset */
394cf0a1 608const char *ath9k_hw_probe(u16 vendorid, u16 devid);
cbe61d8a 609void ath9k_hw_detach(struct ath_hw *ah);
f637cfd6 610int ath9k_hw_init(struct ath_hw *ah);
081b35ab 611void ath9k_hw_rf_free(struct ath_hw *ah);
cbe61d8a 612int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
394cf0a1 613 bool bChannelChange);
eef7a574 614void ath9k_hw_fill_cap_info(struct ath_hw *ah);
cbe61d8a 615bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 616 u32 capability, u32 *result);
cbe61d8a 617bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1
S		 618 u32 capability, u32 setting, int *status);
619
620/* Key Cache Management */
cbe61d8a
S		 621bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
622bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
623bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
394cf0a1 624 const struct ath9k_keyval *k,
e0caf9ea 625 const u8 *mac);
cbe61d8a 626bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
394cf0a1
S		 627
628/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 629void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
630u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
631void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 632 u32 ah_signal_type);
cbe61d8a 633void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 634u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
635void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
636bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
394cf0a1
S		 637 enum ath9k_ant_setting settings,
638 struct ath9k_channel *chan,
639 u8 *tx_chainmask, u8 *rx_chainmask,
640 u8 *antenna_cfgd);
641
642/* General Operation */
0caa7b14 643bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 644u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 645bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3
LR		 646u16 ath9k_hw_computetxtime(struct ath_hw *ah,
647 const struct ath_rate_table *rates,
394cf0a1 648 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 649void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 650 struct ath9k_channel *chan,
651 struct chan_centers *centers);
cbe61d8a
S		 652u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
653void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
654bool ath9k_hw_phy_disable(struct ath_hw *ah);
655bool ath9k_hw_disable(struct ath_hw *ah);
8fbff4b8 656void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
cbe61d8a
S		 657void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
658void ath9k_hw_setopmode(struct ath_hw *ah);
659void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 660void ath9k_hw_setbssidmask(struct ath_hw *ah);
661void ath9k_hw_write_associd(struct ath_hw *ah);
cbe61d8a
S		 662u64 ath9k_hw_gettsf64(struct ath_hw *ah);
663void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
664void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 665void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
cbe61d8a 666bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
25c56eec 667void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 668void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
669void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 670 const struct ath9k_beacon_state *bs);
a91d75ae 671
9ecdef4b 672bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 673
93b1b37f 674void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
394cf0a1
S		 675
676/* Interrupt Handling */
cbe61d8a
S		 677bool ath9k_hw_intrpend(struct ath_hw *ah);
678bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
cbe61d8a 679enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
394cf0a1 680
ff155a45
VT		 681/* Generic hw timer primitives */
682struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
683 void (*trigger)(void *),
684 void (*overflow)(void *),
685 void *arg,
686 u8 timer_index);
cd9bf689
LR		 687void ath9k_hw_gen_timer_start(struct ath_hw *ah,
688 struct ath_gen_timer *timer,
689 u32 timer_next,
690 u32 timer_period);
691void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
692
ff155a45
VT		 693void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
694void ath_gen_timer_isr(struct ath_hw *hw);
1773912b 695u32 ath9k_hw_gettsf32(struct ath_hw *ah);
ff155a45 696
7b6840ab
VT		 697#define ATH_PCIE_CAP_LINK_CTRL 0x70
698#define ATH_PCIE_CAP_LINK_L0S 1
699#define ATH_PCIE_CAP_LINK_L1 2
700
f078f209 701#endif
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