]>
Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef HW_H | |
18 | #define HW_H | |
19 | ||
20 | #include <linux/if_ether.h> | |
21 | #include <linux/delay.h> | |
394cf0a1 S |
22 | #include <linux/io.h> |
23 | ||
24 | #include "mac.h" | |
25 | #include "ani.h" | |
26 | #include "eeprom.h" | |
27 | #include "calib.h" | |
394cf0a1 S |
28 | #include "reg.h" |
29 | #include "phy.h" | |
af03abec | 30 | #include "btcoex.h" |
394cf0a1 | 31 | |
203c4805 | 32 | #include "../regd.h" |
c46917bb | 33 | #include "../debug.h" |
3a702e49 | 34 | |
394cf0a1 | 35 | #define ATHEROS_VENDOR_ID 0x168c |
7976b426 | 36 | |
394cf0a1 S |
37 | #define AR5416_DEVID_PCI 0x0023 |
38 | #define AR5416_DEVID_PCIE 0x0024 | |
39 | #define AR9160_DEVID_PCI 0x0027 | |
40 | #define AR9280_DEVID_PCI 0x0029 | |
41 | #define AR9280_DEVID_PCIE 0x002a | |
42 | #define AR9285_DEVID_PCIE 0x002b | |
5ffaf8a3 | 43 | #define AR2427_DEVID_PCIE 0x002c |
7976b426 | 44 | |
394cf0a1 | 45 | #define AR5416_AR9100_DEVID 0x000b |
7976b426 | 46 | |
394cf0a1 S |
47 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
48 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | |
49 | #define AR5416_MAGIC 0x19641014 | |
50 | ||
ac88b6ec VN |
51 | #define AR5416_DEVID_AR9287_PCI 0x002D |
52 | #define AR5416_DEVID_AR9287_PCIE 0x002E | |
53 | ||
fe12946e VT |
54 | #define AR9280_COEX2WIRE_SUBSYSID 0x309b |
55 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa | |
56 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab | |
57 | ||
e3d01bfc LR |
58 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
59 | ||
cfe8cba9 LR |
60 | #define ATH_DEFAULT_NOISE_FLOOR -95 |
61 | ||
04658fba | 62 | #define ATH9K_RSSI_BAD -128 |
990b70ab | 63 | |
394cf0a1 | 64 | /* Register read/write primitives */ |
9e4bffd2 LR |
65 | #define REG_WRITE(_ah, _reg, _val) \ |
66 | ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg)) | |
67 | ||
68 | #define REG_READ(_ah, _reg) \ | |
69 | ath9k_hw_common(_ah)->ops->read((_ah), (_reg)) | |
394cf0a1 S |
70 | |
71 | #define SM(_v, _f) (((_v) << _f##_S) & _f) | |
72 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | |
73 | #define REG_RMW(_a, _r, _set, _clr) \ | |
74 | REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) | |
75 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ | |
76 | REG_WRITE(_a, _r, \ | |
77 | (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) | |
78 | #define REG_SET_BIT(_a, _r, _f) \ | |
79 | REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) | |
80 | #define REG_CLR_BIT(_a, _r, _f) \ | |
81 | REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) | |
f078f209 | 82 | |
394cf0a1 S |
83 | #define DO_DELAY(x) do { \ |
84 | if ((++(x) % 64) == 0) \ | |
85 | udelay(1); \ | |
86 | } while (0) | |
f078f209 | 87 | |
394cf0a1 S |
88 | #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ |
89 | int r; \ | |
90 | for (r = 0; r < ((iniarray)->ia_rows); r++) { \ | |
91 | REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ | |
92 | INI_RA((iniarray), r, (column))); \ | |
93 | DO_DELAY(regWr); \ | |
94 | } \ | |
95 | } while (0) | |
f078f209 | 96 | |
394cf0a1 S |
97 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
98 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | |
99 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | |
100 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 | |
1773912b | 101 | #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 |
394cf0a1 S |
102 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
103 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | |
f078f209 | 104 | |
394cf0a1 S |
105 | #define AR_GPIOD_MASK 0x00001FFF |
106 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | |
f078f209 | 107 | |
394cf0a1 | 108 | #define BASE_ACTIVATE_DELAY 100 |
63a75b91 | 109 | #define RTC_PLL_SETTLE_DELAY 100 |
394cf0a1 S |
110 | #define COEF_SCALE_S 24 |
111 | #define HT40_CHANNEL_CENTER_SHIFT 10 | |
f078f209 | 112 | |
394cf0a1 S |
113 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
114 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 | |
115 | ||
116 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 | |
117 | #define ATH9K_NUM_QUEUES 10 | |
118 | ||
119 | #define MAX_RATE_POWER 63 | |
0caa7b14 | 120 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
f9b604f6 | 121 | #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ |
394cf0a1 S |
122 | #define AH_TIME_QUANTUM 10 |
123 | #define AR_KEYTABLE_SIZE 128 | |
d8caa839 | 124 | #define POWER_UP_TIME 10000 |
394cf0a1 S |
125 | #define SPUR_RSSI_THRESH 40 |
126 | ||
127 | #define CAB_TIMEOUT_VAL 10 | |
128 | #define BEACON_TIMEOUT_VAL 10 | |
129 | #define MIN_BEACON_TIMEOUT_VAL 1 | |
130 | #define SLEEP_SLOP 3 | |
131 | ||
132 | #define INIT_CONFIG_STATUS 0x00000000 | |
133 | #define INIT_RSSI_THR 0x00000700 | |
134 | #define INIT_BCON_CNTRL_REG 0x00000000 | |
135 | ||
136 | #define TU_TO_USEC(_tu) ((_tu) << 10) | |
137 | ||
138 | enum wireless_mode { | |
139 | ATH9K_MODE_11A = 0, | |
b9b6e15a LR |
140 | ATH9K_MODE_11G, |
141 | ATH9K_MODE_11NA_HT20, | |
142 | ATH9K_MODE_11NG_HT20, | |
143 | ATH9K_MODE_11NA_HT40PLUS, | |
144 | ATH9K_MODE_11NA_HT40MINUS, | |
145 | ATH9K_MODE_11NG_HT40PLUS, | |
146 | ATH9K_MODE_11NG_HT40MINUS, | |
147 | ATH9K_MODE_MAX, | |
394cf0a1 | 148 | }; |
f078f209 | 149 | |
394cf0a1 | 150 | enum ath9k_hw_caps { |
bdbdf46d S |
151 | ATH9K_HW_CAP_MIC_AESCCM = BIT(0), |
152 | ATH9K_HW_CAP_MIC_CKIP = BIT(1), | |
153 | ATH9K_HW_CAP_MIC_TKIP = BIT(2), | |
154 | ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3), | |
155 | ATH9K_HW_CAP_CIPHER_CKIP = BIT(4), | |
156 | ATH9K_HW_CAP_CIPHER_TKIP = BIT(5), | |
157 | ATH9K_HW_CAP_VEOL = BIT(6), | |
158 | ATH9K_HW_CAP_BSSIDMASK = BIT(7), | |
159 | ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8), | |
160 | ATH9K_HW_CAP_HT = BIT(9), | |
161 | ATH9K_HW_CAP_GTT = BIT(10), | |
162 | ATH9K_HW_CAP_FASTCC = BIT(11), | |
163 | ATH9K_HW_CAP_RFSILENT = BIT(12), | |
164 | ATH9K_HW_CAP_CST = BIT(13), | |
165 | ATH9K_HW_CAP_ENHANCEDPM = BIT(14), | |
166 | ATH9K_HW_CAP_AUTOSLEEP = BIT(15), | |
167 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16), | |
394cf0a1 | 168 | }; |
f078f209 | 169 | |
394cf0a1 S |
170 | enum ath9k_capability_type { |
171 | ATH9K_CAP_CIPHER = 0, | |
172 | ATH9K_CAP_TKIP_MIC, | |
173 | ATH9K_CAP_TKIP_SPLIT, | |
394cf0a1 S |
174 | ATH9K_CAP_DIVERSITY, |
175 | ATH9K_CAP_TXPOW, | |
394cf0a1 | 176 | ATH9K_CAP_MCAST_KEYSRCH, |
8bd1d07f | 177 | ATH9K_CAP_DS |
394cf0a1 | 178 | }; |
f078f209 | 179 | |
394cf0a1 S |
180 | struct ath9k_hw_capabilities { |
181 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | |
182 | DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ | |
183 | u16 total_queues; | |
184 | u16 keycache_size; | |
185 | u16 low_5ghz_chan, high_5ghz_chan; | |
186 | u16 low_2ghz_chan, high_2ghz_chan; | |
394cf0a1 S |
187 | u16 rts_aggr_limit; |
188 | u8 tx_chainmask; | |
189 | u8 rx_chainmask; | |
190 | u16 tx_triglevel_max; | |
191 | u16 reg_cap; | |
192 | u8 num_gpio_pins; | |
193 | u8 num_antcfg_2ghz; | |
194 | u8 num_antcfg_5ghz; | |
195 | }; | |
f078f209 | 196 | |
394cf0a1 S |
197 | struct ath9k_ops_config { |
198 | int dma_beacon_response_time; | |
199 | int sw_beacon_response_time; | |
200 | int additional_swba_backoff; | |
201 | int ack_6mb; | |
202 | int cwm_ignore_extcca; | |
203 | u8 pcie_powersave_enable; | |
394cf0a1 S |
204 | u8 pcie_clock_req; |
205 | u32 pcie_waen; | |
394cf0a1 S |
206 | u8 analog_shiftreg; |
207 | u8 ht_enable; | |
208 | u32 ofdm_trig_low; | |
209 | u32 ofdm_trig_high; | |
210 | u32 cck_trig_high; | |
211 | u32 cck_trig_low; | |
212 | u32 enable_ani; | |
394cf0a1 | 213 | int serialize_regmode; |
0ce024cb | 214 | bool rx_intr_mitigation; |
394cf0a1 S |
215 | #define SPUR_DISABLE 0 |
216 | #define SPUR_ENABLE_IOCTL 1 | |
217 | #define SPUR_ENABLE_EEPROM 2 | |
218 | #define AR_EEPROM_MODAL_SPURS 5 | |
219 | #define AR_SPUR_5413_1 1640 | |
220 | #define AR_SPUR_5413_2 1200 | |
221 | #define AR_NO_SPUR 0x8000 | |
222 | #define AR_BASE_FREQ_2GHZ 2300 | |
223 | #define AR_BASE_FREQ_5GHZ 4900 | |
224 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | |
225 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | |
226 | int spurmode; | |
227 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; | |
f4709fdf | 228 | u8 max_txtrig_level; |
394cf0a1 | 229 | }; |
f078f209 | 230 | |
394cf0a1 S |
231 | enum ath9k_int { |
232 | ATH9K_INT_RX = 0x00000001, | |
233 | ATH9K_INT_RXDESC = 0x00000002, | |
234 | ATH9K_INT_RXNOFRM = 0x00000008, | |
235 | ATH9K_INT_RXEOL = 0x00000010, | |
236 | ATH9K_INT_RXORN = 0x00000020, | |
237 | ATH9K_INT_TX = 0x00000040, | |
238 | ATH9K_INT_TXDESC = 0x00000080, | |
239 | ATH9K_INT_TIM_TIMER = 0x00000100, | |
240 | ATH9K_INT_TXURN = 0x00000800, | |
241 | ATH9K_INT_MIB = 0x00001000, | |
242 | ATH9K_INT_RXPHY = 0x00004000, | |
243 | ATH9K_INT_RXKCM = 0x00008000, | |
244 | ATH9K_INT_SWBA = 0x00010000, | |
245 | ATH9K_INT_BMISS = 0x00040000, | |
246 | ATH9K_INT_BNR = 0x00100000, | |
247 | ATH9K_INT_TIM = 0x00200000, | |
248 | ATH9K_INT_DTIM = 0x00400000, | |
249 | ATH9K_INT_DTIMSYNC = 0x00800000, | |
250 | ATH9K_INT_GPIO = 0x01000000, | |
251 | ATH9K_INT_CABEND = 0x02000000, | |
4af9cf4f | 252 | ATH9K_INT_TSFOOR = 0x04000000, |
ff155a45 | 253 | ATH9K_INT_GENTIMER = 0x08000000, |
394cf0a1 S |
254 | ATH9K_INT_CST = 0x10000000, |
255 | ATH9K_INT_GTT = 0x20000000, | |
256 | ATH9K_INT_FATAL = 0x40000000, | |
257 | ATH9K_INT_GLOBAL = 0x80000000, | |
258 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | |
259 | ATH9K_INT_DTIM | | |
260 | ATH9K_INT_DTIMSYNC | | |
4af9cf4f | 261 | ATH9K_INT_TSFOOR | |
394cf0a1 S |
262 | ATH9K_INT_CABEND, |
263 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | |
264 | ATH9K_INT_RXDESC | | |
265 | ATH9K_INT_RXEOL | | |
266 | ATH9K_INT_RXORN | | |
267 | ATH9K_INT_TXURN | | |
268 | ATH9K_INT_TXDESC | | |
269 | ATH9K_INT_MIB | | |
270 | ATH9K_INT_RXPHY | | |
271 | ATH9K_INT_RXKCM | | |
272 | ATH9K_INT_SWBA | | |
273 | ATH9K_INT_BMISS | | |
274 | ATH9K_INT_GPIO, | |
275 | ATH9K_INT_NOCARD = 0xffffffff | |
276 | }; | |
f078f209 | 277 | |
394cf0a1 S |
278 | #define CHANNEL_CW_INT 0x00002 |
279 | #define CHANNEL_CCK 0x00020 | |
280 | #define CHANNEL_OFDM 0x00040 | |
281 | #define CHANNEL_2GHZ 0x00080 | |
282 | #define CHANNEL_5GHZ 0x00100 | |
283 | #define CHANNEL_PASSIVE 0x00200 | |
284 | #define CHANNEL_DYN 0x00400 | |
285 | #define CHANNEL_HALF 0x04000 | |
286 | #define CHANNEL_QUARTER 0x08000 | |
287 | #define CHANNEL_HT20 0x10000 | |
288 | #define CHANNEL_HT40PLUS 0x20000 | |
289 | #define CHANNEL_HT40MINUS 0x40000 | |
290 | ||
394cf0a1 S |
291 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
292 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) | |
293 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) | |
294 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) | |
295 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) | |
296 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) | |
297 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) | |
298 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) | |
299 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) | |
300 | #define CHANNEL_ALL \ | |
301 | (CHANNEL_OFDM| \ | |
302 | CHANNEL_CCK| \ | |
303 | CHANNEL_2GHZ | \ | |
304 | CHANNEL_5GHZ | \ | |
305 | CHANNEL_HT20 | \ | |
306 | CHANNEL_HT40PLUS | \ | |
307 | CHANNEL_HT40MINUS) | |
308 | ||
309 | struct ath9k_channel { | |
310 | struct ieee80211_channel *chan; | |
311 | u16 channel; | |
312 | u32 channelFlags; | |
313 | u32 chanmode; | |
314 | int32_t CalValid; | |
315 | bool oneTimeCalsDone; | |
316 | int8_t iCoff; | |
317 | int8_t qCoff; | |
318 | int16_t rawNoiseFloor; | |
319 | }; | |
f078f209 | 320 | |
394cf0a1 S |
321 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ |
322 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ | |
323 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ | |
324 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) | |
325 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) | |
326 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) | |
327 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) | |
394cf0a1 S |
328 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) |
329 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) | |
330 | #define IS_CHAN_A_5MHZ_SPACED(_c) \ | |
331 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ | |
332 | (((_c)->channel % 20) != 0) && \ | |
333 | (((_c)->channel % 10) != 0)) | |
334 | ||
335 | /* These macros check chanmode and not channelFlags */ | |
336 | #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) | |
337 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ | |
338 | ((_c)->chanmode == CHANNEL_G_HT20)) | |
339 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ | |
340 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ | |
341 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ | |
342 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) | |
343 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) | |
344 | ||
345 | enum ath9k_power_mode { | |
346 | ATH9K_PM_AWAKE = 0, | |
347 | ATH9K_PM_FULL_SLEEP, | |
348 | ATH9K_PM_NETWORK_SLEEP, | |
349 | ATH9K_PM_UNDEFINED | |
350 | }; | |
f078f209 | 351 | |
394cf0a1 S |
352 | enum ath9k_tp_scale { |
353 | ATH9K_TP_SCALE_MAX = 0, | |
354 | ATH9K_TP_SCALE_50, | |
355 | ATH9K_TP_SCALE_25, | |
356 | ATH9K_TP_SCALE_12, | |
357 | ATH9K_TP_SCALE_MIN | |
358 | }; | |
f078f209 | 359 | |
394cf0a1 S |
360 | enum ser_reg_mode { |
361 | SER_REG_MODE_OFF = 0, | |
362 | SER_REG_MODE_ON = 1, | |
363 | SER_REG_MODE_AUTO = 2, | |
364 | }; | |
f078f209 | 365 | |
394cf0a1 S |
366 | struct ath9k_beacon_state { |
367 | u32 bs_nexttbtt; | |
368 | u32 bs_nextdtim; | |
369 | u32 bs_intval; | |
370 | #define ATH9K_BEACON_PERIOD 0x0000ffff | |
371 | #define ATH9K_BEACON_ENA 0x00800000 | |
372 | #define ATH9K_BEACON_RESET_TSF 0x01000000 | |
4af9cf4f | 373 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
394cf0a1 S |
374 | u32 bs_dtimperiod; |
375 | u16 bs_cfpperiod; | |
376 | u16 bs_cfpmaxduration; | |
377 | u32 bs_cfpnext; | |
378 | u16 bs_timoffset; | |
379 | u16 bs_bmissthreshold; | |
380 | u32 bs_sleepduration; | |
4af9cf4f | 381 | u32 bs_tsfoor_threshold; |
394cf0a1 | 382 | }; |
f078f209 | 383 | |
394cf0a1 S |
384 | struct chan_centers { |
385 | u16 synth_center; | |
386 | u16 ctl_center; | |
387 | u16 ext_center; | |
388 | }; | |
f078f209 | 389 | |
394cf0a1 S |
390 | enum { |
391 | ATH9K_RESET_POWER_ON, | |
392 | ATH9K_RESET_WARM, | |
393 | ATH9K_RESET_COLD, | |
394 | }; | |
f078f209 | 395 | |
d535a42a S |
396 | struct ath9k_hw_version { |
397 | u32 magic; | |
398 | u16 devid; | |
399 | u16 subvendorid; | |
400 | u32 macVersion; | |
401 | u16 macRev; | |
402 | u16 phyRev; | |
403 | u16 analog5GhzRev; | |
404 | u16 analog2GhzRev; | |
aeac355d | 405 | u16 subsysid; |
d535a42a | 406 | }; |
394cf0a1 | 407 | |
ff155a45 VT |
408 | /* Generic TSF timer definitions */ |
409 | ||
410 | #define ATH_MAX_GEN_TIMER 16 | |
411 | ||
412 | #define AR_GENTMR_BIT(_index) (1 << (_index)) | |
413 | ||
414 | /* | |
415 | * Using de Bruijin sequence to to look up 1's index in a 32 bit number | |
416 | * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 | |
417 | */ | |
c90017dd | 418 | #define debruijn32 0x077CB531U |
ff155a45 VT |
419 | |
420 | struct ath_gen_timer_configuration { | |
421 | u32 next_addr; | |
422 | u32 period_addr; | |
423 | u32 mode_addr; | |
424 | u32 mode_mask; | |
425 | }; | |
426 | ||
427 | struct ath_gen_timer { | |
428 | void (*trigger)(void *arg); | |
429 | void (*overflow)(void *arg); | |
430 | void *arg; | |
431 | u8 index; | |
432 | }; | |
433 | ||
434 | struct ath_gen_timer_table { | |
435 | u32 gen_timer_index[32]; | |
436 | struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; | |
437 | union { | |
438 | unsigned long timer_bits; | |
439 | u16 val; | |
440 | } timer_mask; | |
441 | }; | |
442 | ||
d70357d5 LR |
443 | /** |
444 | * struct ath_hw_private_ops - callbacks used internally by hardware code | |
445 | * | |
446 | * This structure contains private callbacks designed to only be used internally | |
447 | * by the hardware core. | |
448 | * | |
449 | * @init_cal_settings: Initializes calibration settings | |
450 | * @init_mode_regs: Initializes mode registers | |
451 | * @macversion_supported: If this specific mac revision is supported | |
452 | */ | |
453 | struct ath_hw_private_ops { | |
454 | void (*init_cal_settings)(struct ath_hw *ah); | |
455 | void (*init_mode_regs)(struct ath_hw *ah); | |
456 | bool (*macversion_supported)(u32 macversion); | |
457 | }; | |
458 | ||
459 | /** | |
460 | * struct ath_hw_ops - callbacks used by hardware code and driver code | |
461 | * | |
462 | * This structure contains callbacks designed to to be used internally by | |
463 | * hardware code and also by the lower level driver. | |
464 | * | |
465 | * @config_pci_powersave: | |
466 | */ | |
467 | struct ath_hw_ops { | |
468 | void (*config_pci_powersave)(struct ath_hw *ah, | |
469 | int restore, | |
470 | int power_off); | |
471 | }; | |
472 | ||
cbe61d8a | 473 | struct ath_hw { |
b002a4a9 | 474 | struct ieee80211_hw *hw; |
27c51f1a | 475 | struct ath_common common; |
cbe61d8a | 476 | struct ath9k_hw_version hw_version; |
2660b81a S |
477 | struct ath9k_ops_config config; |
478 | struct ath9k_hw_capabilities caps; | |
2660b81a S |
479 | struct ath9k_channel channels[38]; |
480 | struct ath9k_channel *curchan; | |
394cf0a1 | 481 | |
cbe61d8a S |
482 | union { |
483 | struct ar5416_eeprom_def def; | |
484 | struct ar5416_eeprom_4k map4k; | |
475f5989 | 485 | struct ar9287_eeprom map9287; |
2660b81a | 486 | } eeprom; |
f74df6fb | 487 | const struct eeprom_ops *eep_ops; |
2660b81a | 488 | enum ath9k_eep_map eep_map; |
cbe61d8a S |
489 | |
490 | bool sw_mgmt_crypto; | |
2660b81a | 491 | bool is_pciexpress; |
2eb46d9b | 492 | bool need_an_top2_fixup; |
2660b81a S |
493 | u16 tx_trig_level; |
494 | u16 rfsilent; | |
495 | u32 rfkill_gpio; | |
496 | u32 rfkill_polarity; | |
cbe61d8a | 497 | u32 ah_flags; |
394cf0a1 | 498 | |
d7e7d229 LR |
499 | bool htc_reset_init; |
500 | ||
2660b81a S |
501 | enum nl80211_iftype opmode; |
502 | enum ath9k_power_mode power_mode; | |
f078f209 | 503 | |
cbe61d8a | 504 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
a13883b0 | 505 | struct ath9k_pacal_info pacal_info; |
2660b81a S |
506 | struct ar5416Stats stats; |
507 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; | |
508 | ||
509 | int16_t curchan_rad_index; | |
3069168c | 510 | enum ath9k_int imask; |
74bad5cb | 511 | u32 imrs2_reg; |
2660b81a S |
512 | u32 txok_interrupt_mask; |
513 | u32 txerr_interrupt_mask; | |
514 | u32 txdesc_interrupt_mask; | |
515 | u32 txeol_interrupt_mask; | |
516 | u32 txurn_interrupt_mask; | |
517 | bool chip_fullsleep; | |
518 | u32 atim_window; | |
6a2b9e8c S |
519 | |
520 | /* Calibration */ | |
cbfe9468 S |
521 | enum ath9k_cal_types supp_cals; |
522 | struct ath9k_cal_list iq_caldata; | |
523 | struct ath9k_cal_list adcgain_caldata; | |
524 | struct ath9k_cal_list adcdc_calinitdata; | |
525 | struct ath9k_cal_list adcdc_caldata; | |
526 | struct ath9k_cal_list *cal_list; | |
527 | struct ath9k_cal_list *cal_list_last; | |
528 | struct ath9k_cal_list *cal_list_curr; | |
2660b81a S |
529 | #define totalPowerMeasI meas0.unsign |
530 | #define totalPowerMeasQ meas1.unsign | |
531 | #define totalIqCorrMeas meas2.sign | |
532 | #define totalAdcIOddPhase meas0.unsign | |
533 | #define totalAdcIEvenPhase meas1.unsign | |
534 | #define totalAdcQOddPhase meas2.unsign | |
535 | #define totalAdcQEvenPhase meas3.unsign | |
536 | #define totalAdcDcOffsetIOddPhase meas0.sign | |
537 | #define totalAdcDcOffsetIEvenPhase meas1.sign | |
538 | #define totalAdcDcOffsetQOddPhase meas2.sign | |
539 | #define totalAdcDcOffsetQEvenPhase meas3.sign | |
f078f209 LR |
540 | union { |
541 | u32 unsign[AR5416_MAX_CHAINS]; | |
542 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 543 | } meas0; |
f078f209 LR |
544 | union { |
545 | u32 unsign[AR5416_MAX_CHAINS]; | |
546 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 547 | } meas1; |
f078f209 LR |
548 | union { |
549 | u32 unsign[AR5416_MAX_CHAINS]; | |
550 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 551 | } meas2; |
f078f209 LR |
552 | union { |
553 | u32 unsign[AR5416_MAX_CHAINS]; | |
554 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a S |
555 | } meas3; |
556 | u16 cal_samples; | |
6a2b9e8c | 557 | |
2660b81a S |
558 | u32 sta_id1_defaults; |
559 | u32 misc_mode; | |
f078f209 LR |
560 | enum { |
561 | AUTO_32KHZ, | |
562 | USE_32KHZ, | |
563 | DONT_USE_32KHZ, | |
2660b81a | 564 | } enable_32kHz_clock; |
6a2b9e8c | 565 | |
e68a060b LR |
566 | /* Callback for radio frequency change */ |
567 | int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan); | |
ae478cf6 LR |
568 | |
569 | /* Callback for baseband spur frequency */ | |
570 | void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah, | |
571 | struct ath9k_channel *chan); | |
572 | ||
d70357d5 LR |
573 | /* Private to hardware code */ |
574 | struct ath_hw_private_ops private_ops; | |
575 | /* Accessed by the lower level driver */ | |
576 | struct ath_hw_ops ops; | |
577 | ||
e68a060b | 578 | /* Used to program the radio on non single-chip devices */ |
2660b81a S |
579 | u32 *analogBank0Data; |
580 | u32 *analogBank1Data; | |
581 | u32 *analogBank2Data; | |
582 | u32 *analogBank3Data; | |
583 | u32 *analogBank6Data; | |
584 | u32 *analogBank6TPCData; | |
585 | u32 *analogBank7Data; | |
586 | u32 *addac5416_21; | |
587 | u32 *bank6Temp; | |
588 | ||
589 | int16_t txpower_indexoffset; | |
e239d859 | 590 | int coverage_class; |
2660b81a S |
591 | u32 beacon_interval; |
592 | u32 slottime; | |
2660b81a | 593 | u32 globaltxtimeout; |
6a2b9e8c S |
594 | |
595 | /* ANI */ | |
2660b81a | 596 | u32 proc_phyerr; |
2660b81a S |
597 | u32 aniperiod; |
598 | struct ar5416AniState *curani; | |
599 | struct ar5416AniState ani[255]; | |
600 | int totalSizeDesired[5]; | |
601 | int coarse_high[5]; | |
602 | int coarse_low[5]; | |
603 | int firpwr[5]; | |
604 | enum ath9k_ani_cmd ani_function; | |
605 | ||
af03abec | 606 | /* Bluetooth coexistance */ |
766ec4a9 | 607 | struct ath_btcoex_hw btcoex_hw; |
af03abec | 608 | |
2660b81a | 609 | u32 intr_txqs; |
2660b81a S |
610 | u8 txchainmask; |
611 | u8 rxchainmask; | |
612 | ||
8bd1d07f SB |
613 | u32 originalGain[22]; |
614 | int initPDADC; | |
615 | int PDADCdelta; | |
08fc5c1b | 616 | u8 led_pin; |
8bd1d07f | 617 | |
2660b81a S |
618 | struct ar5416IniArray iniModes; |
619 | struct ar5416IniArray iniCommon; | |
620 | struct ar5416IniArray iniBank0; | |
621 | struct ar5416IniArray iniBB_RfGain; | |
622 | struct ar5416IniArray iniBank1; | |
623 | struct ar5416IniArray iniBank2; | |
624 | struct ar5416IniArray iniBank3; | |
625 | struct ar5416IniArray iniBank6; | |
626 | struct ar5416IniArray iniBank6TPC; | |
627 | struct ar5416IniArray iniBank7; | |
628 | struct ar5416IniArray iniAddac; | |
629 | struct ar5416IniArray iniPcieSerdes; | |
630 | struct ar5416IniArray iniModesAdditional; | |
631 | struct ar5416IniArray iniModesRxGain; | |
632 | struct ar5416IniArray iniModesTxGain; | |
8564328d | 633 | struct ar5416IniArray iniModes_9271_1_0_only; |
193cd458 S |
634 | struct ar5416IniArray iniCckfirNormal; |
635 | struct ar5416IniArray iniCckfirJapan2484; | |
70807e99 S |
636 | struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; |
637 | struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; | |
638 | struct ar5416IniArray iniModes_9271_ANI_reg; | |
639 | struct ar5416IniArray iniModes_high_power_tx_gain_9271; | |
640 | struct ar5416IniArray iniModes_normal_power_tx_gain_9271; | |
ff155a45 VT |
641 | |
642 | u32 intr_gen_timer_trigger; | |
643 | u32 intr_gen_timer_thresh; | |
644 | struct ath_gen_timer_table hw_gen_timers; | |
f078f209 | 645 | }; |
f078f209 | 646 | |
9e4bffd2 LR |
647 | static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) |
648 | { | |
649 | return &ah->common; | |
650 | } | |
651 | ||
652 | static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) | |
653 | { | |
654 | return &(ath9k_hw_common(ah)->regulatory); | |
655 | } | |
656 | ||
d70357d5 LR |
657 | static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) |
658 | { | |
659 | return &ah->private_ops; | |
660 | } | |
661 | ||
662 | static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) | |
663 | { | |
664 | return &ah->ops; | |
665 | } | |
666 | ||
f637cfd6 | 667 | /* Initialization, Detach, Reset */ |
394cf0a1 | 668 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); |
285f2dda | 669 | void ath9k_hw_deinit(struct ath_hw *ah); |
f637cfd6 | 670 | int ath9k_hw_init(struct ath_hw *ah); |
cbe61d8a | 671 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
394cf0a1 | 672 | bool bChannelChange); |
a9a29ce6 | 673 | int ath9k_hw_fill_cap_info(struct ath_hw *ah); |
cbe61d8a | 674 | bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
394cf0a1 | 675 | u32 capability, u32 *result); |
cbe61d8a | 676 | bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
394cf0a1 S |
677 | u32 capability, u32 setting, int *status); |
678 | ||
679 | /* Key Cache Management */ | |
cbe61d8a S |
680 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); |
681 | bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac); | |
682 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, | |
394cf0a1 | 683 | const struct ath9k_keyval *k, |
e0caf9ea | 684 | const u8 *mac); |
cbe61d8a | 685 | bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry); |
394cf0a1 S |
686 | |
687 | /* GPIO / RFKILL / Antennae */ | |
cbe61d8a S |
688 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); |
689 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); | |
690 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, | |
394cf0a1 | 691 | u32 ah_signal_type); |
cbe61d8a | 692 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
cbe61d8a S |
693 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah); |
694 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); | |
394cf0a1 S |
695 | |
696 | /* General Operation */ | |
0caa7b14 | 697 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
394cf0a1 | 698 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
cbe61d8a | 699 | bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high); |
4f0fc7c3 | 700 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 701 | u8 phy, int kbps, |
394cf0a1 | 702 | u32 frameLen, u16 rateix, bool shortPreamble); |
cbe61d8a | 703 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
394cf0a1 S |
704 | struct ath9k_channel *chan, |
705 | struct chan_centers *centers); | |
cbe61d8a S |
706 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
707 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); | |
708 | bool ath9k_hw_phy_disable(struct ath_hw *ah); | |
709 | bool ath9k_hw_disable(struct ath_hw *ah); | |
8fbff4b8 | 710 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit); |
cbe61d8a S |
711 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac); |
712 | void ath9k_hw_setopmode(struct ath_hw *ah); | |
713 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); | |
f2b2143e LR |
714 | void ath9k_hw_setbssidmask(struct ath_hw *ah); |
715 | void ath9k_hw_write_associd(struct ath_hw *ah); | |
cbe61d8a S |
716 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
717 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); | |
718 | void ath9k_hw_reset_tsf(struct ath_hw *ah); | |
54e4cec6 | 719 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); |
30cbd422 | 720 | u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp); |
0005baf4 | 721 | void ath9k_hw_init_global_settings(struct ath_hw *ah); |
25c56eec | 722 | void ath9k_hw_set11nmac2040(struct ath_hw *ah); |
cbe61d8a S |
723 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); |
724 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |
394cf0a1 | 725 | const struct ath9k_beacon_state *bs); |
a91d75ae | 726 | |
9ecdef4b | 727 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); |
a91d75ae | 728 | |
394cf0a1 | 729 | /* Interrupt Handling */ |
cbe61d8a S |
730 | bool ath9k_hw_intrpend(struct ath_hw *ah); |
731 | bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked); | |
cbe61d8a | 732 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints); |
394cf0a1 | 733 | |
ff155a45 VT |
734 | /* Generic hw timer primitives */ |
735 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
736 | void (*trigger)(void *), | |
737 | void (*overflow)(void *), | |
738 | void *arg, | |
739 | u8 timer_index); | |
cd9bf689 LR |
740 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
741 | struct ath_gen_timer *timer, | |
742 | u32 timer_next, | |
743 | u32 timer_period); | |
744 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); | |
745 | ||
ff155a45 VT |
746 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); |
747 | void ath_gen_timer_isr(struct ath_hw *hw); | |
1773912b | 748 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); |
ff155a45 | 749 | |
f934c4d9 | 750 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); |
2da4f01a | 751 | |
05020d23 S |
752 | /* HTC */ |
753 | void ath9k_hw_htc_resetinit(struct ath_hw *ah); | |
754 | ||
7b6840ab VT |
755 | #define ATH_PCIE_CAP_LINK_CTRL 0x70 |
756 | #define ATH_PCIE_CAP_LINK_L0S 1 | |
757 | #define ATH_PCIE_CAP_LINK_L1 2 | |
758 | ||
f078f209 | 759 | #endif |