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f078f209 | 1 | /* |
b3950e6a | 2 | * Copyright (c) 2008-2010 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef HW_H | |
18 | #define HW_H | |
19 | ||
20 | #include <linux/if_ether.h> | |
21 | #include <linux/delay.h> | |
394cf0a1 S |
22 | #include <linux/io.h> |
23 | ||
24 | #include "mac.h" | |
25 | #include "ani.h" | |
26 | #include "eeprom.h" | |
27 | #include "calib.h" | |
394cf0a1 S |
28 | #include "reg.h" |
29 | #include "phy.h" | |
af03abec | 30 | #include "btcoex.h" |
394cf0a1 | 31 | |
203c4805 | 32 | #include "../regd.h" |
c46917bb | 33 | #include "../debug.h" |
3a702e49 | 34 | |
394cf0a1 | 35 | #define ATHEROS_VENDOR_ID 0x168c |
7976b426 | 36 | |
394cf0a1 S |
37 | #define AR5416_DEVID_PCI 0x0023 |
38 | #define AR5416_DEVID_PCIE 0x0024 | |
39 | #define AR9160_DEVID_PCI 0x0027 | |
40 | #define AR9280_DEVID_PCI 0x0029 | |
41 | #define AR9280_DEVID_PCIE 0x002a | |
42 | #define AR9285_DEVID_PCIE 0x002b | |
5ffaf8a3 | 43 | #define AR2427_DEVID_PCIE 0x002c |
db3cc53a SB |
44 | #define AR9287_DEVID_PCI 0x002d |
45 | #define AR9287_DEVID_PCIE 0x002e | |
46 | #define AR9300_DEVID_PCIE 0x0030 | |
7976b426 | 47 | |
394cf0a1 | 48 | #define AR5416_AR9100_DEVID 0x000b |
7976b426 | 49 | |
394cf0a1 S |
50 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
51 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | |
52 | #define AR5416_MAGIC 0x19641014 | |
53 | ||
fe12946e VT |
54 | #define AR9280_COEX2WIRE_SUBSYSID 0x309b |
55 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa | |
56 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab | |
57 | ||
e3d01bfc LR |
58 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
59 | ||
cfe8cba9 LR |
60 | #define ATH_DEFAULT_NOISE_FLOOR -95 |
61 | ||
04658fba | 62 | #define ATH9K_RSSI_BAD -128 |
990b70ab | 63 | |
394cf0a1 | 64 | /* Register read/write primitives */ |
9e4bffd2 LR |
65 | #define REG_WRITE(_ah, _reg, _val) \ |
66 | ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg)) | |
67 | ||
68 | #define REG_READ(_ah, _reg) \ | |
69 | ath9k_hw_common(_ah)->ops->read((_ah), (_reg)) | |
394cf0a1 | 70 | |
20b3efd9 S |
71 | #define ENABLE_REGWRITE_BUFFER(_ah) \ |
72 | do { \ | |
73 | if (AR_SREV_9271(_ah)) \ | |
74 | ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \ | |
75 | } while (0) | |
76 | ||
77 | #define DISABLE_REGWRITE_BUFFER(_ah) \ | |
78 | do { \ | |
79 | if (AR_SREV_9271(_ah)) \ | |
80 | ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \ | |
81 | } while (0) | |
82 | ||
83 | #define REGWRITE_BUFFER_FLUSH(_ah) \ | |
84 | do { \ | |
85 | if (AR_SREV_9271(_ah)) \ | |
86 | ath9k_hw_common(_ah)->ops->write_flush((_ah)); \ | |
87 | } while (0) | |
88 | ||
394cf0a1 S |
89 | #define SM(_v, _f) (((_v) << _f##_S) & _f) |
90 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | |
91 | #define REG_RMW(_a, _r, _set, _clr) \ | |
92 | REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) | |
93 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ | |
94 | REG_WRITE(_a, _r, \ | |
95 | (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) | |
1547da37 LR |
96 | #define REG_READ_FIELD(_a, _r, _f) \ |
97 | (((REG_READ(_a, _r) & _f) >> _f##_S)) | |
394cf0a1 S |
98 | #define REG_SET_BIT(_a, _r, _f) \ |
99 | REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) | |
100 | #define REG_CLR_BIT(_a, _r, _f) \ | |
101 | REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) | |
f078f209 | 102 | |
394cf0a1 S |
103 | #define DO_DELAY(x) do { \ |
104 | if ((++(x) % 64) == 0) \ | |
105 | udelay(1); \ | |
106 | } while (0) | |
f078f209 | 107 | |
394cf0a1 S |
108 | #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ |
109 | int r; \ | |
110 | for (r = 0; r < ((iniarray)->ia_rows); r++) { \ | |
111 | REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ | |
112 | INI_RA((iniarray), r, (column))); \ | |
113 | DO_DELAY(regWr); \ | |
114 | } \ | |
115 | } while (0) | |
f078f209 | 116 | |
394cf0a1 S |
117 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
118 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | |
119 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | |
120 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 | |
1773912b | 121 | #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 |
394cf0a1 S |
122 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
123 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | |
f078f209 | 124 | |
394cf0a1 S |
125 | #define AR_GPIOD_MASK 0x00001FFF |
126 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | |
f078f209 | 127 | |
394cf0a1 | 128 | #define BASE_ACTIVATE_DELAY 100 |
63a75b91 | 129 | #define RTC_PLL_SETTLE_DELAY 100 |
394cf0a1 S |
130 | #define COEF_SCALE_S 24 |
131 | #define HT40_CHANNEL_CENTER_SHIFT 10 | |
f078f209 | 132 | |
394cf0a1 S |
133 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
134 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 | |
135 | ||
136 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 | |
137 | #define ATH9K_NUM_QUEUES 10 | |
138 | ||
139 | #define MAX_RATE_POWER 63 | |
0caa7b14 | 140 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
f9b604f6 | 141 | #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ |
394cf0a1 S |
142 | #define AH_TIME_QUANTUM 10 |
143 | #define AR_KEYTABLE_SIZE 128 | |
d8caa839 | 144 | #define POWER_UP_TIME 10000 |
394cf0a1 S |
145 | #define SPUR_RSSI_THRESH 40 |
146 | ||
147 | #define CAB_TIMEOUT_VAL 10 | |
148 | #define BEACON_TIMEOUT_VAL 10 | |
149 | #define MIN_BEACON_TIMEOUT_VAL 1 | |
150 | #define SLEEP_SLOP 3 | |
151 | ||
152 | #define INIT_CONFIG_STATUS 0x00000000 | |
153 | #define INIT_RSSI_THR 0x00000700 | |
154 | #define INIT_BCON_CNTRL_REG 0x00000000 | |
155 | ||
156 | #define TU_TO_USEC(_tu) ((_tu) << 10) | |
157 | ||
ceb26445 VT |
158 | #define ATH9K_HW_RX_HP_QDEPTH 16 |
159 | #define ATH9K_HW_RX_LP_QDEPTH 128 | |
160 | ||
717f6bed FF |
161 | #define PAPRD_GAIN_TABLE_ENTRIES 32 |
162 | #define PAPRD_TABLE_SZ 24 | |
163 | ||
13ce3e99 LR |
164 | enum ath_ini_subsys { |
165 | ATH_INI_PRE = 0, | |
166 | ATH_INI_CORE, | |
167 | ATH_INI_POST, | |
168 | ATH_INI_NUM_SPLIT, | |
169 | }; | |
170 | ||
394cf0a1 S |
171 | enum wireless_mode { |
172 | ATH9K_MODE_11A = 0, | |
b9b6e15a LR |
173 | ATH9K_MODE_11G, |
174 | ATH9K_MODE_11NA_HT20, | |
175 | ATH9K_MODE_11NG_HT20, | |
176 | ATH9K_MODE_11NA_HT40PLUS, | |
177 | ATH9K_MODE_11NA_HT40MINUS, | |
178 | ATH9K_MODE_11NG_HT40PLUS, | |
179 | ATH9K_MODE_11NG_HT40MINUS, | |
180 | ATH9K_MODE_MAX, | |
394cf0a1 | 181 | }; |
f078f209 | 182 | |
394cf0a1 | 183 | enum ath9k_hw_caps { |
bdbdf46d S |
184 | ATH9K_HW_CAP_MIC_AESCCM = BIT(0), |
185 | ATH9K_HW_CAP_MIC_CKIP = BIT(1), | |
186 | ATH9K_HW_CAP_MIC_TKIP = BIT(2), | |
187 | ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3), | |
188 | ATH9K_HW_CAP_CIPHER_CKIP = BIT(4), | |
189 | ATH9K_HW_CAP_CIPHER_TKIP = BIT(5), | |
190 | ATH9K_HW_CAP_VEOL = BIT(6), | |
191 | ATH9K_HW_CAP_BSSIDMASK = BIT(7), | |
192 | ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8), | |
193 | ATH9K_HW_CAP_HT = BIT(9), | |
194 | ATH9K_HW_CAP_GTT = BIT(10), | |
195 | ATH9K_HW_CAP_FASTCC = BIT(11), | |
196 | ATH9K_HW_CAP_RFSILENT = BIT(12), | |
197 | ATH9K_HW_CAP_CST = BIT(13), | |
198 | ATH9K_HW_CAP_ENHANCEDPM = BIT(14), | |
199 | ATH9K_HW_CAP_AUTOSLEEP = BIT(15), | |
200 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16), | |
1adf02ff | 201 | ATH9K_HW_CAP_EDMA = BIT(17), |
6c84ce08 | 202 | ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18), |
ce01805a | 203 | ATH9K_HW_CAP_LDPC = BIT(19), |
e5553724 | 204 | ATH9K_HW_CAP_FASTCLOCK = BIT(20), |
6473d24d | 205 | ATH9K_HW_CAP_SGI_20 = BIT(21), |
4935250a | 206 | ATH9K_HW_CAP_PAPRD = BIT(22), |
394cf0a1 | 207 | }; |
f078f209 | 208 | |
394cf0a1 S |
209 | struct ath9k_hw_capabilities { |
210 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | |
211 | DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ | |
212 | u16 total_queues; | |
213 | u16 keycache_size; | |
214 | u16 low_5ghz_chan, high_5ghz_chan; | |
215 | u16 low_2ghz_chan, high_2ghz_chan; | |
394cf0a1 S |
216 | u16 rts_aggr_limit; |
217 | u8 tx_chainmask; | |
218 | u8 rx_chainmask; | |
219 | u16 tx_triglevel_max; | |
220 | u16 reg_cap; | |
221 | u8 num_gpio_pins; | |
222 | u8 num_antcfg_2ghz; | |
223 | u8 num_antcfg_5ghz; | |
ceb26445 VT |
224 | u8 rx_hp_qdepth; |
225 | u8 rx_lp_qdepth; | |
226 | u8 rx_status_len; | |
162c3be3 | 227 | u8 tx_desc_len; |
5088c2f1 | 228 | u8 txs_len; |
394cf0a1 | 229 | }; |
f078f209 | 230 | |
394cf0a1 S |
231 | struct ath9k_ops_config { |
232 | int dma_beacon_response_time; | |
233 | int sw_beacon_response_time; | |
234 | int additional_swba_backoff; | |
235 | int ack_6mb; | |
41f3e54d | 236 | u32 cwm_ignore_extcca; |
394cf0a1 | 237 | u8 pcie_powersave_enable; |
6a0ec30a | 238 | bool pcieSerDesWrite; |
394cf0a1 S |
239 | u8 pcie_clock_req; |
240 | u32 pcie_waen; | |
394cf0a1 S |
241 | u8 analog_shiftreg; |
242 | u8 ht_enable; | |
243 | u32 ofdm_trig_low; | |
244 | u32 ofdm_trig_high; | |
245 | u32 cck_trig_high; | |
246 | u32 cck_trig_low; | |
247 | u32 enable_ani; | |
394cf0a1 | 248 | int serialize_regmode; |
0ce024cb | 249 | bool rx_intr_mitigation; |
55e82df4 | 250 | bool tx_intr_mitigation; |
394cf0a1 S |
251 | #define SPUR_DISABLE 0 |
252 | #define SPUR_ENABLE_IOCTL 1 | |
253 | #define SPUR_ENABLE_EEPROM 2 | |
254 | #define AR_EEPROM_MODAL_SPURS 5 | |
255 | #define AR_SPUR_5413_1 1640 | |
256 | #define AR_SPUR_5413_2 1200 | |
257 | #define AR_NO_SPUR 0x8000 | |
258 | #define AR_BASE_FREQ_2GHZ 2300 | |
259 | #define AR_BASE_FREQ_5GHZ 4900 | |
260 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | |
261 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | |
262 | int spurmode; | |
263 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; | |
f4709fdf | 264 | u8 max_txtrig_level; |
e36b27af | 265 | u16 ani_poll_interval; /* ANI poll interval in ms */ |
394cf0a1 | 266 | }; |
f078f209 | 267 | |
394cf0a1 S |
268 | enum ath9k_int { |
269 | ATH9K_INT_RX = 0x00000001, | |
270 | ATH9K_INT_RXDESC = 0x00000002, | |
b5c80475 FF |
271 | ATH9K_INT_RXHP = 0x00000001, |
272 | ATH9K_INT_RXLP = 0x00000002, | |
394cf0a1 S |
273 | ATH9K_INT_RXNOFRM = 0x00000008, |
274 | ATH9K_INT_RXEOL = 0x00000010, | |
275 | ATH9K_INT_RXORN = 0x00000020, | |
276 | ATH9K_INT_TX = 0x00000040, | |
277 | ATH9K_INT_TXDESC = 0x00000080, | |
278 | ATH9K_INT_TIM_TIMER = 0x00000100, | |
aea702b7 | 279 | ATH9K_INT_BB_WATCHDOG = 0x00000400, |
394cf0a1 S |
280 | ATH9K_INT_TXURN = 0x00000800, |
281 | ATH9K_INT_MIB = 0x00001000, | |
282 | ATH9K_INT_RXPHY = 0x00004000, | |
283 | ATH9K_INT_RXKCM = 0x00008000, | |
284 | ATH9K_INT_SWBA = 0x00010000, | |
285 | ATH9K_INT_BMISS = 0x00040000, | |
286 | ATH9K_INT_BNR = 0x00100000, | |
287 | ATH9K_INT_TIM = 0x00200000, | |
288 | ATH9K_INT_DTIM = 0x00400000, | |
289 | ATH9K_INT_DTIMSYNC = 0x00800000, | |
290 | ATH9K_INT_GPIO = 0x01000000, | |
291 | ATH9K_INT_CABEND = 0x02000000, | |
4af9cf4f | 292 | ATH9K_INT_TSFOOR = 0x04000000, |
ff155a45 | 293 | ATH9K_INT_GENTIMER = 0x08000000, |
394cf0a1 S |
294 | ATH9K_INT_CST = 0x10000000, |
295 | ATH9K_INT_GTT = 0x20000000, | |
296 | ATH9K_INT_FATAL = 0x40000000, | |
297 | ATH9K_INT_GLOBAL = 0x80000000, | |
298 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | |
299 | ATH9K_INT_DTIM | | |
300 | ATH9K_INT_DTIMSYNC | | |
4af9cf4f | 301 | ATH9K_INT_TSFOOR | |
394cf0a1 S |
302 | ATH9K_INT_CABEND, |
303 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | |
304 | ATH9K_INT_RXDESC | | |
305 | ATH9K_INT_RXEOL | | |
306 | ATH9K_INT_RXORN | | |
307 | ATH9K_INT_TXURN | | |
308 | ATH9K_INT_TXDESC | | |
309 | ATH9K_INT_MIB | | |
310 | ATH9K_INT_RXPHY | | |
311 | ATH9K_INT_RXKCM | | |
312 | ATH9K_INT_SWBA | | |
313 | ATH9K_INT_BMISS | | |
314 | ATH9K_INT_GPIO, | |
315 | ATH9K_INT_NOCARD = 0xffffffff | |
316 | }; | |
f078f209 | 317 | |
394cf0a1 S |
318 | #define CHANNEL_CW_INT 0x00002 |
319 | #define CHANNEL_CCK 0x00020 | |
320 | #define CHANNEL_OFDM 0x00040 | |
321 | #define CHANNEL_2GHZ 0x00080 | |
322 | #define CHANNEL_5GHZ 0x00100 | |
323 | #define CHANNEL_PASSIVE 0x00200 | |
324 | #define CHANNEL_DYN 0x00400 | |
325 | #define CHANNEL_HALF 0x04000 | |
326 | #define CHANNEL_QUARTER 0x08000 | |
327 | #define CHANNEL_HT20 0x10000 | |
328 | #define CHANNEL_HT40PLUS 0x20000 | |
329 | #define CHANNEL_HT40MINUS 0x40000 | |
330 | ||
394cf0a1 S |
331 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
332 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) | |
333 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) | |
334 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) | |
335 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) | |
336 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) | |
337 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) | |
338 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) | |
339 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) | |
340 | #define CHANNEL_ALL \ | |
341 | (CHANNEL_OFDM| \ | |
342 | CHANNEL_CCK| \ | |
343 | CHANNEL_2GHZ | \ | |
344 | CHANNEL_5GHZ | \ | |
345 | CHANNEL_HT20 | \ | |
346 | CHANNEL_HT40PLUS | \ | |
347 | CHANNEL_HT40MINUS) | |
348 | ||
349 | struct ath9k_channel { | |
350 | struct ieee80211_channel *chan; | |
351 | u16 channel; | |
352 | u32 channelFlags; | |
353 | u32 chanmode; | |
354 | int32_t CalValid; | |
355 | bool oneTimeCalsDone; | |
356 | int8_t iCoff; | |
357 | int8_t qCoff; | |
358 | int16_t rawNoiseFloor; | |
717f6bed FF |
359 | bool paprd_done; |
360 | u16 small_signal_gain[AR9300_MAX_CHAINS]; | |
361 | u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ]; | |
394cf0a1 | 362 | }; |
f078f209 | 363 | |
394cf0a1 S |
364 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ |
365 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ | |
366 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ | |
367 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) | |
368 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) | |
369 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) | |
370 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) | |
394cf0a1 S |
371 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) |
372 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) | |
6b42e8d0 | 373 | #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \ |
394cf0a1 | 374 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ |
6b42e8d0 | 375 | ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)) |
394cf0a1 S |
376 | |
377 | /* These macros check chanmode and not channelFlags */ | |
378 | #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) | |
379 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ | |
380 | ((_c)->chanmode == CHANNEL_G_HT20)) | |
381 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ | |
382 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ | |
383 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ | |
384 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) | |
385 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) | |
386 | ||
387 | enum ath9k_power_mode { | |
388 | ATH9K_PM_AWAKE = 0, | |
389 | ATH9K_PM_FULL_SLEEP, | |
390 | ATH9K_PM_NETWORK_SLEEP, | |
391 | ATH9K_PM_UNDEFINED | |
392 | }; | |
f078f209 | 393 | |
394cf0a1 S |
394 | enum ath9k_tp_scale { |
395 | ATH9K_TP_SCALE_MAX = 0, | |
396 | ATH9K_TP_SCALE_50, | |
397 | ATH9K_TP_SCALE_25, | |
398 | ATH9K_TP_SCALE_12, | |
399 | ATH9K_TP_SCALE_MIN | |
400 | }; | |
f078f209 | 401 | |
394cf0a1 S |
402 | enum ser_reg_mode { |
403 | SER_REG_MODE_OFF = 0, | |
404 | SER_REG_MODE_ON = 1, | |
405 | SER_REG_MODE_AUTO = 2, | |
406 | }; | |
f078f209 | 407 | |
ad7b8060 VT |
408 | enum ath9k_rx_qtype { |
409 | ATH9K_RX_QUEUE_HP, | |
410 | ATH9K_RX_QUEUE_LP, | |
411 | ATH9K_RX_QUEUE_MAX, | |
412 | }; | |
413 | ||
394cf0a1 S |
414 | struct ath9k_beacon_state { |
415 | u32 bs_nexttbtt; | |
416 | u32 bs_nextdtim; | |
417 | u32 bs_intval; | |
418 | #define ATH9K_BEACON_PERIOD 0x0000ffff | |
419 | #define ATH9K_BEACON_ENA 0x00800000 | |
420 | #define ATH9K_BEACON_RESET_TSF 0x01000000 | |
4af9cf4f | 421 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
394cf0a1 S |
422 | u32 bs_dtimperiod; |
423 | u16 bs_cfpperiod; | |
424 | u16 bs_cfpmaxduration; | |
425 | u32 bs_cfpnext; | |
426 | u16 bs_timoffset; | |
427 | u16 bs_bmissthreshold; | |
428 | u32 bs_sleepduration; | |
4af9cf4f | 429 | u32 bs_tsfoor_threshold; |
394cf0a1 | 430 | }; |
f078f209 | 431 | |
394cf0a1 S |
432 | struct chan_centers { |
433 | u16 synth_center; | |
434 | u16 ctl_center; | |
435 | u16 ext_center; | |
436 | }; | |
f078f209 | 437 | |
394cf0a1 S |
438 | enum { |
439 | ATH9K_RESET_POWER_ON, | |
440 | ATH9K_RESET_WARM, | |
441 | ATH9K_RESET_COLD, | |
442 | }; | |
f078f209 | 443 | |
d535a42a S |
444 | struct ath9k_hw_version { |
445 | u32 magic; | |
446 | u16 devid; | |
447 | u16 subvendorid; | |
448 | u32 macVersion; | |
449 | u16 macRev; | |
450 | u16 phyRev; | |
451 | u16 analog5GhzRev; | |
452 | u16 analog2GhzRev; | |
aeac355d | 453 | u16 subsysid; |
d535a42a | 454 | }; |
394cf0a1 | 455 | |
ff155a45 VT |
456 | /* Generic TSF timer definitions */ |
457 | ||
458 | #define ATH_MAX_GEN_TIMER 16 | |
459 | ||
460 | #define AR_GENTMR_BIT(_index) (1 << (_index)) | |
461 | ||
462 | /* | |
77c2061d | 463 | * Using de Bruijin sequence to look up 1's index in a 32 bit number |
ff155a45 VT |
464 | * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 |
465 | */ | |
c90017dd | 466 | #define debruijn32 0x077CB531U |
ff155a45 VT |
467 | |
468 | struct ath_gen_timer_configuration { | |
469 | u32 next_addr; | |
470 | u32 period_addr; | |
471 | u32 mode_addr; | |
472 | u32 mode_mask; | |
473 | }; | |
474 | ||
475 | struct ath_gen_timer { | |
476 | void (*trigger)(void *arg); | |
477 | void (*overflow)(void *arg); | |
478 | void *arg; | |
479 | u8 index; | |
480 | }; | |
481 | ||
482 | struct ath_gen_timer_table { | |
483 | u32 gen_timer_index[32]; | |
484 | struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; | |
485 | union { | |
486 | unsigned long timer_bits; | |
487 | u16 val; | |
488 | } timer_mask; | |
489 | }; | |
490 | ||
d70357d5 LR |
491 | /** |
492 | * struct ath_hw_private_ops - callbacks used internally by hardware code | |
493 | * | |
494 | * This structure contains private callbacks designed to only be used internally | |
495 | * by the hardware core. | |
496 | * | |
795f5e2c LR |
497 | * @init_cal_settings: setup types of calibrations supported |
498 | * @init_cal: starts actual calibration | |
499 | * | |
d70357d5 | 500 | * @init_mode_regs: Initializes mode registers |
991312d8 | 501 | * @init_mode_gain_regs: Initialize TX/RX gain registers |
d70357d5 | 502 | * @macversion_supported: If this specific mac revision is supported |
8fe65368 LR |
503 | * |
504 | * @rf_set_freq: change frequency | |
505 | * @spur_mitigate_freq: spur mitigation | |
506 | * @rf_alloc_ext_banks: | |
507 | * @rf_free_ext_banks: | |
508 | * @set_rf_regs: | |
64773964 LR |
509 | * @compute_pll_control: compute the PLL control value to use for |
510 | * AR_RTC_PLL_CONTROL for a given channel | |
795f5e2c LR |
511 | * @setup_calibration: set up calibration |
512 | * @iscal_supported: used to query if a type of calibration is supported | |
77d6d39a | 513 | * @loadnf: load noise floor read from each chain on the CCA registers |
ac0bb767 LR |
514 | * |
515 | * @ani_reset: reset ANI parameters to default values | |
516 | * @ani_lower_immunity: lower the noise immunity level. The level controls | |
517 | * the power-based packet detection on hardware. If a power jump is | |
518 | * detected the adapter takes it as an indication that a packet has | |
519 | * arrived. The level ranges from 0-5. Each level corresponds to a | |
520 | * few dB more of noise immunity. If you have a strong time-varying | |
521 | * interference that is causing false detections (OFDM timing errors or | |
522 | * CCK timing errors) the level can be increased. | |
e36b27af LR |
523 | * @ani_cache_ini_regs: cache the values for ANI from the initial |
524 | * register settings through the register initialization. | |
d70357d5 LR |
525 | */ |
526 | struct ath_hw_private_ops { | |
795f5e2c | 527 | /* Calibration ops */ |
d70357d5 | 528 | void (*init_cal_settings)(struct ath_hw *ah); |
795f5e2c LR |
529 | bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); |
530 | ||
d70357d5 | 531 | void (*init_mode_regs)(struct ath_hw *ah); |
991312d8 | 532 | void (*init_mode_gain_regs)(struct ath_hw *ah); |
d70357d5 | 533 | bool (*macversion_supported)(u32 macversion); |
795f5e2c LR |
534 | void (*setup_calibration)(struct ath_hw *ah, |
535 | struct ath9k_cal_list *currCal); | |
536 | bool (*iscal_supported)(struct ath_hw *ah, | |
537 | enum ath9k_cal_types calType); | |
8fe65368 LR |
538 | |
539 | /* PHY ops */ | |
540 | int (*rf_set_freq)(struct ath_hw *ah, | |
541 | struct ath9k_channel *chan); | |
542 | void (*spur_mitigate_freq)(struct ath_hw *ah, | |
543 | struct ath9k_channel *chan); | |
544 | int (*rf_alloc_ext_banks)(struct ath_hw *ah); | |
545 | void (*rf_free_ext_banks)(struct ath_hw *ah); | |
546 | bool (*set_rf_regs)(struct ath_hw *ah, | |
547 | struct ath9k_channel *chan, | |
548 | u16 modesIndex); | |
549 | void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); | |
550 | void (*init_bb)(struct ath_hw *ah, | |
551 | struct ath9k_channel *chan); | |
552 | int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); | |
553 | void (*olc_init)(struct ath_hw *ah); | |
554 | void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); | |
555 | void (*mark_phy_inactive)(struct ath_hw *ah); | |
556 | void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); | |
557 | bool (*rfbus_req)(struct ath_hw *ah); | |
558 | void (*rfbus_done)(struct ath_hw *ah); | |
559 | void (*enable_rfkill)(struct ath_hw *ah); | |
560 | void (*restore_chainmask)(struct ath_hw *ah); | |
561 | void (*set_diversity)(struct ath_hw *ah, bool value); | |
64773964 LR |
562 | u32 (*compute_pll_control)(struct ath_hw *ah, |
563 | struct ath9k_channel *chan); | |
c16fcb49 FF |
564 | bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, |
565 | int param); | |
641d9921 | 566 | void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); |
77d6d39a | 567 | void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan); |
ac0bb767 LR |
568 | |
569 | /* ANI */ | |
40346b66 | 570 | void (*ani_reset)(struct ath_hw *ah, bool is_scanning); |
ac0bb767 | 571 | void (*ani_lower_immunity)(struct ath_hw *ah); |
e36b27af | 572 | void (*ani_cache_ini_regs)(struct ath_hw *ah); |
d70357d5 LR |
573 | }; |
574 | ||
575 | /** | |
576 | * struct ath_hw_ops - callbacks used by hardware code and driver code | |
577 | * | |
578 | * This structure contains callbacks designed to to be used internally by | |
579 | * hardware code and also by the lower level driver. | |
580 | * | |
581 | * @config_pci_powersave: | |
795f5e2c | 582 | * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC |
ac0bb767 LR |
583 | * |
584 | * @ani_proc_mib_event: process MIB events, this would happen upon specific ANI | |
585 | * thresholds being reached or having overflowed. | |
586 | * @ani_monitor: called periodically by the core driver to collect | |
587 | * MIB stats and adjust ANI if specific thresholds have been reached. | |
d70357d5 LR |
588 | */ |
589 | struct ath_hw_ops { | |
590 | void (*config_pci_powersave)(struct ath_hw *ah, | |
591 | int restore, | |
592 | int power_off); | |
cee1f625 | 593 | void (*rx_enable)(struct ath_hw *ah); |
87d5efbb VT |
594 | void (*set_desc_link)(void *ds, u32 link); |
595 | void (*get_desc_link)(void *ds, u32 **link); | |
795f5e2c LR |
596 | bool (*calibrate)(struct ath_hw *ah, |
597 | struct ath9k_channel *chan, | |
598 | u8 rxchainmask, | |
599 | bool longcal); | |
55e82df4 | 600 | bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); |
cc610ac0 VT |
601 | void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen, |
602 | bool is_firstseg, bool is_is_lastseg, | |
603 | const void *ds0, dma_addr_t buf_addr, | |
604 | unsigned int qcu); | |
605 | int (*proc_txdesc)(struct ath_hw *ah, void *ds, | |
606 | struct ath_tx_status *ts); | |
607 | void (*set11n_txdesc)(struct ath_hw *ah, void *ds, | |
608 | u32 pktLen, enum ath9k_pkt_type type, | |
609 | u32 txPower, u32 keyIx, | |
610 | enum ath9k_key_type keyType, | |
611 | u32 flags); | |
612 | void (*set11n_ratescenario)(struct ath_hw *ah, void *ds, | |
613 | void *lastds, | |
614 | u32 durUpdateEn, u32 rtsctsRate, | |
615 | u32 rtsctsDuration, | |
616 | struct ath9k_11n_rate_series series[], | |
617 | u32 nseries, u32 flags); | |
618 | void (*set11n_aggr_first)(struct ath_hw *ah, void *ds, | |
619 | u32 aggrLen); | |
620 | void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds, | |
621 | u32 numDelims); | |
622 | void (*set11n_aggr_last)(struct ath_hw *ah, void *ds); | |
623 | void (*clr11n_aggr)(struct ath_hw *ah, void *ds); | |
624 | void (*set11n_burstduration)(struct ath_hw *ah, void *ds, | |
625 | u32 burstDuration); | |
626 | void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds, | |
627 | u32 vmf); | |
ac0bb767 LR |
628 | |
629 | void (*ani_proc_mib_event)(struct ath_hw *ah); | |
630 | void (*ani_monitor)(struct ath_hw *ah, struct ath9k_channel *chan); | |
d70357d5 LR |
631 | }; |
632 | ||
f2552e28 FF |
633 | struct ath_nf_limits { |
634 | s16 max; | |
635 | s16 min; | |
636 | s16 nominal; | |
637 | }; | |
638 | ||
cbe61d8a | 639 | struct ath_hw { |
b002a4a9 | 640 | struct ieee80211_hw *hw; |
27c51f1a | 641 | struct ath_common common; |
cbe61d8a | 642 | struct ath9k_hw_version hw_version; |
2660b81a S |
643 | struct ath9k_ops_config config; |
644 | struct ath9k_hw_capabilities caps; | |
2660b81a S |
645 | struct ath9k_channel channels[38]; |
646 | struct ath9k_channel *curchan; | |
394cf0a1 | 647 | |
cbe61d8a S |
648 | union { |
649 | struct ar5416_eeprom_def def; | |
650 | struct ar5416_eeprom_4k map4k; | |
475f5989 | 651 | struct ar9287_eeprom map9287; |
15c9ee7a | 652 | struct ar9300_eeprom ar9300_eep; |
2660b81a | 653 | } eeprom; |
f74df6fb | 654 | const struct eeprom_ops *eep_ops; |
cbe61d8a S |
655 | |
656 | bool sw_mgmt_crypto; | |
2660b81a | 657 | bool is_pciexpress; |
2eb46d9b | 658 | bool need_an_top2_fixup; |
2660b81a | 659 | u16 tx_trig_level; |
f2552e28 FF |
660 | |
661 | struct ath_nf_limits nf_2g; | |
662 | struct ath_nf_limits nf_5g; | |
2660b81a S |
663 | u16 rfsilent; |
664 | u32 rfkill_gpio; | |
665 | u32 rfkill_polarity; | |
cbe61d8a | 666 | u32 ah_flags; |
394cf0a1 | 667 | |
d7e7d229 LR |
668 | bool htc_reset_init; |
669 | ||
2660b81a S |
670 | enum nl80211_iftype opmode; |
671 | enum ath9k_power_mode power_mode; | |
f078f209 | 672 | |
cbe61d8a | 673 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
a13883b0 | 674 | struct ath9k_pacal_info pacal_info; |
2660b81a S |
675 | struct ar5416Stats stats; |
676 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; | |
677 | ||
678 | int16_t curchan_rad_index; | |
3069168c | 679 | enum ath9k_int imask; |
74bad5cb | 680 | u32 imrs2_reg; |
2660b81a S |
681 | u32 txok_interrupt_mask; |
682 | u32 txerr_interrupt_mask; | |
683 | u32 txdesc_interrupt_mask; | |
684 | u32 txeol_interrupt_mask; | |
685 | u32 txurn_interrupt_mask; | |
686 | bool chip_fullsleep; | |
687 | u32 atim_window; | |
6a2b9e8c S |
688 | |
689 | /* Calibration */ | |
cbfe9468 S |
690 | enum ath9k_cal_types supp_cals; |
691 | struct ath9k_cal_list iq_caldata; | |
692 | struct ath9k_cal_list adcgain_caldata; | |
693 | struct ath9k_cal_list adcdc_calinitdata; | |
694 | struct ath9k_cal_list adcdc_caldata; | |
df23acaa | 695 | struct ath9k_cal_list tempCompCalData; |
cbfe9468 S |
696 | struct ath9k_cal_list *cal_list; |
697 | struct ath9k_cal_list *cal_list_last; | |
698 | struct ath9k_cal_list *cal_list_curr; | |
2660b81a S |
699 | #define totalPowerMeasI meas0.unsign |
700 | #define totalPowerMeasQ meas1.unsign | |
701 | #define totalIqCorrMeas meas2.sign | |
702 | #define totalAdcIOddPhase meas0.unsign | |
703 | #define totalAdcIEvenPhase meas1.unsign | |
704 | #define totalAdcQOddPhase meas2.unsign | |
705 | #define totalAdcQEvenPhase meas3.unsign | |
706 | #define totalAdcDcOffsetIOddPhase meas0.sign | |
707 | #define totalAdcDcOffsetIEvenPhase meas1.sign | |
708 | #define totalAdcDcOffsetQOddPhase meas2.sign | |
709 | #define totalAdcDcOffsetQEvenPhase meas3.sign | |
f078f209 LR |
710 | union { |
711 | u32 unsign[AR5416_MAX_CHAINS]; | |
712 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 713 | } meas0; |
f078f209 LR |
714 | union { |
715 | u32 unsign[AR5416_MAX_CHAINS]; | |
716 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 717 | } meas1; |
f078f209 LR |
718 | union { |
719 | u32 unsign[AR5416_MAX_CHAINS]; | |
720 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 721 | } meas2; |
f078f209 LR |
722 | union { |
723 | u32 unsign[AR5416_MAX_CHAINS]; | |
724 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a S |
725 | } meas3; |
726 | u16 cal_samples; | |
6a2b9e8c | 727 | |
2660b81a S |
728 | u32 sta_id1_defaults; |
729 | u32 misc_mode; | |
f078f209 LR |
730 | enum { |
731 | AUTO_32KHZ, | |
732 | USE_32KHZ, | |
733 | DONT_USE_32KHZ, | |
2660b81a | 734 | } enable_32kHz_clock; |
6a2b9e8c | 735 | |
d70357d5 LR |
736 | /* Private to hardware code */ |
737 | struct ath_hw_private_ops private_ops; | |
738 | /* Accessed by the lower level driver */ | |
739 | struct ath_hw_ops ops; | |
740 | ||
e68a060b | 741 | /* Used to program the radio on non single-chip devices */ |
2660b81a S |
742 | u32 *analogBank0Data; |
743 | u32 *analogBank1Data; | |
744 | u32 *analogBank2Data; | |
745 | u32 *analogBank3Data; | |
746 | u32 *analogBank6Data; | |
747 | u32 *analogBank6TPCData; | |
748 | u32 *analogBank7Data; | |
749 | u32 *addac5416_21; | |
750 | u32 *bank6Temp; | |
751 | ||
597a94b3 | 752 | u8 txpower_limit; |
2660b81a | 753 | int16_t txpower_indexoffset; |
e239d859 | 754 | int coverage_class; |
2660b81a S |
755 | u32 beacon_interval; |
756 | u32 slottime; | |
2660b81a | 757 | u32 globaltxtimeout; |
6a2b9e8c S |
758 | |
759 | /* ANI */ | |
2660b81a | 760 | u32 proc_phyerr; |
2660b81a S |
761 | u32 aniperiod; |
762 | struct ar5416AniState *curani; | |
763 | struct ar5416AniState ani[255]; | |
764 | int totalSizeDesired[5]; | |
765 | int coarse_high[5]; | |
766 | int coarse_low[5]; | |
767 | int firpwr[5]; | |
768 | enum ath9k_ani_cmd ani_function; | |
769 | ||
af03abec | 770 | /* Bluetooth coexistance */ |
766ec4a9 | 771 | struct ath_btcoex_hw btcoex_hw; |
af03abec | 772 | |
2660b81a | 773 | u32 intr_txqs; |
2660b81a S |
774 | u8 txchainmask; |
775 | u8 rxchainmask; | |
776 | ||
8bd1d07f SB |
777 | u32 originalGain[22]; |
778 | int initPDADC; | |
779 | int PDADCdelta; | |
08fc5c1b | 780 | u8 led_pin; |
8bd1d07f | 781 | |
2660b81a S |
782 | struct ar5416IniArray iniModes; |
783 | struct ar5416IniArray iniCommon; | |
784 | struct ar5416IniArray iniBank0; | |
785 | struct ar5416IniArray iniBB_RfGain; | |
786 | struct ar5416IniArray iniBank1; | |
787 | struct ar5416IniArray iniBank2; | |
788 | struct ar5416IniArray iniBank3; | |
789 | struct ar5416IniArray iniBank6; | |
790 | struct ar5416IniArray iniBank6TPC; | |
791 | struct ar5416IniArray iniBank7; | |
792 | struct ar5416IniArray iniAddac; | |
793 | struct ar5416IniArray iniPcieSerdes; | |
13ce3e99 | 794 | struct ar5416IniArray iniPcieSerdesLowPower; |
2660b81a S |
795 | struct ar5416IniArray iniModesAdditional; |
796 | struct ar5416IniArray iniModesRxGain; | |
797 | struct ar5416IniArray iniModesTxGain; | |
8564328d | 798 | struct ar5416IniArray iniModes_9271_1_0_only; |
193cd458 S |
799 | struct ar5416IniArray iniCckfirNormal; |
800 | struct ar5416IniArray iniCckfirJapan2484; | |
70807e99 S |
801 | struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; |
802 | struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; | |
803 | struct ar5416IniArray iniModes_9271_ANI_reg; | |
804 | struct ar5416IniArray iniModes_high_power_tx_gain_9271; | |
805 | struct ar5416IniArray iniModes_normal_power_tx_gain_9271; | |
ff155a45 | 806 | |
13ce3e99 LR |
807 | struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; |
808 | struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; | |
809 | struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; | |
810 | struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; | |
811 | ||
ff155a45 VT |
812 | u32 intr_gen_timer_trigger; |
813 | u32 intr_gen_timer_thresh; | |
814 | struct ath_gen_timer_table hw_gen_timers; | |
744d4025 VT |
815 | |
816 | struct ar9003_txs *ts_ring; | |
817 | void *ts_start; | |
818 | u32 ts_paddr_start; | |
819 | u32 ts_paddr_end; | |
820 | u16 ts_tail; | |
821 | u8 ts_size; | |
aea702b7 LR |
822 | |
823 | u32 bb_watchdog_last_status; | |
824 | u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */ | |
717f6bed FF |
825 | |
826 | u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES]; | |
827 | u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES]; | |
9a658d2b LR |
828 | /* |
829 | * Store the permanent value of Reg 0x4004in WARegVal | |
830 | * so we dont have to R/M/W. We should not be reading | |
831 | * this register when in sleep states. | |
832 | */ | |
833 | u32 WARegVal; | |
f078f209 | 834 | }; |
f078f209 | 835 | |
9e4bffd2 LR |
836 | static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) |
837 | { | |
838 | return &ah->common; | |
839 | } | |
840 | ||
841 | static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) | |
842 | { | |
843 | return &(ath9k_hw_common(ah)->regulatory); | |
844 | } | |
845 | ||
d70357d5 LR |
846 | static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) |
847 | { | |
848 | return &ah->private_ops; | |
849 | } | |
850 | ||
851 | static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) | |
852 | { | |
853 | return &ah->ops; | |
854 | } | |
855 | ||
54bd5006 FF |
856 | static inline int sign_extend(int val, const int nbits) |
857 | { | |
858 | int order = BIT(nbits-1); | |
859 | return (val ^ order) - order; | |
860 | } | |
861 | ||
f637cfd6 | 862 | /* Initialization, Detach, Reset */ |
394cf0a1 | 863 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); |
285f2dda | 864 | void ath9k_hw_deinit(struct ath_hw *ah); |
f637cfd6 | 865 | int ath9k_hw_init(struct ath_hw *ah); |
cbe61d8a | 866 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
394cf0a1 | 867 | bool bChannelChange); |
a9a29ce6 | 868 | int ath9k_hw_fill_cap_info(struct ath_hw *ah); |
8fe65368 | 869 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); |
394cf0a1 S |
870 | |
871 | /* Key Cache Management */ | |
cbe61d8a | 872 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); |
cbe61d8a | 873 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, |
394cf0a1 | 874 | const struct ath9k_keyval *k, |
e0caf9ea | 875 | const u8 *mac); |
394cf0a1 S |
876 | |
877 | /* GPIO / RFKILL / Antennae */ | |
cbe61d8a S |
878 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); |
879 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); | |
880 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, | |
394cf0a1 | 881 | u32 ah_signal_type); |
cbe61d8a | 882 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
cbe61d8a S |
883 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah); |
884 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); | |
394cf0a1 S |
885 | |
886 | /* General Operation */ | |
0caa7b14 | 887 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
394cf0a1 | 888 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
cbe61d8a | 889 | bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high); |
4f0fc7c3 | 890 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 891 | u8 phy, int kbps, |
394cf0a1 | 892 | u32 frameLen, u16 rateix, bool shortPreamble); |
cbe61d8a | 893 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
394cf0a1 S |
894 | struct ath9k_channel *chan, |
895 | struct chan_centers *centers); | |
cbe61d8a S |
896 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
897 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); | |
898 | bool ath9k_hw_phy_disable(struct ath_hw *ah); | |
899 | bool ath9k_hw_disable(struct ath_hw *ah); | |
8fbff4b8 | 900 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit); |
cbe61d8a S |
901 | void ath9k_hw_setopmode(struct ath_hw *ah); |
902 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); | |
f2b2143e LR |
903 | void ath9k_hw_setbssidmask(struct ath_hw *ah); |
904 | void ath9k_hw_write_associd(struct ath_hw *ah); | |
cbe61d8a S |
905 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
906 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); | |
907 | void ath9k_hw_reset_tsf(struct ath_hw *ah); | |
54e4cec6 | 908 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); |
0005baf4 | 909 | void ath9k_hw_init_global_settings(struct ath_hw *ah); |
25c56eec | 910 | void ath9k_hw_set11nmac2040(struct ath_hw *ah); |
cbe61d8a S |
911 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); |
912 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |
394cf0a1 | 913 | const struct ath9k_beacon_state *bs); |
c9c99e5e | 914 | bool ath9k_hw_check_alive(struct ath_hw *ah); |
a91d75ae | 915 | |
9ecdef4b | 916 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); |
a91d75ae | 917 | |
ff155a45 VT |
918 | /* Generic hw timer primitives */ |
919 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
920 | void (*trigger)(void *), | |
921 | void (*overflow)(void *), | |
922 | void *arg, | |
923 | u8 timer_index); | |
cd9bf689 LR |
924 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
925 | struct ath_gen_timer *timer, | |
926 | u32 timer_next, | |
927 | u32 timer_period); | |
928 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); | |
929 | ||
ff155a45 VT |
930 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); |
931 | void ath_gen_timer_isr(struct ath_hw *hw); | |
1773912b | 932 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); |
ff155a45 | 933 | |
f934c4d9 | 934 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); |
2da4f01a | 935 | |
05020d23 S |
936 | /* HTC */ |
937 | void ath9k_hw_htc_resetinit(struct ath_hw *ah); | |
938 | ||
8fe65368 LR |
939 | /* PHY */ |
940 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, | |
941 | u32 *coef_mantissa, u32 *coef_exponent); | |
942 | ||
ebd5a14a LR |
943 | /* |
944 | * Code Specific to AR5008, AR9001 or AR9002, | |
945 | * we stuff these here to avoid callbacks for AR9003. | |
946 | */ | |
d8f492b7 | 947 | void ar9002_hw_cck_chan14_spread(struct ath_hw *ah); |
ebd5a14a | 948 | int ar9002_hw_rf_claim(struct ath_hw *ah); |
78ec2677 | 949 | void ar9002_hw_enable_async_fifo(struct ath_hw *ah); |
e9141f71 | 950 | void ar9002_hw_update_async_fifo(struct ath_hw *ah); |
6c94fdc9 | 951 | void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah); |
d8f492b7 | 952 | |
641d9921 | 953 | /* |
aea702b7 | 954 | * Code specific to AR9003, we stuff these here to avoid callbacks |
641d9921 FF |
955 | * for older families |
956 | */ | |
aea702b7 LR |
957 | void ar9003_hw_bb_watchdog_config(struct ath_hw *ah); |
958 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah); | |
959 | void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah); | |
717f6bed FF |
960 | void ar9003_paprd_enable(struct ath_hw *ah, bool val); |
961 | void ar9003_paprd_populate_single_table(struct ath_hw *ah, | |
962 | struct ath9k_channel *chan, int chain); | |
963 | int ar9003_paprd_create_curve(struct ath_hw *ah, struct ath9k_channel *chan, | |
964 | int chain); | |
965 | int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain); | |
966 | int ar9003_paprd_init_table(struct ath_hw *ah); | |
967 | bool ar9003_paprd_is_done(struct ath_hw *ah); | |
968 | void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains); | |
641d9921 FF |
969 | |
970 | /* Hardware family op attach helpers */ | |
8fe65368 | 971 | void ar5008_hw_attach_phy_ops(struct ath_hw *ah); |
8525f280 LR |
972 | void ar9002_hw_attach_phy_ops(struct ath_hw *ah); |
973 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah); | |
8fe65368 | 974 | |
795f5e2c LR |
975 | void ar9002_hw_attach_calib_ops(struct ath_hw *ah); |
976 | void ar9003_hw_attach_calib_ops(struct ath_hw *ah); | |
977 | ||
b3950e6a LR |
978 | void ar9002_hw_attach_ops(struct ath_hw *ah); |
979 | void ar9003_hw_attach_ops(struct ath_hw *ah); | |
980 | ||
ac0bb767 LR |
981 | /* |
982 | * ANI work can be shared between all families but a next | |
983 | * generation implementation of ANI will be used only for AR9003 only | |
984 | * for now as the other families still need to be tested with the same | |
e36b27af LR |
985 | * next generation ANI. Feel free to start testing it though for the |
986 | * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani. | |
ac0bb767 | 987 | */ |
e36b27af | 988 | extern int modparam_force_new_ani; |
ac0bb767 | 989 | void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah); |
e36b27af | 990 | void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah); |
ac0bb767 | 991 | |
7b6840ab VT |
992 | #define ATH_PCIE_CAP_LINK_CTRL 0x70 |
993 | #define ATH_PCIE_CAP_LINK_L0S 1 | |
994 | #define ATH_PCIE_CAP_LINK_L1 2 | |
995 | ||
73377256 LR |
996 | #define ATH9K_CLOCK_RATE_CCK 22 |
997 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 | |
998 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 | |
999 | #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44 | |
1000 | ||
f078f209 | 1001 | #endif |