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mac80211: fix rates setup on IBSS merge
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
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f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
c46917bb 33#include "../debug.h"
3a702e49 34
394cf0a1 35#define ATHEROS_VENDOR_ID 0x168c
7976b426 36
394cf0a1
S		 37#define AR5416_DEVID_PCI 0x0023
38#define AR5416_DEVID_PCIE 0x0024
39#define AR9160_DEVID_PCI 0x0027
40#define AR9280_DEVID_PCI 0x0029
41#define AR9280_DEVID_PCIE 0x002a
42#define AR9285_DEVID_PCIE 0x002b
5ffaf8a3 43#define AR2427_DEVID_PCIE 0x002c
7976b426 44
394cf0a1 45#define AR5416_AR9100_DEVID 0x000b
7976b426
LR		 46
47#define AR9271_USB 0x9271
48
394cf0a1
S		 49#define AR_SUBVENDOR_ID_NOG 0x0e11
50#define AR_SUBVENDOR_ID_NEW_A 0x7065
51#define AR5416_MAGIC 0x19641014
52
ac88b6ec
VN		 53#define AR5416_DEVID_AR9287_PCI 0x002D
54#define AR5416_DEVID_AR9287_PCIE 0x002E
55
fe12946e
VT		 56#define AR9280_COEX2WIRE_SUBSYSID 0x309b
57#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
58#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
59
e3d01bfc
LR		 60#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
61
cfe8cba9
LR		 62#define ATH_DEFAULT_NOISE_FLOOR -95
63
04658fba 64#define ATH9K_RSSI_BAD -128
990b70ab 65
394cf0a1 66/* Register read/write primitives */
9e4bffd2
LR		 67#define REG_WRITE(_ah, _reg, _val) \
68 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
69
70#define REG_READ(_ah, _reg) \
71 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
394cf0a1
S		 72
73#define SM(_v, _f) (((_v) << _f##_S) & _f)
74#define MS(_v, _f) (((_v) & _f) >> _f##_S)
75#define REG_RMW(_a, _r, _set, _clr) \
76 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
77#define REG_RMW_FIELD(_a, _r, _f, _v) \
78 REG_WRITE(_a, _r, \
79 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
80#define REG_SET_BIT(_a, _r, _f) \
81 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
82#define REG_CLR_BIT(_a, _r, _f) \
83 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 84
394cf0a1
S		 85#define DO_DELAY(x) do { \
86 if ((++(x) % 64) == 0) \
87 udelay(1); \
88 } while (0)
f078f209 89
394cf0a1
S		 90#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
91 int r; \
92 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
93 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
94 INI_RA((iniarray), r, (column))); \
95 DO_DELAY(regWr); \
96 } \
97 } while (0)
f078f209 98
394cf0a1
S		 99#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
100#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
101#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
102#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 103#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 104#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
105#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 106
394cf0a1
S		 107#define AR_GPIOD_MASK 0x00001FFF
108#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 109
394cf0a1 110#define BASE_ACTIVATE_DELAY 100
63a75b91 111#define RTC_PLL_SETTLE_DELAY 100
394cf0a1
S		 112#define COEF_SCALE_S 24
113#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 114
394cf0a1
S		 115#define ATH9K_ANTENNA0_CHAINMASK 0x1
116#define ATH9K_ANTENNA1_CHAINMASK 0x2
117
118#define ATH9K_NUM_DMA_DEBUG_REGS 8
119#define ATH9K_NUM_QUEUES 10
120
121#define MAX_RATE_POWER 63
0caa7b14 122#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 123#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 124#define AH_TIME_QUANTUM 10
125#define AR_KEYTABLE_SIZE 128
d8caa839 126#define POWER_UP_TIME 10000
394cf0a1
S		 127#define SPUR_RSSI_THRESH 40
128
129#define CAB_TIMEOUT_VAL 10
130#define BEACON_TIMEOUT_VAL 10
131#define MIN_BEACON_TIMEOUT_VAL 1
132#define SLEEP_SLOP 3
133
134#define INIT_CONFIG_STATUS 0x00000000
135#define INIT_RSSI_THR 0x00000700
136#define INIT_BCON_CNTRL_REG 0x00000000
137
138#define TU_TO_USEC(_tu) ((_tu) << 10)
139
140enum wireless_mode {
141 ATH9K_MODE_11A = 0,
b9b6e15a
LR		 142 ATH9K_MODE_11G,
143 ATH9K_MODE_11NA_HT20,
144 ATH9K_MODE_11NG_HT20,
145 ATH9K_MODE_11NA_HT40PLUS,
146 ATH9K_MODE_11NA_HT40MINUS,
147 ATH9K_MODE_11NG_HT40PLUS,
148 ATH9K_MODE_11NG_HT40MINUS,
149 ATH9K_MODE_MAX,
394cf0a1 150};
f078f209 151
394cf0a1 152enum ath9k_hw_caps {
bdbdf46d
S		 153 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
154 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
155 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
156 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
157 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
158 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
159 ATH9K_HW_CAP_VEOL = BIT(6),
160 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
161 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
162 ATH9K_HW_CAP_HT = BIT(9),
163 ATH9K_HW_CAP_GTT = BIT(10),
164 ATH9K_HW_CAP_FASTCC = BIT(11),
165 ATH9K_HW_CAP_RFSILENT = BIT(12),
166 ATH9K_HW_CAP_CST = BIT(13),
167 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
168 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
169 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
394cf0a1 170};
f078f209 171
394cf0a1
S		 172enum ath9k_capability_type {
173 ATH9K_CAP_CIPHER = 0,
174 ATH9K_CAP_TKIP_MIC,
175 ATH9K_CAP_TKIP_SPLIT,
394cf0a1
S		 176 ATH9K_CAP_DIVERSITY,
177 ATH9K_CAP_TXPOW,
394cf0a1 178 ATH9K_CAP_MCAST_KEYSRCH,
8bd1d07f 179 ATH9K_CAP_DS
394cf0a1 180};
f078f209 181
394cf0a1
S		 182struct ath9k_hw_capabilities {
183 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
184 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
185 u16 total_queues;
186 u16 keycache_size;
187 u16 low_5ghz_chan, high_5ghz_chan;
188 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 189 u16 rts_aggr_limit;
190 u8 tx_chainmask;
191 u8 rx_chainmask;
192 u16 tx_triglevel_max;
193 u16 reg_cap;
194 u8 num_gpio_pins;
195 u8 num_antcfg_2ghz;
196 u8 num_antcfg_5ghz;
197};
f078f209 198
394cf0a1
S		 199struct ath9k_ops_config {
200 int dma_beacon_response_time;
201 int sw_beacon_response_time;
202 int additional_swba_backoff;
203 int ack_6mb;
204 int cwm_ignore_extcca;
205 u8 pcie_powersave_enable;
394cf0a1
S		 206 u8 pcie_clock_req;
207 u32 pcie_waen;
394cf0a1
S		 208 u8 analog_shiftreg;
209 u8 ht_enable;
210 u32 ofdm_trig_low;
211 u32 ofdm_trig_high;
212 u32 cck_trig_high;
213 u32 cck_trig_low;
214 u32 enable_ani;
394cf0a1 215 int serialize_regmode;
0ce024cb 216 bool rx_intr_mitigation;
394cf0a1
S		 217#define SPUR_DISABLE 0
218#define SPUR_ENABLE_IOCTL 1
219#define SPUR_ENABLE_EEPROM 2
220#define AR_EEPROM_MODAL_SPURS 5
221#define AR_SPUR_5413_1 1640
222#define AR_SPUR_5413_2 1200
223#define AR_NO_SPUR 0x8000
224#define AR_BASE_FREQ_2GHZ 2300
225#define AR_BASE_FREQ_5GHZ 4900
226#define AR_SPUR_FEEQ_BOUND_HT40 19
227#define AR_SPUR_FEEQ_BOUND_HT20 10
228 int spurmode;
229 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 230 u8 max_txtrig_level;
394cf0a1 231};
f078f209 232
394cf0a1
S		 233enum ath9k_int {
234 ATH9K_INT_RX = 0x00000001,
235 ATH9K_INT_RXDESC = 0x00000002,
236 ATH9K_INT_RXNOFRM = 0x00000008,
237 ATH9K_INT_RXEOL = 0x00000010,
238 ATH9K_INT_RXORN = 0x00000020,
239 ATH9K_INT_TX = 0x00000040,
240 ATH9K_INT_TXDESC = 0x00000080,
241 ATH9K_INT_TIM_TIMER = 0x00000100,
242 ATH9K_INT_TXURN = 0x00000800,
243 ATH9K_INT_MIB = 0x00001000,
244 ATH9K_INT_RXPHY = 0x00004000,
245 ATH9K_INT_RXKCM = 0x00008000,
246 ATH9K_INT_SWBA = 0x00010000,
247 ATH9K_INT_BMISS = 0x00040000,
248 ATH9K_INT_BNR = 0x00100000,
249 ATH9K_INT_TIM = 0x00200000,
250 ATH9K_INT_DTIM = 0x00400000,
251 ATH9K_INT_DTIMSYNC = 0x00800000,
252 ATH9K_INT_GPIO = 0x01000000,
253 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 254 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 255 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 256 ATH9K_INT_CST = 0x10000000,
257 ATH9K_INT_GTT = 0x20000000,
258 ATH9K_INT_FATAL = 0x40000000,
259 ATH9K_INT_GLOBAL = 0x80000000,
260 ATH9K_INT_BMISC = ATH9K_INT_TIM |
261 ATH9K_INT_DTIM |
262 ATH9K_INT_DTIMSYNC |
4af9cf4f 263 ATH9K_INT_TSFOOR |
394cf0a1
S		 264 ATH9K_INT_CABEND,
265 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
266 ATH9K_INT_RXDESC |
267 ATH9K_INT_RXEOL |
268 ATH9K_INT_RXORN |
269 ATH9K_INT_TXURN |
270 ATH9K_INT_TXDESC |
271 ATH9K_INT_MIB |
272 ATH9K_INT_RXPHY |
273 ATH9K_INT_RXKCM |
274 ATH9K_INT_SWBA |
275 ATH9K_INT_BMISS |
276 ATH9K_INT_GPIO,
277 ATH9K_INT_NOCARD = 0xffffffff
278};
f078f209 279
394cf0a1
S		 280#define CHANNEL_CW_INT 0x00002
281#define CHANNEL_CCK 0x00020
282#define CHANNEL_OFDM 0x00040
283#define CHANNEL_2GHZ 0x00080
284#define CHANNEL_5GHZ 0x00100
285#define CHANNEL_PASSIVE 0x00200
286#define CHANNEL_DYN 0x00400
287#define CHANNEL_HALF 0x04000
288#define CHANNEL_QUARTER 0x08000
289#define CHANNEL_HT20 0x10000
290#define CHANNEL_HT40PLUS 0x20000
291#define CHANNEL_HT40MINUS 0x40000
292
394cf0a1
S		 293#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
294#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
295#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
296#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
297#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
298#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
299#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
300#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
301#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
302#define CHANNEL_ALL \
303 (CHANNEL_OFDM| \
304 CHANNEL_CCK| \
305 CHANNEL_2GHZ | \
306 CHANNEL_5GHZ | \
307 CHANNEL_HT20 | \
308 CHANNEL_HT40PLUS | \
309 CHANNEL_HT40MINUS)
310
311struct ath9k_channel {
312 struct ieee80211_channel *chan;
313 u16 channel;
314 u32 channelFlags;
315 u32 chanmode;
316 int32_t CalValid;
317 bool oneTimeCalsDone;
318 int8_t iCoff;
319 int8_t qCoff;
320 int16_t rawNoiseFloor;
321};
f078f209 322
394cf0a1
S		 323#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
324 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
325 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
326 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
327#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
328#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
329#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 330#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
331#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
332#define IS_CHAN_A_5MHZ_SPACED(_c) \
333 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
334 (((_c)->channel % 20) != 0) && \
335 (((_c)->channel % 10) != 0))
336
337/* These macros check chanmode and not channelFlags */
338#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
339#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
340 ((_c)->chanmode == CHANNEL_G_HT20))
341#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
342 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
343 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
344 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
345#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
346
347enum ath9k_power_mode {
348 ATH9K_PM_AWAKE = 0,
349 ATH9K_PM_FULL_SLEEP,
350 ATH9K_PM_NETWORK_SLEEP,
351 ATH9K_PM_UNDEFINED
352};
f078f209 353
394cf0a1
S		 354enum ath9k_tp_scale {
355 ATH9K_TP_SCALE_MAX = 0,
356 ATH9K_TP_SCALE_50,
357 ATH9K_TP_SCALE_25,
358 ATH9K_TP_SCALE_12,
359 ATH9K_TP_SCALE_MIN
360};
f078f209 361
394cf0a1
S		 362enum ser_reg_mode {
363 SER_REG_MODE_OFF = 0,
364 SER_REG_MODE_ON = 1,
365 SER_REG_MODE_AUTO = 2,
366};
f078f209 367
394cf0a1
S		 368struct ath9k_beacon_state {
369 u32 bs_nexttbtt;
370 u32 bs_nextdtim;
371 u32 bs_intval;
372#define ATH9K_BEACON_PERIOD 0x0000ffff
373#define ATH9K_BEACON_ENA 0x00800000
374#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 375#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 376 u32 bs_dtimperiod;
377 u16 bs_cfpperiod;
378 u16 bs_cfpmaxduration;
379 u32 bs_cfpnext;
380 u16 bs_timoffset;
381 u16 bs_bmissthreshold;
382 u32 bs_sleepduration;
4af9cf4f 383 u32 bs_tsfoor_threshold;
394cf0a1 384};
f078f209 385
394cf0a1
S		 386struct chan_centers {
387 u16 synth_center;
388 u16 ctl_center;
389 u16 ext_center;
390};
f078f209 391
394cf0a1
S		 392enum {
393 ATH9K_RESET_POWER_ON,
394 ATH9K_RESET_WARM,
395 ATH9K_RESET_COLD,
396};
f078f209 397
d535a42a
S		 398struct ath9k_hw_version {
399 u32 magic;
400 u16 devid;
401 u16 subvendorid;
402 u32 macVersion;
403 u16 macRev;
404 u16 phyRev;
405 u16 analog5GhzRev;
406 u16 analog2GhzRev;
aeac355d 407 u16 subsysid;
d535a42a 408};
394cf0a1 409
ff155a45
VT		 410/* Generic TSF timer definitions */
411
412#define ATH_MAX_GEN_TIMER 16
413
414#define AR_GENTMR_BIT(_index) (1 << (_index))
415
416/*
417 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
418 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
419 */
c90017dd 420#define debruijn32 0x077CB531U
ff155a45
VT		 421
422struct ath_gen_timer_configuration {
423 u32 next_addr;
424 u32 period_addr;
425 u32 mode_addr;
426 u32 mode_mask;
427};
428
429struct ath_gen_timer {
430 void (*trigger)(void *arg);
431 void (*overflow)(void *arg);
432 void *arg;
433 u8 index;
434};
435
436struct ath_gen_timer_table {
437 u32 gen_timer_index[32];
438 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
439 union {
440 unsigned long timer_bits;
441 u16 val;
442 } timer_mask;
443};
444
cbe61d8a 445struct ath_hw {
b002a4a9 446 struct ieee80211_hw *hw;
27c51f1a 447 struct ath_common common;
cbe61d8a 448 struct ath9k_hw_version hw_version;
2660b81a
S		 449 struct ath9k_ops_config config;
450 struct ath9k_hw_capabilities caps;
2660b81a
S		 451 struct ath9k_channel channels[38];
452 struct ath9k_channel *curchan;
394cf0a1 453
cbe61d8a
S		 454 union {
455 struct ar5416_eeprom_def def;
456 struct ar5416_eeprom_4k map4k;
475f5989 457 struct ar9287_eeprom map9287;
2660b81a 458 } eeprom;
f74df6fb 459 const struct eeprom_ops *eep_ops;
2660b81a 460 enum ath9k_eep_map eep_map;
cbe61d8a
S		 461
462 bool sw_mgmt_crypto;
2660b81a 463 bool is_pciexpress;
2660b81a
S		 464 u16 tx_trig_level;
465 u16 rfsilent;
466 u32 rfkill_gpio;
467 u32 rfkill_polarity;
cbe61d8a 468 u32 ah_flags;
394cf0a1 469
d7e7d229
LR		 470 bool htc_reset_init;
471
2660b81a
S		 472 enum nl80211_iftype opmode;
473 enum ath9k_power_mode power_mode;
f078f209 474
cbe61d8a 475 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
a13883b0 476 struct ath9k_pacal_info pacal_info;
2660b81a
S		 477 struct ar5416Stats stats;
478 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
479
480 int16_t curchan_rad_index;
481 u32 mask_reg;
482 u32 txok_interrupt_mask;
483 u32 txerr_interrupt_mask;
484 u32 txdesc_interrupt_mask;
485 u32 txeol_interrupt_mask;
486 u32 txurn_interrupt_mask;
487 bool chip_fullsleep;
488 u32 atim_window;
6a2b9e8c
S		 489
490 /* Calibration */
cbfe9468
S		 491 enum ath9k_cal_types supp_cals;
492 struct ath9k_cal_list iq_caldata;
493 struct ath9k_cal_list adcgain_caldata;
494 struct ath9k_cal_list adcdc_calinitdata;
495 struct ath9k_cal_list adcdc_caldata;
496 struct ath9k_cal_list *cal_list;
497 struct ath9k_cal_list *cal_list_last;
498 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 499#define totalPowerMeasI meas0.unsign
500#define totalPowerMeasQ meas1.unsign
501#define totalIqCorrMeas meas2.sign
502#define totalAdcIOddPhase meas0.unsign
503#define totalAdcIEvenPhase meas1.unsign
504#define totalAdcQOddPhase meas2.unsign
505#define totalAdcQEvenPhase meas3.unsign
506#define totalAdcDcOffsetIOddPhase meas0.sign
507#define totalAdcDcOffsetIEvenPhase meas1.sign
508#define totalAdcDcOffsetQOddPhase meas2.sign
509#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 510 union {
511 u32 unsign[AR5416_MAX_CHAINS];
512 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 513 } meas0;
f078f209
LR		 514 union {
515 u32 unsign[AR5416_MAX_CHAINS];
516 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 517 } meas1;
f078f209
LR		 518 union {
519 u32 unsign[AR5416_MAX_CHAINS];
520 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 521 } meas2;
f078f209
LR		 522 union {
523 u32 unsign[AR5416_MAX_CHAINS];
524 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 525 } meas3;
526 u16 cal_samples;
6a2b9e8c 527
2660b81a
S		 528 u32 sta_id1_defaults;
529 u32 misc_mode;
f078f209
LR		 530 enum {
531 AUTO_32KHZ,
532 USE_32KHZ,
533 DONT_USE_32KHZ,
2660b81a 534 } enable_32kHz_clock;
6a2b9e8c 535
e68a060b
LR		 536 /* Callback for radio frequency change */
537 int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
ae478cf6
LR		 538
539 /* Callback for baseband spur frequency */
540 void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
541 struct ath9k_channel *chan);
542
e68a060b 543 /* Used to program the radio on non single-chip devices */
2660b81a
S		 544 u32 *analogBank0Data;
545 u32 *analogBank1Data;
546 u32 *analogBank2Data;
547 u32 *analogBank3Data;
548 u32 *analogBank6Data;
549 u32 *analogBank6TPCData;
550 u32 *analogBank7Data;
551 u32 *addac5416_21;
552 u32 *bank6Temp;
553
554 int16_t txpower_indexoffset;
e239d859 555 int coverage_class;
2660b81a
S		 556 u32 beacon_interval;
557 u32 slottime;
2660b81a 558 u32 globaltxtimeout;
6a2b9e8c
S		 559
560 /* ANI */
2660b81a 561 u32 proc_phyerr;
2660b81a
S		 562 u32 aniperiod;
563 struct ar5416AniState *curani;
564 struct ar5416AniState ani[255];
565 int totalSizeDesired[5];
566 int coarse_high[5];
567 int coarse_low[5];
568 int firpwr[5];
569 enum ath9k_ani_cmd ani_function;
570
af03abec 571 /* Bluetooth coexistance */
766ec4a9 572 struct ath_btcoex_hw btcoex_hw;
af03abec 573
2660b81a 574 u32 intr_txqs;
2660b81a
S		 575 u8 txchainmask;
576 u8 rxchainmask;
577
8bd1d07f
SB		 578 u32 originalGain[22];
579 int initPDADC;
580 int PDADCdelta;
08fc5c1b 581 u8 led_pin;
8bd1d07f 582
2660b81a
S		 583 struct ar5416IniArray iniModes;
584 struct ar5416IniArray iniCommon;
585 struct ar5416IniArray iniBank0;
586 struct ar5416IniArray iniBB_RfGain;
587 struct ar5416IniArray iniBank1;
588 struct ar5416IniArray iniBank2;
589 struct ar5416IniArray iniBank3;
590 struct ar5416IniArray iniBank6;
591 struct ar5416IniArray iniBank6TPC;
592 struct ar5416IniArray iniBank7;
593 struct ar5416IniArray iniAddac;
594 struct ar5416IniArray iniPcieSerdes;
595 struct ar5416IniArray iniModesAdditional;
596 struct ar5416IniArray iniModesRxGain;
597 struct ar5416IniArray iniModesTxGain;
8564328d 598 struct ar5416IniArray iniModes_9271_1_0_only;
193cd458
S		 599 struct ar5416IniArray iniCckfirNormal;
600 struct ar5416IniArray iniCckfirJapan2484;
ff155a45
VT		 601
602 u32 intr_gen_timer_trigger;
603 u32 intr_gen_timer_thresh;
604 struct ath_gen_timer_table hw_gen_timers;
f078f209 605};
f078f209 606
9e4bffd2
LR		 607static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
608{
609 return &ah->common;
610}
611
612static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
613{
614 return &(ath9k_hw_common(ah)->regulatory);
615}
616
f637cfd6 617/* Initialization, Detach, Reset */
394cf0a1 618const char *ath9k_hw_probe(u16 vendorid, u16 devid);
285f2dda 619void ath9k_hw_deinit(struct ath_hw *ah);
f637cfd6 620int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 621int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
394cf0a1 622 bool bChannelChange);
a9a29ce6 623int ath9k_hw_fill_cap_info(struct ath_hw *ah);
cbe61d8a 624bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 625 u32 capability, u32 *result);
cbe61d8a 626bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1
S		 627 u32 capability, u32 setting, int *status);
628
629/* Key Cache Management */
cbe61d8a
S		 630bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
631bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
632bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
394cf0a1 633 const struct ath9k_keyval *k,
e0caf9ea 634 const u8 *mac);
cbe61d8a 635bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
394cf0a1
S		 636
637/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 638void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
639u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
640void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 641 u32 ah_signal_type);
cbe61d8a 642void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 643u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
644void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
394cf0a1
S		 645
646/* General Operation */
0caa7b14 647bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 648u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 649bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3 650u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 651 u8 phy, int kbps,
394cf0a1 652 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 653void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 654 struct ath9k_channel *chan,
655 struct chan_centers *centers);
cbe61d8a
S		 656u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
657void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
658bool ath9k_hw_phy_disable(struct ath_hw *ah);
659bool ath9k_hw_disable(struct ath_hw *ah);
8fbff4b8 660void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
cbe61d8a
S		 661void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
662void ath9k_hw_setopmode(struct ath_hw *ah);
663void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 664void ath9k_hw_setbssidmask(struct ath_hw *ah);
665void ath9k_hw_write_associd(struct ath_hw *ah);
cbe61d8a
S		 666u64 ath9k_hw_gettsf64(struct ath_hw *ah);
667void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
668void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 669void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
30cbd422 670u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
0005baf4 671void ath9k_hw_init_global_settings(struct ath_hw *ah);
25c56eec 672void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 673void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
674void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 675 const struct ath9k_beacon_state *bs);
a91d75ae 676
9ecdef4b 677bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 678
93b1b37f 679void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off);
394cf0a1
S		 680
681/* Interrupt Handling */
cbe61d8a
S		 682bool ath9k_hw_intrpend(struct ath_hw *ah);
683bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
cbe61d8a 684enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
394cf0a1 685
ff155a45
VT		 686/* Generic hw timer primitives */
687struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
688 void (*trigger)(void *),
689 void (*overflow)(void *),
690 void *arg,
691 u8 timer_index);
cd9bf689
LR		 692void ath9k_hw_gen_timer_start(struct ath_hw *ah,
693 struct ath_gen_timer *timer,
694 u32 timer_next,
695 u32 timer_period);
696void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
697
ff155a45
VT		 698void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
699void ath_gen_timer_isr(struct ath_hw *hw);
1773912b 700u32 ath9k_hw_gettsf32(struct ath_hw *ah);
ff155a45 701
f934c4d9 702void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 703
7b6840ab
VT		 704#define ATH_PCIE_CAP_LINK_CTRL 0x70
705#define ATH_PCIE_CAP_LINK_L0S 1
706#define ATH_PCIE_CAP_LINK_L1 2
707
f078f209 708#endif
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