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ath9k: remove ATH9K_MODE_11B
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
30
203c4805 31#include "../regd.h"
3a702e49 32
394cf0a1
S		 33#define ATHEROS_VENDOR_ID 0x168c
34#define AR5416_DEVID_PCI 0x0023
35#define AR5416_DEVID_PCIE 0x0024
36#define AR9160_DEVID_PCI 0x0027
37#define AR9280_DEVID_PCI 0x0029
38#define AR9280_DEVID_PCIE 0x002a
39#define AR9285_DEVID_PCIE 0x002b
40#define AR5416_AR9100_DEVID 0x000b
41#define AR_SUBVENDOR_ID_NOG 0x0e11
42#define AR_SUBVENDOR_ID_NEW_A 0x7065
43#define AR5416_MAGIC 0x19641014
44
45/* Register read/write primitives */
2d6a5e95
DM		 46#define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))
47#define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
394cf0a1
S		 48
49#define SM(_v, _f) (((_v) << _f##_S) & _f)
50#define MS(_v, _f) (((_v) & _f) >> _f##_S)
51#define REG_RMW(_a, _r, _set, _clr) \
52 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
53#define REG_RMW_FIELD(_a, _r, _f, _v) \
54 REG_WRITE(_a, _r, \
55 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
56#define REG_SET_BIT(_a, _r, _f) \
57 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
58#define REG_CLR_BIT(_a, _r, _f) \
59 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 60
394cf0a1
S		 61#define DO_DELAY(x) do { \
62 if ((++(x) % 64) == 0) \
63 udelay(1); \
64 } while (0)
f078f209 65
394cf0a1
S		 66#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
67 int r; \
68 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
69 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
70 INI_RA((iniarray), r, (column))); \
71 DO_DELAY(regWr); \
72 } \
73 } while (0)
f078f209 74
394cf0a1
S		 75#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
76#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
77#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
78#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
79#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
80#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 81
394cf0a1
S		 82#define AR_GPIOD_MASK 0x00001FFF
83#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 84
394cf0a1
S		 85#define BASE_ACTIVATE_DELAY 100
86#define RTC_PLL_SETTLE_DELAY 1000
87#define COEF_SCALE_S 24
88#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 89
394cf0a1
S		 90#define ATH9K_ANTENNA0_CHAINMASK 0x1
91#define ATH9K_ANTENNA1_CHAINMASK 0x2
92
93#define ATH9K_NUM_DMA_DEBUG_REGS 8
94#define ATH9K_NUM_QUEUES 10
95
96#define MAX_RATE_POWER 63
0caa7b14 97#define AH_WAIT_TIMEOUT 100000 /* (us) */
394cf0a1
S		 98#define AH_TIME_QUANTUM 10
99#define AR_KEYTABLE_SIZE 128
100#define POWER_UP_TIME 200000
101#define SPUR_RSSI_THRESH 40
102
103#define CAB_TIMEOUT_VAL 10
104#define BEACON_TIMEOUT_VAL 10
105#define MIN_BEACON_TIMEOUT_VAL 1
106#define SLEEP_SLOP 3
107
108#define INIT_CONFIG_STATUS 0x00000000
109#define INIT_RSSI_THR 0x00000700
110#define INIT_BCON_CNTRL_REG 0x00000000
111
112#define TU_TO_USEC(_tu) ((_tu) << 10)
113
114enum wireless_mode {
115 ATH9K_MODE_11A = 0,
394cf0a1
S		 116 ATH9K_MODE_11G = 3,
117 ATH9K_MODE_11NA_HT20 = 6,
118 ATH9K_MODE_11NG_HT20 = 7,
119 ATH9K_MODE_11NA_HT40PLUS = 8,
120 ATH9K_MODE_11NA_HT40MINUS = 9,
121 ATH9K_MODE_11NG_HT40PLUS = 10,
122 ATH9K_MODE_11NG_HT40MINUS = 11,
123 ATH9K_MODE_MAX
124};
f078f209 125
394cf0a1 126enum ath9k_hw_caps {
bdbdf46d
S		 127 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
128 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
129 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
130 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
131 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
132 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
133 ATH9K_HW_CAP_VEOL = BIT(6),
134 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
135 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
136 ATH9K_HW_CAP_HT = BIT(9),
137 ATH9K_HW_CAP_GTT = BIT(10),
138 ATH9K_HW_CAP_FASTCC = BIT(11),
139 ATH9K_HW_CAP_RFSILENT = BIT(12),
140 ATH9K_HW_CAP_CST = BIT(13),
141 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
142 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
143 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
144 ATH9K_HW_CAP_BT_COEX = BIT(17)
394cf0a1 145};
f078f209 146
394cf0a1
S		 147enum ath9k_capability_type {
148 ATH9K_CAP_CIPHER = 0,
149 ATH9K_CAP_TKIP_MIC,
150 ATH9K_CAP_TKIP_SPLIT,
394cf0a1
S		 151 ATH9K_CAP_DIVERSITY,
152 ATH9K_CAP_TXPOW,
394cf0a1 153 ATH9K_CAP_MCAST_KEYSRCH,
8bd1d07f 154 ATH9K_CAP_DS
394cf0a1 155};
f078f209 156
394cf0a1
S		 157struct ath9k_hw_capabilities {
158 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
159 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
160 u16 total_queues;
161 u16 keycache_size;
162 u16 low_5ghz_chan, high_5ghz_chan;
163 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 164 u16 rts_aggr_limit;
165 u8 tx_chainmask;
166 u8 rx_chainmask;
167 u16 tx_triglevel_max;
168 u16 reg_cap;
169 u8 num_gpio_pins;
170 u8 num_antcfg_2ghz;
171 u8 num_antcfg_5ghz;
172};
f078f209 173
394cf0a1
S		 174struct ath9k_ops_config {
175 int dma_beacon_response_time;
176 int sw_beacon_response_time;
177 int additional_swba_backoff;
178 int ack_6mb;
179 int cwm_ignore_extcca;
180 u8 pcie_powersave_enable;
394cf0a1
S		 181 u8 pcie_clock_req;
182 u32 pcie_waen;
394cf0a1
S		 183 u8 analog_shiftreg;
184 u8 ht_enable;
185 u32 ofdm_trig_low;
186 u32 ofdm_trig_high;
187 u32 cck_trig_high;
188 u32 cck_trig_low;
189 u32 enable_ani;
394cf0a1
S		 190 u16 diversity_control;
191 u16 antenna_switch_swap;
192 int serialize_regmode;
0ef1f168 193 bool intr_mitigation;
394cf0a1
S		 194#define SPUR_DISABLE 0
195#define SPUR_ENABLE_IOCTL 1
196#define SPUR_ENABLE_EEPROM 2
197#define AR_EEPROM_MODAL_SPURS 5
198#define AR_SPUR_5413_1 1640
199#define AR_SPUR_5413_2 1200
200#define AR_NO_SPUR 0x8000
201#define AR_BASE_FREQ_2GHZ 2300
202#define AR_BASE_FREQ_5GHZ 4900
203#define AR_SPUR_FEEQ_BOUND_HT40 19
204#define AR_SPUR_FEEQ_BOUND_HT20 10
205 int spurmode;
206 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
207};
f078f209 208
394cf0a1
S		 209enum ath9k_int {
210 ATH9K_INT_RX = 0x00000001,
211 ATH9K_INT_RXDESC = 0x00000002,
212 ATH9K_INT_RXNOFRM = 0x00000008,
213 ATH9K_INT_RXEOL = 0x00000010,
214 ATH9K_INT_RXORN = 0x00000020,
215 ATH9K_INT_TX = 0x00000040,
216 ATH9K_INT_TXDESC = 0x00000080,
217 ATH9K_INT_TIM_TIMER = 0x00000100,
218 ATH9K_INT_TXURN = 0x00000800,
219 ATH9K_INT_MIB = 0x00001000,
220 ATH9K_INT_RXPHY = 0x00004000,
221 ATH9K_INT_RXKCM = 0x00008000,
222 ATH9K_INT_SWBA = 0x00010000,
223 ATH9K_INT_BMISS = 0x00040000,
224 ATH9K_INT_BNR = 0x00100000,
225 ATH9K_INT_TIM = 0x00200000,
226 ATH9K_INT_DTIM = 0x00400000,
227 ATH9K_INT_DTIMSYNC = 0x00800000,
228 ATH9K_INT_GPIO = 0x01000000,
229 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 230 ATH9K_INT_TSFOOR = 0x04000000,
394cf0a1
S		 231 ATH9K_INT_CST = 0x10000000,
232 ATH9K_INT_GTT = 0x20000000,
233 ATH9K_INT_FATAL = 0x40000000,
234 ATH9K_INT_GLOBAL = 0x80000000,
235 ATH9K_INT_BMISC = ATH9K_INT_TIM |
236 ATH9K_INT_DTIM |
237 ATH9K_INT_DTIMSYNC |
4af9cf4f 238 ATH9K_INT_TSFOOR |
394cf0a1
S		 239 ATH9K_INT_CABEND,
240 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
241 ATH9K_INT_RXDESC |
242 ATH9K_INT_RXEOL |
243 ATH9K_INT_RXORN |
244 ATH9K_INT_TXURN |
245 ATH9K_INT_TXDESC |
246 ATH9K_INT_MIB |
247 ATH9K_INT_RXPHY |
248 ATH9K_INT_RXKCM |
249 ATH9K_INT_SWBA |
250 ATH9K_INT_BMISS |
251 ATH9K_INT_GPIO,
252 ATH9K_INT_NOCARD = 0xffffffff
253};
f078f209 254
394cf0a1
S		 255#define CHANNEL_CW_INT 0x00002
256#define CHANNEL_CCK 0x00020
257#define CHANNEL_OFDM 0x00040
258#define CHANNEL_2GHZ 0x00080
259#define CHANNEL_5GHZ 0x00100
260#define CHANNEL_PASSIVE 0x00200
261#define CHANNEL_DYN 0x00400
262#define CHANNEL_HALF 0x04000
263#define CHANNEL_QUARTER 0x08000
264#define CHANNEL_HT20 0x10000
265#define CHANNEL_HT40PLUS 0x20000
266#define CHANNEL_HT40MINUS 0x40000
267
394cf0a1
S		 268#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
269#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
270#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
271#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
272#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
273#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
274#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
275#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
276#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
277#define CHANNEL_ALL \
278 (CHANNEL_OFDM| \
279 CHANNEL_CCK| \
280 CHANNEL_2GHZ | \
281 CHANNEL_5GHZ | \
282 CHANNEL_HT20 | \
283 CHANNEL_HT40PLUS | \
284 CHANNEL_HT40MINUS)
285
286struct ath9k_channel {
287 struct ieee80211_channel *chan;
288 u16 channel;
289 u32 channelFlags;
290 u32 chanmode;
291 int32_t CalValid;
292 bool oneTimeCalsDone;
293 int8_t iCoff;
294 int8_t qCoff;
295 int16_t rawNoiseFloor;
296};
f078f209 297
394cf0a1
S		 298#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
299 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
300 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
301 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
302#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
303#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
304#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 305#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
306#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
307#define IS_CHAN_A_5MHZ_SPACED(_c) \
308 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
309 (((_c)->channel % 20) != 0) && \
310 (((_c)->channel % 10) != 0))
311
312/* These macros check chanmode and not channelFlags */
313#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
314#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
315 ((_c)->chanmode == CHANNEL_G_HT20))
316#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
317 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
318 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
319 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
320#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
321
322enum ath9k_power_mode {
323 ATH9K_PM_AWAKE = 0,
324 ATH9K_PM_FULL_SLEEP,
325 ATH9K_PM_NETWORK_SLEEP,
326 ATH9K_PM_UNDEFINED
327};
f078f209 328
394cf0a1
S		 329enum ath9k_ant_setting {
330 ATH9K_ANT_VARIABLE = 0,
331 ATH9K_ANT_FIXED_A,
332 ATH9K_ANT_FIXED_B
333};
f078f209 334
394cf0a1
S		 335enum ath9k_tp_scale {
336 ATH9K_TP_SCALE_MAX = 0,
337 ATH9K_TP_SCALE_50,
338 ATH9K_TP_SCALE_25,
339 ATH9K_TP_SCALE_12,
340 ATH9K_TP_SCALE_MIN
341};
f078f209 342
394cf0a1
S		 343enum ser_reg_mode {
344 SER_REG_MODE_OFF = 0,
345 SER_REG_MODE_ON = 1,
346 SER_REG_MODE_AUTO = 2,
347};
f078f209 348
394cf0a1
S		 349struct ath9k_beacon_state {
350 u32 bs_nexttbtt;
351 u32 bs_nextdtim;
352 u32 bs_intval;
353#define ATH9K_BEACON_PERIOD 0x0000ffff
354#define ATH9K_BEACON_ENA 0x00800000
355#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 356#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 357 u32 bs_dtimperiod;
358 u16 bs_cfpperiod;
359 u16 bs_cfpmaxduration;
360 u32 bs_cfpnext;
361 u16 bs_timoffset;
362 u16 bs_bmissthreshold;
363 u32 bs_sleepduration;
4af9cf4f 364 u32 bs_tsfoor_threshold;
394cf0a1 365};
f078f209 366
394cf0a1
S		 367struct chan_centers {
368 u16 synth_center;
369 u16 ctl_center;
370 u16 ext_center;
371};
f078f209 372
394cf0a1
S		 373enum {
374 ATH9K_RESET_POWER_ON,
375 ATH9K_RESET_WARM,
376 ATH9K_RESET_COLD,
377};
f078f209 378
d535a42a
S		 379struct ath9k_hw_version {
380 u32 magic;
381 u16 devid;
382 u16 subvendorid;
383 u32 macVersion;
384 u16 macRev;
385 u16 phyRev;
386 u16 analog5GhzRev;
387 u16 analog2GhzRev;
388};
394cf0a1 389
cbe61d8a 390struct ath_hw {
394cf0a1 391 struct ath_softc *ah_sc;
cbe61d8a 392 struct ath9k_hw_version hw_version;
2660b81a
S		 393 struct ath9k_ops_config config;
394 struct ath9k_hw_capabilities caps;
3a702e49 395 struct ath_regulatory regulatory;
2660b81a
S		 396 struct ath9k_channel channels[38];
397 struct ath9k_channel *curchan;
394cf0a1 398
cbe61d8a
S		 399 union {
400 struct ar5416_eeprom_def def;
401 struct ar5416_eeprom_4k map4k;
2660b81a 402 } eeprom;
f74df6fb 403 const struct eeprom_ops *eep_ops;
2660b81a 404 enum ath9k_eep_map eep_map;
cbe61d8a
S		 405
406 bool sw_mgmt_crypto;
2660b81a 407 bool is_pciexpress;
cbe61d8a 408 u8 macaddr[ETH_ALEN];
2660b81a
S		 409 u16 tx_trig_level;
410 u16 rfsilent;
411 u32 rfkill_gpio;
412 u32 rfkill_polarity;
413 u32 btactive_gpio;
414 u32 wlanactive_gpio;
cbe61d8a 415 u32 ah_flags;
394cf0a1 416
2660b81a
S		 417 enum nl80211_iftype opmode;
418 enum ath9k_power_mode power_mode;
419 enum ath9k_power_mode restore_mode;
f078f209 420
cbe61d8a 421 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
2660b81a
S		 422 struct ar5416Stats stats;
423 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
424
425 int16_t curchan_rad_index;
426 u32 mask_reg;
427 u32 txok_interrupt_mask;
428 u32 txerr_interrupt_mask;
429 u32 txdesc_interrupt_mask;
430 u32 txeol_interrupt_mask;
431 u32 txurn_interrupt_mask;
432 bool chip_fullsleep;
433 u32 atim_window;
434 u16 antenna_switch_swap;
435 enum ath9k_ant_setting diversity_control;
6a2b9e8c
S		 436
437 /* Calibration */
cbfe9468
S		 438 enum ath9k_cal_types supp_cals;
439 struct ath9k_cal_list iq_caldata;
440 struct ath9k_cal_list adcgain_caldata;
441 struct ath9k_cal_list adcdc_calinitdata;
442 struct ath9k_cal_list adcdc_caldata;
443 struct ath9k_cal_list *cal_list;
444 struct ath9k_cal_list *cal_list_last;
445 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 446#define totalPowerMeasI meas0.unsign
447#define totalPowerMeasQ meas1.unsign
448#define totalIqCorrMeas meas2.sign
449#define totalAdcIOddPhase meas0.unsign
450#define totalAdcIEvenPhase meas1.unsign
451#define totalAdcQOddPhase meas2.unsign
452#define totalAdcQEvenPhase meas3.unsign
453#define totalAdcDcOffsetIOddPhase meas0.sign
454#define totalAdcDcOffsetIEvenPhase meas1.sign
455#define totalAdcDcOffsetQOddPhase meas2.sign
456#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 457 union {
458 u32 unsign[AR5416_MAX_CHAINS];
459 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 460 } meas0;
f078f209
LR		 461 union {
462 u32 unsign[AR5416_MAX_CHAINS];
463 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 464 } meas1;
f078f209
LR		 465 union {
466 u32 unsign[AR5416_MAX_CHAINS];
467 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 468 } meas2;
f078f209
LR		 469 union {
470 u32 unsign[AR5416_MAX_CHAINS];
471 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 472 } meas3;
473 u16 cal_samples;
6a2b9e8c 474
2660b81a
S		 475 u32 sta_id1_defaults;
476 u32 misc_mode;
f078f209
LR		 477 enum {
478 AUTO_32KHZ,
479 USE_32KHZ,
480 DONT_USE_32KHZ,
2660b81a 481 } enable_32kHz_clock;
6a2b9e8c
S		 482
483 /* RF */
2660b81a
S		 484 u32 *analogBank0Data;
485 u32 *analogBank1Data;
486 u32 *analogBank2Data;
487 u32 *analogBank3Data;
488 u32 *analogBank6Data;
489 u32 *analogBank6TPCData;
490 u32 *analogBank7Data;
491 u32 *addac5416_21;
492 u32 *bank6Temp;
493
494 int16_t txpower_indexoffset;
495 u32 beacon_interval;
496 u32 slottime;
497 u32 acktimeout;
498 u32 ctstimeout;
499 u32 globaltxtimeout;
500 u8 gbeacon_rate;
6a2b9e8c
S		 501
502 /* ANI */
2660b81a
S		 503 u32 proc_phyerr;
504 bool has_hw_phycounters;
505 u32 aniperiod;
506 struct ar5416AniState *curani;
507 struct ar5416AniState ani[255];
508 int totalSizeDesired[5];
509 int coarse_high[5];
510 int coarse_low[5];
511 int firpwr[5];
512 enum ath9k_ani_cmd ani_function;
513
514 u32 intr_txqs;
2660b81a
S		 515 enum ath9k_ht_extprotspacing extprotspacing;
516 u8 txchainmask;
517 u8 rxchainmask;
518
8bd1d07f
SB		 519 u32 originalGain[22];
520 int initPDADC;
521 int PDADCdelta;
522
2660b81a
S		 523 struct ar5416IniArray iniModes;
524 struct ar5416IniArray iniCommon;
525 struct ar5416IniArray iniBank0;
526 struct ar5416IniArray iniBB_RfGain;
527 struct ar5416IniArray iniBank1;
528 struct ar5416IniArray iniBank2;
529 struct ar5416IniArray iniBank3;
530 struct ar5416IniArray iniBank6;
531 struct ar5416IniArray iniBank6TPC;
532 struct ar5416IniArray iniBank7;
533 struct ar5416IniArray iniAddac;
534 struct ar5416IniArray iniPcieSerdes;
535 struct ar5416IniArray iniModesAdditional;
536 struct ar5416IniArray iniModesRxGain;
537 struct ar5416IniArray iniModesTxGain;
f078f209 538};
f078f209 539
394cf0a1
S		 540/* Attach, Detach, Reset */
541const char *ath9k_hw_probe(u16 vendorid, u16 devid);
cbe61d8a
S		 542void ath9k_hw_detach(struct ath_hw *ah);
543struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error);
544void ath9k_hw_rfdetach(struct ath_hw *ah);
545int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
394cf0a1 546 bool bChannelChange);
eef7a574 547void ath9k_hw_fill_cap_info(struct ath_hw *ah);
cbe61d8a 548bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 549 u32 capability, u32 *result);
cbe61d8a 550bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1
S		 551 u32 capability, u32 setting, int *status);
552
553/* Key Cache Management */
cbe61d8a
S		 554bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
555bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
556bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
394cf0a1 557 const struct ath9k_keyval *k,
e0caf9ea 558 const u8 *mac);
cbe61d8a 559bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
394cf0a1
S		 560
561/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 562void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
563u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
564void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 565 u32 ah_signal_type);
cbe61d8a 566void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 567u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
568void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
569bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
394cf0a1
S		 570 enum ath9k_ant_setting settings,
571 struct ath9k_channel *chan,
572 u8 *tx_chainmask, u8 *rx_chainmask,
573 u8 *antenna_cfgd);
574
575/* General Operation */
0caa7b14 576bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 577u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 578bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3
LR		 579u16 ath9k_hw_computetxtime(struct ath_hw *ah,
580 const struct ath_rate_table *rates,
394cf0a1 581 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 582void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 583 struct ath9k_channel *chan,
584 struct chan_centers *centers);
cbe61d8a
S		 585u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
586void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
587bool ath9k_hw_phy_disable(struct ath_hw *ah);
588bool ath9k_hw_disable(struct ath_hw *ah);
8fbff4b8 589void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
cbe61d8a
S		 590void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
591void ath9k_hw_setopmode(struct ath_hw *ah);
592void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
ba52da58
S		 593void ath9k_hw_setbssidmask(struct ath_softc *sc);
594void ath9k_hw_write_associd(struct ath_softc *sc);
cbe61d8a
S		 595u64 ath9k_hw_gettsf64(struct ath_hw *ah);
596void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
597void ath9k_hw_reset_tsf(struct ath_hw *ah);
598bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
599bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
600void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode);
601void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
602void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 603 const struct ath9k_beacon_state *bs);
cbe61d8a 604bool ath9k_hw_setpower(struct ath_hw *ah,
394cf0a1 605 enum ath9k_power_mode mode);
cbe61d8a 606void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore);
394cf0a1
S		 607
608/* Interrupt Handling */
cbe61d8a
S		 609bool ath9k_hw_intrpend(struct ath_hw *ah);
610bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
611enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah);
612enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
394cf0a1 613
cbe61d8a 614void ath9k_hw_btcoex_enable(struct ath_hw *ah);
f078f209
LR		 615
616#endif
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