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ath9k_hw: Cleanup MCI bits from hw.h
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / hw.h
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
3a702e49 33
394cf0a1 34#define ATHEROS_VENDOR_ID 0x168c
7976b426 35
394cf0a1
S		 36#define AR5416_DEVID_PCI 0x0023
37#define AR5416_DEVID_PCIE 0x0024
38#define AR9160_DEVID_PCI 0x0027
39#define AR9280_DEVID_PCI 0x0029
40#define AR9280_DEVID_PCIE 0x002a
41#define AR9285_DEVID_PCIE 0x002b
5ffaf8a3 42#define AR2427_DEVID_PCIE 0x002c
db3cc53a
SB		 43#define AR9287_DEVID_PCI 0x002d
44#define AR9287_DEVID_PCIE 0x002e
45#define AR9300_DEVID_PCIE 0x0030
b99a7be4 46#define AR9300_DEVID_AR9340 0x0031
3050c914 47#define AR9300_DEVID_AR9485_PCIE 0x0032
5a63ef0f 48#define AR9300_DEVID_AR9580 0x0033
423e38e8 49#define AR9300_DEVID_AR9462 0x0034
03689301 50#define AR9300_DEVID_AR9330 0x0035
7976b426 51
394cf0a1 52#define AR5416_AR9100_DEVID 0x000b
7976b426 53
394cf0a1
S		 54#define AR_SUBVENDOR_ID_NOG 0x0e11
55#define AR_SUBVENDOR_ID_NEW_A 0x7065
56#define AR5416_MAGIC 0x19641014
57
fe12946e
VT		 58#define AR9280_COEX2WIRE_SUBSYSID 0x309b
59#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
60#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
61
e3d01bfc
LR		 62#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
63
cfe8cba9
LR		 64#define ATH_DEFAULT_NOISE_FLOOR -95
65
04658fba 66#define ATH9K_RSSI_BAD -128
990b70ab 67
cac4220b
FF		 68#define ATH9K_NUM_CHANNELS 38
69
394cf0a1 70/* Register read/write primitives */
9e4bffd2 71#define REG_WRITE(_ah, _reg, _val) \
f9f84e96 72 (_ah)->reg_ops.write((_ah), (_val), (_reg))
9e4bffd2
LR		 73
74#define REG_READ(_ah, _reg) \
f9f84e96 75 (_ah)->reg_ops.read((_ah), (_reg))
394cf0a1 76
09a525d3 77#define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
f9f84e96 78 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
09a525d3 79
845e03c9
FF		 80#define REG_RMW(_ah, _reg, _set, _clr) \
81 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
82
20b3efd9
S		 83#define ENABLE_REGWRITE_BUFFER(_ah) \
84 do { \
f9f84e96
FF		 85 if ((_ah)->reg_ops.enable_write_buffer) \
86 (_ah)->reg_ops.enable_write_buffer((_ah)); \
20b3efd9
S		 87 } while (0)
88
20b3efd9
S		 89#define REGWRITE_BUFFER_FLUSH(_ah) \
90 do { \
f9f84e96
FF		 91 if ((_ah)->reg_ops.write_flush) \
92 (_ah)->reg_ops.write_flush((_ah)); \
20b3efd9
S		 93 } while (0)
94
26526202
RM		 95#define PR_EEP(_s, _val) \
96 do { \
97 len += snprintf(buf + len, size - len, "%20s : %10d\n", \
98 _s, (_val)); \
99 } while (0)
100
394cf0a1
S		 101#define SM(_v, _f) (((_v) << _f##_S) & _f)
102#define MS(_v, _f) (((_v) & _f) >> _f##_S)
394cf0a1 103#define REG_RMW_FIELD(_a, _r, _f, _v) \
845e03c9 104 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
1547da37
LR		 105#define REG_READ_FIELD(_a, _r, _f) \
106 (((REG_READ(_a, _r) & _f) >> _f##_S))
394cf0a1 107#define REG_SET_BIT(_a, _r, _f) \
845e03c9 108 REG_RMW(_a, _r, (_f), 0)
394cf0a1 109#define REG_CLR_BIT(_a, _r, _f) \
845e03c9 110 REG_RMW(_a, _r, 0, (_f))
f078f209 111
e7fc6338
RM		 112#define DO_DELAY(x) do { \
113 if (((++(x) % 64) == 0) && \
114 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
115 != ATH_USB)) \
116 udelay(1); \
394cf0a1 117 } while (0)
f078f209 118
a9b6b256
FF		 119#define REG_WRITE_ARRAY(iniarray, column, regWr) \
120 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
f078f209 121
394cf0a1
S		 122#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
123#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
124#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
125#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 126#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 127#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
128#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
93d36e99
MSS		 129#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
130#define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
131#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
132#define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
133#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
134#define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
135#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
136#define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
137#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
138#define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
f078f209 139
394cf0a1
S		 140#define AR_GPIOD_MASK 0x00001FFF
141#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 142
394cf0a1 143#define BASE_ACTIVATE_DELAY 100
0b488ac6 144#define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
394cf0a1
S		 145#define COEF_SCALE_S 24
146#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 147
394cf0a1
S		 148#define ATH9K_ANTENNA0_CHAINMASK 0x1
149#define ATH9K_ANTENNA1_CHAINMASK 0x2
150
151#define ATH9K_NUM_DMA_DEBUG_REGS 8
152#define ATH9K_NUM_QUEUES 10
153
154#define MAX_RATE_POWER 63
0caa7b14 155#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 156#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 157#define AH_TIME_QUANTUM 10
158#define AR_KEYTABLE_SIZE 128
d8caa839 159#define POWER_UP_TIME 10000
394cf0a1 160#define SPUR_RSSI_THRESH 40
331c5ea2
MSS		 161#define UPPER_5G_SUB_BAND_START 5700
162#define MID_5G_SUB_BAND_START 5400
394cf0a1
S		 163
164#define CAB_TIMEOUT_VAL 10
165#define BEACON_TIMEOUT_VAL 10
166#define MIN_BEACON_TIMEOUT_VAL 1
167#define SLEEP_SLOP 3
168
169#define INIT_CONFIG_STATUS 0x00000000
170#define INIT_RSSI_THR 0x00000700
171#define INIT_BCON_CNTRL_REG 0x00000000
172
173#define TU_TO_USEC(_tu) ((_tu) << 10)
174
ceb26445
VT		 175#define ATH9K_HW_RX_HP_QDEPTH 16
176#define ATH9K_HW_RX_LP_QDEPTH 128
177
0e44d48c
MSS		 178#define PAPRD_GAIN_TABLE_ENTRIES 32
179#define PAPRD_TABLE_SZ 24
180#define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
717f6bed 181
066dae93
FF		 182enum ath_hw_txq_subtype {
183 ATH_TXQ_AC_BE = 0,
184 ATH_TXQ_AC_BK = 1,
185 ATH_TXQ_AC_VI = 2,
186 ATH_TXQ_AC_VO = 3,
187};
188
13ce3e99
LR		 189enum ath_ini_subsys {
190 ATH_INI_PRE = 0,
191 ATH_INI_CORE,
192 ATH_INI_POST,
193 ATH_INI_NUM_SPLIT,
194};
195
394cf0a1 196enum ath9k_hw_caps {
364734fa
FF		 197 ATH9K_HW_CAP_HT = BIT(0),
198 ATH9K_HW_CAP_RFSILENT = BIT(1),
1b2538b2
MSS		 199 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
200 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
201 ATH9K_HW_CAP_EDMA = BIT(4),
202 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
203 ATH9K_HW_CAP_LDPC = BIT(6),
204 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
205 ATH9K_HW_CAP_SGI_20 = BIT(8),
206 ATH9K_HW_CAP_PAPRD = BIT(9),
207 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
208 ATH9K_HW_CAP_2GHZ = BIT(11),
209 ATH9K_HW_CAP_5GHZ = BIT(12),
210 ATH9K_HW_CAP_APM = BIT(13),
211 ATH9K_HW_CAP_RTT = BIT(14),
8a309305 212#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1b2538b2 213 ATH9K_HW_CAP_MCI = BIT(15),
8a309305
FF		 214#else
215 ATH9K_HW_CAP_MCI = 0,
216#endif
1b2538b2 217 ATH9K_HW_CAP_DFS = BIT(16),
394cf0a1 218};
f078f209 219
394cf0a1
S		 220struct ath9k_hw_capabilities {
221 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
394cf0a1
S		 222 u16 rts_aggr_limit;
223 u8 tx_chainmask;
224 u8 rx_chainmask;
47c80de6
VT		 225 u8 max_txchains;
226 u8 max_rxchains;
394cf0a1 227 u8 num_gpio_pins;
ceb26445
VT		 228 u8 rx_hp_qdepth;
229 u8 rx_lp_qdepth;
230 u8 rx_status_len;
162c3be3 231 u8 tx_desc_len;
5088c2f1 232 u8 txs_len;
8060e169
VT		 233 u16 pcie_lcr_offset;
234 bool pcie_lcr_extsync_en;
394cf0a1 235};
f078f209 236
394cf0a1
S		 237struct ath9k_ops_config {
238 int dma_beacon_response_time;
239 int sw_beacon_response_time;
240 int additional_swba_backoff;
241 int ack_6mb;
41f3e54d 242 u32 cwm_ignore_extcca;
6a0ec30a 243 bool pcieSerDesWrite;
394cf0a1
S		 244 u8 pcie_clock_req;
245 u32 pcie_waen;
394cf0a1 246 u8 analog_shiftreg;
6f481010 247 u8 paprd_disable;
394cf0a1
S		 248 u32 ofdm_trig_low;
249 u32 ofdm_trig_high;
250 u32 cck_trig_high;
251 u32 cck_trig_low;
252 u32 enable_ani;
394cf0a1 253 int serialize_regmode;
0ce024cb 254 bool rx_intr_mitigation;
55e82df4 255 bool tx_intr_mitigation;
394cf0a1
S		 256#define SPUR_DISABLE 0
257#define SPUR_ENABLE_IOCTL 1
258#define SPUR_ENABLE_EEPROM 2
394cf0a1
S		 259#define AR_SPUR_5413_1 1640
260#define AR_SPUR_5413_2 1200
261#define AR_NO_SPUR 0x8000
262#define AR_BASE_FREQ_2GHZ 2300
263#define AR_BASE_FREQ_5GHZ 4900
264#define AR_SPUR_FEEQ_BOUND_HT40 19
265#define AR_SPUR_FEEQ_BOUND_HT20 10
266 int spurmode;
267 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 268 u8 max_txtrig_level;
e36b27af 269 u16 ani_poll_interval; /* ANI poll interval in ms */
394cf0a1 270};
f078f209 271
394cf0a1
S		 272enum ath9k_int {
273 ATH9K_INT_RX = 0x00000001,
274 ATH9K_INT_RXDESC = 0x00000002,
b5c80475
FF		 275 ATH9K_INT_RXHP = 0x00000001,
276 ATH9K_INT_RXLP = 0x00000002,
394cf0a1
S		 277 ATH9K_INT_RXNOFRM = 0x00000008,
278 ATH9K_INT_RXEOL = 0x00000010,
279 ATH9K_INT_RXORN = 0x00000020,
280 ATH9K_INT_TX = 0x00000040,
281 ATH9K_INT_TXDESC = 0x00000080,
282 ATH9K_INT_TIM_TIMER = 0x00000100,
2ee4bd1e 283 ATH9K_INT_MCI = 0x00000200,
aea702b7 284 ATH9K_INT_BB_WATCHDOG = 0x00000400,
394cf0a1
S		 285 ATH9K_INT_TXURN = 0x00000800,
286 ATH9K_INT_MIB = 0x00001000,
287 ATH9K_INT_RXPHY = 0x00004000,
288 ATH9K_INT_RXKCM = 0x00008000,
289 ATH9K_INT_SWBA = 0x00010000,
290 ATH9K_INT_BMISS = 0x00040000,
291 ATH9K_INT_BNR = 0x00100000,
292 ATH9K_INT_TIM = 0x00200000,
293 ATH9K_INT_DTIM = 0x00400000,
294 ATH9K_INT_DTIMSYNC = 0x00800000,
295 ATH9K_INT_GPIO = 0x01000000,
296 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 297 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 298 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 299 ATH9K_INT_CST = 0x10000000,
300 ATH9K_INT_GTT = 0x20000000,
301 ATH9K_INT_FATAL = 0x40000000,
302 ATH9K_INT_GLOBAL = 0x80000000,
303 ATH9K_INT_BMISC = ATH9K_INT_TIM |
304 ATH9K_INT_DTIM |
305 ATH9K_INT_DTIMSYNC |
4af9cf4f 306 ATH9K_INT_TSFOOR |
394cf0a1
S		 307 ATH9K_INT_CABEND,
308 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
309 ATH9K_INT_RXDESC |
310 ATH9K_INT_RXEOL |
311 ATH9K_INT_RXORN |
312 ATH9K_INT_TXURN |
313 ATH9K_INT_TXDESC |
314 ATH9K_INT_MIB |
315 ATH9K_INT_RXPHY |
316 ATH9K_INT_RXKCM |
317 ATH9K_INT_SWBA |
318 ATH9K_INT_BMISS |
319 ATH9K_INT_GPIO,
320 ATH9K_INT_NOCARD = 0xffffffff
321};
f078f209 322
394cf0a1
S		 323#define CHANNEL_CW_INT 0x00002
324#define CHANNEL_CCK 0x00020
325#define CHANNEL_OFDM 0x00040
326#define CHANNEL_2GHZ 0x00080
327#define CHANNEL_5GHZ 0x00100
328#define CHANNEL_PASSIVE 0x00200
329#define CHANNEL_DYN 0x00400
330#define CHANNEL_HALF 0x04000
331#define CHANNEL_QUARTER 0x08000
332#define CHANNEL_HT20 0x10000
333#define CHANNEL_HT40PLUS 0x20000
334#define CHANNEL_HT40MINUS 0x40000
335
394cf0a1
S		 336#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
337#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
338#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
339#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
340#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
341#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
342#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
343#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
344#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
345#define CHANNEL_ALL \
346 (CHANNEL_OFDM| \
347 CHANNEL_CCK| \
348 CHANNEL_2GHZ | \
349 CHANNEL_5GHZ | \
350 CHANNEL_HT20 | \
351 CHANNEL_HT40PLUS | \
352 CHANNEL_HT40MINUS)
353
324c74ad
RM		 354#define MAX_RTT_TABLE_ENTRY 6
355#define RTT_HIST_MAX 3
356struct ath9k_rtt_hist {
357 u32 table[AR9300_MAX_CHAINS][RTT_HIST_MAX][MAX_RTT_TABLE_ENTRY];
358 u8 num_readings;
359};
360
5f0c04ea 361#define MAX_IQCAL_MEASUREMENT 8
77a5a664 362#define MAX_CL_TAB_ENTRY 16
5f0c04ea 363
20bd2a09 364struct ath9k_hw_cal_data {
394cf0a1
S		 365 u16 channel;
366 u32 channelFlags;
394cf0a1 367 int32_t CalValid;
394cf0a1
S		 368 int8_t iCoff;
369 int8_t qCoff;
717f6bed 370 bool paprd_done;
4254bc1c 371 bool nfcal_pending;
70cf1533 372 bool nfcal_interference;
5f0c04ea 373 bool done_txiqcal_once;
77a5a664 374 bool done_txclcal_once;
717f6bed
FF		 375 u16 small_signal_gain[AR9300_MAX_CHAINS];
376 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
5f0c04ea
RM		 377 u32 num_measures[AR9300_MAX_CHAINS];
378 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
77a5a664 379 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
20bd2a09 380 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
324c74ad 381 struct ath9k_rtt_hist rtt_hist;
20bd2a09
FF		 382};
383
384struct ath9k_channel {
385 struct ieee80211_channel *chan;
093115b7 386 struct ar5416AniState ani;
20bd2a09
FF		 387 u16 channel;
388 u32 channelFlags;
389 u32 chanmode;
d9891c78 390 s16 noisefloor;
394cf0a1 391};
f078f209 392
394cf0a1
S		 393#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
394 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
395 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
396 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
397#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
398#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
399#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 400#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
401#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
6b42e8d0 402#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
394cf0a1 403 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
6b42e8d0 404 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
394cf0a1
S		 405
406/* These macros check chanmode and not channelFlags */
407#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
408#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
409 ((_c)->chanmode == CHANNEL_G_HT20))
410#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
411 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
412 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
413 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
414#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
415
416enum ath9k_power_mode {
417 ATH9K_PM_AWAKE = 0,
418 ATH9K_PM_FULL_SLEEP,
419 ATH9K_PM_NETWORK_SLEEP,
420 ATH9K_PM_UNDEFINED
421};
f078f209 422
394cf0a1
S		 423enum ser_reg_mode {
424 SER_REG_MODE_OFF = 0,
425 SER_REG_MODE_ON = 1,
426 SER_REG_MODE_AUTO = 2,
427};
f078f209 428
ad7b8060
VT		 429enum ath9k_rx_qtype {
430 ATH9K_RX_QUEUE_HP,
431 ATH9K_RX_QUEUE_LP,
432 ATH9K_RX_QUEUE_MAX,
433};
434
394cf0a1
S		 435struct ath9k_beacon_state {
436 u32 bs_nexttbtt;
437 u32 bs_nextdtim;
438 u32 bs_intval;
4af9cf4f 439#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 440 u32 bs_dtimperiod;
441 u16 bs_cfpperiod;
442 u16 bs_cfpmaxduration;
443 u32 bs_cfpnext;
444 u16 bs_timoffset;
445 u16 bs_bmissthreshold;
446 u32 bs_sleepduration;
4af9cf4f 447 u32 bs_tsfoor_threshold;
394cf0a1 448};
f078f209 449
394cf0a1
S		 450struct chan_centers {
451 u16 synth_center;
452 u16 ctl_center;
453 u16 ext_center;
454};
f078f209 455
394cf0a1
S		 456enum {
457 ATH9K_RESET_POWER_ON,
458 ATH9K_RESET_WARM,
459 ATH9K_RESET_COLD,
460};
f078f209 461
d535a42a
S		 462struct ath9k_hw_version {
463 u32 magic;
464 u16 devid;
465 u16 subvendorid;
466 u32 macVersion;
467 u16 macRev;
468 u16 phyRev;
469 u16 analog5GhzRev;
470 u16 analog2GhzRev;
0b5ead91 471 enum ath_usb_dev usbdev;
d535a42a 472};
394cf0a1 473
ff155a45
VT		 474/* Generic TSF timer definitions */
475
476#define ATH_MAX_GEN_TIMER 16
477
478#define AR_GENTMR_BIT(_index) (1 << (_index))
479
480/*
77c2061d 481 * Using de Bruijin sequence to look up 1's index in a 32 bit number
ff155a45
VT		 482 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
483 */
c90017dd 484#define debruijn32 0x077CB531U
ff155a45
VT		 485
486struct ath_gen_timer_configuration {
487 u32 next_addr;
488 u32 period_addr;
489 u32 mode_addr;
490 u32 mode_mask;
491};
492
493struct ath_gen_timer {
494 void (*trigger)(void *arg);
495 void (*overflow)(void *arg);
496 void *arg;
497 u8 index;
498};
499
500struct ath_gen_timer_table {
501 u32 gen_timer_index[32];
502 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
503 union {
504 unsigned long timer_bits;
505 u16 val;
506 } timer_mask;
507};
508
21cc630f
VT		 509struct ath_hw_antcomb_conf {
510 u8 main_lna_conf;
511 u8 alt_lna_conf;
512 u8 fast_div_bias;
c6ba9feb
MSS		 513 u8 main_gaintb;
514 u8 alt_gaintb;
515 int lna1_lna2_delta;
8afbcc8b 516 u8 div_group;
21cc630f
VT		 517};
518
4e8c14e9
FF		 519/**
520 * struct ath_hw_radar_conf - radar detection initialization parameters
521 *
522 * @pulse_inband: threshold for checking the ratio of in-band power
523 * to total power for short radar pulses (half dB steps)
524 * @pulse_inband_step: threshold for checking an in-band power to total
525 * power ratio increase for short radar pulses (half dB steps)
526 * @pulse_height: threshold for detecting the beginning of a short
527 * radar pulse (dB step)
528 * @pulse_rssi: threshold for detecting if a short radar pulse is
529 * gone (dB step)
530 * @pulse_maxlen: maximum pulse length (0.8 us steps)
531 *
532 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
533 * @radar_inband: threshold for checking the ratio of in-band power
534 * to total power for long radar pulses (half dB steps)
535 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
536 *
537 * @ext_channel: enable extension channel radar detection
538 */
539struct ath_hw_radar_conf {
540 unsigned int pulse_inband;
541 unsigned int pulse_inband_step;
542 unsigned int pulse_height;
543 unsigned int pulse_rssi;
544 unsigned int pulse_maxlen;
545
546 unsigned int radar_rssi;
547 unsigned int radar_inband;
548 int fir_power;
549
550 bool ext_channel;
551};
552
d70357d5
LR		 553/**
554 * struct ath_hw_private_ops - callbacks used internally by hardware code
555 *
556 * This structure contains private callbacks designed to only be used internally
557 * by the hardware core.
558 *
795f5e2c
LR		 559 * @init_cal_settings: setup types of calibrations supported
560 * @init_cal: starts actual calibration
561 *
d70357d5 562 * @init_mode_regs: Initializes mode registers
991312d8 563 * @init_mode_gain_regs: Initialize TX/RX gain registers
8fe65368
LR		 564 *
565 * @rf_set_freq: change frequency
566 * @spur_mitigate_freq: spur mitigation
567 * @rf_alloc_ext_banks:
568 * @rf_free_ext_banks:
569 * @set_rf_regs:
64773964
LR		 570 * @compute_pll_control: compute the PLL control value to use for
571 * AR_RTC_PLL_CONTROL for a given channel
795f5e2c
LR		 572 * @setup_calibration: set up calibration
573 * @iscal_supported: used to query if a type of calibration is supported
ac0bb767 574 *
e36b27af
LR		 575 * @ani_cache_ini_regs: cache the values for ANI from the initial
576 * register settings through the register initialization.
d70357d5
LR		 577 */
578struct ath_hw_private_ops {
795f5e2c 579 /* Calibration ops */
d70357d5 580 void (*init_cal_settings)(struct ath_hw *ah);
795f5e2c
LR		 581 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
582
d70357d5 583 void (*init_mode_regs)(struct ath_hw *ah);
991312d8 584 void (*init_mode_gain_regs)(struct ath_hw *ah);
795f5e2c
LR		 585 void (*setup_calibration)(struct ath_hw *ah,
586 struct ath9k_cal_list *currCal);
8fe65368
LR		 587
588 /* PHY ops */
589 int (*rf_set_freq)(struct ath_hw *ah,
590 struct ath9k_channel *chan);
591 void (*spur_mitigate_freq)(struct ath_hw *ah,
592 struct ath9k_channel *chan);
593 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
594 void (*rf_free_ext_banks)(struct ath_hw *ah);
595 bool (*set_rf_regs)(struct ath_hw *ah,
596 struct ath9k_channel *chan,
597 u16 modesIndex);
598 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
599 void (*init_bb)(struct ath_hw *ah,
600 struct ath9k_channel *chan);
601 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
602 void (*olc_init)(struct ath_hw *ah);
603 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
604 void (*mark_phy_inactive)(struct ath_hw *ah);
605 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
606 bool (*rfbus_req)(struct ath_hw *ah);
607 void (*rfbus_done)(struct ath_hw *ah);
8fe65368 608 void (*restore_chainmask)(struct ath_hw *ah);
64773964
LR		 609 u32 (*compute_pll_control)(struct ath_hw *ah,
610 struct ath9k_channel *chan);
c16fcb49
FF		 611 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
612 int param);
641d9921 613 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
4e8c14e9
FF		 614 void (*set_radar_params)(struct ath_hw *ah,
615 struct ath_hw_radar_conf *conf);
5f0c04ea
RM		 616 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
617 u8 *ini_reloaded);
ac0bb767
LR		 618
619 /* ANI */
e36b27af 620 void (*ani_cache_ini_regs)(struct ath_hw *ah);
d70357d5
LR		 621};
622
623/**
624 * struct ath_hw_ops - callbacks used by hardware code and driver code
625 *
626 * This structure contains callbacks designed to to be used internally by
627 * hardware code and also by the lower level driver.
628 *
629 * @config_pci_powersave:
795f5e2c 630 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
d70357d5
LR		 631 */
632struct ath_hw_ops {
633 void (*config_pci_powersave)(struct ath_hw *ah,
84c87dc8 634 bool power_off);
cee1f625 635 void (*rx_enable)(struct ath_hw *ah);
87d5efbb 636 void (*set_desc_link)(void *ds, u32 link);
795f5e2c
LR		 637 bool (*calibrate)(struct ath_hw *ah,
638 struct ath9k_channel *chan,
639 u8 rxchainmask,
640 bool longcal);
55e82df4 641 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
2b63a41d
FF		 642 void (*set_txdesc)(struct ath_hw *ah, void *ds,
643 struct ath_tx_info *i);
cc610ac0
VT		 644 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
645 struct ath_tx_status *ts);
69de3721
MSS		 646 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
647 struct ath_hw_antcomb_conf *antconf);
648 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
649 struct ath_hw_antcomb_conf *antconf);
650
d70357d5
LR		 651};
652
f2552e28
FF		 653struct ath_nf_limits {
654 s16 max;
655 s16 min;
656 s16 nominal;
657};
658
8ad74c4d
RM		 659enum ath_cal_list {
660 TX_IQ_CAL = BIT(0),
661 TX_IQ_ON_AGC_CAL = BIT(1),
662 TX_CL_CAL = BIT(2),
663};
664
97dcec57
SM		 665/* ah_flags */
666#define AH_USE_EEPROM 0x1
667#define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
a126ff51 668#define AH_FASTCC 0x4
97dcec57 669
cbe61d8a 670struct ath_hw {
f9f84e96
FF		 671 struct ath_ops reg_ops;
672
b002a4a9 673 struct ieee80211_hw *hw;
27c51f1a 674 struct ath_common common;
cbe61d8a 675 struct ath9k_hw_version hw_version;
2660b81a
S		 676 struct ath9k_ops_config config;
677 struct ath9k_hw_capabilities caps;
cac4220b 678 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
2660b81a 679 struct ath9k_channel *curchan;
394cf0a1 680
cbe61d8a
S		 681 union {
682 struct ar5416_eeprom_def def;
683 struct ar5416_eeprom_4k map4k;
475f5989 684 struct ar9287_eeprom map9287;
15c9ee7a 685 struct ar9300_eeprom ar9300_eep;
2660b81a 686 } eeprom;
f74df6fb 687 const struct eeprom_ops *eep_ops;
cbe61d8a
S		 688
689 bool sw_mgmt_crypto;
2660b81a 690 bool is_pciexpress;
d4930086 691 bool aspm_enabled;
5f841b41 692 bool is_monitoring;
2eb46d9b 693 bool need_an_top2_fixup;
2660b81a 694 u16 tx_trig_level;
f2552e28 695
bbacee13 696 u32 nf_regs[6];
f2552e28
FF		 697 struct ath_nf_limits nf_2g;
698 struct ath_nf_limits nf_5g;
2660b81a
S		 699 u16 rfsilent;
700 u32 rfkill_gpio;
701 u32 rfkill_polarity;
cbe61d8a 702 u32 ah_flags;
394cf0a1 703
d7e7d229
LR		 704 bool htc_reset_init;
705
2660b81a
S		 706 enum nl80211_iftype opmode;
707 enum ath9k_power_mode power_mode;
f078f209 708
f23fba49 709 s8 noise;
20bd2a09 710 struct ath9k_hw_cal_data *caldata;
a13883b0 711 struct ath9k_pacal_info pacal_info;
2660b81a
S		 712 struct ar5416Stats stats;
713 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
714
715 int16_t curchan_rad_index;
3069168c 716 enum ath9k_int imask;
74bad5cb 717 u32 imrs2_reg;
2660b81a
S		 718 u32 txok_interrupt_mask;
719 u32 txerr_interrupt_mask;
720 u32 txdesc_interrupt_mask;
721 u32 txeol_interrupt_mask;
722 u32 txurn_interrupt_mask;
e8fe7336 723 atomic_t intr_ref_cnt;
2660b81a
S		 724 bool chip_fullsleep;
725 u32 atim_window;
5f0c04ea 726 u32 modes_index;
6a2b9e8c
S		 727
728 /* Calibration */
6497827f 729 u32 supp_cals;
cbfe9468
S		 730 struct ath9k_cal_list iq_caldata;
731 struct ath9k_cal_list adcgain_caldata;
cbfe9468 732 struct ath9k_cal_list adcdc_caldata;
df23acaa 733 struct ath9k_cal_list tempCompCalData;
cbfe9468
S		 734 struct ath9k_cal_list *cal_list;
735 struct ath9k_cal_list *cal_list_last;
736 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 737#define totalPowerMeasI meas0.unsign
738#define totalPowerMeasQ meas1.unsign
739#define totalIqCorrMeas meas2.sign
740#define totalAdcIOddPhase meas0.unsign
741#define totalAdcIEvenPhase meas1.unsign
742#define totalAdcQOddPhase meas2.unsign
743#define totalAdcQEvenPhase meas3.unsign
744#define totalAdcDcOffsetIOddPhase meas0.sign
745#define totalAdcDcOffsetIEvenPhase meas1.sign
746#define totalAdcDcOffsetQOddPhase meas2.sign
747#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 748 union {
749 u32 unsign[AR5416_MAX_CHAINS];
750 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 751 } meas0;
f078f209
LR		 752 union {
753 u32 unsign[AR5416_MAX_CHAINS];
754 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 755 } meas1;
f078f209
LR		 756 union {
757 u32 unsign[AR5416_MAX_CHAINS];
758 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 759 } meas2;
f078f209
LR		 760 union {
761 u32 unsign[AR5416_MAX_CHAINS];
762 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 763 } meas3;
764 u16 cal_samples;
8ad74c4d 765 u8 enabled_cals;
6a2b9e8c 766
2660b81a
S		 767 u32 sta_id1_defaults;
768 u32 misc_mode;
f078f209
LR		 769 enum {
770 AUTO_32KHZ,
771 USE_32KHZ,
772 DONT_USE_32KHZ,
2660b81a 773 } enable_32kHz_clock;
6a2b9e8c 774
d70357d5
LR		 775 /* Private to hardware code */
776 struct ath_hw_private_ops private_ops;
777 /* Accessed by the lower level driver */
778 struct ath_hw_ops ops;
779
e68a060b 780 /* Used to program the radio on non single-chip devices */
2660b81a
S		 781 u32 *analogBank0Data;
782 u32 *analogBank1Data;
783 u32 *analogBank2Data;
784 u32 *analogBank3Data;
785 u32 *analogBank6Data;
786 u32 *analogBank6TPCData;
787 u32 *analogBank7Data;
788 u32 *addac5416_21;
789 u32 *bank6Temp;
790
597a94b3 791 u8 txpower_limit;
e239d859 792 int coverage_class;
2660b81a 793 u32 slottime;
2660b81a 794 u32 globaltxtimeout;
6a2b9e8c
S		 795
796 /* ANI */
2660b81a 797 u32 proc_phyerr;
2660b81a 798 u32 aniperiod;
2660b81a
S		 799 int totalSizeDesired[5];
800 int coarse_high[5];
801 int coarse_low[5];
802 int firpwr[5];
803 enum ath9k_ani_cmd ani_function;
804
af03abec 805 /* Bluetooth coexistance */
766ec4a9 806 struct ath_btcoex_hw btcoex_hw;
af03abec 807
2660b81a 808 u32 intr_txqs;
2660b81a
S		 809 u8 txchainmask;
810 u8 rxchainmask;
811
c5d0855a
FF		 812 struct ath_hw_radar_conf radar_conf;
813
8bd1d07f
SB		 814 u32 originalGain[22];
815 int initPDADC;
816 int PDADCdelta;
6de66dd9 817 int led_pin;
691680b8
FF		 818 u32 gpio_mask;
819 u32 gpio_val;
8bd1d07f 820
2660b81a
S		 821 struct ar5416IniArray iniModes;
822 struct ar5416IniArray iniCommon;
823 struct ar5416IniArray iniBank0;
824 struct ar5416IniArray iniBB_RfGain;
825 struct ar5416IniArray iniBank1;
826 struct ar5416IniArray iniBank2;
827 struct ar5416IniArray iniBank3;
828 struct ar5416IniArray iniBank6;
829 struct ar5416IniArray iniBank6TPC;
830 struct ar5416IniArray iniBank7;
831 struct ar5416IniArray iniAddac;
832 struct ar5416IniArray iniPcieSerdes;
13ce3e99 833 struct ar5416IniArray iniPcieSerdesLowPower;
2660b81a 834 struct ar5416IniArray iniModesAdditional;
d89baac8 835 struct ar5416IniArray iniModesAdditional_40M;
2660b81a
S		 836 struct ar5416IniArray iniModesRxGain;
837 struct ar5416IniArray iniModesTxGain;
8564328d 838 struct ar5416IniArray iniModes_9271_1_0_only;
193cd458
S		 839 struct ar5416IniArray iniCckfirNormal;
840 struct ar5416IniArray iniCckfirJapan2484;
ce407afc 841 struct ar5416IniArray ini_japan2484;
70807e99
S		 842 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
843 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
844 struct ar5416IniArray iniModes_9271_ANI_reg;
845 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
846 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
ce407afc
SB		 847 struct ar5416IniArray ini_radio_post_sys2ant;
848 struct ar5416IniArray ini_BTCOEX_MAX_TXPWR;
ff155a45 849
13ce3e99
LR		 850 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
851 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
852 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
853 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
854
ff155a45
VT		 855 u32 intr_gen_timer_trigger;
856 u32 intr_gen_timer_thresh;
857 struct ath_gen_timer_table hw_gen_timers;
744d4025
VT		 858
859 struct ar9003_txs *ts_ring;
860 void *ts_start;
861 u32 ts_paddr_start;
862 u32 ts_paddr_end;
863 u16 ts_tail;
016c2177 864 u16 ts_size;
aea702b7
LR		 865
866 u32 bb_watchdog_last_status;
867 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
51ac8cbb 868 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
717f6bed 869
1bf38661
FF		 870 unsigned int paprd_target_power;
871 unsigned int paprd_training_power;
7072bf62 872 unsigned int paprd_ratemask;
f1a8abb0 873 unsigned int paprd_ratemask_ht40;
45ef6a0b 874 bool paprd_table_write_done;
717f6bed
FF		 875 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
876 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
9a658d2b
LR		 877 /*
878 * Store the permanent value of Reg 0x4004in WARegVal
879 * so we dont have to R/M/W. We should not be reading
880 * this register when in sleep states.
881 */
882 u32 WARegVal;
6ee63f55
SB		 883
884 /* Enterprise mode cap */
885 u32 ent_mode;
f2f5f2a1
VT		 886
887 bool is_clk_25mhz;
3762561a 888 int (*get_mac_revision)(void);
7d95847c 889 int (*external_reset)(void);
f078f209 890};
f078f209 891
0cb9e06b
FF		 892struct ath_bus_ops {
893 enum ath_bus_type ath_bus_type;
894 void (*read_cachesize)(struct ath_common *common, int *csz);
895 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
896 void (*bt_coex_prep)(struct ath_common *common);
897 void (*extn_synch_en)(struct ath_common *common);
d4930086 898 void (*aspm_init)(struct ath_common *common);
0cb9e06b
FF		 899};
900
9e4bffd2
LR		 901static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
902{
903 return &ah->common;
904}
905
906static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
907{
908 return &(ath9k_hw_common(ah)->regulatory);
909}
910
d70357d5
LR		 911static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
912{
913 return &ah->private_ops;
914}
915
916static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
917{
918 return &ah->ops;
919}
920
895ad7eb
VT		 921static inline u8 get_streams(int mask)
922{
923 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
924}
925
f637cfd6 926/* Initialization, Detach, Reset */
394cf0a1 927const char *ath9k_hw_probe(u16 vendorid, u16 devid);
285f2dda 928void ath9k_hw_deinit(struct ath_hw *ah);
f637cfd6 929int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 930int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 931 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
a9a29ce6 932int ath9k_hw_fill_cap_info(struct ath_hw *ah);
8fe65368 933u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
394cf0a1 934
394cf0a1 935/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 936void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
937u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
938void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 939 u32 ah_signal_type);
cbe61d8a 940void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 941u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
942void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
394cf0a1
S		 943
944/* General Operation */
0caa7b14 945bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
a9b6b256
FF		 946void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
947 int column, unsigned int *writecnt);
394cf0a1 948u32 ath9k_hw_reverse_bits(u32 val, u32 n);
4f0fc7c3 949u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 950 u8 phy, int kbps,
394cf0a1 951 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 952void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 953 struct ath9k_channel *chan,
954 struct chan_centers *centers);
cbe61d8a
S		 955u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
956void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
957bool ath9k_hw_phy_disable(struct ath_hw *ah);
958bool ath9k_hw_disable(struct ath_hw *ah);
de40f316 959void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
cbe61d8a
S		 960void ath9k_hw_setopmode(struct ath_hw *ah);
961void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e 962void ath9k_hw_write_associd(struct ath_hw *ah);
dd347f2f 963u32 ath9k_hw_gettsf32(struct ath_hw *ah);
cbe61d8a
S		 964u64 ath9k_hw_gettsf64(struct ath_hw *ah);
965void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
966void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 967void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
0005baf4 968void ath9k_hw_init_global_settings(struct ath_hw *ah);
b84628eb 969u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
25c56eec 970void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 971void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
972void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 973 const struct ath9k_beacon_state *bs);
c9c99e5e 974bool ath9k_hw_check_alive(struct ath_hw *ah);
a91d75ae 975
9ecdef4b 976bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 977
ff155a45
VT		 978/* Generic hw timer primitives */
979struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
980 void (*trigger)(void *),
981 void (*overflow)(void *),
982 void *arg,
983 u8 timer_index);
cd9bf689
LR		 984void ath9k_hw_gen_timer_start(struct ath_hw *ah,
985 struct ath_gen_timer *timer,
986 u32 timer_next,
987 u32 timer_period);
988void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
989
ff155a45
VT		 990void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
991void ath_gen_timer_isr(struct ath_hw *hw);
992
f934c4d9 993void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 994
05020d23
S		 995/* HTC */
996void ath9k_hw_htc_resetinit(struct ath_hw *ah);
997
8fe65368
LR		 998/* PHY */
999void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1000 u32 *coef_mantissa, u32 *coef_exponent);
ca2c68cc 1001void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan);
8fe65368 1002
ebd5a14a
LR		 1003/*
1004 * Code Specific to AR5008, AR9001 or AR9002,
1005 * we stuff these here to avoid callbacks for AR9003.
1006 */
d8f492b7 1007void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
ebd5a14a 1008int ar9002_hw_rf_claim(struct ath_hw *ah);
78ec2677 1009void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
d8f492b7 1010
641d9921 1011/*
aea702b7 1012 * Code specific to AR9003, we stuff these here to avoid callbacks
641d9921
FF		 1013 * for older families
1014 */
aea702b7
LR		 1015void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1016void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1017void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
51ac8cbb 1018void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
717f6bed
FF		 1019void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1020void ar9003_paprd_populate_single_table(struct ath_hw *ah,
20bd2a09
FF		 1021 struct ath9k_hw_cal_data *caldata,
1022 int chain);
1023int ar9003_paprd_create_curve(struct ath_hw *ah,
1024 struct ath9k_hw_cal_data *caldata, int chain);
717f6bed
FF		 1025int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1026int ar9003_paprd_init_table(struct ath_hw *ah);
1027bool ar9003_paprd_is_done(struct ath_hw *ah);
1028void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
641d9921
FF		 1029
1030/* Hardware family op attach helpers */
8fe65368 1031void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
8525f280
LR		 1032void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1033void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
8fe65368 1034
795f5e2c
LR		 1035void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1036void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1037
b3950e6a
LR		 1038void ar9002_hw_attach_ops(struct ath_hw *ah);
1039void ar9003_hw_attach_ops(struct ath_hw *ah);
1040
c2ba3342 1041void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767
LR		 1042/*
1043 * ANI work can be shared between all families but a next
1044 * generation implementation of ANI will be used only for AR9003 only
1045 * for now as the other families still need to be tested with the same
e36b27af
LR		 1046 * next generation ANI. Feel free to start testing it though for the
1047 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
ac0bb767 1048 */
e36b27af 1049extern int modparam_force_new_ani;
8eb4980c 1050void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
bfc472bb 1051void ath9k_hw_proc_mib_event(struct ath_hw *ah);
95792178 1052void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767 1053
8a309305
FF		 1054#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1055static inline enum ath_btcoex_scheme
1056ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1057{
1058 return ah->btcoex_hw.scheme;
1059}
1060#else
1061#define ath9k_hw_get_btcoex_scheme(...) ATH_BTCOEX_CFG_NONE
1062#endif
1063
73377256
LR		 1064#define ATH9K_CLOCK_RATE_CCK 22
1065#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1066#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1067#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1068
f078f209 1069#endif
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