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55624204 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
55624204 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
516304b0 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
b7f080cf | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
6fb1b1e1 | 21 | #include <linux/ath9k_platform.h> |
9d9779e7 | 22 | #include <linux/module.h> |
5a0e3ad6 | 23 | |
55624204 S |
24 | #include "ath9k.h" |
25 | ||
ab5c4f71 GJ |
26 | struct ath9k_eeprom_ctx { |
27 | struct completion complete; | |
28 | struct ath_hw *ah; | |
29 | }; | |
30 | ||
55624204 S |
31 | static char *dev_info = "ath9k"; |
32 | ||
33 | MODULE_AUTHOR("Atheros Communications"); | |
34 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
35 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
36 | MODULE_LICENSE("Dual BSD/GPL"); | |
37 | ||
38 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
39 | module_param_named(debug, ath9k_debug, uint, 0); | |
40 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
41 | ||
3e6109c5 JL |
42 | int ath9k_modparam_nohwcrypt; |
43 | module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); | |
55624204 S |
44 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); |
45 | ||
93dbbcc4 | 46 | int led_blink; |
9a75c2ff VN |
47 | module_param_named(blink, led_blink, int, 0444); |
48 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); | |
49 | ||
8f5dcb1c VT |
50 | static int ath9k_btcoex_enable; |
51 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
52 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
53 | ||
e09f2dc7 SM |
54 | static int ath9k_enable_diversity; |
55 | module_param_named(enable_diversity, ath9k_enable_diversity, int, 0444); | |
56 | MODULE_PARM_DESC(enable_diversity, "Enable Antenna diversity for AR9565"); | |
57 | ||
d584747b | 58 | bool is_ath9k_unloaded; |
55624204 S |
59 | /* We use the hw_value as an index into our private channel structure */ |
60 | ||
61 | #define CHAN2G(_freq, _idx) { \ | |
b1c1d000 | 62 | .band = IEEE80211_BAND_2GHZ, \ |
55624204 S |
63 | .center_freq = (_freq), \ |
64 | .hw_value = (_idx), \ | |
65 | .max_power = 20, \ | |
66 | } | |
67 | ||
68 | #define CHAN5G(_freq, _idx) { \ | |
69 | .band = IEEE80211_BAND_5GHZ, \ | |
70 | .center_freq = (_freq), \ | |
71 | .hw_value = (_idx), \ | |
72 | .max_power = 20, \ | |
73 | } | |
74 | ||
75 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
76 | * on 5 MHz steps, we support the channels which we know | |
77 | * we have calibration data for all cards though to make | |
78 | * this static */ | |
f209f529 | 79 | static const struct ieee80211_channel ath9k_2ghz_chantable[] = { |
55624204 S |
80 | CHAN2G(2412, 0), /* Channel 1 */ |
81 | CHAN2G(2417, 1), /* Channel 2 */ | |
82 | CHAN2G(2422, 2), /* Channel 3 */ | |
83 | CHAN2G(2427, 3), /* Channel 4 */ | |
84 | CHAN2G(2432, 4), /* Channel 5 */ | |
85 | CHAN2G(2437, 5), /* Channel 6 */ | |
86 | CHAN2G(2442, 6), /* Channel 7 */ | |
87 | CHAN2G(2447, 7), /* Channel 8 */ | |
88 | CHAN2G(2452, 8), /* Channel 9 */ | |
89 | CHAN2G(2457, 9), /* Channel 10 */ | |
90 | CHAN2G(2462, 10), /* Channel 11 */ | |
91 | CHAN2G(2467, 11), /* Channel 12 */ | |
92 | CHAN2G(2472, 12), /* Channel 13 */ | |
93 | CHAN2G(2484, 13), /* Channel 14 */ | |
94 | }; | |
95 | ||
96 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
97 | * on 5 MHz steps, we support the channels which we know | |
98 | * we have calibration data for all cards though to make | |
99 | * this static */ | |
f209f529 | 100 | static const struct ieee80211_channel ath9k_5ghz_chantable[] = { |
55624204 S |
101 | /* _We_ call this UNII 1 */ |
102 | CHAN5G(5180, 14), /* Channel 36 */ | |
103 | CHAN5G(5200, 15), /* Channel 40 */ | |
104 | CHAN5G(5220, 16), /* Channel 44 */ | |
105 | CHAN5G(5240, 17), /* Channel 48 */ | |
106 | /* _We_ call this UNII 2 */ | |
107 | CHAN5G(5260, 18), /* Channel 52 */ | |
108 | CHAN5G(5280, 19), /* Channel 56 */ | |
109 | CHAN5G(5300, 20), /* Channel 60 */ | |
110 | CHAN5G(5320, 21), /* Channel 64 */ | |
111 | /* _We_ call this "Middle band" */ | |
112 | CHAN5G(5500, 22), /* Channel 100 */ | |
113 | CHAN5G(5520, 23), /* Channel 104 */ | |
114 | CHAN5G(5540, 24), /* Channel 108 */ | |
115 | CHAN5G(5560, 25), /* Channel 112 */ | |
116 | CHAN5G(5580, 26), /* Channel 116 */ | |
117 | CHAN5G(5600, 27), /* Channel 120 */ | |
118 | CHAN5G(5620, 28), /* Channel 124 */ | |
119 | CHAN5G(5640, 29), /* Channel 128 */ | |
120 | CHAN5G(5660, 30), /* Channel 132 */ | |
121 | CHAN5G(5680, 31), /* Channel 136 */ | |
122 | CHAN5G(5700, 32), /* Channel 140 */ | |
123 | /* _We_ call this UNII 3 */ | |
124 | CHAN5G(5745, 33), /* Channel 149 */ | |
125 | CHAN5G(5765, 34), /* Channel 153 */ | |
126 | CHAN5G(5785, 35), /* Channel 157 */ | |
127 | CHAN5G(5805, 36), /* Channel 161 */ | |
128 | CHAN5G(5825, 37), /* Channel 165 */ | |
129 | }; | |
130 | ||
131 | /* Atheros hardware rate code addition for short premble */ | |
132 | #define SHPCHECK(__hw_rate, __flags) \ | |
133 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) | |
134 | ||
135 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
136 | .bitrate = (_bitrate), \ | |
137 | .flags = (_flags), \ | |
138 | .hw_value = (_hw_rate), \ | |
139 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
140 | } | |
141 | ||
142 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
143 | RATE(10, 0x1b, 0), | |
144 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), | |
145 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), | |
146 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), | |
147 | RATE(60, 0x0b, 0), | |
148 | RATE(90, 0x0f, 0), | |
149 | RATE(120, 0x0a, 0), | |
150 | RATE(180, 0x0e, 0), | |
151 | RATE(240, 0x09, 0), | |
152 | RATE(360, 0x0d, 0), | |
153 | RATE(480, 0x08, 0), | |
154 | RATE(540, 0x0c, 0), | |
155 | }; | |
156 | ||
0cf55c21 FF |
157 | #ifdef CONFIG_MAC80211_LEDS |
158 | static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { | |
159 | { .throughput = 0 * 1024, .blink_time = 334 }, | |
160 | { .throughput = 1 * 1024, .blink_time = 260 }, | |
161 | { .throughput = 5 * 1024, .blink_time = 220 }, | |
162 | { .throughput = 10 * 1024, .blink_time = 190 }, | |
163 | { .throughput = 20 * 1024, .blink_time = 170 }, | |
164 | { .throughput = 50 * 1024, .blink_time = 150 }, | |
165 | { .throughput = 70 * 1024, .blink_time = 130 }, | |
166 | { .throughput = 100 * 1024, .blink_time = 110 }, | |
167 | { .throughput = 200 * 1024, .blink_time = 80 }, | |
168 | { .throughput = 300 * 1024, .blink_time = 50 }, | |
169 | }; | |
170 | #endif | |
171 | ||
285f2dda | 172 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
173 | |
174 | /* | |
175 | * Read and write, they both share the same lock. We do this to serialize | |
176 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
177 | * as the FIFO on these devices can only accept sanely 2 requests. | |
178 | */ | |
179 | ||
180 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
181 | { | |
182 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
183 | struct ath_common *common = ath9k_hw_common(ah); | |
184 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
185 | ||
f3eef645 | 186 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
187 | unsigned long flags; |
188 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
189 | iowrite32(val, sc->mem + reg_offset); | |
190 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
191 | } else | |
192 | iowrite32(val, sc->mem + reg_offset); | |
193 | } | |
194 | ||
195 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
196 | { | |
197 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
198 | struct ath_common *common = ath9k_hw_common(ah); | |
199 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
200 | u32 val; | |
201 | ||
f3eef645 | 202 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
203 | unsigned long flags; |
204 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
205 | val = ioread32(sc->mem + reg_offset); | |
206 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
207 | } else | |
208 | val = ioread32(sc->mem + reg_offset); | |
209 | return val; | |
210 | } | |
211 | ||
5479de6e RM |
212 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, |
213 | u32 set, u32 clr) | |
214 | { | |
215 | u32 val; | |
216 | ||
217 | val = ioread32(sc->mem + reg_offset); | |
218 | val &= ~clr; | |
219 | val |= set; | |
220 | iowrite32(val, sc->mem + reg_offset); | |
221 | ||
222 | return val; | |
223 | } | |
224 | ||
845e03c9 FF |
225 | static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) |
226 | { | |
227 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
228 | struct ath_common *common = ath9k_hw_common(ah); | |
229 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
230 | unsigned long uninitialized_var(flags); | |
231 | u32 val; | |
232 | ||
f3eef645 | 233 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
845e03c9 | 234 | spin_lock_irqsave(&sc->sc_serial_rw, flags); |
5479de6e | 235 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); |
845e03c9 | 236 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); |
5479de6e RM |
237 | } else |
238 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); | |
845e03c9 FF |
239 | |
240 | return val; | |
241 | } | |
242 | ||
55624204 S |
243 | /**************************/ |
244 | /* Initialization */ | |
245 | /**************************/ | |
246 | ||
247 | static void setup_ht_cap(struct ath_softc *sc, | |
248 | struct ieee80211_sta_ht_cap *ht_info) | |
249 | { | |
3bb065a7 FF |
250 | struct ath_hw *ah = sc->sc_ah; |
251 | struct ath_common *common = ath9k_hw_common(ah); | |
55624204 | 252 | u8 tx_streams, rx_streams; |
3bb065a7 | 253 | int i, max_streams; |
55624204 S |
254 | |
255 | ht_info->ht_supported = true; | |
256 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
257 | IEEE80211_HT_CAP_SM_PS | | |
258 | IEEE80211_HT_CAP_SGI_40 | | |
259 | IEEE80211_HT_CAP_DSSSCCK40; | |
260 | ||
b0a33448 LR |
261 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) |
262 | ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; | |
263 | ||
6473d24d VT |
264 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) |
265 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
266 | ||
55624204 S |
267 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
268 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
269 | ||
e41db61d | 270 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) |
7f1c7a6a | 271 | max_streams = 1; |
e7104195 MSS |
272 | else if (AR_SREV_9462(ah)) |
273 | max_streams = 2; | |
7f1c7a6a | 274 | else if (AR_SREV_9300_20_OR_LATER(ah)) |
3bb065a7 FF |
275 | max_streams = 3; |
276 | else | |
277 | max_streams = 2; | |
278 | ||
7a37081e | 279 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
074a8c0d FF |
280 | if (max_streams >= 2) |
281 | ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; | |
282 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
283 | } | |
284 | ||
55624204 S |
285 | /* set up supported mcs set */ |
286 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
82b2d334 FF |
287 | tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); |
288 | rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); | |
3bb065a7 | 289 | |
d2182b69 | 290 | ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n", |
226afe68 | 291 | tx_streams, rx_streams); |
55624204 S |
292 | |
293 | if (tx_streams != rx_streams) { | |
55624204 S |
294 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
295 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
296 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
297 | } | |
298 | ||
3bb065a7 FF |
299 | for (i = 0; i < rx_streams; i++) |
300 | ht_info->mcs.rx_mask[i] = 0xff; | |
55624204 S |
301 | |
302 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; | |
303 | } | |
304 | ||
0c0280bd LR |
305 | static void ath9k_reg_notifier(struct wiphy *wiphy, |
306 | struct regulatory_request *request) | |
55624204 S |
307 | { |
308 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
9ac58615 | 309 | struct ath_softc *sc = hw->priv; |
687f545e RM |
310 | struct ath_hw *ah = sc->sc_ah; |
311 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
687f545e | 312 | |
0c0280bd | 313 | ath_reg_notifier_apply(wiphy, request, reg); |
687f545e RM |
314 | |
315 | /* Set tx power */ | |
316 | if (ah->curchan) { | |
317 | sc->config.txpowlimit = 2 * ah->curchan->chan->max_power; | |
318 | ath9k_ps_wakeup(sc); | |
319 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); | |
320 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; | |
321 | ath9k_ps_restore(sc); | |
322 | } | |
55624204 S |
323 | } |
324 | ||
325 | /* | |
326 | * This function will allocate both the DMA descriptor structure, and the | |
327 | * buffers it contains. These are used to contain the descriptors used | |
328 | * by the system. | |
329 | */ | |
330 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
331 | struct list_head *head, const char *name, | |
4adfcded | 332 | int nbuf, int ndesc, bool is_tx) |
55624204 | 333 | { |
55624204 | 334 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4adfcded | 335 | u8 *ds; |
55624204 | 336 | struct ath_buf *bf; |
4adfcded | 337 | int i, bsize, error, desc_len; |
55624204 | 338 | |
d2182b69 | 339 | ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
226afe68 | 340 | name, nbuf, ndesc); |
55624204 S |
341 | |
342 | INIT_LIST_HEAD(head); | |
4adfcded VT |
343 | |
344 | if (is_tx) | |
345 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
346 | else | |
347 | desc_len = sizeof(struct ath_desc); | |
348 | ||
55624204 | 349 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 350 | if ((desc_len % 4) != 0) { |
3800276a | 351 | ath_err(common, "ath_desc not DWORD aligned\n"); |
4adfcded | 352 | BUG_ON((desc_len % 4) != 0); |
55624204 S |
353 | error = -ENOMEM; |
354 | goto fail; | |
355 | } | |
356 | ||
4adfcded | 357 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
358 | |
359 | /* | |
360 | * Need additional DMA memory because we can't use | |
361 | * descriptors that cross the 4K page boundary. Assume | |
362 | * one skipped descriptor per 4K page. | |
363 | */ | |
364 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
365 | u32 ndesc_skipped = | |
366 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
367 | u32 dma_len; | |
368 | ||
369 | while (ndesc_skipped) { | |
4adfcded | 370 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
371 | dd->dd_desc_len += dma_len; |
372 | ||
373 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 374 | } |
55624204 S |
375 | } |
376 | ||
377 | /* allocate descriptors */ | |
378 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, | |
379 | &dd->dd_desc_paddr, GFP_KERNEL); | |
380 | if (dd->dd_desc == NULL) { | |
381 | error = -ENOMEM; | |
382 | goto fail; | |
383 | } | |
4adfcded | 384 | ds = (u8 *) dd->dd_desc; |
d2182b69 | 385 | ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
226afe68 JP |
386 | name, ds, (u32) dd->dd_desc_len, |
387 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
55624204 S |
388 | |
389 | /* allocate buffers */ | |
390 | bsize = sizeof(struct ath_buf) * nbuf; | |
391 | bf = kzalloc(bsize, GFP_KERNEL); | |
392 | if (bf == NULL) { | |
393 | error = -ENOMEM; | |
394 | goto fail2; | |
395 | } | |
396 | dd->dd_bufptr = bf; | |
397 | ||
4adfcded | 398 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { |
55624204 S |
399 | bf->bf_desc = ds; |
400 | bf->bf_daddr = DS2PHYS(dd, ds); | |
401 | ||
402 | if (!(sc->sc_ah->caps.hw_caps & | |
403 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
404 | /* | |
405 | * Skip descriptor addresses which can cause 4KB | |
406 | * boundary crossing (addr + length) with a 32 dword | |
407 | * descriptor fetch. | |
408 | */ | |
409 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
410 | BUG_ON((caddr_t) bf->bf_desc >= | |
411 | ((caddr_t) dd->dd_desc + | |
412 | dd->dd_desc_len)); | |
413 | ||
4adfcded | 414 | ds += (desc_len * ndesc); |
55624204 S |
415 | bf->bf_desc = ds; |
416 | bf->bf_daddr = DS2PHYS(dd, ds); | |
417 | } | |
418 | } | |
419 | list_add_tail(&bf->list, head); | |
420 | } | |
421 | return 0; | |
422 | fail2: | |
423 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
424 | dd->dd_desc_paddr); | |
425 | fail: | |
426 | memset(dd, 0, sizeof(*dd)); | |
427 | return error; | |
55624204 S |
428 | } |
429 | ||
285f2dda S |
430 | static int ath9k_init_queues(struct ath_softc *sc) |
431 | { | |
285f2dda S |
432 | int i = 0; |
433 | ||
285f2dda | 434 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 435 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
436 | |
437 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; | |
438 | ath_cabq_update(sc); | |
439 | ||
bea843c7 | 440 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
066dae93 | 441 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); |
60f2d1d5 | 442 | sc->tx.txq_map[i]->mac80211_qnum = i; |
7702e788 | 443 | sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; |
60f2d1d5 | 444 | } |
285f2dda | 445 | return 0; |
285f2dda S |
446 | } |
447 | ||
f209f529 | 448 | static int ath9k_init_channels_rates(struct ath_softc *sc) |
285f2dda | 449 | { |
f209f529 FF |
450 | void *channels; |
451 | ||
cac4220b FF |
452 | BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + |
453 | ARRAY_SIZE(ath9k_5ghz_chantable) != | |
454 | ATH9K_NUM_CHANNELS); | |
455 | ||
d4659912 | 456 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { |
f209f529 FF |
457 | channels = kmemdup(ath9k_2ghz_chantable, |
458 | sizeof(ath9k_2ghz_chantable), GFP_KERNEL); | |
459 | if (!channels) | |
460 | return -ENOMEM; | |
461 | ||
462 | sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; | |
285f2dda S |
463 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; |
464 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
465 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
466 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
467 | sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
468 | ARRAY_SIZE(ath9k_legacy_rates); | |
55624204 S |
469 | } |
470 | ||
d4659912 | 471 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { |
f209f529 FF |
472 | channels = kmemdup(ath9k_5ghz_chantable, |
473 | sizeof(ath9k_5ghz_chantable), GFP_KERNEL); | |
474 | if (!channels) { | |
475 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) | |
476 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
477 | return -ENOMEM; | |
478 | } | |
479 | ||
480 | sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; | |
285f2dda S |
481 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; |
482 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
483 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
484 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
485 | ath9k_legacy_rates + 4; | |
486 | sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
487 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
488 | } | |
f209f529 | 489 | return 0; |
285f2dda | 490 | } |
55624204 | 491 | |
285f2dda S |
492 | static void ath9k_init_misc(struct ath_softc *sc) |
493 | { | |
494 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
495 | int i = 0; | |
3d4e20f2 | 496 | |
285f2dda | 497 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 | 498 | |
aaa1ec46 | 499 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
55624204 | 500 | sc->config.txpowlimit = ATH_TXPOWER_MAX; |
364734fa | 501 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
285f2dda | 502 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 503 | |
7545daf4 | 504 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) |
55624204 | 505 | sc->beacon.bslot[i] = NULL; |
102885a5 VT |
506 | |
507 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
508 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
285f2dda | 509 | } |
55624204 | 510 | |
ab5c4f71 GJ |
511 | static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, |
512 | void *ctx) | |
513 | { | |
514 | struct ath9k_eeprom_ctx *ec = ctx; | |
515 | ||
516 | if (eeprom_blob) | |
517 | ec->ah->eeprom_blob = eeprom_blob; | |
518 | ||
519 | complete(&ec->complete); | |
520 | } | |
521 | ||
522 | static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) | |
523 | { | |
524 | struct ath9k_eeprom_ctx ec; | |
525 | struct ath_hw *ah = ah = sc->sc_ah; | |
526 | int err; | |
527 | ||
528 | /* try to load the EEPROM content asynchronously */ | |
529 | init_completion(&ec.complete); | |
530 | ec.ah = sc->sc_ah; | |
531 | ||
532 | err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, | |
533 | &ec, ath9k_eeprom_request_cb); | |
534 | if (err < 0) { | |
535 | ath_err(ath9k_hw_common(ah), | |
536 | "EEPROM request failed\n"); | |
537 | return err; | |
538 | } | |
539 | ||
540 | wait_for_completion(&ec.complete); | |
541 | ||
542 | if (!ah->eeprom_blob) { | |
543 | ath_err(ath9k_hw_common(ah), | |
544 | "Unable to load EEPROM file %s\n", name); | |
545 | return -EINVAL; | |
546 | } | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
551 | static void ath9k_eeprom_release(struct ath_softc *sc) | |
552 | { | |
553 | release_firmware(sc->sc_ah->eeprom_blob); | |
554 | } | |
555 | ||
eb93e891 | 556 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, |
285f2dda S |
557 | const struct ath_bus_ops *bus_ops) |
558 | { | |
6fb1b1e1 | 559 | struct ath9k_platform_data *pdata = sc->dev->platform_data; |
285f2dda S |
560 | struct ath_hw *ah = NULL; |
561 | struct ath_common *common; | |
562 | int ret = 0, i; | |
563 | int csz = 0; | |
55624204 | 564 | |
285f2dda S |
565 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); |
566 | if (!ah) | |
567 | return -ENOMEM; | |
568 | ||
233536e1 | 569 | ah->hw = sc->hw; |
285f2dda | 570 | ah->hw_version.devid = devid; |
f9f84e96 FF |
571 | ah->reg_ops.read = ath9k_ioread32; |
572 | ah->reg_ops.write = ath9k_iowrite32; | |
845e03c9 | 573 | ah->reg_ops.rmw = ath9k_reg_rmw; |
e8fe7336 | 574 | atomic_set(&ah->intr_ref_cnt, -1); |
285f2dda S |
575 | sc->sc_ah = ah; |
576 | ||
8e92d3f2 ZK |
577 | sc->dfs_detector = dfs_pattern_detector_init(NL80211_DFS_UNSET); |
578 | ||
6de66dd9 | 579 | if (!pdata) { |
a05b5d45 | 580 | ah->ah_flags |= AH_USE_EEPROM; |
6de66dd9 FF |
581 | sc->sc_ah->led_pin = -1; |
582 | } else { | |
583 | sc->sc_ah->gpio_mask = pdata->gpio_mask; | |
584 | sc->sc_ah->gpio_val = pdata->gpio_val; | |
585 | sc->sc_ah->led_pin = pdata->led_pin; | |
f2f5f2a1 | 586 | ah->is_clk_25mhz = pdata->is_clk_25mhz; |
3762561a | 587 | ah->get_mac_revision = pdata->get_mac_revision; |
7d95847c | 588 | ah->external_reset = pdata->external_reset; |
6de66dd9 | 589 | } |
a05b5d45 | 590 | |
285f2dda | 591 | common = ath9k_hw_common(ah); |
f9f84e96 | 592 | common->ops = &ah->reg_ops; |
285f2dda S |
593 | common->bus_ops = bus_ops; |
594 | common->ah = ah; | |
595 | common->hw = sc->hw; | |
596 | common->priv = sc; | |
597 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 598 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
05c0be2f | 599 | common->disable_ani = false; |
e09f2dc7 SM |
600 | |
601 | /* | |
602 | * Enable Antenna diversity only when BTCOEX is disabled | |
603 | * and the user manually requests the feature. | |
604 | */ | |
605 | if (!common->btcoex_enabled && ath9k_enable_diversity) | |
606 | common->antenna_diversity = 1; | |
607 | ||
20b25744 | 608 | spin_lock_init(&common->cc_lock); |
285f2dda | 609 | |
285f2dda S |
610 | spin_lock_init(&sc->sc_serial_rw); |
611 | spin_lock_init(&sc->sc_pm_lock); | |
612 | mutex_init(&sc->mutex); | |
5baec742 FF |
613 | #ifdef CONFIG_ATH9K_MAC_DEBUG |
614 | spin_lock_init(&sc->debug.samp_lock); | |
7f010c93 | 615 | #endif |
285f2dda | 616 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); |
fb6e252f | 617 | tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, |
285f2dda S |
618 | (unsigned long)sc); |
619 | ||
aaa1ec46 SM |
620 | INIT_WORK(&sc->hw_reset_work, ath_reset_work); |
621 | INIT_WORK(&sc->hw_check_work, ath_hw_check); | |
622 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); | |
623 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); | |
624 | setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc); | |
625 | ||
285f2dda S |
626 | /* |
627 | * Cache line size is used to size and align various | |
628 | * structures used to communicate with the hardware. | |
629 | */ | |
630 | ath_read_cachesize(common, &csz); | |
631 | common->cachelsz = csz << 2; /* convert to bytes */ | |
632 | ||
36b07d15 | 633 | if (pdata && pdata->eeprom_name) { |
ab5c4f71 GJ |
634 | ret = ath9k_eeprom_request(sc, pdata->eeprom_name); |
635 | if (ret) | |
636 | goto err_eeprom; | |
637 | } | |
638 | ||
d70357d5 | 639 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 640 | ret = ath9k_hw_init(ah); |
d70357d5 | 641 | if (ret) |
285f2dda | 642 | goto err_hw; |
55624204 | 643 | |
6fb1b1e1 FF |
644 | if (pdata && pdata->macaddr) |
645 | memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); | |
646 | ||
285f2dda S |
647 | ret = ath9k_init_queues(sc); |
648 | if (ret) | |
649 | goto err_queues; | |
650 | ||
651 | ret = ath9k_init_btcoex(sc); | |
652 | if (ret) | |
653 | goto err_btcoex; | |
654 | ||
f209f529 FF |
655 | ret = ath9k_init_channels_rates(sc); |
656 | if (ret) | |
657 | goto err_btcoex; | |
658 | ||
f82b4bde | 659 | ath9k_cmn_init_crypto(sc->sc_ah); |
285f2dda | 660 | ath9k_init_misc(sc); |
8f176a3a | 661 | ath_fill_led_pin(sc); |
285f2dda | 662 | |
d09f5f4c SM |
663 | if (common->bus_ops->aspm_init) |
664 | common->bus_ops->aspm_init(common); | |
665 | ||
55624204 | 666 | return 0; |
285f2dda S |
667 | |
668 | err_btcoex: | |
55624204 S |
669 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
670 | if (ATH_TXQ_SETUP(sc, i)) | |
671 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda | 672 | err_queues: |
285f2dda S |
673 | ath9k_hw_deinit(ah); |
674 | err_hw: | |
ab5c4f71 GJ |
675 | ath9k_eeprom_release(sc); |
676 | err_eeprom: | |
285f2dda S |
677 | kfree(ah); |
678 | sc->sc_ah = NULL; | |
679 | ||
680 | return ret; | |
55624204 S |
681 | } |
682 | ||
babcbc29 FF |
683 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
684 | { | |
685 | struct ieee80211_supported_band *sband; | |
686 | struct ieee80211_channel *chan; | |
687 | struct ath_hw *ah = sc->sc_ah; | |
babcbc29 FF |
688 | int i; |
689 | ||
690 | sband = &sc->sbands[band]; | |
691 | for (i = 0; i < sband->n_channels; i++) { | |
692 | chan = &sband->channels[i]; | |
693 | ah->curchan = &ah->channels[chan->hw_value]; | |
694 | ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20); | |
695 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); | |
babcbc29 FF |
696 | } |
697 | } | |
698 | ||
699 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
700 | { | |
701 | struct ath_hw *ah = sc->sc_ah; | |
702 | struct ath9k_channel *curchan = ah->curchan; | |
703 | ||
704 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
705 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | |
706 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
707 | ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); | |
708 | ||
709 | ah->curchan = curchan; | |
710 | } | |
711 | ||
43c35284 FF |
712 | void ath9k_reload_chainmask_settings(struct ath_softc *sc) |
713 | { | |
714 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)) | |
715 | return; | |
716 | ||
717 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
718 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); | |
719 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
720 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); | |
721 | } | |
722 | ||
20c8e8dc FF |
723 | static const struct ieee80211_iface_limit if_limits[] = { |
724 | { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) | | |
725 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
726 | BIT(NL80211_IFTYPE_WDS) }, | |
727 | { .max = 8, .types = | |
728 | #ifdef CONFIG_MAC80211_MESH | |
729 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
730 | #endif | |
731 | BIT(NL80211_IFTYPE_AP) | | |
732 | BIT(NL80211_IFTYPE_P2P_GO) }, | |
733 | }; | |
734 | ||
735 | static const struct ieee80211_iface_combination if_comb = { | |
736 | .limits = if_limits, | |
737 | .n_limits = ARRAY_SIZE(if_limits), | |
738 | .max_interfaces = 2048, | |
739 | .num_different_channels = 1, | |
aebc0d40 | 740 | .beacon_int_infra_match = true, |
20c8e8dc | 741 | }; |
43c35284 | 742 | |
285f2dda | 743 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 744 | { |
43c35284 FF |
745 | struct ath_hw *ah = sc->sc_ah; |
746 | struct ath_common *common = ath9k_hw_common(ah); | |
285f2dda | 747 | |
55624204 S |
748 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
749 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
750 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 S |
751 | IEEE80211_HW_SUPPORTS_PS | |
752 | IEEE80211_HW_PS_NULLFUNC_STACK | | |
05df4986 | 753 | IEEE80211_HW_SPECTRUM_MGMT | |
bd8027a7 | 754 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; |
55624204 | 755 | |
5ffaf8a3 LR |
756 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
757 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
758 | ||
3e6109c5 | 759 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) |
55624204 S |
760 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; |
761 | ||
762 | hw->wiphy->interface_modes = | |
c426ee24 JB |
763 | BIT(NL80211_IFTYPE_P2P_GO) | |
764 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
55624204 | 765 | BIT(NL80211_IFTYPE_AP) | |
e51f3eff | 766 | BIT(NL80211_IFTYPE_WDS) | |
55624204 S |
767 | BIT(NL80211_IFTYPE_STATION) | |
768 | BIT(NL80211_IFTYPE_ADHOC) | | |
769 | BIT(NL80211_IFTYPE_MESH_POINT); | |
770 | ||
20c8e8dc FF |
771 | hw->wiphy->iface_combinations = &if_comb; |
772 | hw->wiphy->n_iface_combinations = 1; | |
773 | ||
008443de LR |
774 | if (AR_SREV_5416(sc->sc_ah)) |
775 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
55624204 | 776 | |
cfdc9a8b | 777 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; |
fd656234 | 778 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; |
81ddbb5c | 779 | hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; |
cfdc9a8b | 780 | |
9f11e16e MSS |
781 | #ifdef CONFIG_PM_SLEEP |
782 | ||
783 | if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) && | |
784 | device_can_wakeup(sc->dev)) { | |
785 | ||
786 | hw->wiphy->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT | | |
787 | WIPHY_WOWLAN_DISCONNECT; | |
788 | hw->wiphy->wowlan.n_patterns = MAX_NUM_USER_PATTERN; | |
789 | hw->wiphy->wowlan.pattern_min_len = 1; | |
790 | hw->wiphy->wowlan.pattern_max_len = MAX_PATTERN_SIZE; | |
791 | ||
792 | } | |
793 | ||
794 | atomic_set(&sc->wow_sleep_proc_intr, -1); | |
795 | atomic_set(&sc->wow_got_bmiss_intr, -1); | |
796 | ||
797 | #endif | |
798 | ||
55624204 S |
799 | hw->queues = 4; |
800 | hw->max_rates = 4; | |
801 | hw->channel_change_time = 5000; | |
195ca3b1 | 802 | hw->max_listen_interval = 1; |
65896510 | 803 | hw->max_rate_tries = 10; |
55624204 S |
804 | hw->sta_data_size = sizeof(struct ath_node); |
805 | hw->vif_data_size = sizeof(struct ath_vif); | |
806 | ||
43c35284 FF |
807 | hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; |
808 | hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; | |
809 | ||
810 | /* single chain devices with rx diversity */ | |
811 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
812 | hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); | |
813 | ||
814 | sc->ant_rx = hw->wiphy->available_antennas_rx; | |
815 | sc->ant_tx = hw->wiphy->available_antennas_tx; | |
816 | ||
6e5c2b4e | 817 | #ifdef CONFIG_ATH9K_RATE_CONTROL |
55624204 | 818 | hw->rate_control_algorithm = "ath9k_rate_control"; |
6e5c2b4e | 819 | #endif |
55624204 | 820 | |
d4659912 | 821 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
55624204 S |
822 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
823 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
d4659912 | 824 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
55624204 S |
825 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
826 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
285f2dda | 827 | |
43c35284 | 828 | ath9k_reload_chainmask_settings(sc); |
285f2dda S |
829 | |
830 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
831 | } |
832 | ||
eb93e891 | 833 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
55624204 S |
834 | const struct ath_bus_ops *bus_ops) |
835 | { | |
836 | struct ieee80211_hw *hw = sc->hw; | |
837 | struct ath_common *common; | |
838 | struct ath_hw *ah; | |
285f2dda | 839 | int error = 0; |
55624204 S |
840 | struct ath_regulatory *reg; |
841 | ||
285f2dda | 842 | /* Bring up device */ |
eb93e891 | 843 | error = ath9k_init_softc(devid, sc, bus_ops); |
55624204 | 844 | if (error != 0) |
285f2dda | 845 | goto error_init; |
55624204 S |
846 | |
847 | ah = sc->sc_ah; | |
848 | common = ath9k_hw_common(ah); | |
285f2dda | 849 | ath9k_set_hw_capab(sc, hw); |
55624204 | 850 | |
285f2dda | 851 | /* Initialize regulatory */ |
55624204 S |
852 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
853 | ath9k_reg_notifier); | |
854 | if (error) | |
285f2dda | 855 | goto error_regd; |
55624204 S |
856 | |
857 | reg = &common->regulatory; | |
858 | ||
285f2dda | 859 | /* Setup TX DMA */ |
55624204 S |
860 | error = ath_tx_init(sc, ATH_TXBUF); |
861 | if (error != 0) | |
285f2dda | 862 | goto error_tx; |
55624204 | 863 | |
285f2dda | 864 | /* Setup RX DMA */ |
55624204 S |
865 | error = ath_rx_init(sc, ATH_RXBUF); |
866 | if (error != 0) | |
285f2dda | 867 | goto error_rx; |
55624204 | 868 | |
babcbc29 FF |
869 | ath9k_init_txpower_limits(sc); |
870 | ||
0cf55c21 FF |
871 | #ifdef CONFIG_MAC80211_LEDS |
872 | /* must be initialized before ieee80211_register_hw */ | |
873 | sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, | |
874 | IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, | |
875 | ARRAY_SIZE(ath9k_tpt_blink)); | |
876 | #endif | |
877 | ||
285f2dda | 878 | /* Register with mac80211 */ |
55624204 | 879 | error = ieee80211_register_hw(hw); |
285f2dda S |
880 | if (error) |
881 | goto error_register; | |
55624204 | 882 | |
eb272441 BG |
883 | error = ath9k_init_debug(ah); |
884 | if (error) { | |
3800276a | 885 | ath_err(common, "Unable to create debugfs files\n"); |
eb272441 BG |
886 | goto error_world; |
887 | } | |
888 | ||
285f2dda | 889 | /* Handle world regulatory */ |
55624204 S |
890 | if (!ath_is_world_regd(reg)) { |
891 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
892 | if (error) | |
285f2dda | 893 | goto error_world; |
55624204 S |
894 | } |
895 | ||
285f2dda | 896 | ath_init_leds(sc); |
55624204 S |
897 | ath_start_rfkill_poll(sc); |
898 | ||
899 | return 0; | |
900 | ||
285f2dda S |
901 | error_world: |
902 | ieee80211_unregister_hw(hw); | |
903 | error_register: | |
904 | ath_rx_cleanup(sc); | |
905 | error_rx: | |
906 | ath_tx_cleanup(sc); | |
907 | error_tx: | |
908 | /* Nothing */ | |
909 | error_regd: | |
910 | ath9k_deinit_softc(sc); | |
911 | error_init: | |
55624204 S |
912 | return error; |
913 | } | |
914 | ||
915 | /*****************************/ | |
916 | /* De-Initialization */ | |
917 | /*****************************/ | |
918 | ||
285f2dda | 919 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 920 | { |
285f2dda | 921 | int i = 0; |
55624204 | 922 | |
f209f529 FF |
923 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) |
924 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
925 | ||
926 | if (sc->sbands[IEEE80211_BAND_5GHZ].channels) | |
927 | kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels); | |
928 | ||
5908120f | 929 | ath9k_deinit_btcoex(sc); |
19686ddf | 930 | |
285f2dda S |
931 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
932 | if (ATH_TXQ_SETUP(sc, i)) | |
933 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
934 | ||
285f2dda | 935 | ath9k_hw_deinit(sc->sc_ah); |
8e92d3f2 ZK |
936 | if (sc->dfs_detector != NULL) |
937 | sc->dfs_detector->exit(sc->dfs_detector); | |
285f2dda | 938 | |
ab5c4f71 | 939 | ath9k_eeprom_release(sc); |
736b3a27 S |
940 | kfree(sc->sc_ah); |
941 | sc->sc_ah = NULL; | |
55624204 S |
942 | } |
943 | ||
285f2dda | 944 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
945 | { |
946 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
947 | |
948 | ath9k_ps_wakeup(sc); | |
949 | ||
55624204 | 950 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 951 | ath_deinit_leds(sc); |
55624204 | 952 | |
c7c18060 RM |
953 | ath9k_ps_restore(sc); |
954 | ||
55624204 S |
955 | ieee80211_unregister_hw(hw); |
956 | ath_rx_cleanup(sc); | |
957 | ath_tx_cleanup(sc); | |
285f2dda | 958 | ath9k_deinit_softc(sc); |
55624204 S |
959 | } |
960 | ||
961 | void ath_descdma_cleanup(struct ath_softc *sc, | |
962 | struct ath_descdma *dd, | |
963 | struct list_head *head) | |
964 | { | |
965 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
966 | dd->dd_desc_paddr); | |
967 | ||
968 | INIT_LIST_HEAD(head); | |
969 | kfree(dd->dd_bufptr); | |
970 | memset(dd, 0, sizeof(*dd)); | |
971 | } | |
972 | ||
55624204 S |
973 | /************************/ |
974 | /* Module Hooks */ | |
975 | /************************/ | |
976 | ||
977 | static int __init ath9k_init(void) | |
978 | { | |
979 | int error; | |
980 | ||
981 | /* Register rate control algorithm */ | |
982 | error = ath_rate_control_register(); | |
983 | if (error != 0) { | |
516304b0 JP |
984 | pr_err("Unable to register rate control algorithm: %d\n", |
985 | error); | |
55624204 S |
986 | goto err_out; |
987 | } | |
988 | ||
55624204 S |
989 | error = ath_pci_init(); |
990 | if (error < 0) { | |
516304b0 | 991 | pr_err("No PCI devices found, driver not installed\n"); |
55624204 | 992 | error = -ENODEV; |
eb272441 | 993 | goto err_rate_unregister; |
55624204 S |
994 | } |
995 | ||
996 | error = ath_ahb_init(); | |
997 | if (error < 0) { | |
998 | error = -ENODEV; | |
999 | goto err_pci_exit; | |
1000 | } | |
1001 | ||
1002 | return 0; | |
1003 | ||
1004 | err_pci_exit: | |
1005 | ath_pci_exit(); | |
1006 | ||
55624204 S |
1007 | err_rate_unregister: |
1008 | ath_rate_control_unregister(); | |
1009 | err_out: | |
1010 | return error; | |
1011 | } | |
1012 | module_init(ath9k_init); | |
1013 | ||
1014 | static void __exit ath9k_exit(void) | |
1015 | { | |
d584747b | 1016 | is_ath9k_unloaded = true; |
55624204 S |
1017 | ath_ahb_exit(); |
1018 | ath_pci_exit(); | |
55624204 | 1019 | ath_rate_control_unregister(); |
516304b0 | 1020 | pr_info("%s: Driver unloaded\n", dev_info); |
55624204 S |
1021 | } |
1022 | module_exit(ath9k_exit); |