]>
Commit | Line | Data |
---|---|---|
55624204 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
55624204 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
516304b0 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
b7f080cf | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
6fb1b1e1 | 21 | #include <linux/ath9k_platform.h> |
9d9779e7 | 22 | #include <linux/module.h> |
e93d083f | 23 | #include <linux/relay.h> |
b0a1ae97 | 24 | #include <net/ieee80211_radiotap.h> |
5a0e3ad6 | 25 | |
55624204 S |
26 | #include "ath9k.h" |
27 | ||
ab5c4f71 GJ |
28 | struct ath9k_eeprom_ctx { |
29 | struct completion complete; | |
30 | struct ath_hw *ah; | |
31 | }; | |
32 | ||
55624204 S |
33 | static char *dev_info = "ath9k"; |
34 | ||
35 | MODULE_AUTHOR("Atheros Communications"); | |
36 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
37 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
38 | MODULE_LICENSE("Dual BSD/GPL"); | |
39 | ||
40 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
41 | module_param_named(debug, ath9k_debug, uint, 0); | |
42 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
43 | ||
3e6109c5 JL |
44 | int ath9k_modparam_nohwcrypt; |
45 | module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); | |
55624204 S |
46 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); |
47 | ||
93dbbcc4 | 48 | int led_blink; |
9a75c2ff VN |
49 | module_param_named(blink, led_blink, int, 0444); |
50 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); | |
51 | ||
8f5dcb1c VT |
52 | static int ath9k_btcoex_enable; |
53 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
54 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
55 | ||
63081305 SM |
56 | static int ath9k_bt_ant_diversity; |
57 | module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); | |
58 | MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); | |
e09f2dc7 | 59 | |
8298383c SM |
60 | static int ath9k_ps_enable; |
61 | module_param_named(ps_enable, ath9k_ps_enable, int, 0444); | |
62 | MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); | |
63 | ||
499afacc SM |
64 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
65 | ||
78b21949 | 66 | int ath9k_use_chanctx; |
71a5f881 RM |
67 | module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444); |
68 | MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency"); | |
69 | ||
499afacc SM |
70 | #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ |
71 | ||
d584747b | 72 | bool is_ath9k_unloaded; |
55624204 | 73 | |
0cf55c21 FF |
74 | #ifdef CONFIG_MAC80211_LEDS |
75 | static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { | |
76 | { .throughput = 0 * 1024, .blink_time = 334 }, | |
77 | { .throughput = 1 * 1024, .blink_time = 260 }, | |
78 | { .throughput = 5 * 1024, .blink_time = 220 }, | |
79 | { .throughput = 10 * 1024, .blink_time = 190 }, | |
80 | { .throughput = 20 * 1024, .blink_time = 170 }, | |
81 | { .throughput = 50 * 1024, .blink_time = 150 }, | |
82 | { .throughput = 70 * 1024, .blink_time = 130 }, | |
83 | { .throughput = 100 * 1024, .blink_time = 110 }, | |
84 | { .throughput = 200 * 1024, .blink_time = 80 }, | |
85 | { .throughput = 300 * 1024, .blink_time = 50 }, | |
86 | }; | |
87 | #endif | |
88 | ||
285f2dda | 89 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
90 | |
91 | /* | |
92 | * Read and write, they both share the same lock. We do this to serialize | |
93 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
94 | * as the FIFO on these devices can only accept sanely 2 requests. | |
95 | */ | |
96 | ||
97 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
98 | { | |
99 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
100 | struct ath_common *common = ath9k_hw_common(ah); | |
101 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
102 | ||
f3eef645 | 103 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
104 | unsigned long flags; |
105 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
106 | iowrite32(val, sc->mem + reg_offset); | |
107 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
108 | } else | |
109 | iowrite32(val, sc->mem + reg_offset); | |
110 | } | |
111 | ||
112 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
113 | { | |
114 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
115 | struct ath_common *common = ath9k_hw_common(ah); | |
116 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
117 | u32 val; | |
118 | ||
f3eef645 | 119 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
120 | unsigned long flags; |
121 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
122 | val = ioread32(sc->mem + reg_offset); | |
123 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
124 | } else | |
125 | val = ioread32(sc->mem + reg_offset); | |
126 | return val; | |
127 | } | |
128 | ||
5479de6e RM |
129 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, |
130 | u32 set, u32 clr) | |
131 | { | |
132 | u32 val; | |
133 | ||
134 | val = ioread32(sc->mem + reg_offset); | |
135 | val &= ~clr; | |
136 | val |= set; | |
137 | iowrite32(val, sc->mem + reg_offset); | |
138 | ||
139 | return val; | |
140 | } | |
141 | ||
845e03c9 FF |
142 | static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) |
143 | { | |
144 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
145 | struct ath_common *common = ath9k_hw_common(ah); | |
146 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
147 | unsigned long uninitialized_var(flags); | |
148 | u32 val; | |
149 | ||
f3eef645 | 150 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
845e03c9 | 151 | spin_lock_irqsave(&sc->sc_serial_rw, flags); |
5479de6e | 152 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); |
845e03c9 | 153 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); |
5479de6e RM |
154 | } else |
155 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); | |
845e03c9 FF |
156 | |
157 | return val; | |
158 | } | |
159 | ||
55624204 S |
160 | /**************************/ |
161 | /* Initialization */ | |
162 | /**************************/ | |
163 | ||
0c0280bd LR |
164 | static void ath9k_reg_notifier(struct wiphy *wiphy, |
165 | struct regulatory_request *request) | |
55624204 S |
166 | { |
167 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
9ac58615 | 168 | struct ath_softc *sc = hw->priv; |
687f545e RM |
169 | struct ath_hw *ah = sc->sc_ah; |
170 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
687f545e | 171 | |
0c0280bd | 172 | ath_reg_notifier_apply(wiphy, request, reg); |
687f545e RM |
173 | |
174 | /* Set tx power */ | |
175 | if (ah->curchan) { | |
bc7e1be7 | 176 | sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power; |
687f545e | 177 | ath9k_ps_wakeup(sc); |
bc7e1be7 | 178 | ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); |
687f545e | 179 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; |
73e4937d ZK |
180 | /* synchronize DFS detector if regulatory domain changed */ |
181 | if (sc->dfs_detector != NULL) | |
182 | sc->dfs_detector->set_dfs_domain(sc->dfs_detector, | |
183 | request->dfs_region); | |
687f545e RM |
184 | ath9k_ps_restore(sc); |
185 | } | |
55624204 S |
186 | } |
187 | ||
188 | /* | |
189 | * This function will allocate both the DMA descriptor structure, and the | |
190 | * buffers it contains. These are used to contain the descriptors used | |
191 | * by the system. | |
192 | */ | |
193 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
194 | struct list_head *head, const char *name, | |
4adfcded | 195 | int nbuf, int ndesc, bool is_tx) |
55624204 | 196 | { |
55624204 | 197 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4adfcded | 198 | u8 *ds; |
b81950b1 | 199 | int i, bsize, desc_len; |
55624204 | 200 | |
d2182b69 | 201 | ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
226afe68 | 202 | name, nbuf, ndesc); |
55624204 S |
203 | |
204 | INIT_LIST_HEAD(head); | |
4adfcded VT |
205 | |
206 | if (is_tx) | |
207 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
208 | else | |
209 | desc_len = sizeof(struct ath_desc); | |
210 | ||
55624204 | 211 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 212 | if ((desc_len % 4) != 0) { |
3800276a | 213 | ath_err(common, "ath_desc not DWORD aligned\n"); |
4adfcded | 214 | BUG_ON((desc_len % 4) != 0); |
b81950b1 | 215 | return -ENOMEM; |
55624204 S |
216 | } |
217 | ||
4adfcded | 218 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
219 | |
220 | /* | |
221 | * Need additional DMA memory because we can't use | |
222 | * descriptors that cross the 4K page boundary. Assume | |
223 | * one skipped descriptor per 4K page. | |
224 | */ | |
225 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
226 | u32 ndesc_skipped = | |
227 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
228 | u32 dma_len; | |
229 | ||
230 | while (ndesc_skipped) { | |
4adfcded | 231 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
232 | dd->dd_desc_len += dma_len; |
233 | ||
234 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 235 | } |
55624204 S |
236 | } |
237 | ||
238 | /* allocate descriptors */ | |
b81950b1 FF |
239 | dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, |
240 | &dd->dd_desc_paddr, GFP_KERNEL); | |
241 | if (!dd->dd_desc) | |
242 | return -ENOMEM; | |
243 | ||
4adfcded | 244 | ds = (u8 *) dd->dd_desc; |
d2182b69 | 245 | ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
226afe68 JP |
246 | name, ds, (u32) dd->dd_desc_len, |
247 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
55624204 S |
248 | |
249 | /* allocate buffers */ | |
1a04d59d FF |
250 | if (is_tx) { |
251 | struct ath_buf *bf; | |
252 | ||
253 | bsize = sizeof(struct ath_buf) * nbuf; | |
254 | bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); | |
255 | if (!bf) | |
256 | return -ENOMEM; | |
257 | ||
258 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { | |
259 | bf->bf_desc = ds; | |
260 | bf->bf_daddr = DS2PHYS(dd, ds); | |
261 | ||
262 | if (!(sc->sc_ah->caps.hw_caps & | |
263 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
264 | /* | |
265 | * Skip descriptor addresses which can cause 4KB | |
266 | * boundary crossing (addr + length) with a 32 dword | |
267 | * descriptor fetch. | |
268 | */ | |
269 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
270 | BUG_ON((caddr_t) bf->bf_desc >= | |
271 | ((caddr_t) dd->dd_desc + | |
272 | dd->dd_desc_len)); | |
273 | ||
274 | ds += (desc_len * ndesc); | |
275 | bf->bf_desc = ds; | |
276 | bf->bf_daddr = DS2PHYS(dd, ds); | |
277 | } | |
278 | } | |
279 | list_add_tail(&bf->list, head); | |
280 | } | |
281 | } else { | |
282 | struct ath_rxbuf *bf; | |
283 | ||
284 | bsize = sizeof(struct ath_rxbuf) * nbuf; | |
285 | bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); | |
286 | if (!bf) | |
287 | return -ENOMEM; | |
288 | ||
289 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { | |
290 | bf->bf_desc = ds; | |
291 | bf->bf_daddr = DS2PHYS(dd, ds); | |
292 | ||
293 | if (!(sc->sc_ah->caps.hw_caps & | |
294 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
295 | /* | |
296 | * Skip descriptor addresses which can cause 4KB | |
297 | * boundary crossing (addr + length) with a 32 dword | |
298 | * descriptor fetch. | |
299 | */ | |
300 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
301 | BUG_ON((caddr_t) bf->bf_desc >= | |
302 | ((caddr_t) dd->dd_desc + | |
303 | dd->dd_desc_len)); | |
304 | ||
305 | ds += (desc_len * ndesc); | |
306 | bf->bf_desc = ds; | |
307 | bf->bf_daddr = DS2PHYS(dd, ds); | |
308 | } | |
55624204 | 309 | } |
1a04d59d | 310 | list_add_tail(&bf->list, head); |
55624204 | 311 | } |
55624204 S |
312 | } |
313 | return 0; | |
55624204 S |
314 | } |
315 | ||
285f2dda S |
316 | static int ath9k_init_queues(struct ath_softc *sc) |
317 | { | |
285f2dda S |
318 | int i = 0; |
319 | ||
285f2dda | 320 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 321 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
322 | ath_cabq_update(sc); |
323 | ||
f2c7a793 FF |
324 | sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); |
325 | ||
bea843c7 | 326 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
066dae93 | 327 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); |
60f2d1d5 | 328 | sc->tx.txq_map[i]->mac80211_qnum = i; |
7702e788 | 329 | sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; |
60f2d1d5 | 330 | } |
285f2dda | 331 | return 0; |
285f2dda S |
332 | } |
333 | ||
285f2dda S |
334 | static void ath9k_init_misc(struct ath_softc *sc) |
335 | { | |
336 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
337 | int i = 0; | |
3d4e20f2 | 338 | |
285f2dda | 339 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 | 340 | |
32efb0cc | 341 | common->last_rssi = ATH_RSSI_DUMMY_MARKER; |
364734fa | 342 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
285f2dda | 343 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 344 | |
7545daf4 | 345 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) |
55624204 | 346 | sc->beacon.bslot[i] = NULL; |
102885a5 VT |
347 | |
348 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
349 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
04ccd4a1 SW |
350 | |
351 | sc->spec_config.enabled = 0; | |
352 | sc->spec_config.short_repeat = true; | |
353 | sc->spec_config.count = 8; | |
354 | sc->spec_config.endless = false; | |
355 | sc->spec_config.period = 0xFF; | |
356 | sc->spec_config.fft_period = 0xF; | |
285f2dda | 357 | } |
55624204 | 358 | |
0f978bfa | 359 | static void ath9k_init_pcoem_platform(struct ath_softc *sc) |
9b60b64b SM |
360 | { |
361 | struct ath_hw *ah = sc->sc_ah; | |
3f2da955 | 362 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
9b60b64b SM |
363 | struct ath_common *common = ath9k_hw_common(ah); |
364 | ||
365 | if (common->bus_ops->ath_bus_type != ATH_PCI) | |
366 | return; | |
367 | ||
e861ef52 SM |
368 | if (sc->driver_data & (ATH9K_PCI_CUS198 | |
369 | ATH9K_PCI_CUS230)) { | |
9b60b64b SM |
370 | ah->config.xlna_gpio = 9; |
371 | ah->config.xatten_margin_cfg = true; | |
e083a42e | 372 | ah->config.alt_mingainidx = true; |
31fd216d | 373 | ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; |
3afa6b4f SM |
374 | sc->ant_comb.low_rssi_thresh = 20; |
375 | sc->ant_comb.fast_div_bias = 3; | |
9b60b64b | 376 | |
e861ef52 SM |
377 | ath_info(common, "Set parameters for %s\n", |
378 | (sc->driver_data & ATH9K_PCI_CUS198) ? | |
379 | "CUS198" : "CUS230"); | |
3f2da955 SM |
380 | } |
381 | ||
382 | if (sc->driver_data & ATH9K_PCI_CUS217) | |
12eea640 | 383 | ath_info(common, "CUS217 card detected\n"); |
3f2da955 | 384 | |
10631336 SM |
385 | if (sc->driver_data & ATH9K_PCI_CUS252) |
386 | ath_info(common, "CUS252 card detected\n"); | |
387 | ||
3fcdd0a1 SM |
388 | if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) |
389 | ath_info(common, "WB335 1-ANT card detected\n"); | |
390 | ||
391 | if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) | |
392 | ath_info(common, "WB335 2-ANT card detected\n"); | |
393 | ||
4dd35640 SM |
394 | if (sc->driver_data & ATH9K_PCI_KILLER) |
395 | ath_info(common, "Killer Wireless card detected\n"); | |
396 | ||
3fcdd0a1 SM |
397 | /* |
398 | * Some WB335 cards do not support antenna diversity. Since | |
399 | * we use a hardcoded value for AR9565 instead of using the | |
400 | * EEPROM/OTP data, remove the combining feature from | |
401 | * the HW capabilities bitmap. | |
402 | */ | |
403 | if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { | |
404 | if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) | |
405 | pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; | |
406 | } | |
407 | ||
3f2da955 SM |
408 | if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { |
409 | pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; | |
410 | ath_info(common, "Set BT/WLAN RX diversity capability\n"); | |
9b60b64b | 411 | } |
d1ae25a0 SM |
412 | |
413 | if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { | |
414 | ah->config.pcie_waen = 0x0040473b; | |
415 | ath_info(common, "Enable WAR for ASPM D3/L1\n"); | |
416 | } | |
2d22c7dd SM |
417 | |
418 | if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { | |
419 | ah->config.no_pll_pwrsave = true; | |
420 | ath_info(common, "Disable PLL PowerSave\n"); | |
421 | } | |
9b60b64b SM |
422 | } |
423 | ||
ab5c4f71 GJ |
424 | static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, |
425 | void *ctx) | |
426 | { | |
427 | struct ath9k_eeprom_ctx *ec = ctx; | |
428 | ||
429 | if (eeprom_blob) | |
430 | ec->ah->eeprom_blob = eeprom_blob; | |
431 | ||
432 | complete(&ec->complete); | |
433 | } | |
434 | ||
435 | static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) | |
436 | { | |
437 | struct ath9k_eeprom_ctx ec; | |
438 | struct ath_hw *ah = ah = sc->sc_ah; | |
439 | int err; | |
440 | ||
441 | /* try to load the EEPROM content asynchronously */ | |
442 | init_completion(&ec.complete); | |
443 | ec.ah = sc->sc_ah; | |
444 | ||
445 | err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, | |
446 | &ec, ath9k_eeprom_request_cb); | |
447 | if (err < 0) { | |
448 | ath_err(ath9k_hw_common(ah), | |
449 | "EEPROM request failed\n"); | |
450 | return err; | |
451 | } | |
452 | ||
453 | wait_for_completion(&ec.complete); | |
454 | ||
455 | if (!ah->eeprom_blob) { | |
456 | ath_err(ath9k_hw_common(ah), | |
457 | "Unable to load EEPROM file %s\n", name); | |
458 | return -EINVAL; | |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | static void ath9k_eeprom_release(struct ath_softc *sc) | |
465 | { | |
466 | release_firmware(sc->sc_ah->eeprom_blob); | |
467 | } | |
468 | ||
0f978bfa SM |
469 | static int ath9k_init_soc_platform(struct ath_softc *sc) |
470 | { | |
471 | struct ath9k_platform_data *pdata = sc->dev->platform_data; | |
472 | struct ath_hw *ah = sc->sc_ah; | |
473 | int ret = 0; | |
474 | ||
475 | if (!pdata) | |
476 | return 0; | |
477 | ||
478 | if (pdata->eeprom_name) { | |
479 | ret = ath9k_eeprom_request(sc, pdata->eeprom_name); | |
480 | if (ret) | |
481 | return ret; | |
482 | } | |
483 | ||
484 | if (pdata->tx_gain_buffalo) | |
485 | ah->config.tx_gain_buffalo = true; | |
486 | ||
487 | return ret; | |
488 | } | |
489 | ||
eb93e891 | 490 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, |
285f2dda S |
491 | const struct ath_bus_ops *bus_ops) |
492 | { | |
6fb1b1e1 | 493 | struct ath9k_platform_data *pdata = sc->dev->platform_data; |
285f2dda | 494 | struct ath_hw *ah = NULL; |
3f2da955 | 495 | struct ath9k_hw_capabilities *pCap; |
285f2dda S |
496 | struct ath_common *common; |
497 | int ret = 0, i; | |
498 | int csz = 0; | |
55624204 | 499 | |
b81950b1 | 500 | ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); |
285f2dda S |
501 | if (!ah) |
502 | return -ENOMEM; | |
503 | ||
c1b976d2 | 504 | ah->dev = sc->dev; |
233536e1 | 505 | ah->hw = sc->hw; |
285f2dda | 506 | ah->hw_version.devid = devid; |
f9f84e96 FF |
507 | ah->reg_ops.read = ath9k_ioread32; |
508 | ah->reg_ops.write = ath9k_iowrite32; | |
845e03c9 | 509 | ah->reg_ops.rmw = ath9k_reg_rmw; |
285f2dda | 510 | sc->sc_ah = ah; |
3f2da955 | 511 | pCap = &ah->caps; |
285f2dda | 512 | |
95a5992e JD |
513 | common = ath9k_hw_common(ah); |
514 | sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); | |
89f927af | 515 | sc->tx99_power = MAX_RATE_POWER + 1; |
10e23181 | 516 | init_waitqueue_head(&sc->tx_wait); |
ca900ac9 | 517 | sc->cur_chan = &sc->chanctx[0]; |
499afacc | 518 | if (!ath9k_is_chanctx_enabled()) |
3ad9c386 | 519 | sc->cur_chan->hw_queue_base = 0; |
8e92d3f2 | 520 | |
552a5157 | 521 | if (!pdata || pdata->use_eeprom) { |
a05b5d45 | 522 | ah->ah_flags |= AH_USE_EEPROM; |
6de66dd9 FF |
523 | sc->sc_ah->led_pin = -1; |
524 | } else { | |
525 | sc->sc_ah->gpio_mask = pdata->gpio_mask; | |
526 | sc->sc_ah->gpio_val = pdata->gpio_val; | |
527 | sc->sc_ah->led_pin = pdata->led_pin; | |
f2f5f2a1 | 528 | ah->is_clk_25mhz = pdata->is_clk_25mhz; |
3762561a | 529 | ah->get_mac_revision = pdata->get_mac_revision; |
7d95847c | 530 | ah->external_reset = pdata->external_reset; |
6de66dd9 | 531 | } |
a05b5d45 | 532 | |
f9f84e96 | 533 | common->ops = &ah->reg_ops; |
285f2dda S |
534 | common->bus_ops = bus_ops; |
535 | common->ah = ah; | |
536 | common->hw = sc->hw; | |
537 | common->priv = sc; | |
538 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 539 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
05c0be2f | 540 | common->disable_ani = false; |
e09f2dc7 | 541 | |
9b60b64b SM |
542 | /* |
543 | * Platform quirks. | |
544 | */ | |
0f978bfa SM |
545 | ath9k_init_pcoem_platform(sc); |
546 | ||
547 | ret = ath9k_init_soc_platform(sc); | |
548 | if (ret) | |
549 | return ret; | |
9b60b64b | 550 | |
e09f2dc7 | 551 | /* |
3f2da955 SM |
552 | * Enable WLAN/BT RX Antenna diversity only when: |
553 | * | |
7d845871 | 554 | * - BTCOEX is disabled. |
3f2da955 SM |
555 | * - the user manually requests the feature. |
556 | * - the HW cap is set using the platform data. | |
e09f2dc7 | 557 | */ |
7d845871 | 558 | if (!common->btcoex_enabled && ath9k_bt_ant_diversity && |
3f2da955 | 559 | (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) |
63081305 | 560 | common->bt_ant_diversity = 1; |
e09f2dc7 | 561 | |
20b25744 | 562 | spin_lock_init(&common->cc_lock); |
285f2dda S |
563 | spin_lock_init(&sc->sc_serial_rw); |
564 | spin_lock_init(&sc->sc_pm_lock); | |
bff11766 | 565 | spin_lock_init(&sc->chan_lock); |
285f2dda S |
566 | mutex_init(&sc->mutex); |
567 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | |
fb6e252f | 568 | tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, |
285f2dda S |
569 | (unsigned long)sc); |
570 | ||
bf3dac5a | 571 | setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc); |
aaa1ec46 | 572 | INIT_WORK(&sc->hw_reset_work, ath_reset_work); |
aaa1ec46 SM |
573 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); |
574 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); | |
705d0bf8 SM |
575 | |
576 | ath9k_init_channel_context(sc); | |
aaa1ec46 | 577 | |
285f2dda S |
578 | /* |
579 | * Cache line size is used to size and align various | |
580 | * structures used to communicate with the hardware. | |
581 | */ | |
582 | ath_read_cachesize(common, &csz); | |
583 | common->cachelsz = csz << 2; /* convert to bytes */ | |
584 | ||
d70357d5 | 585 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 586 | ret = ath9k_hw_init(ah); |
d70357d5 | 587 | if (ret) |
285f2dda | 588 | goto err_hw; |
55624204 | 589 | |
6fb1b1e1 FF |
590 | if (pdata && pdata->macaddr) |
591 | memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); | |
592 | ||
285f2dda S |
593 | ret = ath9k_init_queues(sc); |
594 | if (ret) | |
595 | goto err_queues; | |
596 | ||
597 | ret = ath9k_init_btcoex(sc); | |
598 | if (ret) | |
599 | goto err_btcoex; | |
600 | ||
13f71050 | 601 | ret = ath9k_cmn_init_channels_rates(common); |
f209f529 FF |
602 | if (ret) |
603 | goto err_btcoex; | |
604 | ||
c7dd40c9 SM |
605 | ret = ath9k_init_p2p(sc); |
606 | if (ret) | |
4f681691 | 607 | goto err_btcoex; |
d463af4a | 608 | |
f82b4bde | 609 | ath9k_cmn_init_crypto(sc->sc_ah); |
285f2dda | 610 | ath9k_init_misc(sc); |
8f176a3a | 611 | ath_fill_led_pin(sc); |
fbbcd146 | 612 | ath_chanctx_init(sc); |
e90e302a | 613 | ath9k_offchannel_init(sc); |
285f2dda | 614 | |
d09f5f4c SM |
615 | if (common->bus_ops->aspm_init) |
616 | common->bus_ops->aspm_init(common); | |
617 | ||
55624204 | 618 | return 0; |
285f2dda S |
619 | |
620 | err_btcoex: | |
55624204 S |
621 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
622 | if (ATH_TXQ_SETUP(sc, i)) | |
623 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda | 624 | err_queues: |
285f2dda S |
625 | ath9k_hw_deinit(ah); |
626 | err_hw: | |
ab5c4f71 | 627 | ath9k_eeprom_release(sc); |
89f927af | 628 | dev_kfree_skb_any(sc->tx99_skb); |
285f2dda | 629 | return ret; |
55624204 S |
630 | } |
631 | ||
babcbc29 FF |
632 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
633 | { | |
634 | struct ieee80211_supported_band *sband; | |
635 | struct ieee80211_channel *chan; | |
636 | struct ath_hw *ah = sc->sc_ah; | |
13f71050 | 637 | struct ath_common *common = ath9k_hw_common(ah); |
0671894f | 638 | struct cfg80211_chan_def chandef; |
babcbc29 FF |
639 | int i; |
640 | ||
13f71050 | 641 | sband = &common->sbands[band]; |
babcbc29 FF |
642 | for (i = 0; i < sband->n_channels; i++) { |
643 | chan = &sband->channels[i]; | |
644 | ah->curchan = &ah->channels[chan->hw_value]; | |
0671894f | 645 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); |
2297f1c7 | 646 | ath9k_cmn_get_channel(sc->hw, ah, &chandef); |
babcbc29 | 647 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); |
babcbc29 FF |
648 | } |
649 | } | |
650 | ||
651 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
652 | { | |
653 | struct ath_hw *ah = sc->sc_ah; | |
654 | struct ath9k_channel *curchan = ah->curchan; | |
655 | ||
656 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
657 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | |
658 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
659 | ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); | |
660 | ||
661 | ah->curchan = curchan; | |
662 | } | |
663 | ||
20c8e8dc | 664 | static const struct ieee80211_iface_limit if_limits[] = { |
71a5f881 | 665 | { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, |
20c8e8dc FF |
666 | { .max = 8, .types = |
667 | #ifdef CONFIG_MAC80211_MESH | |
668 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
669 | #endif | |
95ae4812 FF |
670 | BIT(NL80211_IFTYPE_AP) }, |
671 | { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
20c8e8dc FF |
672 | BIT(NL80211_IFTYPE_P2P_GO) }, |
673 | }; | |
674 | ||
71a5f881 RM |
675 | static const struct ieee80211_iface_limit wds_limits[] = { |
676 | { .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) }, | |
677 | }; | |
678 | ||
499afacc SM |
679 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
680 | ||
a4068323 | 681 | static const struct ieee80211_iface_limit if_limits_multi[] = { |
86162d49 SM |
682 | { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) | |
683 | BIT(NL80211_IFTYPE_AP) | | |
684 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
a4068323 | 685 | BIT(NL80211_IFTYPE_P2P_GO) }, |
86162d49 | 686 | { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) }, |
a4068323 RM |
687 | }; |
688 | ||
a4068323 RM |
689 | static const struct ieee80211_iface_combination if_comb_multi[] = { |
690 | { | |
691 | .limits = if_limits_multi, | |
692 | .n_limits = ARRAY_SIZE(if_limits_multi), | |
693 | .max_interfaces = 2, | |
694 | .num_different_channels = 2, | |
695 | .beacon_int_infra_match = true, | |
696 | }, | |
697 | }; | |
698 | ||
499afacc SM |
699 | #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ |
700 | ||
701 | static const struct ieee80211_iface_limit if_dfs_limits[] = { | |
702 | { .max = 1, .types = BIT(NL80211_IFTYPE_AP) | | |
703 | #ifdef CONFIG_MAC80211_MESH | |
704 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
705 | #endif | |
706 | BIT(NL80211_IFTYPE_ADHOC) }, | |
707 | }; | |
708 | ||
e9cdedf6 ZK |
709 | static const struct ieee80211_iface_combination if_comb[] = { |
710 | { | |
711 | .limits = if_limits, | |
712 | .n_limits = ARRAY_SIZE(if_limits), | |
713 | .max_interfaces = 2048, | |
714 | .num_different_channels = 1, | |
715 | .beacon_int_infra_match = true, | |
716 | }, | |
71a5f881 RM |
717 | { |
718 | .limits = wds_limits, | |
719 | .n_limits = ARRAY_SIZE(wds_limits), | |
720 | .max_interfaces = 2048, | |
721 | .num_different_channels = 1, | |
722 | .beacon_int_infra_match = true, | |
723 | }, | |
4d762480 | 724 | #ifdef CONFIG_ATH9K_DFS_CERTIFIED |
e9cdedf6 ZK |
725 | { |
726 | .limits = if_dfs_limits, | |
727 | .n_limits = ARRAY_SIZE(if_dfs_limits), | |
728 | .max_interfaces = 1, | |
729 | .num_different_channels = 1, | |
730 | .beacon_int_infra_match = true, | |
87eb0167 JD |
731 | .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | |
732 | BIT(NL80211_CHAN_WIDTH_20), | |
e9cdedf6 | 733 | } |
4d762480 | 734 | #endif |
20c8e8dc | 735 | }; |
43c35284 | 736 | |
868caae3 SM |
737 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
738 | static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw) | |
739 | { | |
740 | struct ath_hw *ah = sc->sc_ah; | |
741 | struct ath_common *common = ath9k_hw_common(ah); | |
742 | ||
743 | if (!ath9k_is_chanctx_enabled()) | |
744 | return; | |
745 | ||
746 | hw->flags |= IEEE80211_HW_QUEUE_CONTROL; | |
747 | hw->queues = ATH9K_NUM_TX_QUEUES; | |
748 | hw->offchannel_tx_hw_queue = hw->queues - 1; | |
749 | hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS); | |
750 | hw->wiphy->iface_combinations = if_comb_multi; | |
751 | hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi); | |
752 | hw->wiphy->max_scan_ssids = 255; | |
753 | hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; | |
754 | hw->wiphy->max_remain_on_channel_duration = 10000; | |
755 | hw->chanctx_data_size = sizeof(void *); | |
756 | hw->extra_beacon_tailroom = | |
757 | sizeof(struct ieee80211_p2p_noa_attr) + 9; | |
758 | ||
759 | ath_dbg(common, CHAN_CTX, "Use channel contexts\n"); | |
760 | } | |
761 | #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ | |
762 | ||
7b6ef998 | 763 | static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 764 | { |
43c35284 FF |
765 | struct ath_hw *ah = sc->sc_ah; |
766 | struct ath_common *common = ath9k_hw_common(ah); | |
285f2dda | 767 | |
55624204 S |
768 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
769 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
770 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 | 771 | IEEE80211_HW_PS_NULLFUNC_STACK | |
05df4986 | 772 | IEEE80211_HW_SPECTRUM_MGMT | |
79acac07 | 773 | IEEE80211_HW_REPORTS_TX_ACK_STATUS | |
2dfca312 FF |
774 | IEEE80211_HW_SUPPORTS_RC_TABLE | |
775 | IEEE80211_HW_SUPPORTS_HT_CCK_RATES; | |
55624204 | 776 | |
8298383c SM |
777 | if (ath9k_ps_enable) |
778 | hw->flags |= IEEE80211_HW_SUPPORTS_PS; | |
779 | ||
b0a1ae97 OR |
780 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
781 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
782 | ||
783 | if (AR_SREV_9280_20_OR_LATER(ah)) | |
784 | hw->radiotap_mcs_details |= | |
785 | IEEE80211_RADIOTAP_MCS_HAVE_STBC; | |
786 | } | |
5ffaf8a3 | 787 | |
3e6109c5 | 788 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) |
55624204 S |
789 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; |
790 | ||
fdcf1bd4 SM |
791 | hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR | |
792 | NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | | |
793 | NL80211_FEATURE_P2P_GO_CTWIN; | |
ec26bcc0 | 794 | |
89f927af LR |
795 | if (!config_enabled(CONFIG_ATH9K_TX99)) { |
796 | hw->wiphy->interface_modes = | |
797 | BIT(NL80211_IFTYPE_P2P_GO) | | |
798 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
799 | BIT(NL80211_IFTYPE_AP) | | |
89f927af LR |
800 | BIT(NL80211_IFTYPE_STATION) | |
801 | BIT(NL80211_IFTYPE_ADHOC) | | |
499afacc SM |
802 | BIT(NL80211_IFTYPE_MESH_POINT) | |
803 | BIT(NL80211_IFTYPE_WDS); | |
804 | ||
a4068323 | 805 | hw->wiphy->iface_combinations = if_comb; |
71a5f881 | 806 | hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); |
89f927af | 807 | } |
20c8e8dc | 808 | |
531671cb | 809 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
55624204 | 810 | |
cfdc9a8b | 811 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; |
fd656234 | 812 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; |
81ddbb5c | 813 | hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; |
6fac8bbc | 814 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; |
d074e8d5 | 815 | hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; |
7b4f663e | 816 | hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; |
cfdc9a8b | 817 | |
868caae3 | 818 | hw->queues = 4; |
55624204 | 819 | hw->max_rates = 4; |
5f2f9e44 | 820 | hw->max_listen_interval = 10; |
65896510 | 821 | hw->max_rate_tries = 10; |
55624204 S |
822 | hw->sta_data_size = sizeof(struct ath_node); |
823 | hw->vif_data_size = sizeof(struct ath_vif); | |
824 | ||
43c35284 FF |
825 | hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; |
826 | hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; | |
827 | ||
828 | /* single chain devices with rx diversity */ | |
829 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
830 | hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); | |
831 | ||
832 | sc->ant_rx = hw->wiphy->available_antennas_rx; | |
833 | sc->ant_tx = hw->wiphy->available_antennas_tx; | |
834 | ||
d4659912 | 835 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
55624204 | 836 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
13f71050 | 837 | &common->sbands[IEEE80211_BAND_2GHZ]; |
d4659912 | 838 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
55624204 | 839 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
13f71050 | 840 | &common->sbands[IEEE80211_BAND_5GHZ]; |
285f2dda | 841 | |
868caae3 SM |
842 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
843 | ath9k_set_mcc_capab(sc, hw); | |
844 | #endif | |
babaa80a | 845 | ath9k_init_wow(hw); |
b57ba3b2 | 846 | ath9k_cmn_reload_chainmask(ah); |
285f2dda S |
847 | |
848 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
849 | } |
850 | ||
eb93e891 | 851 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
55624204 S |
852 | const struct ath_bus_ops *bus_ops) |
853 | { | |
854 | struct ieee80211_hw *hw = sc->hw; | |
855 | struct ath_common *common; | |
856 | struct ath_hw *ah; | |
285f2dda | 857 | int error = 0; |
55624204 S |
858 | struct ath_regulatory *reg; |
859 | ||
285f2dda | 860 | /* Bring up device */ |
eb93e891 | 861 | error = ath9k_init_softc(devid, sc, bus_ops); |
b81950b1 FF |
862 | if (error) |
863 | return error; | |
55624204 S |
864 | |
865 | ah = sc->sc_ah; | |
866 | common = ath9k_hw_common(ah); | |
285f2dda | 867 | ath9k_set_hw_capab(sc, hw); |
55624204 | 868 | |
8c7ae357 RM |
869 | /* Will be cleared in ath9k_start() */ |
870 | set_bit(ATH_OP_INVALID, &common->op_flags); | |
871 | ||
285f2dda | 872 | /* Initialize regulatory */ |
55624204 S |
873 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
874 | ath9k_reg_notifier); | |
875 | if (error) | |
b81950b1 | 876 | goto deinit; |
55624204 S |
877 | |
878 | reg = &common->regulatory; | |
879 | ||
285f2dda | 880 | /* Setup TX DMA */ |
55624204 S |
881 | error = ath_tx_init(sc, ATH_TXBUF); |
882 | if (error != 0) | |
b81950b1 | 883 | goto deinit; |
55624204 | 884 | |
285f2dda | 885 | /* Setup RX DMA */ |
55624204 S |
886 | error = ath_rx_init(sc, ATH_RXBUF); |
887 | if (error != 0) | |
b81950b1 | 888 | goto deinit; |
55624204 | 889 | |
babcbc29 FF |
890 | ath9k_init_txpower_limits(sc); |
891 | ||
0cf55c21 FF |
892 | #ifdef CONFIG_MAC80211_LEDS |
893 | /* must be initialized before ieee80211_register_hw */ | |
894 | sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, | |
895 | IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, | |
896 | ARRAY_SIZE(ath9k_tpt_blink)); | |
897 | #endif | |
898 | ||
285f2dda | 899 | /* Register with mac80211 */ |
55624204 | 900 | error = ieee80211_register_hw(hw); |
285f2dda | 901 | if (error) |
b81950b1 | 902 | goto rx_cleanup; |
55624204 | 903 | |
eb272441 BG |
904 | error = ath9k_init_debug(ah); |
905 | if (error) { | |
3800276a | 906 | ath_err(common, "Unable to create debugfs files\n"); |
b81950b1 | 907 | goto unregister; |
eb272441 BG |
908 | } |
909 | ||
285f2dda | 910 | /* Handle world regulatory */ |
55624204 S |
911 | if (!ath_is_world_regd(reg)) { |
912 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
913 | if (error) | |
af690092 | 914 | goto debug_cleanup; |
55624204 S |
915 | } |
916 | ||
285f2dda | 917 | ath_init_leds(sc); |
55624204 S |
918 | ath_start_rfkill_poll(sc); |
919 | ||
920 | return 0; | |
921 | ||
af690092 SM |
922 | debug_cleanup: |
923 | ath9k_deinit_debug(sc); | |
b81950b1 | 924 | unregister: |
285f2dda | 925 | ieee80211_unregister_hw(hw); |
b81950b1 | 926 | rx_cleanup: |
285f2dda | 927 | ath_rx_cleanup(sc); |
b81950b1 | 928 | deinit: |
285f2dda | 929 | ath9k_deinit_softc(sc); |
55624204 S |
930 | return error; |
931 | } | |
932 | ||
933 | /*****************************/ | |
934 | /* De-Initialization */ | |
935 | /*****************************/ | |
936 | ||
285f2dda | 937 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 938 | { |
285f2dda | 939 | int i = 0; |
55624204 | 940 | |
c7dd40c9 | 941 | ath9k_deinit_p2p(sc); |
5908120f | 942 | ath9k_deinit_btcoex(sc); |
19686ddf | 943 | |
285f2dda S |
944 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
945 | if (ATH_TXQ_SETUP(sc, i)) | |
946 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
947 | ||
bf3dac5a | 948 | del_timer_sync(&sc->sleep_timer); |
285f2dda | 949 | ath9k_hw_deinit(sc->sc_ah); |
8e92d3f2 ZK |
950 | if (sc->dfs_detector != NULL) |
951 | sc->dfs_detector->exit(sc->dfs_detector); | |
285f2dda | 952 | |
ab5c4f71 | 953 | ath9k_eeprom_release(sc); |
55624204 S |
954 | } |
955 | ||
285f2dda | 956 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
957 | { |
958 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
959 | |
960 | ath9k_ps_wakeup(sc); | |
961 | ||
55624204 | 962 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 963 | ath_deinit_leds(sc); |
55624204 | 964 | |
c7c18060 RM |
965 | ath9k_ps_restore(sc); |
966 | ||
af690092 | 967 | ath9k_deinit_debug(sc); |
55624204 S |
968 | ieee80211_unregister_hw(hw); |
969 | ath_rx_cleanup(sc); | |
285f2dda | 970 | ath9k_deinit_softc(sc); |
55624204 S |
971 | } |
972 | ||
55624204 S |
973 | /************************/ |
974 | /* Module Hooks */ | |
975 | /************************/ | |
976 | ||
977 | static int __init ath9k_init(void) | |
978 | { | |
979 | int error; | |
980 | ||
55624204 S |
981 | error = ath_pci_init(); |
982 | if (error < 0) { | |
516304b0 | 983 | pr_err("No PCI devices found, driver not installed\n"); |
55624204 | 984 | error = -ENODEV; |
9e495a26 | 985 | goto err_out; |
55624204 S |
986 | } |
987 | ||
988 | error = ath_ahb_init(); | |
989 | if (error < 0) { | |
990 | error = -ENODEV; | |
991 | goto err_pci_exit; | |
992 | } | |
993 | ||
994 | return 0; | |
995 | ||
996 | err_pci_exit: | |
997 | ath_pci_exit(); | |
55624204 S |
998 | err_out: |
999 | return error; | |
1000 | } | |
1001 | module_init(ath9k_init); | |
1002 | ||
1003 | static void __exit ath9k_exit(void) | |
1004 | { | |
d584747b | 1005 | is_ath9k_unloaded = true; |
55624204 S |
1006 | ath_ahb_exit(); |
1007 | ath_pci_exit(); | |
516304b0 | 1008 | pr_info("%s: Driver unloaded\n", dev_info); |
55624204 S |
1009 | } |
1010 | module_exit(ath9k_exit); |