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55624204 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
55624204 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
516304b0 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
b7f080cf | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
6fb1b1e1 | 21 | #include <linux/ath9k_platform.h> |
9d9779e7 | 22 | #include <linux/module.h> |
138b4125 MB |
23 | #include <linux/of.h> |
24 | #include <linux/of_net.h> | |
e93d083f | 25 | #include <linux/relay.h> |
3153b68e | 26 | #include <linux/dmi.h> |
b0a1ae97 | 27 | #include <net/ieee80211_radiotap.h> |
5a0e3ad6 | 28 | |
55624204 S |
29 | #include "ath9k.h" |
30 | ||
ab5c4f71 GJ |
31 | struct ath9k_eeprom_ctx { |
32 | struct completion complete; | |
33 | struct ath_hw *ah; | |
34 | }; | |
35 | ||
55624204 S |
36 | static char *dev_info = "ath9k"; |
37 | ||
38 | MODULE_AUTHOR("Atheros Communications"); | |
39 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
55624204 S |
40 | MODULE_LICENSE("Dual BSD/GPL"); |
41 | ||
42 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
43 | module_param_named(debug, ath9k_debug, uint, 0); | |
44 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
45 | ||
3e6109c5 JL |
46 | int ath9k_modparam_nohwcrypt; |
47 | module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); | |
55624204 S |
48 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); |
49 | ||
0c8a1e43 HX |
50 | int ath9k_led_blink; |
51 | module_param_named(blink, ath9k_led_blink, int, 0444); | |
9a75c2ff VN |
52 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); |
53 | ||
cd84042c VGV |
54 | static int ath9k_led_active_high = -1; |
55 | module_param_named(led_active_high, ath9k_led_active_high, int, 0444); | |
56 | MODULE_PARM_DESC(led_active_high, "Invert LED polarity"); | |
57 | ||
8f5dcb1c VT |
58 | static int ath9k_btcoex_enable; |
59 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
60 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
61 | ||
63081305 SM |
62 | static int ath9k_bt_ant_diversity; |
63 | module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444); | |
64 | MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity"); | |
e09f2dc7 | 65 | |
8298383c SM |
66 | static int ath9k_ps_enable; |
67 | module_param_named(ps_enable, ath9k_ps_enable, int, 0444); | |
68 | MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave"); | |
69 | ||
499afacc SM |
70 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
71 | ||
78b21949 | 72 | int ath9k_use_chanctx; |
71a5f881 RM |
73 | module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444); |
74 | MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency"); | |
75 | ||
499afacc SM |
76 | #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ |
77 | ||
7368160f RH |
78 | int ath9k_use_msi; |
79 | module_param_named(use_msi, ath9k_use_msi, int, 0444); | |
80 | MODULE_PARM_DESC(use_msi, "Use MSI instead of INTx if possible"); | |
81 | ||
d584747b | 82 | bool is_ath9k_unloaded; |
55624204 | 83 | |
0cf55c21 FF |
84 | #ifdef CONFIG_MAC80211_LEDS |
85 | static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { | |
86 | { .throughput = 0 * 1024, .blink_time = 334 }, | |
87 | { .throughput = 1 * 1024, .blink_time = 260 }, | |
88 | { .throughput = 5 * 1024, .blink_time = 220 }, | |
89 | { .throughput = 10 * 1024, .blink_time = 190 }, | |
90 | { .throughput = 20 * 1024, .blink_time = 170 }, | |
91 | { .throughput = 50 * 1024, .blink_time = 150 }, | |
92 | { .throughput = 70 * 1024, .blink_time = 130 }, | |
93 | { .throughput = 100 * 1024, .blink_time = 110 }, | |
94 | { .throughput = 200 * 1024, .blink_time = 80 }, | |
95 | { .throughput = 300 * 1024, .blink_time = 50 }, | |
96 | }; | |
97 | #endif | |
98 | ||
3153b68e AK |
99 | static int __init set_use_msi(const struct dmi_system_id *dmi) |
100 | { | |
101 | ath9k_use_msi = 1; | |
102 | return 1; | |
103 | } | |
104 | ||
105 | static const struct dmi_system_id ath9k_quirks[] __initconst = { | |
106 | { | |
107 | .callback = set_use_msi, | |
108 | .ident = "Dell Inspiron 24-3460", | |
109 | .matches = { | |
110 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
111 | DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 24-3460"), | |
112 | }, | |
113 | }, | |
114 | { | |
115 | .callback = set_use_msi, | |
116 | .ident = "Dell Vostro 3262", | |
117 | .matches = { | |
118 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
119 | DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 3262"), | |
120 | }, | |
121 | }, | |
122 | { | |
123 | .callback = set_use_msi, | |
124 | .ident = "Dell Inspiron 3472", | |
125 | .matches = { | |
126 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
127 | DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 3472"), | |
128 | }, | |
129 | }, | |
130 | { | |
131 | .callback = set_use_msi, | |
132 | .ident = "Dell Vostro 15-3572", | |
133 | .matches = { | |
134 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
135 | DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 15-3572"), | |
136 | }, | |
137 | }, | |
138 | { | |
139 | .callback = set_use_msi, | |
140 | .ident = "Dell Inspiron 14-3473", | |
141 | .matches = { | |
142 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
143 | DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14-3473"), | |
144 | }, | |
145 | }, | |
146 | {} | |
147 | }; | |
148 | ||
285f2dda | 149 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 | 150 | |
d81f9a09 | 151 | static void ath9k_op_ps_wakeup(struct ath_common *common) |
99d2217b OR |
152 | { |
153 | ath9k_ps_wakeup((struct ath_softc *) common->priv); | |
154 | } | |
155 | ||
d81f9a09 | 156 | static void ath9k_op_ps_restore(struct ath_common *common) |
99d2217b OR |
157 | { |
158 | ath9k_ps_restore((struct ath_softc *) common->priv); | |
159 | } | |
160 | ||
3588e111 | 161 | static const struct ath_ps_ops ath9k_ps_ops = { |
99d2217b OR |
162 | .wakeup = ath9k_op_ps_wakeup, |
163 | .restore = ath9k_op_ps_restore, | |
164 | }; | |
165 | ||
55624204 S |
166 | /* |
167 | * Read and write, they both share the same lock. We do this to serialize | |
168 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
169 | * as the FIFO on these devices can only accept sanely 2 requests. | |
170 | */ | |
171 | ||
172 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
173 | { | |
50c8cd44 | 174 | struct ath_hw *ah = hw_priv; |
55624204 S |
175 | struct ath_common *common = ath9k_hw_common(ah); |
176 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
177 | ||
f3eef645 | 178 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
179 | unsigned long flags; |
180 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
181 | iowrite32(val, sc->mem + reg_offset); | |
182 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
183 | } else | |
184 | iowrite32(val, sc->mem + reg_offset); | |
185 | } | |
186 | ||
187 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
188 | { | |
50c8cd44 | 189 | struct ath_hw *ah = hw_priv; |
55624204 S |
190 | struct ath_common *common = ath9k_hw_common(ah); |
191 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
192 | u32 val; | |
193 | ||
f3eef645 | 194 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
195 | unsigned long flags; |
196 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
197 | val = ioread32(sc->mem + reg_offset); | |
198 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
199 | } else | |
200 | val = ioread32(sc->mem + reg_offset); | |
201 | return val; | |
202 | } | |
203 | ||
d55ce0a6 OR |
204 | static void ath9k_multi_ioread32(void *hw_priv, u32 *addr, |
205 | u32 *val, u16 count) | |
206 | { | |
207 | int i; | |
208 | ||
209 | for (i = 0; i < count; i++) | |
210 | val[i] = ath9k_ioread32(hw_priv, addr[i]); | |
211 | } | |
212 | ||
213 | ||
5479de6e RM |
214 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, |
215 | u32 set, u32 clr) | |
216 | { | |
217 | u32 val; | |
218 | ||
219 | val = ioread32(sc->mem + reg_offset); | |
220 | val &= ~clr; | |
221 | val |= set; | |
222 | iowrite32(val, sc->mem + reg_offset); | |
223 | ||
224 | return val; | |
225 | } | |
226 | ||
845e03c9 FF |
227 | static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) |
228 | { | |
50c8cd44 | 229 | struct ath_hw *ah = hw_priv; |
845e03c9 FF |
230 | struct ath_common *common = ath9k_hw_common(ah); |
231 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
3f649ab7 | 232 | unsigned long flags; |
845e03c9 FF |
233 | u32 val; |
234 | ||
f3eef645 | 235 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
845e03c9 | 236 | spin_lock_irqsave(&sc->sc_serial_rw, flags); |
5479de6e | 237 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); |
845e03c9 | 238 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); |
5479de6e RM |
239 | } else |
240 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); | |
845e03c9 FF |
241 | |
242 | return val; | |
243 | } | |
244 | ||
55624204 S |
245 | /**************************/ |
246 | /* Initialization */ | |
247 | /**************************/ | |
248 | ||
0c0280bd LR |
249 | static void ath9k_reg_notifier(struct wiphy *wiphy, |
250 | struct regulatory_request *request) | |
55624204 S |
251 | { |
252 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
9ac58615 | 253 | struct ath_softc *sc = hw->priv; |
687f545e RM |
254 | struct ath_hw *ah = sc->sc_ah; |
255 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
687f545e | 256 | |
0c0280bd | 257 | ath_reg_notifier_apply(wiphy, request, reg); |
687f545e | 258 | |
4415d58c TR |
259 | /* synchronize DFS detector if regulatory domain changed */ |
260 | if (sc->dfs_detector != NULL) | |
261 | sc->dfs_detector->set_dfs_domain(sc->dfs_detector, | |
262 | request->dfs_region); | |
263 | ||
687f545e | 264 | /* Set tx power */ |
d385c5c2 FF |
265 | if (!ah->curchan) |
266 | return; | |
267 | ||
268 | sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power; | |
269 | ath9k_ps_wakeup(sc); | |
270 | ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); | |
271 | ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower, | |
272 | sc->cur_chan->txpower, | |
273 | &sc->cur_chan->cur_txpower); | |
d385c5c2 | 274 | ath9k_ps_restore(sc); |
55624204 S |
275 | } |
276 | ||
277 | /* | |
278 | * This function will allocate both the DMA descriptor structure, and the | |
279 | * buffers it contains. These are used to contain the descriptors used | |
280 | * by the system. | |
281 | */ | |
282 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
283 | struct list_head *head, const char *name, | |
4adfcded | 284 | int nbuf, int ndesc, bool is_tx) |
55624204 | 285 | { |
55624204 | 286 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4adfcded | 287 | u8 *ds; |
b81950b1 | 288 | int i, bsize, desc_len; |
55624204 | 289 | |
d2182b69 | 290 | ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
226afe68 | 291 | name, nbuf, ndesc); |
55624204 S |
292 | |
293 | INIT_LIST_HEAD(head); | |
4adfcded VT |
294 | |
295 | if (is_tx) | |
296 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
297 | else | |
298 | desc_len = sizeof(struct ath_desc); | |
299 | ||
55624204 | 300 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 301 | if ((desc_len % 4) != 0) { |
3800276a | 302 | ath_err(common, "ath_desc not DWORD aligned\n"); |
4adfcded | 303 | BUG_ON((desc_len % 4) != 0); |
b81950b1 | 304 | return -ENOMEM; |
55624204 S |
305 | } |
306 | ||
4adfcded | 307 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
308 | |
309 | /* | |
310 | * Need additional DMA memory because we can't use | |
311 | * descriptors that cross the 4K page boundary. Assume | |
312 | * one skipped descriptor per 4K page. | |
313 | */ | |
314 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
315 | u32 ndesc_skipped = | |
316 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
317 | u32 dma_len; | |
318 | ||
319 | while (ndesc_skipped) { | |
4adfcded | 320 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
321 | dd->dd_desc_len += dma_len; |
322 | ||
323 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 324 | } |
55624204 S |
325 | } |
326 | ||
327 | /* allocate descriptors */ | |
b81950b1 FF |
328 | dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, |
329 | &dd->dd_desc_paddr, GFP_KERNEL); | |
330 | if (!dd->dd_desc) | |
331 | return -ENOMEM; | |
332 | ||
50c8cd44 | 333 | ds = dd->dd_desc; |
d2182b69 | 334 | ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
226afe68 JP |
335 | name, ds, (u32) dd->dd_desc_len, |
336 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
55624204 S |
337 | |
338 | /* allocate buffers */ | |
1a04d59d FF |
339 | if (is_tx) { |
340 | struct ath_buf *bf; | |
341 | ||
342 | bsize = sizeof(struct ath_buf) * nbuf; | |
343 | bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); | |
344 | if (!bf) | |
345 | return -ENOMEM; | |
346 | ||
347 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { | |
348 | bf->bf_desc = ds; | |
349 | bf->bf_daddr = DS2PHYS(dd, ds); | |
350 | ||
351 | if (!(sc->sc_ah->caps.hw_caps & | |
352 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
353 | /* | |
354 | * Skip descriptor addresses which can cause 4KB | |
355 | * boundary crossing (addr + length) with a 32 dword | |
356 | * descriptor fetch. | |
357 | */ | |
358 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
359 | BUG_ON((caddr_t) bf->bf_desc >= | |
360 | ((caddr_t) dd->dd_desc + | |
361 | dd->dd_desc_len)); | |
362 | ||
363 | ds += (desc_len * ndesc); | |
364 | bf->bf_desc = ds; | |
365 | bf->bf_daddr = DS2PHYS(dd, ds); | |
366 | } | |
367 | } | |
368 | list_add_tail(&bf->list, head); | |
369 | } | |
370 | } else { | |
371 | struct ath_rxbuf *bf; | |
372 | ||
373 | bsize = sizeof(struct ath_rxbuf) * nbuf; | |
374 | bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL); | |
375 | if (!bf) | |
376 | return -ENOMEM; | |
377 | ||
378 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { | |
379 | bf->bf_desc = ds; | |
380 | bf->bf_daddr = DS2PHYS(dd, ds); | |
381 | ||
382 | if (!(sc->sc_ah->caps.hw_caps & | |
383 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
384 | /* | |
385 | * Skip descriptor addresses which can cause 4KB | |
386 | * boundary crossing (addr + length) with a 32 dword | |
387 | * descriptor fetch. | |
388 | */ | |
389 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
390 | BUG_ON((caddr_t) bf->bf_desc >= | |
391 | ((caddr_t) dd->dd_desc + | |
392 | dd->dd_desc_len)); | |
393 | ||
394 | ds += (desc_len * ndesc); | |
395 | bf->bf_desc = ds; | |
396 | bf->bf_daddr = DS2PHYS(dd, ds); | |
397 | } | |
55624204 | 398 | } |
1a04d59d | 399 | list_add_tail(&bf->list, head); |
55624204 | 400 | } |
55624204 S |
401 | } |
402 | return 0; | |
55624204 S |
403 | } |
404 | ||
285f2dda S |
405 | static int ath9k_init_queues(struct ath_softc *sc) |
406 | { | |
285f2dda S |
407 | int i = 0; |
408 | ||
285f2dda | 409 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 410 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
411 | ath_cabq_update(sc); |
412 | ||
f2c7a793 FF |
413 | sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0); |
414 | ||
bea843c7 | 415 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
066dae93 | 416 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); |
60f2d1d5 BG |
417 | sc->tx.txq_map[i]->mac80211_qnum = i; |
418 | } | |
285f2dda | 419 | return 0; |
285f2dda S |
420 | } |
421 | ||
285f2dda S |
422 | static void ath9k_init_misc(struct ath_softc *sc) |
423 | { | |
424 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
425 | int i = 0; | |
3d4e20f2 | 426 | |
7ac76764 | 427 | timer_setup(&common->ani.timer, ath_ani_calibrate, 0); |
55624204 | 428 | |
32efb0cc | 429 | common->last_rssi = ATH_RSSI_DUMMY_MARKER; |
a72c9262 | 430 | eth_broadcast_addr(common->bssidmask); |
11b0ac2e | 431 | sc->beacon.slottime = 9; |
55624204 | 432 | |
7545daf4 | 433 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) |
55624204 | 434 | sc->beacon.bslot[i] = NULL; |
102885a5 VT |
435 | |
436 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
437 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
04ccd4a1 | 438 | |
dd7657be | 439 | sc->spec_priv.ah = sc->sc_ah; |
21af25d0 OR |
440 | sc->spec_priv.spec_config.enabled = 0; |
441 | sc->spec_priv.spec_config.short_repeat = true; | |
442 | sc->spec_priv.spec_config.count = 8; | |
443 | sc->spec_priv.spec_config.endless = false; | |
444 | sc->spec_priv.spec_config.period = 0xFF; | |
445 | sc->spec_priv.spec_config.fft_period = 0xF; | |
285f2dda | 446 | } |
55624204 | 447 | |
0f978bfa | 448 | static void ath9k_init_pcoem_platform(struct ath_softc *sc) |
9b60b64b SM |
449 | { |
450 | struct ath_hw *ah = sc->sc_ah; | |
3f2da955 | 451 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
9b60b64b SM |
452 | struct ath_common *common = ath9k_hw_common(ah); |
453 | ||
935477ed FF |
454 | if (!IS_ENABLED(CONFIG_ATH9K_PCOEM)) |
455 | return; | |
456 | ||
9b60b64b SM |
457 | if (common->bus_ops->ath_bus_type != ATH_PCI) |
458 | return; | |
459 | ||
e861ef52 SM |
460 | if (sc->driver_data & (ATH9K_PCI_CUS198 | |
461 | ATH9K_PCI_CUS230)) { | |
9b60b64b SM |
462 | ah->config.xlna_gpio = 9; |
463 | ah->config.xatten_margin_cfg = true; | |
e083a42e | 464 | ah->config.alt_mingainidx = true; |
31fd216d | 465 | ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88; |
3afa6b4f SM |
466 | sc->ant_comb.low_rssi_thresh = 20; |
467 | sc->ant_comb.fast_div_bias = 3; | |
9b60b64b | 468 | |
e861ef52 SM |
469 | ath_info(common, "Set parameters for %s\n", |
470 | (sc->driver_data & ATH9K_PCI_CUS198) ? | |
471 | "CUS198" : "CUS230"); | |
3f2da955 SM |
472 | } |
473 | ||
474 | if (sc->driver_data & ATH9K_PCI_CUS217) | |
12eea640 | 475 | ath_info(common, "CUS217 card detected\n"); |
3f2da955 | 476 | |
10631336 SM |
477 | if (sc->driver_data & ATH9K_PCI_CUS252) |
478 | ath_info(common, "CUS252 card detected\n"); | |
479 | ||
3fcdd0a1 SM |
480 | if (sc->driver_data & ATH9K_PCI_AR9565_1ANT) |
481 | ath_info(common, "WB335 1-ANT card detected\n"); | |
482 | ||
483 | if (sc->driver_data & ATH9K_PCI_AR9565_2ANT) | |
484 | ath_info(common, "WB335 2-ANT card detected\n"); | |
485 | ||
4dd35640 SM |
486 | if (sc->driver_data & ATH9K_PCI_KILLER) |
487 | ath_info(common, "Killer Wireless card detected\n"); | |
488 | ||
3fcdd0a1 SM |
489 | /* |
490 | * Some WB335 cards do not support antenna diversity. Since | |
491 | * we use a hardcoded value for AR9565 instead of using the | |
492 | * EEPROM/OTP data, remove the combining feature from | |
493 | * the HW capabilities bitmap. | |
494 | */ | |
495 | if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) { | |
496 | if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV)) | |
497 | pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB; | |
498 | } | |
499 | ||
3f2da955 SM |
500 | if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) { |
501 | pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV; | |
502 | ath_info(common, "Set BT/WLAN RX diversity capability\n"); | |
9b60b64b | 503 | } |
d1ae25a0 SM |
504 | |
505 | if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) { | |
506 | ah->config.pcie_waen = 0x0040473b; | |
507 | ath_info(common, "Enable WAR for ASPM D3/L1\n"); | |
508 | } | |
2d22c7dd | 509 | |
afa7e6db SM |
510 | /* |
511 | * The default value of pll_pwrsave is 1. | |
512 | * For certain AR9485 cards, it is set to 0. | |
656cd75c | 513 | * For AR9462, AR9565 it's set to 7. |
afa7e6db SM |
514 | */ |
515 | ah->config.pll_pwrsave = 1; | |
516 | ||
2d22c7dd | 517 | if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) { |
afa7e6db | 518 | ah->config.pll_pwrsave = 0; |
2d22c7dd SM |
519 | ath_info(common, "Disable PLL PowerSave\n"); |
520 | } | |
aeeb2065 SM |
521 | |
522 | if (sc->driver_data & ATH9K_PCI_LED_ACT_HI) | |
523 | ah->config.led_active_high = true; | |
9b60b64b SM |
524 | } |
525 | ||
ab5c4f71 GJ |
526 | static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob, |
527 | void *ctx) | |
528 | { | |
529 | struct ath9k_eeprom_ctx *ec = ctx; | |
530 | ||
531 | if (eeprom_blob) | |
532 | ec->ah->eeprom_blob = eeprom_blob; | |
533 | ||
534 | complete(&ec->complete); | |
535 | } | |
536 | ||
537 | static int ath9k_eeprom_request(struct ath_softc *sc, const char *name) | |
538 | { | |
539 | struct ath9k_eeprom_ctx ec; | |
47f58b1e | 540 | struct ath_hw *ah = sc->sc_ah; |
ab5c4f71 GJ |
541 | int err; |
542 | ||
543 | /* try to load the EEPROM content asynchronously */ | |
544 | init_completion(&ec.complete); | |
545 | ec.ah = sc->sc_ah; | |
546 | ||
547 | err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL, | |
548 | &ec, ath9k_eeprom_request_cb); | |
549 | if (err < 0) { | |
550 | ath_err(ath9k_hw_common(ah), | |
551 | "EEPROM request failed\n"); | |
552 | return err; | |
553 | } | |
554 | ||
555 | wait_for_completion(&ec.complete); | |
556 | ||
557 | if (!ah->eeprom_blob) { | |
558 | ath_err(ath9k_hw_common(ah), | |
559 | "Unable to load EEPROM file %s\n", name); | |
560 | return -EINVAL; | |
561 | } | |
562 | ||
563 | return 0; | |
564 | } | |
565 | ||
566 | static void ath9k_eeprom_release(struct ath_softc *sc) | |
567 | { | |
568 | release_firmware(sc->sc_ah->eeprom_blob); | |
569 | } | |
570 | ||
28755b8f | 571 | static int ath9k_init_platform(struct ath_softc *sc) |
0f978bfa SM |
572 | { |
573 | struct ath9k_platform_data *pdata = sc->dev->platform_data; | |
574 | struct ath_hw *ah = sc->sc_ah; | |
28755b8f MB |
575 | struct ath_common *common = ath9k_hw_common(ah); |
576 | int ret; | |
0f978bfa SM |
577 | |
578 | if (!pdata) | |
579 | return 0; | |
580 | ||
28755b8f MB |
581 | if (!pdata->use_eeprom) { |
582 | ah->ah_flags &= ~AH_USE_EEPROM; | |
583 | ah->gpio_mask = pdata->gpio_mask; | |
584 | ah->gpio_val = pdata->gpio_val; | |
585 | ah->led_pin = pdata->led_pin; | |
586 | ah->is_clk_25mhz = pdata->is_clk_25mhz; | |
587 | ah->get_mac_revision = pdata->get_mac_revision; | |
588 | ah->external_reset = pdata->external_reset; | |
589 | ah->disable_2ghz = pdata->disable_2ghz; | |
590 | ah->disable_5ghz = pdata->disable_5ghz; | |
591 | ||
592 | if (!pdata->endian_check) | |
593 | ah->ah_flags |= AH_NO_EEP_SWAP; | |
594 | } | |
595 | ||
0f978bfa SM |
596 | if (pdata->eeprom_name) { |
597 | ret = ath9k_eeprom_request(sc, pdata->eeprom_name); | |
598 | if (ret) | |
599 | return ret; | |
600 | } | |
601 | ||
3467f0d4 MB |
602 | if (pdata->led_active_high) |
603 | ah->config.led_active_high = true; | |
604 | ||
0f978bfa SM |
605 | if (pdata->tx_gain_buffalo) |
606 | ah->config.tx_gain_buffalo = true; | |
607 | ||
28755b8f MB |
608 | if (pdata->macaddr) |
609 | ether_addr_copy(common->macaddr, pdata->macaddr); | |
610 | ||
611 | return 0; | |
0f978bfa SM |
612 | } |
613 | ||
138b4125 MB |
614 | static int ath9k_of_init(struct ath_softc *sc) |
615 | { | |
616 | struct device_node *np = sc->dev->of_node; | |
617 | struct ath_hw *ah = sc->sc_ah; | |
618 | struct ath_common *common = ath9k_hw_common(ah); | |
619 | enum ath_bus_type bus_type = common->bus_ops->ath_bus_type; | |
620 | const char *mac; | |
621 | char eeprom_name[100]; | |
622 | int ret; | |
623 | ||
624 | if (!of_device_is_available(np)) | |
625 | return 0; | |
626 | ||
627 | ath_dbg(common, CONFIG, "parsing configuration from OF node\n"); | |
628 | ||
629 | if (of_property_read_bool(np, "qca,no-eeprom")) { | |
630 | /* ath9k-eeprom-<bus>-<id>.bin */ | |
631 | scnprintf(eeprom_name, sizeof(eeprom_name), | |
632 | "ath9k-eeprom-%s-%s.bin", | |
633 | ath_bus_type_to_string(bus_type), dev_name(ah->dev)); | |
634 | ||
635 | ret = ath9k_eeprom_request(sc, eeprom_name); | |
636 | if (ret) | |
637 | return ret; | |
ce938231 DD |
638 | |
639 | ah->ah_flags &= ~AH_USE_EEPROM; | |
640 | ah->ah_flags |= AH_NO_EEP_SWAP; | |
138b4125 MB |
641 | } |
642 | ||
643 | mac = of_get_mac_address(np); | |
d31a36b5 | 644 | if (!IS_ERR(mac)) |
138b4125 MB |
645 | ether_addr_copy(common->macaddr, mac); |
646 | ||
138b4125 MB |
647 | return 0; |
648 | } | |
649 | ||
eb93e891 | 650 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, |
285f2dda S |
651 | const struct ath_bus_ops *bus_ops) |
652 | { | |
653 | struct ath_hw *ah = NULL; | |
3f2da955 | 654 | struct ath9k_hw_capabilities *pCap; |
285f2dda S |
655 | struct ath_common *common; |
656 | int ret = 0, i; | |
657 | int csz = 0; | |
55624204 | 658 | |
b81950b1 | 659 | ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL); |
285f2dda S |
660 | if (!ah) |
661 | return -ENOMEM; | |
662 | ||
c1b976d2 | 663 | ah->dev = sc->dev; |
233536e1 | 664 | ah->hw = sc->hw; |
285f2dda | 665 | ah->hw_version.devid = devid; |
28755b8f MB |
666 | ah->ah_flags |= AH_USE_EEPROM; |
667 | ah->led_pin = -1; | |
f9f84e96 | 668 | ah->reg_ops.read = ath9k_ioread32; |
d55ce0a6 | 669 | ah->reg_ops.multi_read = ath9k_multi_ioread32; |
f9f84e96 | 670 | ah->reg_ops.write = ath9k_iowrite32; |
845e03c9 | 671 | ah->reg_ops.rmw = ath9k_reg_rmw; |
3f2da955 | 672 | pCap = &ah->caps; |
285f2dda | 673 | |
95a5992e | 674 | common = ath9k_hw_common(ah); |
56bdbe0d FF |
675 | |
676 | /* Will be cleared in ath9k_start() */ | |
677 | set_bit(ATH_OP_INVALID, &common->op_flags); | |
678 | ||
679 | sc->sc_ah = ah; | |
95a5992e | 680 | sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET); |
89f927af | 681 | sc->tx99_power = MAX_RATE_POWER + 1; |
10e23181 | 682 | init_waitqueue_head(&sc->tx_wait); |
ca900ac9 | 683 | sc->cur_chan = &sc->chanctx[0]; |
499afacc | 684 | if (!ath9k_is_chanctx_enabled()) |
3ad9c386 | 685 | sc->cur_chan->hw_queue_base = 0; |
8e92d3f2 | 686 | |
f9f84e96 | 687 | common->ops = &ah->reg_ops; |
285f2dda | 688 | common->bus_ops = bus_ops; |
99d2217b | 689 | common->ps_ops = &ath9k_ps_ops; |
285f2dda S |
690 | common->ah = ah; |
691 | common->hw = sc->hw; | |
692 | common->priv = sc; | |
693 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 694 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
05c0be2f | 695 | common->disable_ani = false; |
e09f2dc7 | 696 | |
9b60b64b SM |
697 | /* |
698 | * Platform quirks. | |
699 | */ | |
0f978bfa SM |
700 | ath9k_init_pcoem_platform(sc); |
701 | ||
28755b8f | 702 | ret = ath9k_init_platform(sc); |
0f978bfa SM |
703 | if (ret) |
704 | return ret; | |
9b60b64b | 705 | |
138b4125 MB |
706 | ret = ath9k_of_init(sc); |
707 | if (ret) | |
708 | return ret; | |
709 | ||
cd84042c VGV |
710 | if (ath9k_led_active_high != -1) |
711 | ah->config.led_active_high = ath9k_led_active_high == 1; | |
712 | ||
e09f2dc7 | 713 | /* |
3f2da955 SM |
714 | * Enable WLAN/BT RX Antenna diversity only when: |
715 | * | |
7d845871 | 716 | * - BTCOEX is disabled. |
3f2da955 SM |
717 | * - the user manually requests the feature. |
718 | * - the HW cap is set using the platform data. | |
e09f2dc7 | 719 | */ |
7d845871 | 720 | if (!common->btcoex_enabled && ath9k_bt_ant_diversity && |
3f2da955 | 721 | (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV)) |
63081305 | 722 | common->bt_ant_diversity = 1; |
e09f2dc7 | 723 | |
20b25744 | 724 | spin_lock_init(&common->cc_lock); |
3a5e969b | 725 | spin_lock_init(&sc->intr_lock); |
285f2dda S |
726 | spin_lock_init(&sc->sc_serial_rw); |
727 | spin_lock_init(&sc->sc_pm_lock); | |
bff11766 | 728 | spin_lock_init(&sc->chan_lock); |
285f2dda | 729 | mutex_init(&sc->mutex); |
f91a35b4 AP |
730 | tasklet_setup(&sc->intr_tq, ath9k_tasklet); |
731 | tasklet_setup(&sc->bcon_tasklet, ath9k_beacon_tasklet); | |
285f2dda | 732 | |
7ac76764 | 733 | timer_setup(&sc->sleep_timer, ath_ps_full_sleep, 0); |
aaa1ec46 | 734 | INIT_WORK(&sc->hw_reset_work, ath_reset_work); |
aaa1ec46 SM |
735 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); |
736 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); | |
d63ffc45 | 737 | INIT_DELAYED_WORK(&sc->hw_check_work, ath_hw_check_work); |
705d0bf8 SM |
738 | |
739 | ath9k_init_channel_context(sc); | |
aaa1ec46 | 740 | |
285f2dda S |
741 | /* |
742 | * Cache line size is used to size and align various | |
743 | * structures used to communicate with the hardware. | |
744 | */ | |
745 | ath_read_cachesize(common, &csz); | |
746 | common->cachelsz = csz << 2; /* convert to bytes */ | |
747 | ||
d70357d5 | 748 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 749 | ret = ath9k_hw_init(ah); |
d70357d5 | 750 | if (ret) |
285f2dda | 751 | goto err_hw; |
55624204 | 752 | |
285f2dda S |
753 | ret = ath9k_init_queues(sc); |
754 | if (ret) | |
755 | goto err_queues; | |
756 | ||
757 | ret = ath9k_init_btcoex(sc); | |
758 | if (ret) | |
759 | goto err_btcoex; | |
760 | ||
13f71050 | 761 | ret = ath9k_cmn_init_channels_rates(common); |
f209f529 FF |
762 | if (ret) |
763 | goto err_btcoex; | |
764 | ||
c7dd40c9 SM |
765 | ret = ath9k_init_p2p(sc); |
766 | if (ret) | |
4f681691 | 767 | goto err_btcoex; |
d463af4a | 768 | |
f82b4bde | 769 | ath9k_cmn_init_crypto(sc->sc_ah); |
285f2dda | 770 | ath9k_init_misc(sc); |
fbbcd146 | 771 | ath_chanctx_init(sc); |
e90e302a | 772 | ath9k_offchannel_init(sc); |
285f2dda | 773 | |
d09f5f4c SM |
774 | if (common->bus_ops->aspm_init) |
775 | common->bus_ops->aspm_init(common); | |
776 | ||
55624204 | 777 | return 0; |
285f2dda S |
778 | |
779 | err_btcoex: | |
55624204 S |
780 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
781 | if (ATH_TXQ_SETUP(sc, i)) | |
782 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda | 783 | err_queues: |
285f2dda S |
784 | ath9k_hw_deinit(ah); |
785 | err_hw: | |
ab5c4f71 | 786 | ath9k_eeprom_release(sc); |
89f927af | 787 | dev_kfree_skb_any(sc->tx99_skb); |
285f2dda | 788 | return ret; |
55624204 S |
789 | } |
790 | ||
babcbc29 FF |
791 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
792 | { | |
793 | struct ieee80211_supported_band *sband; | |
794 | struct ieee80211_channel *chan; | |
795 | struct ath_hw *ah = sc->sc_ah; | |
13f71050 | 796 | struct ath_common *common = ath9k_hw_common(ah); |
0671894f | 797 | struct cfg80211_chan_def chandef; |
babcbc29 FF |
798 | int i; |
799 | ||
13f71050 | 800 | sband = &common->sbands[band]; |
babcbc29 FF |
801 | for (i = 0; i < sband->n_channels; i++) { |
802 | chan = &sband->channels[i]; | |
803 | ah->curchan = &ah->channels[chan->hw_value]; | |
0671894f | 804 | cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20); |
2297f1c7 | 805 | ath9k_cmn_get_channel(sc->hw, ah, &chandef); |
b037b107 | 806 | ath9k_hw_set_txpowerlimit(ah, MAX_COMBINED_POWER, true); |
babcbc29 FF |
807 | } |
808 | } | |
809 | ||
810 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
811 | { | |
812 | struct ath_hw *ah = sc->sc_ah; | |
813 | struct ath9k_channel *curchan = ah->curchan; | |
814 | ||
815 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
57fbcce3 | 816 | ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ); |
babcbc29 | 817 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
57fbcce3 | 818 | ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ); |
babcbc29 FF |
819 | |
820 | ah->curchan = curchan; | |
821 | } | |
822 | ||
20c8e8dc | 823 | static const struct ieee80211_iface_limit if_limits[] = { |
71a5f881 | 824 | { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, |
20c8e8dc FF |
825 | { .max = 8, .types = |
826 | #ifdef CONFIG_MAC80211_MESH | |
827 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
828 | #endif | |
95ae4812 FF |
829 | BIT(NL80211_IFTYPE_AP) }, |
830 | { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
20c8e8dc FF |
831 | BIT(NL80211_IFTYPE_P2P_GO) }, |
832 | }; | |
833 | ||
499afacc SM |
834 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
835 | ||
a4068323 | 836 | static const struct ieee80211_iface_limit if_limits_multi[] = { |
86162d49 SM |
837 | { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) | |
838 | BIT(NL80211_IFTYPE_AP) | | |
839 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
a4068323 | 840 | BIT(NL80211_IFTYPE_P2P_GO) }, |
86162d49 | 841 | { .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) }, |
eb61f9f6 | 842 | { .max = 1, .types = BIT(NL80211_IFTYPE_P2P_DEVICE) }, |
a4068323 RM |
843 | }; |
844 | ||
a4068323 RM |
845 | static const struct ieee80211_iface_combination if_comb_multi[] = { |
846 | { | |
847 | .limits = if_limits_multi, | |
848 | .n_limits = ARRAY_SIZE(if_limits_multi), | |
eb61f9f6 | 849 | .max_interfaces = 3, |
a4068323 RM |
850 | .num_different_channels = 2, |
851 | .beacon_int_infra_match = true, | |
852 | }, | |
853 | }; | |
854 | ||
499afacc SM |
855 | #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ |
856 | ||
e9cdedf6 ZK |
857 | static const struct ieee80211_iface_combination if_comb[] = { |
858 | { | |
859 | .limits = if_limits, | |
860 | .n_limits = ARRAY_SIZE(if_limits), | |
861 | .max_interfaces = 2048, | |
862 | .num_different_channels = 1, | |
863 | .beacon_int_infra_match = true, | |
1286558e FF |
864 | #ifdef CONFIG_ATH9K_DFS_CERTIFIED |
865 | .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | | |
866 | BIT(NL80211_CHAN_WIDTH_20) | | |
867 | BIT(NL80211_CHAN_WIDTH_40), | |
868 | #endif | |
e9cdedf6 | 869 | }, |
20c8e8dc | 870 | }; |
43c35284 | 871 | |
868caae3 SM |
872 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
873 | static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw) | |
874 | { | |
875 | struct ath_hw *ah = sc->sc_ah; | |
876 | struct ath_common *common = ath9k_hw_common(ah); | |
877 | ||
878 | if (!ath9k_is_chanctx_enabled()) | |
879 | return; | |
880 | ||
30686bf7 | 881 | ieee80211_hw_set(hw, QUEUE_CONTROL); |
868caae3 SM |
882 | hw->queues = ATH9K_NUM_TX_QUEUES; |
883 | hw->offchannel_tx_hw_queue = hw->queues - 1; | |
868caae3 SM |
884 | hw->wiphy->iface_combinations = if_comb_multi; |
885 | hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi); | |
886 | hw->wiphy->max_scan_ssids = 255; | |
887 | hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; | |
888 | hw->wiphy->max_remain_on_channel_duration = 10000; | |
889 | hw->chanctx_data_size = sizeof(void *); | |
890 | hw->extra_beacon_tailroom = | |
891 | sizeof(struct ieee80211_p2p_noa_attr) + 9; | |
892 | ||
893 | ath_dbg(common, CHAN_CTX, "Use channel contexts\n"); | |
894 | } | |
895 | #endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */ | |
896 | ||
7b6ef998 | 897 | static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 898 | { |
43c35284 FF |
899 | struct ath_hw *ah = sc->sc_ah; |
900 | struct ath_common *common = ath9k_hw_common(ah); | |
285f2dda | 901 | |
30686bf7 JB |
902 | ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES); |
903 | ieee80211_hw_set(hw, SUPPORTS_RC_TABLE); | |
904 | ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); | |
905 | ieee80211_hw_set(hw, SPECTRUM_MGMT); | |
906 | ieee80211_hw_set(hw, PS_NULLFUNC_STACK); | |
907 | ieee80211_hw_set(hw, SIGNAL_DBM); | |
908 | ieee80211_hw_set(hw, RX_INCLUDES_FCS); | |
909 | ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING); | |
f419c5f1 | 910 | ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); |
50e81e2f | 911 | ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS); |
55624204 | 912 | |
8298383c | 913 | if (ath9k_ps_enable) |
30686bf7 | 914 | ieee80211_hw_set(hw, SUPPORTS_PS); |
8298383c | 915 | |
b0a1ae97 | 916 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
30686bf7 | 917 | ieee80211_hw_set(hw, AMPDU_AGGREGATION); |
b0a1ae97 OR |
918 | |
919 | if (AR_SREV_9280_20_OR_LATER(ah)) | |
920 | hw->radiotap_mcs_details |= | |
921 | IEEE80211_RADIOTAP_MCS_HAVE_STBC; | |
922 | } | |
5ffaf8a3 | 923 | |
3e6109c5 | 924 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) |
30686bf7 | 925 | ieee80211_hw_set(hw, MFP_CAPABLE); |
55624204 | 926 | |
fdcf1bd4 SM |
927 | hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR | |
928 | NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | | |
929 | NL80211_FEATURE_P2P_GO_CTWIN; | |
ec26bcc0 | 930 | |
97f2645f | 931 | if (!IS_ENABLED(CONFIG_ATH9K_TX99)) { |
89f927af LR |
932 | hw->wiphy->interface_modes = |
933 | BIT(NL80211_IFTYPE_P2P_GO) | | |
934 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
935 | BIT(NL80211_IFTYPE_AP) | | |
89f927af LR |
936 | BIT(NL80211_IFTYPE_STATION) | |
937 | BIT(NL80211_IFTYPE_ADHOC) | | |
499afacc | 938 | BIT(NL80211_IFTYPE_MESH_POINT) | |
862a336c | 939 | BIT(NL80211_IFTYPE_OCB); |
499afacc | 940 | |
eb61f9f6 JD |
941 | if (ath9k_is_chanctx_enabled()) |
942 | hw->wiphy->interface_modes |= | |
943 | BIT(NL80211_IFTYPE_P2P_DEVICE); | |
944 | ||
362210e0 AB |
945 | hw->wiphy->iface_combinations = if_comb; |
946 | hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb); | |
89f927af | 947 | } |
20c8e8dc | 948 | |
531671cb | 949 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; |
55624204 | 950 | |
cfdc9a8b | 951 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; |
fd656234 | 952 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; |
81ddbb5c | 953 | hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; |
6fac8bbc | 954 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; |
d074e8d5 | 955 | hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; |
7b4f663e | 956 | hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; |
cfdc9a8b | 957 | |
868caae3 | 958 | hw->queues = 4; |
55624204 | 959 | hw->max_rates = 4; |
5f2f9e44 | 960 | hw->max_listen_interval = 10; |
65896510 | 961 | hw->max_rate_tries = 10; |
55624204 S |
962 | hw->sta_data_size = sizeof(struct ath_node); |
963 | hw->vif_data_size = sizeof(struct ath_vif); | |
50f08edf | 964 | hw->txq_data_size = sizeof(struct ath_atx_tid); |
029cd037 | 965 | hw->extra_tx_headroom = 4; |
55624204 | 966 | |
43c35284 FF |
967 | hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; |
968 | hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; | |
969 | ||
970 | /* single chain devices with rx diversity */ | |
971 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
972 | hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); | |
973 | ||
974 | sc->ant_rx = hw->wiphy->available_antennas_rx; | |
975 | sc->ant_tx = hw->wiphy->available_antennas_tx; | |
976 | ||
d4659912 | 977 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
57fbcce3 JB |
978 | hw->wiphy->bands[NL80211_BAND_2GHZ] = |
979 | &common->sbands[NL80211_BAND_2GHZ]; | |
d4659912 | 980 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
57fbcce3 JB |
981 | hw->wiphy->bands[NL80211_BAND_5GHZ] = |
982 | &common->sbands[NL80211_BAND_5GHZ]; | |
285f2dda | 983 | |
868caae3 SM |
984 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
985 | ath9k_set_mcc_capab(sc, hw); | |
986 | #endif | |
babaa80a | 987 | ath9k_init_wow(hw); |
b57ba3b2 | 988 | ath9k_cmn_reload_chainmask(ah); |
285f2dda S |
989 | |
990 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
ae44b502 AZ |
991 | |
992 | wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); | |
89cea749 | 993 | wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_AIRTIME_FAIRNESS); |
c01c320d JM |
994 | wiphy_ext_feature_set(hw->wiphy, |
995 | NL80211_EXT_FEATURE_MULTICAST_REGISTRATIONS); | |
4bad3a20 | 996 | wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); |
55624204 S |
997 | } |
998 | ||
eb93e891 | 999 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
55624204 S |
1000 | const struct ath_bus_ops *bus_ops) |
1001 | { | |
1002 | struct ieee80211_hw *hw = sc->hw; | |
1003 | struct ath_common *common; | |
1004 | struct ath_hw *ah; | |
285f2dda | 1005 | int error = 0; |
55624204 S |
1006 | struct ath_regulatory *reg; |
1007 | ||
285f2dda | 1008 | /* Bring up device */ |
eb93e891 | 1009 | error = ath9k_init_softc(devid, sc, bus_ops); |
b81950b1 FF |
1010 | if (error) |
1011 | return error; | |
55624204 S |
1012 | |
1013 | ah = sc->sc_ah; | |
1014 | common = ath9k_hw_common(ah); | |
285f2dda | 1015 | ath9k_set_hw_capab(sc, hw); |
55624204 | 1016 | |
285f2dda | 1017 | /* Initialize regulatory */ |
55624204 S |
1018 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
1019 | ath9k_reg_notifier); | |
1020 | if (error) | |
b81950b1 | 1021 | goto deinit; |
55624204 S |
1022 | |
1023 | reg = &common->regulatory; | |
1024 | ||
285f2dda | 1025 | /* Setup TX DMA */ |
55624204 S |
1026 | error = ath_tx_init(sc, ATH_TXBUF); |
1027 | if (error != 0) | |
b81950b1 | 1028 | goto deinit; |
55624204 | 1029 | |
285f2dda | 1030 | /* Setup RX DMA */ |
55624204 S |
1031 | error = ath_rx_init(sc, ATH_RXBUF); |
1032 | if (error != 0) | |
b81950b1 | 1033 | goto deinit; |
55624204 | 1034 | |
babcbc29 FF |
1035 | ath9k_init_txpower_limits(sc); |
1036 | ||
0cf55c21 FF |
1037 | #ifdef CONFIG_MAC80211_LEDS |
1038 | /* must be initialized before ieee80211_register_hw */ | |
1039 | sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, | |
1040 | IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, | |
1041 | ARRAY_SIZE(ath9k_tpt_blink)); | |
1042 | #endif | |
1043 | ||
285f2dda | 1044 | /* Register with mac80211 */ |
55624204 | 1045 | error = ieee80211_register_hw(hw); |
285f2dda | 1046 | if (error) |
b81950b1 | 1047 | goto rx_cleanup; |
55624204 | 1048 | |
eb272441 BG |
1049 | error = ath9k_init_debug(ah); |
1050 | if (error) { | |
3800276a | 1051 | ath_err(common, "Unable to create debugfs files\n"); |
b81950b1 | 1052 | goto unregister; |
eb272441 BG |
1053 | } |
1054 | ||
285f2dda | 1055 | /* Handle world regulatory */ |
55624204 S |
1056 | if (!ath_is_world_regd(reg)) { |
1057 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
1058 | if (error) | |
af690092 | 1059 | goto debug_cleanup; |
55624204 S |
1060 | } |
1061 | ||
285f2dda | 1062 | ath_init_leds(sc); |
55624204 S |
1063 | ath_start_rfkill_poll(sc); |
1064 | ||
1065 | return 0; | |
1066 | ||
af690092 SM |
1067 | debug_cleanup: |
1068 | ath9k_deinit_debug(sc); | |
b81950b1 | 1069 | unregister: |
285f2dda | 1070 | ieee80211_unregister_hw(hw); |
b81950b1 | 1071 | rx_cleanup: |
285f2dda | 1072 | ath_rx_cleanup(sc); |
b81950b1 | 1073 | deinit: |
285f2dda | 1074 | ath9k_deinit_softc(sc); |
55624204 S |
1075 | return error; |
1076 | } | |
1077 | ||
1078 | /*****************************/ | |
1079 | /* De-Initialization */ | |
1080 | /*****************************/ | |
1081 | ||
285f2dda | 1082 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 1083 | { |
285f2dda | 1084 | int i = 0; |
55624204 | 1085 | |
c7dd40c9 | 1086 | ath9k_deinit_p2p(sc); |
5908120f | 1087 | ath9k_deinit_btcoex(sc); |
19686ddf | 1088 | |
285f2dda S |
1089 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
1090 | if (ATH_TXQ_SETUP(sc, i)) | |
1091 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
1092 | ||
bf3dac5a | 1093 | del_timer_sync(&sc->sleep_timer); |
285f2dda | 1094 | ath9k_hw_deinit(sc->sc_ah); |
8e92d3f2 ZK |
1095 | if (sc->dfs_detector != NULL) |
1096 | sc->dfs_detector->exit(sc->dfs_detector); | |
285f2dda | 1097 | |
ab5c4f71 | 1098 | ath9k_eeprom_release(sc); |
55624204 S |
1099 | } |
1100 | ||
285f2dda | 1101 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
1102 | { |
1103 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
1104 | |
1105 | ath9k_ps_wakeup(sc); | |
1106 | ||
55624204 | 1107 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 1108 | ath_deinit_leds(sc); |
55624204 | 1109 | |
c7c18060 RM |
1110 | ath9k_ps_restore(sc); |
1111 | ||
af690092 | 1112 | ath9k_deinit_debug(sc); |
661d2581 | 1113 | ath9k_deinit_wow(hw); |
55624204 S |
1114 | ieee80211_unregister_hw(hw); |
1115 | ath_rx_cleanup(sc); | |
285f2dda | 1116 | ath9k_deinit_softc(sc); |
55624204 S |
1117 | } |
1118 | ||
55624204 S |
1119 | /************************/ |
1120 | /* Module Hooks */ | |
1121 | /************************/ | |
1122 | ||
1123 | static int __init ath9k_init(void) | |
1124 | { | |
1125 | int error; | |
1126 | ||
55624204 S |
1127 | error = ath_pci_init(); |
1128 | if (error < 0) { | |
516304b0 | 1129 | pr_err("No PCI devices found, driver not installed\n"); |
55624204 | 1130 | error = -ENODEV; |
9e495a26 | 1131 | goto err_out; |
55624204 S |
1132 | } |
1133 | ||
1134 | error = ath_ahb_init(); | |
1135 | if (error < 0) { | |
1136 | error = -ENODEV; | |
1137 | goto err_pci_exit; | |
1138 | } | |
1139 | ||
3153b68e AK |
1140 | dmi_check_system(ath9k_quirks); |
1141 | ||
55624204 S |
1142 | return 0; |
1143 | ||
1144 | err_pci_exit: | |
1145 | ath_pci_exit(); | |
55624204 S |
1146 | err_out: |
1147 | return error; | |
1148 | } | |
1149 | module_init(ath9k_init); | |
1150 | ||
1151 | static void __exit ath9k_exit(void) | |
1152 | { | |
d584747b | 1153 | is_ath9k_unloaded = true; |
55624204 S |
1154 | ath_ahb_exit(); |
1155 | ath_pci_exit(); | |
516304b0 | 1156 | pr_info("%s: Driver unloaded\n", dev_info); |
55624204 S |
1157 | } |
1158 | module_exit(ath9k_exit); |