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Commit | Line | Data |
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55624204 S |
1 | /* |
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
5a0e3ad6 | 17 | #include <linux/slab.h> |
10598c12 | 18 | #include <linux/pm_qos_params.h> |
5a0e3ad6 | 19 | |
55624204 S |
20 | #include "ath9k.h" |
21 | ||
22 | static char *dev_info = "ath9k"; | |
23 | ||
24 | MODULE_AUTHOR("Atheros Communications"); | |
25 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
26 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
27 | MODULE_LICENSE("Dual BSD/GPL"); | |
28 | ||
29 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
30 | module_param_named(debug, ath9k_debug, uint, 0); | |
31 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
32 | ||
33 | int modparam_nohwcrypt; | |
34 | module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); | |
35 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); | |
36 | ||
93dbbcc4 | 37 | int led_blink; |
9a75c2ff VN |
38 | module_param_named(blink, led_blink, int, 0444); |
39 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); | |
40 | ||
8f5dcb1c VT |
41 | static int ath9k_btcoex_enable; |
42 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
43 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
44 | ||
55624204 S |
45 | /* We use the hw_value as an index into our private channel structure */ |
46 | ||
47 | #define CHAN2G(_freq, _idx) { \ | |
48 | .center_freq = (_freq), \ | |
49 | .hw_value = (_idx), \ | |
50 | .max_power = 20, \ | |
51 | } | |
52 | ||
53 | #define CHAN5G(_freq, _idx) { \ | |
54 | .band = IEEE80211_BAND_5GHZ, \ | |
55 | .center_freq = (_freq), \ | |
56 | .hw_value = (_idx), \ | |
57 | .max_power = 20, \ | |
58 | } | |
59 | ||
60 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
61 | * on 5 MHz steps, we support the channels which we know | |
62 | * we have calibration data for all cards though to make | |
63 | * this static */ | |
f209f529 | 64 | static const struct ieee80211_channel ath9k_2ghz_chantable[] = { |
55624204 S |
65 | CHAN2G(2412, 0), /* Channel 1 */ |
66 | CHAN2G(2417, 1), /* Channel 2 */ | |
67 | CHAN2G(2422, 2), /* Channel 3 */ | |
68 | CHAN2G(2427, 3), /* Channel 4 */ | |
69 | CHAN2G(2432, 4), /* Channel 5 */ | |
70 | CHAN2G(2437, 5), /* Channel 6 */ | |
71 | CHAN2G(2442, 6), /* Channel 7 */ | |
72 | CHAN2G(2447, 7), /* Channel 8 */ | |
73 | CHAN2G(2452, 8), /* Channel 9 */ | |
74 | CHAN2G(2457, 9), /* Channel 10 */ | |
75 | CHAN2G(2462, 10), /* Channel 11 */ | |
76 | CHAN2G(2467, 11), /* Channel 12 */ | |
77 | CHAN2G(2472, 12), /* Channel 13 */ | |
78 | CHAN2G(2484, 13), /* Channel 14 */ | |
79 | }; | |
80 | ||
81 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
82 | * on 5 MHz steps, we support the channels which we know | |
83 | * we have calibration data for all cards though to make | |
84 | * this static */ | |
f209f529 | 85 | static const struct ieee80211_channel ath9k_5ghz_chantable[] = { |
55624204 S |
86 | /* _We_ call this UNII 1 */ |
87 | CHAN5G(5180, 14), /* Channel 36 */ | |
88 | CHAN5G(5200, 15), /* Channel 40 */ | |
89 | CHAN5G(5220, 16), /* Channel 44 */ | |
90 | CHAN5G(5240, 17), /* Channel 48 */ | |
91 | /* _We_ call this UNII 2 */ | |
92 | CHAN5G(5260, 18), /* Channel 52 */ | |
93 | CHAN5G(5280, 19), /* Channel 56 */ | |
94 | CHAN5G(5300, 20), /* Channel 60 */ | |
95 | CHAN5G(5320, 21), /* Channel 64 */ | |
96 | /* _We_ call this "Middle band" */ | |
97 | CHAN5G(5500, 22), /* Channel 100 */ | |
98 | CHAN5G(5520, 23), /* Channel 104 */ | |
99 | CHAN5G(5540, 24), /* Channel 108 */ | |
100 | CHAN5G(5560, 25), /* Channel 112 */ | |
101 | CHAN5G(5580, 26), /* Channel 116 */ | |
102 | CHAN5G(5600, 27), /* Channel 120 */ | |
103 | CHAN5G(5620, 28), /* Channel 124 */ | |
104 | CHAN5G(5640, 29), /* Channel 128 */ | |
105 | CHAN5G(5660, 30), /* Channel 132 */ | |
106 | CHAN5G(5680, 31), /* Channel 136 */ | |
107 | CHAN5G(5700, 32), /* Channel 140 */ | |
108 | /* _We_ call this UNII 3 */ | |
109 | CHAN5G(5745, 33), /* Channel 149 */ | |
110 | CHAN5G(5765, 34), /* Channel 153 */ | |
111 | CHAN5G(5785, 35), /* Channel 157 */ | |
112 | CHAN5G(5805, 36), /* Channel 161 */ | |
113 | CHAN5G(5825, 37), /* Channel 165 */ | |
114 | }; | |
115 | ||
116 | /* Atheros hardware rate code addition for short premble */ | |
117 | #define SHPCHECK(__hw_rate, __flags) \ | |
118 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) | |
119 | ||
120 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
121 | .bitrate = (_bitrate), \ | |
122 | .flags = (_flags), \ | |
123 | .hw_value = (_hw_rate), \ | |
124 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
125 | } | |
126 | ||
127 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
128 | RATE(10, 0x1b, 0), | |
129 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), | |
130 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), | |
131 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), | |
132 | RATE(60, 0x0b, 0), | |
133 | RATE(90, 0x0f, 0), | |
134 | RATE(120, 0x0a, 0), | |
135 | RATE(180, 0x0e, 0), | |
136 | RATE(240, 0x09, 0), | |
137 | RATE(360, 0x0d, 0), | |
138 | RATE(480, 0x08, 0), | |
139 | RATE(540, 0x0c, 0), | |
140 | }; | |
141 | ||
285f2dda | 142 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
143 | |
144 | /* | |
145 | * Read and write, they both share the same lock. We do this to serialize | |
146 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
147 | * as the FIFO on these devices can only accept sanely 2 requests. | |
148 | */ | |
149 | ||
150 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
151 | { | |
152 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
153 | struct ath_common *common = ath9k_hw_common(ah); | |
154 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
155 | ||
156 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
157 | unsigned long flags; | |
158 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
159 | iowrite32(val, sc->mem + reg_offset); | |
160 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
161 | } else | |
162 | iowrite32(val, sc->mem + reg_offset); | |
163 | } | |
164 | ||
165 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
166 | { | |
167 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
168 | struct ath_common *common = ath9k_hw_common(ah); | |
169 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
170 | u32 val; | |
171 | ||
172 | if (ah->config.serialize_regmode == SER_REG_MODE_ON) { | |
173 | unsigned long flags; | |
174 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
175 | val = ioread32(sc->mem + reg_offset); | |
176 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
177 | } else | |
178 | val = ioread32(sc->mem + reg_offset); | |
179 | return val; | |
180 | } | |
181 | ||
182 | static const struct ath_ops ath9k_common_ops = { | |
183 | .read = ath9k_ioread32, | |
184 | .write = ath9k_iowrite32, | |
185 | }; | |
186 | ||
10598c12 VN |
187 | struct pm_qos_request_list ath9k_pm_qos_req; |
188 | ||
55624204 S |
189 | /**************************/ |
190 | /* Initialization */ | |
191 | /**************************/ | |
192 | ||
193 | static void setup_ht_cap(struct ath_softc *sc, | |
194 | struct ieee80211_sta_ht_cap *ht_info) | |
195 | { | |
3bb065a7 FF |
196 | struct ath_hw *ah = sc->sc_ah; |
197 | struct ath_common *common = ath9k_hw_common(ah); | |
55624204 | 198 | u8 tx_streams, rx_streams; |
3bb065a7 | 199 | int i, max_streams; |
55624204 S |
200 | |
201 | ht_info->ht_supported = true; | |
202 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
203 | IEEE80211_HT_CAP_SM_PS | | |
204 | IEEE80211_HT_CAP_SGI_40 | | |
205 | IEEE80211_HT_CAP_DSSSCCK40; | |
206 | ||
b0a33448 LR |
207 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) |
208 | ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; | |
209 | ||
6473d24d VT |
210 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) |
211 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
212 | ||
55624204 S |
213 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
214 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
215 | ||
3bb065a7 FF |
216 | if (AR_SREV_9300_20_OR_LATER(ah)) |
217 | max_streams = 3; | |
218 | else | |
219 | max_streams = 2; | |
220 | ||
7a37081e | 221 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
074a8c0d FF |
222 | if (max_streams >= 2) |
223 | ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; | |
224 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
225 | } | |
226 | ||
55624204 S |
227 | /* set up supported mcs set */ |
228 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
61389f3e S |
229 | tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams); |
230 | rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams); | |
3bb065a7 FF |
231 | |
232 | ath_print(common, ATH_DBG_CONFIG, | |
233 | "TX streams %d, RX streams: %d\n", | |
234 | tx_streams, rx_streams); | |
55624204 S |
235 | |
236 | if (tx_streams != rx_streams) { | |
55624204 S |
237 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
238 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
239 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
240 | } | |
241 | ||
3bb065a7 FF |
242 | for (i = 0; i < rx_streams; i++) |
243 | ht_info->mcs.rx_mask[i] = 0xff; | |
55624204 S |
244 | |
245 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; | |
246 | } | |
247 | ||
248 | static int ath9k_reg_notifier(struct wiphy *wiphy, | |
249 | struct regulatory_request *request) | |
250 | { | |
251 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
252 | struct ath_wiphy *aphy = hw->priv; | |
253 | struct ath_softc *sc = aphy->sc; | |
254 | struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah); | |
255 | ||
256 | return ath_reg_notifier_apply(wiphy, request, reg); | |
257 | } | |
258 | ||
259 | /* | |
260 | * This function will allocate both the DMA descriptor structure, and the | |
261 | * buffers it contains. These are used to contain the descriptors used | |
262 | * by the system. | |
263 | */ | |
264 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
265 | struct list_head *head, const char *name, | |
4adfcded | 266 | int nbuf, int ndesc, bool is_tx) |
55624204 S |
267 | { |
268 | #define DS2PHYS(_dd, _ds) \ | |
269 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
270 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
271 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
272 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
4adfcded | 273 | u8 *ds; |
55624204 | 274 | struct ath_buf *bf; |
4adfcded | 275 | int i, bsize, error, desc_len; |
55624204 S |
276 | |
277 | ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", | |
278 | name, nbuf, ndesc); | |
279 | ||
280 | INIT_LIST_HEAD(head); | |
4adfcded VT |
281 | |
282 | if (is_tx) | |
283 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
284 | else | |
285 | desc_len = sizeof(struct ath_desc); | |
286 | ||
55624204 | 287 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 288 | if ((desc_len % 4) != 0) { |
55624204 S |
289 | ath_print(common, ATH_DBG_FATAL, |
290 | "ath_desc not DWORD aligned\n"); | |
4adfcded | 291 | BUG_ON((desc_len % 4) != 0); |
55624204 S |
292 | error = -ENOMEM; |
293 | goto fail; | |
294 | } | |
295 | ||
4adfcded | 296 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
297 | |
298 | /* | |
299 | * Need additional DMA memory because we can't use | |
300 | * descriptors that cross the 4K page boundary. Assume | |
301 | * one skipped descriptor per 4K page. | |
302 | */ | |
303 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
304 | u32 ndesc_skipped = | |
305 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
306 | u32 dma_len; | |
307 | ||
308 | while (ndesc_skipped) { | |
4adfcded | 309 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
310 | dd->dd_desc_len += dma_len; |
311 | ||
312 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 313 | } |
55624204 S |
314 | } |
315 | ||
316 | /* allocate descriptors */ | |
317 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, | |
318 | &dd->dd_desc_paddr, GFP_KERNEL); | |
319 | if (dd->dd_desc == NULL) { | |
320 | error = -ENOMEM; | |
321 | goto fail; | |
322 | } | |
4adfcded | 323 | ds = (u8 *) dd->dd_desc; |
55624204 S |
324 | ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
325 | name, ds, (u32) dd->dd_desc_len, | |
326 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
327 | ||
328 | /* allocate buffers */ | |
329 | bsize = sizeof(struct ath_buf) * nbuf; | |
330 | bf = kzalloc(bsize, GFP_KERNEL); | |
331 | if (bf == NULL) { | |
332 | error = -ENOMEM; | |
333 | goto fail2; | |
334 | } | |
335 | dd->dd_bufptr = bf; | |
336 | ||
4adfcded | 337 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { |
55624204 S |
338 | bf->bf_desc = ds; |
339 | bf->bf_daddr = DS2PHYS(dd, ds); | |
340 | ||
341 | if (!(sc->sc_ah->caps.hw_caps & | |
342 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
343 | /* | |
344 | * Skip descriptor addresses which can cause 4KB | |
345 | * boundary crossing (addr + length) with a 32 dword | |
346 | * descriptor fetch. | |
347 | */ | |
348 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
349 | BUG_ON((caddr_t) bf->bf_desc >= | |
350 | ((caddr_t) dd->dd_desc + | |
351 | dd->dd_desc_len)); | |
352 | ||
4adfcded | 353 | ds += (desc_len * ndesc); |
55624204 S |
354 | bf->bf_desc = ds; |
355 | bf->bf_daddr = DS2PHYS(dd, ds); | |
356 | } | |
357 | } | |
358 | list_add_tail(&bf->list, head); | |
359 | } | |
360 | return 0; | |
361 | fail2: | |
362 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
363 | dd->dd_desc_paddr); | |
364 | fail: | |
365 | memset(dd, 0, sizeof(*dd)); | |
366 | return error; | |
367 | #undef ATH_DESC_4KB_BOUND_CHECK | |
368 | #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED | |
369 | #undef DS2PHYS | |
370 | } | |
371 | ||
285f2dda | 372 | static void ath9k_init_crypto(struct ath_softc *sc) |
55624204 | 373 | { |
285f2dda S |
374 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
375 | int i = 0; | |
55624204 S |
376 | |
377 | /* Get the hardware key cache size. */ | |
285f2dda | 378 | common->keymax = sc->sc_ah->caps.keycache_size; |
55624204 S |
379 | if (common->keymax > ATH_KEYMAX) { |
380 | ath_print(common, ATH_DBG_ANY, | |
381 | "Warning, using only %u entries in %u key cache\n", | |
382 | ATH_KEYMAX, common->keymax); | |
383 | common->keymax = ATH_KEYMAX; | |
384 | } | |
385 | ||
386 | /* | |
387 | * Reset the key cache since some parts do not | |
388 | * reset the contents on initial power up. | |
389 | */ | |
390 | for (i = 0; i < common->keymax; i++) | |
040e539e | 391 | ath_hw_keyreset(common, (u16) i); |
55624204 | 392 | |
55624204 | 393 | /* |
285f2dda S |
394 | * Check whether the separate key cache entries |
395 | * are required to handle both tx+rx MIC keys. | |
396 | * With split mic keys the number of stations is limited | |
397 | * to 27 otherwise 59. | |
55624204 | 398 | */ |
117675d0 BR |
399 | if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) |
400 | common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED; | |
285f2dda S |
401 | } |
402 | ||
403 | static int ath9k_init_btcoex(struct ath_softc *sc) | |
404 | { | |
066dae93 FF |
405 | struct ath_txq *txq; |
406 | int r; | |
285f2dda S |
407 | |
408 | switch (sc->sc_ah->btcoex_hw.scheme) { | |
409 | case ATH_BTCOEX_CFG_NONE: | |
410 | break; | |
411 | case ATH_BTCOEX_CFG_2WIRE: | |
412 | ath9k_hw_btcoex_init_2wire(sc->sc_ah); | |
413 | break; | |
414 | case ATH_BTCOEX_CFG_3WIRE: | |
415 | ath9k_hw_btcoex_init_3wire(sc->sc_ah); | |
416 | r = ath_init_btcoex_timer(sc); | |
417 | if (r) | |
418 | return -1; | |
066dae93 FF |
419 | txq = sc->tx.txq_map[WME_AC_BE]; |
420 | ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum); | |
285f2dda S |
421 | sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; |
422 | break; | |
423 | default: | |
424 | WARN_ON(1); | |
425 | break; | |
426 | } | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
431 | static int ath9k_init_queues(struct ath_softc *sc) | |
432 | { | |
285f2dda S |
433 | int i = 0; |
434 | ||
285f2dda | 435 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 436 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
437 | |
438 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; | |
439 | ath_cabq_update(sc); | |
440 | ||
066dae93 FF |
441 | for (i = 0; i < WME_NUM_AC; i++) |
442 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); | |
55624204 | 443 | |
285f2dda | 444 | return 0; |
285f2dda S |
445 | } |
446 | ||
f209f529 | 447 | static int ath9k_init_channels_rates(struct ath_softc *sc) |
285f2dda | 448 | { |
f209f529 FF |
449 | void *channels; |
450 | ||
cac4220b FF |
451 | BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + |
452 | ARRAY_SIZE(ath9k_5ghz_chantable) != | |
453 | ATH9K_NUM_CHANNELS); | |
454 | ||
d4659912 | 455 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { |
f209f529 FF |
456 | channels = kmemdup(ath9k_2ghz_chantable, |
457 | sizeof(ath9k_2ghz_chantable), GFP_KERNEL); | |
458 | if (!channels) | |
459 | return -ENOMEM; | |
460 | ||
461 | sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; | |
285f2dda S |
462 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; |
463 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
464 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
465 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
466 | sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
467 | ARRAY_SIZE(ath9k_legacy_rates); | |
55624204 S |
468 | } |
469 | ||
d4659912 | 470 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { |
f209f529 FF |
471 | channels = kmemdup(ath9k_5ghz_chantable, |
472 | sizeof(ath9k_5ghz_chantable), GFP_KERNEL); | |
473 | if (!channels) { | |
474 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) | |
475 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
476 | return -ENOMEM; | |
477 | } | |
478 | ||
479 | sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; | |
285f2dda S |
480 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; |
481 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
482 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
483 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
484 | ath9k_legacy_rates + 4; | |
485 | sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
486 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
487 | } | |
f209f529 | 488 | return 0; |
285f2dda | 489 | } |
55624204 | 490 | |
285f2dda S |
491 | static void ath9k_init_misc(struct ath_softc *sc) |
492 | { | |
493 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
494 | int i = 0; | |
495 | ||
285f2dda | 496 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 S |
497 | |
498 | sc->config.txpowlimit = ATH_TXPOWER_MAX; | |
499 | ||
285f2dda | 500 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
55624204 S |
501 | sc->sc_flags |= SC_OP_TXAGGR; |
502 | sc->sc_flags |= SC_OP_RXAGGR; | |
503 | } | |
504 | ||
285f2dda S |
505 | common->tx_chainmask = sc->sc_ah->caps.tx_chainmask; |
506 | common->rx_chainmask = sc->sc_ah->caps.rx_chainmask; | |
55624204 | 507 | |
8fe65368 | 508 | ath9k_hw_set_diversity(sc->sc_ah, true); |
285f2dda | 509 | sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah); |
55624204 | 510 | |
364734fa | 511 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
55624204 | 512 | |
285f2dda | 513 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 514 | |
55624204 S |
515 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
516 | sc->beacon.bslot[i] = NULL; | |
517 | sc->beacon.bslot_aphy[i] = NULL; | |
518 | } | |
102885a5 VT |
519 | |
520 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
521 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
285f2dda | 522 | } |
55624204 | 523 | |
285f2dda S |
524 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid, |
525 | const struct ath_bus_ops *bus_ops) | |
526 | { | |
527 | struct ath_hw *ah = NULL; | |
528 | struct ath_common *common; | |
529 | int ret = 0, i; | |
530 | int csz = 0; | |
55624204 | 531 | |
285f2dda S |
532 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); |
533 | if (!ah) | |
534 | return -ENOMEM; | |
535 | ||
536 | ah->hw_version.devid = devid; | |
537 | ah->hw_version.subsysid = subsysid; | |
538 | sc->sc_ah = ah; | |
539 | ||
a05b5d45 FF |
540 | if (!sc->dev->platform_data) |
541 | ah->ah_flags |= AH_USE_EEPROM; | |
542 | ||
285f2dda S |
543 | common = ath9k_hw_common(ah); |
544 | common->ops = &ath9k_common_ops; | |
545 | common->bus_ops = bus_ops; | |
546 | common->ah = ah; | |
547 | common->hw = sc->hw; | |
548 | common->priv = sc; | |
549 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 550 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
20b25744 | 551 | spin_lock_init(&common->cc_lock); |
285f2dda S |
552 | |
553 | spin_lock_init(&sc->wiphy_lock); | |
285f2dda S |
554 | spin_lock_init(&sc->sc_serial_rw); |
555 | spin_lock_init(&sc->sc_pm_lock); | |
556 | mutex_init(&sc->mutex); | |
557 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | |
558 | tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, | |
559 | (unsigned long)sc); | |
560 | ||
561 | /* | |
562 | * Cache line size is used to size and align various | |
563 | * structures used to communicate with the hardware. | |
564 | */ | |
565 | ath_read_cachesize(common, &csz); | |
566 | common->cachelsz = csz << 2; /* convert to bytes */ | |
567 | ||
d70357d5 | 568 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 569 | ret = ath9k_hw_init(ah); |
d70357d5 | 570 | if (ret) |
285f2dda | 571 | goto err_hw; |
55624204 | 572 | |
285f2dda S |
573 | ret = ath9k_init_debug(ah); |
574 | if (ret) { | |
575 | ath_print(common, ATH_DBG_FATAL, | |
576 | "Unable to create debugfs files\n"); | |
577 | goto err_debug; | |
55624204 S |
578 | } |
579 | ||
285f2dda S |
580 | ret = ath9k_init_queues(sc); |
581 | if (ret) | |
582 | goto err_queues; | |
583 | ||
584 | ret = ath9k_init_btcoex(sc); | |
585 | if (ret) | |
586 | goto err_btcoex; | |
587 | ||
f209f529 FF |
588 | ret = ath9k_init_channels_rates(sc); |
589 | if (ret) | |
590 | goto err_btcoex; | |
591 | ||
285f2dda | 592 | ath9k_init_crypto(sc); |
285f2dda S |
593 | ath9k_init_misc(sc); |
594 | ||
55624204 | 595 | return 0; |
285f2dda S |
596 | |
597 | err_btcoex: | |
55624204 S |
598 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
599 | if (ATH_TXQ_SETUP(sc, i)) | |
600 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda S |
601 | err_queues: |
602 | ath9k_exit_debug(ah); | |
603 | err_debug: | |
604 | ath9k_hw_deinit(ah); | |
605 | err_hw: | |
606 | tasklet_kill(&sc->intr_tq); | |
607 | tasklet_kill(&sc->bcon_tasklet); | |
55624204 | 608 | |
285f2dda S |
609 | kfree(ah); |
610 | sc->sc_ah = NULL; | |
611 | ||
612 | return ret; | |
55624204 S |
613 | } |
614 | ||
babcbc29 FF |
615 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
616 | { | |
617 | struct ieee80211_supported_band *sband; | |
618 | struct ieee80211_channel *chan; | |
619 | struct ath_hw *ah = sc->sc_ah; | |
620 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
621 | int i; | |
622 | ||
623 | sband = &sc->sbands[band]; | |
624 | for (i = 0; i < sband->n_channels; i++) { | |
625 | chan = &sband->channels[i]; | |
626 | ah->curchan = &ah->channels[chan->hw_value]; | |
627 | ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20); | |
628 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); | |
629 | chan->max_power = reg->max_power_level / 2; | |
630 | } | |
631 | } | |
632 | ||
633 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
634 | { | |
635 | struct ath_hw *ah = sc->sc_ah; | |
636 | struct ath9k_channel *curchan = ah->curchan; | |
637 | ||
638 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
639 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | |
640 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
641 | ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); | |
642 | ||
643 | ah->curchan = curchan; | |
644 | } | |
645 | ||
285f2dda | 646 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 647 | { |
285f2dda S |
648 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
649 | ||
55624204 S |
650 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
651 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
652 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 S |
653 | IEEE80211_HW_SUPPORTS_PS | |
654 | IEEE80211_HW_PS_NULLFUNC_STACK | | |
05df4986 VN |
655 | IEEE80211_HW_SPECTRUM_MGMT | |
656 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; | |
55624204 | 657 | |
5ffaf8a3 LR |
658 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
659 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
660 | ||
55624204 S |
661 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt) |
662 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; | |
663 | ||
664 | hw->wiphy->interface_modes = | |
665 | BIT(NL80211_IFTYPE_AP) | | |
e51f3eff | 666 | BIT(NL80211_IFTYPE_WDS) | |
55624204 S |
667 | BIT(NL80211_IFTYPE_STATION) | |
668 | BIT(NL80211_IFTYPE_ADHOC) | | |
669 | BIT(NL80211_IFTYPE_MESH_POINT); | |
670 | ||
008443de LR |
671 | if (AR_SREV_5416(sc->sc_ah)) |
672 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
55624204 S |
673 | |
674 | hw->queues = 4; | |
675 | hw->max_rates = 4; | |
676 | hw->channel_change_time = 5000; | |
677 | hw->max_listen_interval = 10; | |
65896510 | 678 | hw->max_rate_tries = 10; |
55624204 S |
679 | hw->sta_data_size = sizeof(struct ath_node); |
680 | hw->vif_data_size = sizeof(struct ath_vif); | |
681 | ||
6e5c2b4e | 682 | #ifdef CONFIG_ATH9K_RATE_CONTROL |
55624204 | 683 | hw->rate_control_algorithm = "ath9k_rate_control"; |
6e5c2b4e | 684 | #endif |
55624204 | 685 | |
d4659912 | 686 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
55624204 S |
687 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
688 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
d4659912 | 689 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
55624204 S |
690 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
691 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
285f2dda S |
692 | |
693 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { | |
d4659912 | 694 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
285f2dda | 695 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); |
d4659912 | 696 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
285f2dda S |
697 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); |
698 | } | |
699 | ||
700 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
701 | } |
702 | ||
285f2dda | 703 | int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, |
55624204 S |
704 | const struct ath_bus_ops *bus_ops) |
705 | { | |
706 | struct ieee80211_hw *hw = sc->hw; | |
9fa23e17 | 707 | struct ath_wiphy *aphy = hw->priv; |
55624204 S |
708 | struct ath_common *common; |
709 | struct ath_hw *ah; | |
285f2dda | 710 | int error = 0; |
55624204 S |
711 | struct ath_regulatory *reg; |
712 | ||
285f2dda S |
713 | /* Bring up device */ |
714 | error = ath9k_init_softc(devid, sc, subsysid, bus_ops); | |
55624204 | 715 | if (error != 0) |
285f2dda | 716 | goto error_init; |
55624204 S |
717 | |
718 | ah = sc->sc_ah; | |
719 | common = ath9k_hw_common(ah); | |
285f2dda | 720 | ath9k_set_hw_capab(sc, hw); |
55624204 | 721 | |
285f2dda | 722 | /* Initialize regulatory */ |
55624204 S |
723 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
724 | ath9k_reg_notifier); | |
725 | if (error) | |
285f2dda | 726 | goto error_regd; |
55624204 S |
727 | |
728 | reg = &common->regulatory; | |
729 | ||
285f2dda | 730 | /* Setup TX DMA */ |
55624204 S |
731 | error = ath_tx_init(sc, ATH_TXBUF); |
732 | if (error != 0) | |
285f2dda | 733 | goto error_tx; |
55624204 | 734 | |
285f2dda | 735 | /* Setup RX DMA */ |
55624204 S |
736 | error = ath_rx_init(sc, ATH_RXBUF); |
737 | if (error != 0) | |
285f2dda | 738 | goto error_rx; |
55624204 | 739 | |
babcbc29 FF |
740 | ath9k_init_txpower_limits(sc); |
741 | ||
285f2dda | 742 | /* Register with mac80211 */ |
55624204 | 743 | error = ieee80211_register_hw(hw); |
285f2dda S |
744 | if (error) |
745 | goto error_register; | |
55624204 | 746 | |
285f2dda | 747 | /* Handle world regulatory */ |
55624204 S |
748 | if (!ath_is_world_regd(reg)) { |
749 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
750 | if (error) | |
285f2dda | 751 | goto error_world; |
55624204 S |
752 | } |
753 | ||
347809fc | 754 | INIT_WORK(&sc->hw_check_work, ath_hw_check); |
9f42c2b6 | 755 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); |
285f2dda S |
756 | INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work); |
757 | INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work); | |
758 | sc->wiphy_scheduler_int = msecs_to_jiffies(500); | |
9fa23e17 | 759 | aphy->last_rssi = ATH_RSSI_DUMMY_MARKER; |
55624204 | 760 | |
285f2dda | 761 | ath_init_leds(sc); |
55624204 S |
762 | ath_start_rfkill_poll(sc); |
763 | ||
10598c12 VN |
764 | pm_qos_add_request(&ath9k_pm_qos_req, PM_QOS_CPU_DMA_LATENCY, |
765 | PM_QOS_DEFAULT_VALUE); | |
766 | ||
55624204 S |
767 | return 0; |
768 | ||
285f2dda S |
769 | error_world: |
770 | ieee80211_unregister_hw(hw); | |
771 | error_register: | |
772 | ath_rx_cleanup(sc); | |
773 | error_rx: | |
774 | ath_tx_cleanup(sc); | |
775 | error_tx: | |
776 | /* Nothing */ | |
777 | error_regd: | |
778 | ath9k_deinit_softc(sc); | |
779 | error_init: | |
55624204 S |
780 | return error; |
781 | } | |
782 | ||
783 | /*****************************/ | |
784 | /* De-Initialization */ | |
785 | /*****************************/ | |
786 | ||
285f2dda | 787 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 788 | { |
285f2dda | 789 | int i = 0; |
55624204 | 790 | |
f209f529 FF |
791 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) |
792 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
793 | ||
794 | if (sc->sbands[IEEE80211_BAND_5GHZ].channels) | |
795 | kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels); | |
796 | ||
285f2dda S |
797 | if ((sc->btcoex.no_stomp_timer) && |
798 | sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) | |
799 | ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer); | |
55624204 | 800 | |
285f2dda S |
801 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
802 | if (ATH_TXQ_SETUP(sc, i)) | |
803 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
804 | ||
805 | ath9k_exit_debug(sc->sc_ah); | |
806 | ath9k_hw_deinit(sc->sc_ah); | |
807 | ||
808 | tasklet_kill(&sc->intr_tq); | |
809 | tasklet_kill(&sc->bcon_tasklet); | |
736b3a27 S |
810 | |
811 | kfree(sc->sc_ah); | |
812 | sc->sc_ah = NULL; | |
55624204 S |
813 | } |
814 | ||
285f2dda | 815 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
816 | { |
817 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
818 | int i = 0; |
819 | ||
820 | ath9k_ps_wakeup(sc); | |
821 | ||
55624204 | 822 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 823 | ath_deinit_leds(sc); |
55624204 S |
824 | |
825 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
826 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
827 | if (aphy == NULL) | |
828 | continue; | |
829 | sc->sec_wiphy[i] = NULL; | |
830 | ieee80211_unregister_hw(aphy->hw); | |
831 | ieee80211_free_hw(aphy->hw); | |
832 | } | |
285f2dda | 833 | |
55624204 | 834 | ieee80211_unregister_hw(hw); |
e8364bb8 | 835 | pm_qos_remove_request(&ath9k_pm_qos_req); |
55624204 S |
836 | ath_rx_cleanup(sc); |
837 | ath_tx_cleanup(sc); | |
285f2dda | 838 | ath9k_deinit_softc(sc); |
447a42c2 | 839 | kfree(sc->sec_wiphy); |
55624204 S |
840 | } |
841 | ||
842 | void ath_descdma_cleanup(struct ath_softc *sc, | |
843 | struct ath_descdma *dd, | |
844 | struct list_head *head) | |
845 | { | |
846 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
847 | dd->dd_desc_paddr); | |
848 | ||
849 | INIT_LIST_HEAD(head); | |
850 | kfree(dd->dd_bufptr); | |
851 | memset(dd, 0, sizeof(*dd)); | |
852 | } | |
853 | ||
55624204 S |
854 | /************************/ |
855 | /* Module Hooks */ | |
856 | /************************/ | |
857 | ||
858 | static int __init ath9k_init(void) | |
859 | { | |
860 | int error; | |
861 | ||
862 | /* Register rate control algorithm */ | |
863 | error = ath_rate_control_register(); | |
864 | if (error != 0) { | |
865 | printk(KERN_ERR | |
866 | "ath9k: Unable to register rate control " | |
867 | "algorithm: %d\n", | |
868 | error); | |
869 | goto err_out; | |
870 | } | |
871 | ||
872 | error = ath9k_debug_create_root(); | |
873 | if (error) { | |
874 | printk(KERN_ERR | |
875 | "ath9k: Unable to create debugfs root: %d\n", | |
876 | error); | |
877 | goto err_rate_unregister; | |
878 | } | |
879 | ||
880 | error = ath_pci_init(); | |
881 | if (error < 0) { | |
882 | printk(KERN_ERR | |
883 | "ath9k: No PCI devices found, driver not installed.\n"); | |
884 | error = -ENODEV; | |
885 | goto err_remove_root; | |
886 | } | |
887 | ||
888 | error = ath_ahb_init(); | |
889 | if (error < 0) { | |
890 | error = -ENODEV; | |
891 | goto err_pci_exit; | |
892 | } | |
893 | ||
894 | return 0; | |
895 | ||
896 | err_pci_exit: | |
897 | ath_pci_exit(); | |
898 | ||
899 | err_remove_root: | |
900 | ath9k_debug_remove_root(); | |
901 | err_rate_unregister: | |
902 | ath_rate_control_unregister(); | |
903 | err_out: | |
904 | return error; | |
905 | } | |
906 | module_init(ath9k_init); | |
907 | ||
908 | static void __exit ath9k_exit(void) | |
909 | { | |
910 | ath_ahb_exit(); | |
911 | ath_pci_exit(); | |
912 | ath9k_debug_remove_root(); | |
913 | ath_rate_control_unregister(); | |
914 | printk(KERN_INFO "%s: Driver unloaded\n", dev_info); | |
915 | } | |
916 | module_exit(ath9k_exit); |