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Commit | Line | Data |
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55624204 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
55624204 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
516304b0 JP |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
18 | ||
b7f080cf | 19 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
6fb1b1e1 | 21 | #include <linux/ath9k_platform.h> |
9d9779e7 | 22 | #include <linux/module.h> |
5a0e3ad6 | 23 | |
55624204 S |
24 | #include "ath9k.h" |
25 | ||
26 | static char *dev_info = "ath9k"; | |
27 | ||
28 | MODULE_AUTHOR("Atheros Communications"); | |
29 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
30 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
31 | MODULE_LICENSE("Dual BSD/GPL"); | |
32 | ||
33 | static unsigned int ath9k_debug = ATH_DBG_DEFAULT; | |
34 | module_param_named(debug, ath9k_debug, uint, 0); | |
35 | MODULE_PARM_DESC(debug, "Debugging mask"); | |
36 | ||
3e6109c5 JL |
37 | int ath9k_modparam_nohwcrypt; |
38 | module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444); | |
55624204 S |
39 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); |
40 | ||
93dbbcc4 | 41 | int led_blink; |
9a75c2ff VN |
42 | module_param_named(blink, led_blink, int, 0444); |
43 | MODULE_PARM_DESC(blink, "Enable LED blink on activity"); | |
44 | ||
8f5dcb1c VT |
45 | static int ath9k_btcoex_enable; |
46 | module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444); | |
47 | MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence"); | |
48 | ||
e09f2dc7 SM |
49 | static int ath9k_enable_diversity; |
50 | module_param_named(enable_diversity, ath9k_enable_diversity, int, 0444); | |
51 | MODULE_PARM_DESC(enable_diversity, "Enable Antenna diversity for AR9565"); | |
52 | ||
d584747b | 53 | bool is_ath9k_unloaded; |
55624204 S |
54 | /* We use the hw_value as an index into our private channel structure */ |
55 | ||
56 | #define CHAN2G(_freq, _idx) { \ | |
b1c1d000 | 57 | .band = IEEE80211_BAND_2GHZ, \ |
55624204 S |
58 | .center_freq = (_freq), \ |
59 | .hw_value = (_idx), \ | |
60 | .max_power = 20, \ | |
61 | } | |
62 | ||
63 | #define CHAN5G(_freq, _idx) { \ | |
64 | .band = IEEE80211_BAND_5GHZ, \ | |
65 | .center_freq = (_freq), \ | |
66 | .hw_value = (_idx), \ | |
67 | .max_power = 20, \ | |
68 | } | |
69 | ||
70 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
71 | * on 5 MHz steps, we support the channels which we know | |
72 | * we have calibration data for all cards though to make | |
73 | * this static */ | |
f209f529 | 74 | static const struct ieee80211_channel ath9k_2ghz_chantable[] = { |
55624204 S |
75 | CHAN2G(2412, 0), /* Channel 1 */ |
76 | CHAN2G(2417, 1), /* Channel 2 */ | |
77 | CHAN2G(2422, 2), /* Channel 3 */ | |
78 | CHAN2G(2427, 3), /* Channel 4 */ | |
79 | CHAN2G(2432, 4), /* Channel 5 */ | |
80 | CHAN2G(2437, 5), /* Channel 6 */ | |
81 | CHAN2G(2442, 6), /* Channel 7 */ | |
82 | CHAN2G(2447, 7), /* Channel 8 */ | |
83 | CHAN2G(2452, 8), /* Channel 9 */ | |
84 | CHAN2G(2457, 9), /* Channel 10 */ | |
85 | CHAN2G(2462, 10), /* Channel 11 */ | |
86 | CHAN2G(2467, 11), /* Channel 12 */ | |
87 | CHAN2G(2472, 12), /* Channel 13 */ | |
88 | CHAN2G(2484, 13), /* Channel 14 */ | |
89 | }; | |
90 | ||
91 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
92 | * on 5 MHz steps, we support the channels which we know | |
93 | * we have calibration data for all cards though to make | |
94 | * this static */ | |
f209f529 | 95 | static const struct ieee80211_channel ath9k_5ghz_chantable[] = { |
55624204 S |
96 | /* _We_ call this UNII 1 */ |
97 | CHAN5G(5180, 14), /* Channel 36 */ | |
98 | CHAN5G(5200, 15), /* Channel 40 */ | |
99 | CHAN5G(5220, 16), /* Channel 44 */ | |
100 | CHAN5G(5240, 17), /* Channel 48 */ | |
101 | /* _We_ call this UNII 2 */ | |
102 | CHAN5G(5260, 18), /* Channel 52 */ | |
103 | CHAN5G(5280, 19), /* Channel 56 */ | |
104 | CHAN5G(5300, 20), /* Channel 60 */ | |
105 | CHAN5G(5320, 21), /* Channel 64 */ | |
106 | /* _We_ call this "Middle band" */ | |
107 | CHAN5G(5500, 22), /* Channel 100 */ | |
108 | CHAN5G(5520, 23), /* Channel 104 */ | |
109 | CHAN5G(5540, 24), /* Channel 108 */ | |
110 | CHAN5G(5560, 25), /* Channel 112 */ | |
111 | CHAN5G(5580, 26), /* Channel 116 */ | |
112 | CHAN5G(5600, 27), /* Channel 120 */ | |
113 | CHAN5G(5620, 28), /* Channel 124 */ | |
114 | CHAN5G(5640, 29), /* Channel 128 */ | |
115 | CHAN5G(5660, 30), /* Channel 132 */ | |
116 | CHAN5G(5680, 31), /* Channel 136 */ | |
117 | CHAN5G(5700, 32), /* Channel 140 */ | |
118 | /* _We_ call this UNII 3 */ | |
119 | CHAN5G(5745, 33), /* Channel 149 */ | |
120 | CHAN5G(5765, 34), /* Channel 153 */ | |
121 | CHAN5G(5785, 35), /* Channel 157 */ | |
122 | CHAN5G(5805, 36), /* Channel 161 */ | |
123 | CHAN5G(5825, 37), /* Channel 165 */ | |
124 | }; | |
125 | ||
126 | /* Atheros hardware rate code addition for short premble */ | |
127 | #define SHPCHECK(__hw_rate, __flags) \ | |
128 | ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0) | |
129 | ||
130 | #define RATE(_bitrate, _hw_rate, _flags) { \ | |
131 | .bitrate = (_bitrate), \ | |
132 | .flags = (_flags), \ | |
133 | .hw_value = (_hw_rate), \ | |
134 | .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ | |
135 | } | |
136 | ||
137 | static struct ieee80211_rate ath9k_legacy_rates[] = { | |
138 | RATE(10, 0x1b, 0), | |
139 | RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), | |
140 | RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), | |
141 | RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), | |
142 | RATE(60, 0x0b, 0), | |
143 | RATE(90, 0x0f, 0), | |
144 | RATE(120, 0x0a, 0), | |
145 | RATE(180, 0x0e, 0), | |
146 | RATE(240, 0x09, 0), | |
147 | RATE(360, 0x0d, 0), | |
148 | RATE(480, 0x08, 0), | |
149 | RATE(540, 0x0c, 0), | |
150 | }; | |
151 | ||
0cf55c21 FF |
152 | #ifdef CONFIG_MAC80211_LEDS |
153 | static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = { | |
154 | { .throughput = 0 * 1024, .blink_time = 334 }, | |
155 | { .throughput = 1 * 1024, .blink_time = 260 }, | |
156 | { .throughput = 5 * 1024, .blink_time = 220 }, | |
157 | { .throughput = 10 * 1024, .blink_time = 190 }, | |
158 | { .throughput = 20 * 1024, .blink_time = 170 }, | |
159 | { .throughput = 50 * 1024, .blink_time = 150 }, | |
160 | { .throughput = 70 * 1024, .blink_time = 130 }, | |
161 | { .throughput = 100 * 1024, .blink_time = 110 }, | |
162 | { .throughput = 200 * 1024, .blink_time = 80 }, | |
163 | { .throughput = 300 * 1024, .blink_time = 50 }, | |
164 | }; | |
165 | #endif | |
166 | ||
285f2dda | 167 | static void ath9k_deinit_softc(struct ath_softc *sc); |
55624204 S |
168 | |
169 | /* | |
170 | * Read and write, they both share the same lock. We do this to serialize | |
171 | * reads and writes on Atheros 802.11n PCI devices only. This is required | |
172 | * as the FIFO on these devices can only accept sanely 2 requests. | |
173 | */ | |
174 | ||
175 | static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
176 | { | |
177 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
178 | struct ath_common *common = ath9k_hw_common(ah); | |
179 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
180 | ||
f3eef645 | 181 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
182 | unsigned long flags; |
183 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
184 | iowrite32(val, sc->mem + reg_offset); | |
185 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
186 | } else | |
187 | iowrite32(val, sc->mem + reg_offset); | |
188 | } | |
189 | ||
190 | static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset) | |
191 | { | |
192 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
193 | struct ath_common *common = ath9k_hw_common(ah); | |
194 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
195 | u32 val; | |
196 | ||
f3eef645 | 197 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
55624204 S |
198 | unsigned long flags; |
199 | spin_lock_irqsave(&sc->sc_serial_rw, flags); | |
200 | val = ioread32(sc->mem + reg_offset); | |
201 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); | |
202 | } else | |
203 | val = ioread32(sc->mem + reg_offset); | |
204 | return val; | |
205 | } | |
206 | ||
5479de6e RM |
207 | static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset, |
208 | u32 set, u32 clr) | |
209 | { | |
210 | u32 val; | |
211 | ||
212 | val = ioread32(sc->mem + reg_offset); | |
213 | val &= ~clr; | |
214 | val |= set; | |
215 | iowrite32(val, sc->mem + reg_offset); | |
216 | ||
217 | return val; | |
218 | } | |
219 | ||
845e03c9 FF |
220 | static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr) |
221 | { | |
222 | struct ath_hw *ah = (struct ath_hw *) hw_priv; | |
223 | struct ath_common *common = ath9k_hw_common(ah); | |
224 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
225 | unsigned long uninitialized_var(flags); | |
226 | u32 val; | |
227 | ||
f3eef645 | 228 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { |
845e03c9 | 229 | spin_lock_irqsave(&sc->sc_serial_rw, flags); |
5479de6e | 230 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); |
845e03c9 | 231 | spin_unlock_irqrestore(&sc->sc_serial_rw, flags); |
5479de6e RM |
232 | } else |
233 | val = __ath9k_reg_rmw(sc, reg_offset, set, clr); | |
845e03c9 FF |
234 | |
235 | return val; | |
236 | } | |
237 | ||
55624204 S |
238 | /**************************/ |
239 | /* Initialization */ | |
240 | /**************************/ | |
241 | ||
242 | static void setup_ht_cap(struct ath_softc *sc, | |
243 | struct ieee80211_sta_ht_cap *ht_info) | |
244 | { | |
3bb065a7 FF |
245 | struct ath_hw *ah = sc->sc_ah; |
246 | struct ath_common *common = ath9k_hw_common(ah); | |
55624204 | 247 | u8 tx_streams, rx_streams; |
3bb065a7 | 248 | int i, max_streams; |
55624204 S |
249 | |
250 | ht_info->ht_supported = true; | |
251 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
252 | IEEE80211_HT_CAP_SM_PS | | |
253 | IEEE80211_HT_CAP_SGI_40 | | |
254 | IEEE80211_HT_CAP_DSSSCCK40; | |
255 | ||
b0a33448 LR |
256 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) |
257 | ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING; | |
258 | ||
6473d24d VT |
259 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) |
260 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
261 | ||
55624204 S |
262 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
263 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
264 | ||
e41db61d | 265 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) |
7f1c7a6a | 266 | max_streams = 1; |
e7104195 MSS |
267 | else if (AR_SREV_9462(ah)) |
268 | max_streams = 2; | |
7f1c7a6a | 269 | else if (AR_SREV_9300_20_OR_LATER(ah)) |
3bb065a7 FF |
270 | max_streams = 3; |
271 | else | |
272 | max_streams = 2; | |
273 | ||
7a37081e | 274 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
074a8c0d FF |
275 | if (max_streams >= 2) |
276 | ht_info->cap |= IEEE80211_HT_CAP_TX_STBC; | |
277 | ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); | |
278 | } | |
279 | ||
55624204 S |
280 | /* set up supported mcs set */ |
281 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
82b2d334 FF |
282 | tx_streams = ath9k_cmn_count_streams(ah->txchainmask, max_streams); |
283 | rx_streams = ath9k_cmn_count_streams(ah->rxchainmask, max_streams); | |
3bb065a7 | 284 | |
d2182b69 | 285 | ath_dbg(common, CONFIG, "TX streams %d, RX streams: %d\n", |
226afe68 | 286 | tx_streams, rx_streams); |
55624204 S |
287 | |
288 | if (tx_streams != rx_streams) { | |
55624204 S |
289 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
290 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
291 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
292 | } | |
293 | ||
3bb065a7 FF |
294 | for (i = 0; i < rx_streams; i++) |
295 | ht_info->mcs.rx_mask[i] = 0xff; | |
55624204 S |
296 | |
297 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; | |
298 | } | |
299 | ||
300 | static int ath9k_reg_notifier(struct wiphy *wiphy, | |
301 | struct regulatory_request *request) | |
302 | { | |
303 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
9ac58615 | 304 | struct ath_softc *sc = hw->priv; |
687f545e RM |
305 | struct ath_hw *ah = sc->sc_ah; |
306 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
307 | int ret; | |
308 | ||
309 | ret = ath_reg_notifier_apply(wiphy, request, reg); | |
310 | ||
311 | /* Set tx power */ | |
312 | if (ah->curchan) { | |
313 | sc->config.txpowlimit = 2 * ah->curchan->chan->max_power; | |
314 | ath9k_ps_wakeup(sc); | |
315 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false); | |
316 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; | |
317 | ath9k_ps_restore(sc); | |
318 | } | |
55624204 | 319 | |
687f545e | 320 | return ret; |
55624204 S |
321 | } |
322 | ||
323 | /* | |
324 | * This function will allocate both the DMA descriptor structure, and the | |
325 | * buffers it contains. These are used to contain the descriptors used | |
326 | * by the system. | |
327 | */ | |
328 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
329 | struct list_head *head, const char *name, | |
4adfcded | 330 | int nbuf, int ndesc, bool is_tx) |
55624204 | 331 | { |
55624204 | 332 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4adfcded | 333 | u8 *ds; |
55624204 | 334 | struct ath_buf *bf; |
4adfcded | 335 | int i, bsize, error, desc_len; |
55624204 | 336 | |
d2182b69 | 337 | ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
226afe68 | 338 | name, nbuf, ndesc); |
55624204 S |
339 | |
340 | INIT_LIST_HEAD(head); | |
4adfcded VT |
341 | |
342 | if (is_tx) | |
343 | desc_len = sc->sc_ah->caps.tx_desc_len; | |
344 | else | |
345 | desc_len = sizeof(struct ath_desc); | |
346 | ||
55624204 | 347 | /* ath_desc must be a multiple of DWORDs */ |
4adfcded | 348 | if ((desc_len % 4) != 0) { |
3800276a | 349 | ath_err(common, "ath_desc not DWORD aligned\n"); |
4adfcded | 350 | BUG_ON((desc_len % 4) != 0); |
55624204 S |
351 | error = -ENOMEM; |
352 | goto fail; | |
353 | } | |
354 | ||
4adfcded | 355 | dd->dd_desc_len = desc_len * nbuf * ndesc; |
55624204 S |
356 | |
357 | /* | |
358 | * Need additional DMA memory because we can't use | |
359 | * descriptors that cross the 4K page boundary. Assume | |
360 | * one skipped descriptor per 4K page. | |
361 | */ | |
362 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
363 | u32 ndesc_skipped = | |
364 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
365 | u32 dma_len; | |
366 | ||
367 | while (ndesc_skipped) { | |
4adfcded | 368 | dma_len = ndesc_skipped * desc_len; |
55624204 S |
369 | dd->dd_desc_len += dma_len; |
370 | ||
371 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
ee289b64 | 372 | } |
55624204 S |
373 | } |
374 | ||
375 | /* allocate descriptors */ | |
376 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, | |
377 | &dd->dd_desc_paddr, GFP_KERNEL); | |
378 | if (dd->dd_desc == NULL) { | |
379 | error = -ENOMEM; | |
380 | goto fail; | |
381 | } | |
4adfcded | 382 | ds = (u8 *) dd->dd_desc; |
d2182b69 | 383 | ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
226afe68 JP |
384 | name, ds, (u32) dd->dd_desc_len, |
385 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); | |
55624204 S |
386 | |
387 | /* allocate buffers */ | |
388 | bsize = sizeof(struct ath_buf) * nbuf; | |
389 | bf = kzalloc(bsize, GFP_KERNEL); | |
390 | if (bf == NULL) { | |
391 | error = -ENOMEM; | |
392 | goto fail2; | |
393 | } | |
394 | dd->dd_bufptr = bf; | |
395 | ||
4adfcded | 396 | for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) { |
55624204 S |
397 | bf->bf_desc = ds; |
398 | bf->bf_daddr = DS2PHYS(dd, ds); | |
399 | ||
400 | if (!(sc->sc_ah->caps.hw_caps & | |
401 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
402 | /* | |
403 | * Skip descriptor addresses which can cause 4KB | |
404 | * boundary crossing (addr + length) with a 32 dword | |
405 | * descriptor fetch. | |
406 | */ | |
407 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
408 | BUG_ON((caddr_t) bf->bf_desc >= | |
409 | ((caddr_t) dd->dd_desc + | |
410 | dd->dd_desc_len)); | |
411 | ||
4adfcded | 412 | ds += (desc_len * ndesc); |
55624204 S |
413 | bf->bf_desc = ds; |
414 | bf->bf_daddr = DS2PHYS(dd, ds); | |
415 | } | |
416 | } | |
417 | list_add_tail(&bf->list, head); | |
418 | } | |
419 | return 0; | |
420 | fail2: | |
421 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
422 | dd->dd_desc_paddr); | |
423 | fail: | |
424 | memset(dd, 0, sizeof(*dd)); | |
425 | return error; | |
55624204 S |
426 | } |
427 | ||
285f2dda S |
428 | static int ath9k_init_queues(struct ath_softc *sc) |
429 | { | |
285f2dda S |
430 | int i = 0; |
431 | ||
285f2dda | 432 | sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah); |
55624204 | 433 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
55624204 S |
434 | |
435 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; | |
436 | ath_cabq_update(sc); | |
437 | ||
bea843c7 | 438 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
066dae93 | 439 | sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i); |
60f2d1d5 | 440 | sc->tx.txq_map[i]->mac80211_qnum = i; |
7702e788 | 441 | sc->tx.txq_max_pending[i] = ATH_MAX_QDEPTH; |
60f2d1d5 | 442 | } |
285f2dda | 443 | return 0; |
285f2dda S |
444 | } |
445 | ||
f209f529 | 446 | static int ath9k_init_channels_rates(struct ath_softc *sc) |
285f2dda | 447 | { |
f209f529 FF |
448 | void *channels; |
449 | ||
cac4220b FF |
450 | BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) + |
451 | ARRAY_SIZE(ath9k_5ghz_chantable) != | |
452 | ATH9K_NUM_CHANNELS); | |
453 | ||
d4659912 | 454 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { |
f209f529 FF |
455 | channels = kmemdup(ath9k_2ghz_chantable, |
456 | sizeof(ath9k_2ghz_chantable), GFP_KERNEL); | |
457 | if (!channels) | |
458 | return -ENOMEM; | |
459 | ||
460 | sc->sbands[IEEE80211_BAND_2GHZ].channels = channels; | |
285f2dda S |
461 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; |
462 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = | |
463 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
464 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; | |
465 | sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates = | |
466 | ARRAY_SIZE(ath9k_legacy_rates); | |
55624204 S |
467 | } |
468 | ||
d4659912 | 469 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { |
f209f529 FF |
470 | channels = kmemdup(ath9k_5ghz_chantable, |
471 | sizeof(ath9k_5ghz_chantable), GFP_KERNEL); | |
472 | if (!channels) { | |
473 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) | |
474 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
475 | return -ENOMEM; | |
476 | } | |
477 | ||
478 | sc->sbands[IEEE80211_BAND_5GHZ].channels = channels; | |
285f2dda S |
479 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; |
480 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = | |
481 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
482 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
483 | ath9k_legacy_rates + 4; | |
484 | sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates = | |
485 | ARRAY_SIZE(ath9k_legacy_rates) - 4; | |
486 | } | |
f209f529 | 487 | return 0; |
285f2dda | 488 | } |
55624204 | 489 | |
285f2dda S |
490 | static void ath9k_init_misc(struct ath_softc *sc) |
491 | { | |
492 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
493 | int i = 0; | |
3d4e20f2 | 494 | |
285f2dda | 495 | setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc); |
55624204 | 496 | |
aaa1ec46 | 497 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
55624204 | 498 | sc->config.txpowlimit = ATH_TXPOWER_MAX; |
364734fa | 499 | memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); |
285f2dda | 500 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; |
55624204 | 501 | |
7545daf4 | 502 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) |
55624204 | 503 | sc->beacon.bslot[i] = NULL; |
102885a5 VT |
504 | |
505 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
506 | sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT; | |
285f2dda | 507 | } |
55624204 | 508 | |
eb93e891 | 509 | static int ath9k_init_softc(u16 devid, struct ath_softc *sc, |
285f2dda S |
510 | const struct ath_bus_ops *bus_ops) |
511 | { | |
6fb1b1e1 | 512 | struct ath9k_platform_data *pdata = sc->dev->platform_data; |
285f2dda S |
513 | struct ath_hw *ah = NULL; |
514 | struct ath_common *common; | |
515 | int ret = 0, i; | |
516 | int csz = 0; | |
55624204 | 517 | |
285f2dda S |
518 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); |
519 | if (!ah) | |
520 | return -ENOMEM; | |
521 | ||
233536e1 | 522 | ah->hw = sc->hw; |
285f2dda | 523 | ah->hw_version.devid = devid; |
f9f84e96 FF |
524 | ah->reg_ops.read = ath9k_ioread32; |
525 | ah->reg_ops.write = ath9k_iowrite32; | |
845e03c9 | 526 | ah->reg_ops.rmw = ath9k_reg_rmw; |
e8fe7336 | 527 | atomic_set(&ah->intr_ref_cnt, -1); |
285f2dda S |
528 | sc->sc_ah = ah; |
529 | ||
8e92d3f2 ZK |
530 | sc->dfs_detector = dfs_pattern_detector_init(NL80211_DFS_UNSET); |
531 | ||
6de66dd9 | 532 | if (!pdata) { |
a05b5d45 | 533 | ah->ah_flags |= AH_USE_EEPROM; |
6de66dd9 FF |
534 | sc->sc_ah->led_pin = -1; |
535 | } else { | |
536 | sc->sc_ah->gpio_mask = pdata->gpio_mask; | |
537 | sc->sc_ah->gpio_val = pdata->gpio_val; | |
538 | sc->sc_ah->led_pin = pdata->led_pin; | |
f2f5f2a1 | 539 | ah->is_clk_25mhz = pdata->is_clk_25mhz; |
3762561a | 540 | ah->get_mac_revision = pdata->get_mac_revision; |
7d95847c | 541 | ah->external_reset = pdata->external_reset; |
6de66dd9 | 542 | } |
a05b5d45 | 543 | |
285f2dda | 544 | common = ath9k_hw_common(ah); |
f9f84e96 | 545 | common->ops = &ah->reg_ops; |
285f2dda S |
546 | common->bus_ops = bus_ops; |
547 | common->ah = ah; | |
548 | common->hw = sc->hw; | |
549 | common->priv = sc; | |
550 | common->debug_mask = ath9k_debug; | |
8f5dcb1c | 551 | common->btcoex_enabled = ath9k_btcoex_enable == 1; |
05c0be2f | 552 | common->disable_ani = false; |
e09f2dc7 SM |
553 | |
554 | /* | |
555 | * Enable Antenna diversity only when BTCOEX is disabled | |
556 | * and the user manually requests the feature. | |
557 | */ | |
558 | if (!common->btcoex_enabled && ath9k_enable_diversity) | |
559 | common->antenna_diversity = 1; | |
560 | ||
20b25744 | 561 | spin_lock_init(&common->cc_lock); |
285f2dda | 562 | |
285f2dda S |
563 | spin_lock_init(&sc->sc_serial_rw); |
564 | spin_lock_init(&sc->sc_pm_lock); | |
565 | mutex_init(&sc->mutex); | |
7f010c93 BG |
566 | #ifdef CONFIG_ATH9K_DEBUGFS |
567 | spin_lock_init(&sc->nodes_lock); | |
568 | INIT_LIST_HEAD(&sc->nodes); | |
5baec742 FF |
569 | #endif |
570 | #ifdef CONFIG_ATH9K_MAC_DEBUG | |
571 | spin_lock_init(&sc->debug.samp_lock); | |
7f010c93 | 572 | #endif |
285f2dda | 573 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); |
fb6e252f | 574 | tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, |
285f2dda S |
575 | (unsigned long)sc); |
576 | ||
aaa1ec46 SM |
577 | INIT_WORK(&sc->hw_reset_work, ath_reset_work); |
578 | INIT_WORK(&sc->hw_check_work, ath_hw_check); | |
579 | INIT_WORK(&sc->paprd_work, ath_paprd_calibrate); | |
580 | INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work); | |
581 | setup_timer(&sc->rx_poll_timer, ath_rx_poll, (unsigned long)sc); | |
582 | ||
285f2dda S |
583 | /* |
584 | * Cache line size is used to size and align various | |
585 | * structures used to communicate with the hardware. | |
586 | */ | |
587 | ath_read_cachesize(common, &csz); | |
588 | common->cachelsz = csz << 2; /* convert to bytes */ | |
589 | ||
d70357d5 | 590 | /* Initializes the hardware for all supported chipsets */ |
285f2dda | 591 | ret = ath9k_hw_init(ah); |
d70357d5 | 592 | if (ret) |
285f2dda | 593 | goto err_hw; |
55624204 | 594 | |
6fb1b1e1 FF |
595 | if (pdata && pdata->macaddr) |
596 | memcpy(common->macaddr, pdata->macaddr, ETH_ALEN); | |
597 | ||
285f2dda S |
598 | ret = ath9k_init_queues(sc); |
599 | if (ret) | |
600 | goto err_queues; | |
601 | ||
602 | ret = ath9k_init_btcoex(sc); | |
603 | if (ret) | |
604 | goto err_btcoex; | |
605 | ||
f209f529 FF |
606 | ret = ath9k_init_channels_rates(sc); |
607 | if (ret) | |
608 | goto err_btcoex; | |
609 | ||
f82b4bde | 610 | ath9k_cmn_init_crypto(sc->sc_ah); |
285f2dda | 611 | ath9k_init_misc(sc); |
8f176a3a | 612 | ath_fill_led_pin(sc); |
285f2dda | 613 | |
d09f5f4c SM |
614 | if (common->bus_ops->aspm_init) |
615 | common->bus_ops->aspm_init(common); | |
616 | ||
55624204 | 617 | return 0; |
285f2dda S |
618 | |
619 | err_btcoex: | |
55624204 S |
620 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
621 | if (ATH_TXQ_SETUP(sc, i)) | |
622 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
285f2dda | 623 | err_queues: |
285f2dda S |
624 | ath9k_hw_deinit(ah); |
625 | err_hw: | |
55624204 | 626 | |
285f2dda S |
627 | kfree(ah); |
628 | sc->sc_ah = NULL; | |
629 | ||
630 | return ret; | |
55624204 S |
631 | } |
632 | ||
babcbc29 FF |
633 | static void ath9k_init_band_txpower(struct ath_softc *sc, int band) |
634 | { | |
635 | struct ieee80211_supported_band *sband; | |
636 | struct ieee80211_channel *chan; | |
637 | struct ath_hw *ah = sc->sc_ah; | |
babcbc29 FF |
638 | int i; |
639 | ||
640 | sband = &sc->sbands[band]; | |
641 | for (i = 0; i < sband->n_channels; i++) { | |
642 | chan = &sband->channels[i]; | |
643 | ah->curchan = &ah->channels[chan->hw_value]; | |
644 | ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20); | |
645 | ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true); | |
babcbc29 FF |
646 | } |
647 | } | |
648 | ||
649 | static void ath9k_init_txpower_limits(struct ath_softc *sc) | |
650 | { | |
651 | struct ath_hw *ah = sc->sc_ah; | |
652 | struct ath9k_channel *curchan = ah->curchan; | |
653 | ||
654 | if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
655 | ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ); | |
656 | if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
657 | ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ); | |
658 | ||
659 | ah->curchan = curchan; | |
660 | } | |
661 | ||
43c35284 FF |
662 | void ath9k_reload_chainmask_settings(struct ath_softc *sc) |
663 | { | |
664 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)) | |
665 | return; | |
666 | ||
667 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) | |
668 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); | |
669 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) | |
670 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); | |
671 | } | |
672 | ||
20c8e8dc FF |
673 | static const struct ieee80211_iface_limit if_limits[] = { |
674 | { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) | | |
675 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
676 | BIT(NL80211_IFTYPE_WDS) }, | |
677 | { .max = 8, .types = | |
678 | #ifdef CONFIG_MAC80211_MESH | |
679 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
680 | #endif | |
681 | BIT(NL80211_IFTYPE_AP) | | |
682 | BIT(NL80211_IFTYPE_P2P_GO) }, | |
683 | }; | |
684 | ||
685 | static const struct ieee80211_iface_combination if_comb = { | |
686 | .limits = if_limits, | |
687 | .n_limits = ARRAY_SIZE(if_limits), | |
688 | .max_interfaces = 2048, | |
689 | .num_different_channels = 1, | |
aebc0d40 | 690 | .beacon_int_infra_match = true, |
20c8e8dc | 691 | }; |
43c35284 | 692 | |
285f2dda | 693 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
55624204 | 694 | { |
43c35284 FF |
695 | struct ath_hw *ah = sc->sc_ah; |
696 | struct ath_common *common = ath9k_hw_common(ah); | |
285f2dda | 697 | |
55624204 S |
698 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
699 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
700 | IEEE80211_HW_SIGNAL_DBM | | |
55624204 S |
701 | IEEE80211_HW_SUPPORTS_PS | |
702 | IEEE80211_HW_PS_NULLFUNC_STACK | | |
05df4986 | 703 | IEEE80211_HW_SPECTRUM_MGMT | |
bd8027a7 | 704 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; |
55624204 | 705 | |
5ffaf8a3 LR |
706 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
707 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
708 | ||
3e6109c5 | 709 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt) |
55624204 S |
710 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; |
711 | ||
712 | hw->wiphy->interface_modes = | |
c426ee24 JB |
713 | BIT(NL80211_IFTYPE_P2P_GO) | |
714 | BIT(NL80211_IFTYPE_P2P_CLIENT) | | |
55624204 | 715 | BIT(NL80211_IFTYPE_AP) | |
e51f3eff | 716 | BIT(NL80211_IFTYPE_WDS) | |
55624204 S |
717 | BIT(NL80211_IFTYPE_STATION) | |
718 | BIT(NL80211_IFTYPE_ADHOC) | | |
719 | BIT(NL80211_IFTYPE_MESH_POINT); | |
720 | ||
20c8e8dc FF |
721 | hw->wiphy->iface_combinations = &if_comb; |
722 | hw->wiphy->n_iface_combinations = 1; | |
723 | ||
008443de LR |
724 | if (AR_SREV_5416(sc->sc_ah)) |
725 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
55624204 | 726 | |
cfdc9a8b | 727 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; |
fd656234 | 728 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; |
81ddbb5c | 729 | hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; |
cfdc9a8b | 730 | |
9f11e16e MSS |
731 | #ifdef CONFIG_PM_SLEEP |
732 | ||
733 | if ((ah->caps.hw_caps & ATH9K_HW_WOW_DEVICE_CAPABLE) && | |
734 | device_can_wakeup(sc->dev)) { | |
735 | ||
736 | hw->wiphy->wowlan.flags = WIPHY_WOWLAN_MAGIC_PKT | | |
737 | WIPHY_WOWLAN_DISCONNECT; | |
738 | hw->wiphy->wowlan.n_patterns = MAX_NUM_USER_PATTERN; | |
739 | hw->wiphy->wowlan.pattern_min_len = 1; | |
740 | hw->wiphy->wowlan.pattern_max_len = MAX_PATTERN_SIZE; | |
741 | ||
742 | } | |
743 | ||
744 | atomic_set(&sc->wow_sleep_proc_intr, -1); | |
745 | atomic_set(&sc->wow_got_bmiss_intr, -1); | |
746 | ||
747 | #endif | |
748 | ||
55624204 S |
749 | hw->queues = 4; |
750 | hw->max_rates = 4; | |
751 | hw->channel_change_time = 5000; | |
195ca3b1 | 752 | hw->max_listen_interval = 1; |
65896510 | 753 | hw->max_rate_tries = 10; |
55624204 S |
754 | hw->sta_data_size = sizeof(struct ath_node); |
755 | hw->vif_data_size = sizeof(struct ath_vif); | |
756 | ||
43c35284 FF |
757 | hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1; |
758 | hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1; | |
759 | ||
760 | /* single chain devices with rx diversity */ | |
761 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) | |
762 | hw->wiphy->available_antennas_rx = BIT(0) | BIT(1); | |
763 | ||
764 | sc->ant_rx = hw->wiphy->available_antennas_rx; | |
765 | sc->ant_tx = hw->wiphy->available_antennas_tx; | |
766 | ||
6e5c2b4e | 767 | #ifdef CONFIG_ATH9K_RATE_CONTROL |
55624204 | 768 | hw->rate_control_algorithm = "ath9k_rate_control"; |
6e5c2b4e | 769 | #endif |
55624204 | 770 | |
d4659912 | 771 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) |
55624204 S |
772 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
773 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
d4659912 | 774 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) |
55624204 S |
775 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = |
776 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
285f2dda | 777 | |
43c35284 | 778 | ath9k_reload_chainmask_settings(sc); |
285f2dda S |
779 | |
780 | SET_IEEE80211_PERM_ADDR(hw, common->macaddr); | |
55624204 S |
781 | } |
782 | ||
eb93e891 | 783 | int ath9k_init_device(u16 devid, struct ath_softc *sc, |
55624204 S |
784 | const struct ath_bus_ops *bus_ops) |
785 | { | |
786 | struct ieee80211_hw *hw = sc->hw; | |
787 | struct ath_common *common; | |
788 | struct ath_hw *ah; | |
285f2dda | 789 | int error = 0; |
55624204 S |
790 | struct ath_regulatory *reg; |
791 | ||
285f2dda | 792 | /* Bring up device */ |
eb93e891 | 793 | error = ath9k_init_softc(devid, sc, bus_ops); |
55624204 | 794 | if (error != 0) |
285f2dda | 795 | goto error_init; |
55624204 S |
796 | |
797 | ah = sc->sc_ah; | |
798 | common = ath9k_hw_common(ah); | |
285f2dda | 799 | ath9k_set_hw_capab(sc, hw); |
55624204 | 800 | |
285f2dda | 801 | /* Initialize regulatory */ |
55624204 S |
802 | error = ath_regd_init(&common->regulatory, sc->hw->wiphy, |
803 | ath9k_reg_notifier); | |
804 | if (error) | |
285f2dda | 805 | goto error_regd; |
55624204 S |
806 | |
807 | reg = &common->regulatory; | |
808 | ||
285f2dda | 809 | /* Setup TX DMA */ |
55624204 S |
810 | error = ath_tx_init(sc, ATH_TXBUF); |
811 | if (error != 0) | |
285f2dda | 812 | goto error_tx; |
55624204 | 813 | |
285f2dda | 814 | /* Setup RX DMA */ |
55624204 S |
815 | error = ath_rx_init(sc, ATH_RXBUF); |
816 | if (error != 0) | |
285f2dda | 817 | goto error_rx; |
55624204 | 818 | |
babcbc29 FF |
819 | ath9k_init_txpower_limits(sc); |
820 | ||
0cf55c21 FF |
821 | #ifdef CONFIG_MAC80211_LEDS |
822 | /* must be initialized before ieee80211_register_hw */ | |
823 | sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw, | |
824 | IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink, | |
825 | ARRAY_SIZE(ath9k_tpt_blink)); | |
826 | #endif | |
827 | ||
285f2dda | 828 | /* Register with mac80211 */ |
55624204 | 829 | error = ieee80211_register_hw(hw); |
285f2dda S |
830 | if (error) |
831 | goto error_register; | |
55624204 | 832 | |
eb272441 BG |
833 | error = ath9k_init_debug(ah); |
834 | if (error) { | |
3800276a | 835 | ath_err(common, "Unable to create debugfs files\n"); |
eb272441 BG |
836 | goto error_world; |
837 | } | |
838 | ||
285f2dda | 839 | /* Handle world regulatory */ |
55624204 S |
840 | if (!ath_is_world_regd(reg)) { |
841 | error = regulatory_hint(hw->wiphy, reg->alpha2); | |
842 | if (error) | |
285f2dda | 843 | goto error_world; |
55624204 S |
844 | } |
845 | ||
285f2dda | 846 | ath_init_leds(sc); |
55624204 S |
847 | ath_start_rfkill_poll(sc); |
848 | ||
849 | return 0; | |
850 | ||
285f2dda S |
851 | error_world: |
852 | ieee80211_unregister_hw(hw); | |
853 | error_register: | |
854 | ath_rx_cleanup(sc); | |
855 | error_rx: | |
856 | ath_tx_cleanup(sc); | |
857 | error_tx: | |
858 | /* Nothing */ | |
859 | error_regd: | |
860 | ath9k_deinit_softc(sc); | |
861 | error_init: | |
55624204 S |
862 | return error; |
863 | } | |
864 | ||
865 | /*****************************/ | |
866 | /* De-Initialization */ | |
867 | /*****************************/ | |
868 | ||
285f2dda | 869 | static void ath9k_deinit_softc(struct ath_softc *sc) |
55624204 | 870 | { |
285f2dda | 871 | int i = 0; |
55624204 | 872 | |
f209f529 FF |
873 | if (sc->sbands[IEEE80211_BAND_2GHZ].channels) |
874 | kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels); | |
875 | ||
876 | if (sc->sbands[IEEE80211_BAND_5GHZ].channels) | |
877 | kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels); | |
878 | ||
5908120f | 879 | ath9k_deinit_btcoex(sc); |
19686ddf | 880 | |
285f2dda S |
881 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
882 | if (ATH_TXQ_SETUP(sc, i)) | |
883 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
884 | ||
285f2dda | 885 | ath9k_hw_deinit(sc->sc_ah); |
8e92d3f2 ZK |
886 | if (sc->dfs_detector != NULL) |
887 | sc->dfs_detector->exit(sc->dfs_detector); | |
285f2dda | 888 | |
736b3a27 S |
889 | kfree(sc->sc_ah); |
890 | sc->sc_ah = NULL; | |
55624204 S |
891 | } |
892 | ||
285f2dda | 893 | void ath9k_deinit_device(struct ath_softc *sc) |
55624204 S |
894 | { |
895 | struct ieee80211_hw *hw = sc->hw; | |
55624204 S |
896 | |
897 | ath9k_ps_wakeup(sc); | |
898 | ||
55624204 | 899 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
285f2dda | 900 | ath_deinit_leds(sc); |
55624204 | 901 | |
c7c18060 RM |
902 | ath9k_ps_restore(sc); |
903 | ||
55624204 S |
904 | ieee80211_unregister_hw(hw); |
905 | ath_rx_cleanup(sc); | |
906 | ath_tx_cleanup(sc); | |
285f2dda | 907 | ath9k_deinit_softc(sc); |
55624204 S |
908 | } |
909 | ||
910 | void ath_descdma_cleanup(struct ath_softc *sc, | |
911 | struct ath_descdma *dd, | |
912 | struct list_head *head) | |
913 | { | |
914 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, | |
915 | dd->dd_desc_paddr); | |
916 | ||
917 | INIT_LIST_HEAD(head); | |
918 | kfree(dd->dd_bufptr); | |
919 | memset(dd, 0, sizeof(*dd)); | |
920 | } | |
921 | ||
55624204 S |
922 | /************************/ |
923 | /* Module Hooks */ | |
924 | /************************/ | |
925 | ||
926 | static int __init ath9k_init(void) | |
927 | { | |
928 | int error; | |
929 | ||
930 | /* Register rate control algorithm */ | |
931 | error = ath_rate_control_register(); | |
932 | if (error != 0) { | |
516304b0 JP |
933 | pr_err("Unable to register rate control algorithm: %d\n", |
934 | error); | |
55624204 S |
935 | goto err_out; |
936 | } | |
937 | ||
55624204 S |
938 | error = ath_pci_init(); |
939 | if (error < 0) { | |
516304b0 | 940 | pr_err("No PCI devices found, driver not installed\n"); |
55624204 | 941 | error = -ENODEV; |
eb272441 | 942 | goto err_rate_unregister; |
55624204 S |
943 | } |
944 | ||
945 | error = ath_ahb_init(); | |
946 | if (error < 0) { | |
947 | error = -ENODEV; | |
948 | goto err_pci_exit; | |
949 | } | |
950 | ||
951 | return 0; | |
952 | ||
953 | err_pci_exit: | |
954 | ath_pci_exit(); | |
955 | ||
55624204 S |
956 | err_rate_unregister: |
957 | ath_rate_control_unregister(); | |
958 | err_out: | |
959 | return error; | |
960 | } | |
961 | module_init(ath9k_init); | |
962 | ||
963 | static void __exit ath9k_exit(void) | |
964 | { | |
d584747b | 965 | is_ath9k_unloaded = true; |
55624204 S |
966 | ath_ahb_exit(); |
967 | ath_pci_exit(); | |
55624204 | 968 | ath_rate_control_unregister(); |
516304b0 | 969 | pr_info("%s: Driver unloaded\n", dev_info); |
55624204 S |
970 | } |
971 | module_exit(ath9k_exit); |