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Commit | Line | Data |
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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ff37e337 S |
21 | static void ath_update_txpow(struct ath_softc *sc) |
22 | { | |
cbe61d8a | 23 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 | 24 | |
17d7904d S |
25 | if (sc->curtxpow != sc->config.txpowlimit) { |
26 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 | 27 | /* read back in case value is clamped */ |
9cc3271f | 28 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; |
ff37e337 S |
29 | } |
30 | } | |
31 | ||
32 | static u8 parse_mpdudensity(u8 mpdudensity) | |
33 | { | |
34 | /* | |
35 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
36 | * 0 for no restriction | |
37 | * 1 for 1/4 us | |
38 | * 2 for 1/2 us | |
39 | * 3 for 1 us | |
40 | * 4 for 2 us | |
41 | * 5 for 4 us | |
42 | * 6 for 8 us | |
43 | * 7 for 16 us | |
44 | */ | |
45 | switch (mpdudensity) { | |
46 | case 0: | |
47 | return 0; | |
48 | case 1: | |
49 | case 2: | |
50 | case 3: | |
51 | /* Our lower layer calculations limit our precision to | |
52 | 1 microsecond */ | |
53 | return 1; | |
54 | case 4: | |
55 | return 2; | |
56 | case 5: | |
57 | return 4; | |
58 | case 6: | |
59 | return 8; | |
60 | case 7: | |
61 | return 16; | |
62 | default: | |
63 | return 0; | |
64 | } | |
65 | } | |
66 | ||
82880a7c VT |
67 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
68 | struct ieee80211_hw *hw) | |
69 | { | |
70 | struct ieee80211_channel *curchan = hw->conf.channel; | |
71 | struct ath9k_channel *channel; | |
72 | u8 chan_idx; | |
73 | ||
74 | chan_idx = curchan->hw_value; | |
75 | channel = &sc->sc_ah->channels[chan_idx]; | |
76 | ath9k_update_ichannel(sc, hw, channel); | |
77 | return channel; | |
78 | } | |
79 | ||
55624204 | 80 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
81 | { |
82 | unsigned long flags; | |
83 | bool ret; | |
84 | ||
9ecdef4b LR |
85 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
86 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
87 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
88 | |
89 | return ret; | |
90 | } | |
91 | ||
a91d75ae LR |
92 | void ath9k_ps_wakeup(struct ath_softc *sc) |
93 | { | |
898c914a | 94 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae LR |
95 | unsigned long flags; |
96 | ||
97 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
98 | if (++sc->ps_usecount != 1) | |
99 | goto unlock; | |
100 | ||
9ecdef4b | 101 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 102 | |
898c914a FF |
103 | /* |
104 | * While the hardware is asleep, the cycle counters contain no | |
105 | * useful data. Better clear them now so that they don't mess up | |
106 | * survey data results. | |
107 | */ | |
108 | spin_lock(&common->cc_lock); | |
109 | ath_hw_cycle_counters_update(common); | |
110 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
111 | spin_unlock(&common->cc_lock); | |
112 | ||
a91d75ae LR |
113 | unlock: |
114 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
115 | } | |
116 | ||
117 | void ath9k_ps_restore(struct ath_softc *sc) | |
118 | { | |
898c914a | 119 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae LR |
120 | unsigned long flags; |
121 | ||
122 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
123 | if (--sc->ps_usecount != 0) | |
124 | goto unlock; | |
125 | ||
898c914a FF |
126 | spin_lock(&common->cc_lock); |
127 | ath_hw_cycle_counters_update(common); | |
128 | spin_unlock(&common->cc_lock); | |
129 | ||
1dbfd9d4 VN |
130 | if (sc->ps_idle) |
131 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
132 | else if (sc->ps_enabled && | |
133 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
134 | PS_WAIT_FOR_CAB | |
135 | PS_WAIT_FOR_PSPOLL_DATA | | |
136 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 137 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
138 | |
139 | unlock: | |
140 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
141 | } | |
142 | ||
5ee08656 FF |
143 | static void ath_start_ani(struct ath_common *common) |
144 | { | |
145 | struct ath_hw *ah = common->ah; | |
146 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
147 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
148 | ||
149 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
150 | return; | |
151 | ||
152 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
153 | return; | |
154 | ||
155 | common->ani.longcal_timer = timestamp; | |
156 | common->ani.shortcal_timer = timestamp; | |
157 | common->ani.checkani_timer = timestamp; | |
158 | ||
159 | mod_timer(&common->ani.timer, | |
160 | jiffies + | |
161 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
162 | } | |
163 | ||
3430098a FF |
164 | static void ath_update_survey_nf(struct ath_softc *sc, int channel) |
165 | { | |
166 | struct ath_hw *ah = sc->sc_ah; | |
167 | struct ath9k_channel *chan = &ah->channels[channel]; | |
168 | struct survey_info *survey = &sc->survey[channel]; | |
169 | ||
170 | if (chan->noisefloor) { | |
171 | survey->filled |= SURVEY_INFO_NOISE_DBM; | |
172 | survey->noise = chan->noisefloor; | |
173 | } | |
174 | } | |
175 | ||
176 | static void ath_update_survey_stats(struct ath_softc *sc) | |
177 | { | |
178 | struct ath_hw *ah = sc->sc_ah; | |
179 | struct ath_common *common = ath9k_hw_common(ah); | |
180 | int pos = ah->curchan - &ah->channels[0]; | |
181 | struct survey_info *survey = &sc->survey[pos]; | |
182 | struct ath_cycle_counters *cc = &common->cc_survey; | |
183 | unsigned int div = common->clockrate * 1000; | |
184 | ||
0845735e FF |
185 | if (!ah->curchan) |
186 | return; | |
187 | ||
898c914a FF |
188 | if (ah->power_mode == ATH9K_PM_AWAKE) |
189 | ath_hw_cycle_counters_update(common); | |
3430098a FF |
190 | |
191 | if (cc->cycles > 0) { | |
192 | survey->filled |= SURVEY_INFO_CHANNEL_TIME | | |
193 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
194 | SURVEY_INFO_CHANNEL_TIME_RX | | |
195 | SURVEY_INFO_CHANNEL_TIME_TX; | |
196 | survey->channel_time += cc->cycles / div; | |
197 | survey->channel_time_busy += cc->rx_busy / div; | |
198 | survey->channel_time_rx += cc->rx_frame / div; | |
199 | survey->channel_time_tx += cc->tx_frame / div; | |
200 | } | |
201 | memset(cc, 0, sizeof(*cc)); | |
202 | ||
203 | ath_update_survey_nf(sc, pos); | |
204 | } | |
205 | ||
ff37e337 S |
206 | /* |
207 | * Set/change channels. If the channel is really being changed, it's done | |
208 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
209 | * DMA, then restart stuff. | |
210 | */ | |
0e2dedf9 JM |
211 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
212 | struct ath9k_channel *hchan) | |
ff37e337 | 213 | { |
20bd2a09 | 214 | struct ath_wiphy *aphy = hw->priv; |
cbe61d8a | 215 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 216 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 217 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 218 | bool fastcc = true, stopped; |
ae8d2858 | 219 | struct ieee80211_channel *channel = hw->conf.channel; |
20bd2a09 | 220 | struct ath9k_hw_cal_data *caldata = NULL; |
ae8d2858 | 221 | int r; |
ff37e337 S |
222 | |
223 | if (sc->sc_flags & SC_OP_INVALID) | |
224 | return -EIO; | |
225 | ||
5ee08656 FF |
226 | del_timer_sync(&common->ani.timer); |
227 | cancel_work_sync(&sc->paprd_work); | |
228 | cancel_work_sync(&sc->hw_check_work); | |
229 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
230 | ||
3cbb5dd7 VN |
231 | ath9k_ps_wakeup(sc); |
232 | ||
c0d7c7af LR |
233 | /* |
234 | * This is only performed if the channel settings have | |
235 | * actually changed. | |
236 | * | |
237 | * To switch channels clear any pending DMA operations; | |
238 | * wait long enough for the RX fifo to drain, reset the | |
239 | * hardware at the new frequency, and then re-enable | |
240 | * the relevant bits of the h/w. | |
241 | */ | |
242 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 243 | ath_drain_all_txq(sc, false); |
5e848f78 LR |
244 | |
245 | spin_lock_bh(&sc->rx.pcu_lock); | |
246 | ||
c0d7c7af | 247 | stopped = ath_stoprecv(sc); |
ff37e337 | 248 | |
c0d7c7af LR |
249 | /* XXX: do not flush receive queue here. We don't want |
250 | * to flush data frames already in queue because of | |
251 | * changing channel. */ | |
ff37e337 | 252 | |
5ee08656 | 253 | if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL)) |
c0d7c7af LR |
254 | fastcc = false; |
255 | ||
20bd2a09 FF |
256 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) |
257 | caldata = &aphy->caldata; | |
258 | ||
c46917bb | 259 | ath_print(common, ATH_DBG_CONFIG, |
1e51b2ff | 260 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", |
c46917bb | 261 | sc->sc_ah->curchan->channel, |
1e51b2ff LR |
262 | channel->center_freq, conf_is_ht40(conf), |
263 | fastcc); | |
ff37e337 | 264 | |
c0d7c7af LR |
265 | spin_lock_bh(&sc->sc_resetlock); |
266 | ||
20bd2a09 | 267 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); |
c0d7c7af | 268 | if (r) { |
c46917bb | 269 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 270 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
271 | "reset status %d\n", |
272 | channel->center_freq, r); | |
c0d7c7af | 273 | spin_unlock_bh(&sc->sc_resetlock); |
5e848f78 | 274 | spin_unlock_bh(&sc->rx.pcu_lock); |
3989279c | 275 | goto ps_restore; |
ff37e337 | 276 | } |
c0d7c7af LR |
277 | spin_unlock_bh(&sc->sc_resetlock); |
278 | ||
c0d7c7af | 279 | if (ath_startrecv(sc) != 0) { |
c46917bb LR |
280 | ath_print(common, ATH_DBG_FATAL, |
281 | "Unable to restart recv logic\n"); | |
3989279c | 282 | r = -EIO; |
5e848f78 | 283 | spin_unlock_bh(&sc->rx.pcu_lock); |
3989279c | 284 | goto ps_restore; |
c0d7c7af LR |
285 | } |
286 | ||
5e848f78 LR |
287 | spin_unlock_bh(&sc->rx.pcu_lock); |
288 | ||
c0d7c7af | 289 | ath_update_txpow(sc); |
3069168c | 290 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c | 291 | |
48a6a468 LR |
292 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) { |
293 | ath_beacon_config(sc, NULL); | |
5ee08656 | 294 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
48a6a468 | 295 | ath_start_ani(common); |
5ee08656 FF |
296 | } |
297 | ||
3989279c | 298 | ps_restore: |
3cbb5dd7 | 299 | ath9k_ps_restore(sc); |
3989279c | 300 | return r; |
ff37e337 S |
301 | } |
302 | ||
9f42c2b6 FF |
303 | static void ath_paprd_activate(struct ath_softc *sc) |
304 | { | |
305 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 306 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 307 | struct ath_common *common = ath9k_hw_common(ah); |
9f42c2b6 FF |
308 | int chain; |
309 | ||
20bd2a09 | 310 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
311 | return; |
312 | ||
313 | ath9k_ps_wakeup(sc); | |
ddfef792 | 314 | ar9003_paprd_enable(ah, false); |
9f42c2b6 | 315 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
9094537c | 316 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
317 | continue; |
318 | ||
20bd2a09 | 319 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
320 | } |
321 | ||
322 | ar9003_paprd_enable(ah, true); | |
323 | ath9k_ps_restore(sc); | |
324 | } | |
325 | ||
326 | void ath_paprd_calibrate(struct work_struct *work) | |
327 | { | |
328 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
329 | struct ieee80211_hw *hw = sc->hw; | |
330 | struct ath_hw *ah = sc->sc_ah; | |
331 | struct ieee80211_hdr *hdr; | |
332 | struct sk_buff *skb = NULL; | |
333 | struct ieee80211_tx_info *tx_info; | |
334 | int band = hw->conf.channel->band; | |
335 | struct ieee80211_supported_band *sband = &sc->sbands[band]; | |
336 | struct ath_tx_control txctl; | |
20bd2a09 | 337 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 338 | struct ath_common *common = ath9k_hw_common(ah); |
9f42c2b6 FF |
339 | int qnum, ftype; |
340 | int chain_ok = 0; | |
341 | int chain; | |
342 | int len = 1800; | |
343 | int time_left; | |
344 | int i; | |
345 | ||
20bd2a09 FF |
346 | if (!caldata) |
347 | return; | |
348 | ||
9f42c2b6 FF |
349 | skb = alloc_skb(len, GFP_KERNEL); |
350 | if (!skb) | |
351 | return; | |
352 | ||
353 | tx_info = IEEE80211_SKB_CB(skb); | |
354 | ||
355 | skb_put(skb, len); | |
356 | memset(skb->data, 0, len); | |
357 | hdr = (struct ieee80211_hdr *)skb->data; | |
358 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
359 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 360 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
361 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
362 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
363 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
364 | ||
365 | memset(&txctl, 0, sizeof(txctl)); | |
366 | qnum = sc->tx.hwq_map[WME_AC_BE]; | |
367 | txctl.txq = &sc->tx.txq[qnum]; | |
368 | ||
47399f1a | 369 | ath9k_ps_wakeup(sc); |
9f42c2b6 FF |
370 | ar9003_paprd_init_table(ah); |
371 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { | |
9094537c | 372 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
373 | continue; |
374 | ||
375 | chain_ok = 0; | |
376 | memset(tx_info, 0, sizeof(*tx_info)); | |
377 | tx_info->band = band; | |
378 | ||
379 | for (i = 0; i < 4; i++) { | |
380 | tx_info->control.rates[i].idx = sband->n_bitrates - 1; | |
381 | tx_info->control.rates[i].count = 6; | |
382 | } | |
383 | ||
384 | init_completion(&sc->paprd_complete); | |
385 | ar9003_paprd_setup_gain_table(ah, chain); | |
386 | txctl.paprd = BIT(chain); | |
387 | if (ath_tx_start(hw, skb, &txctl) != 0) | |
388 | break; | |
389 | ||
390 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
ca369eb4 | 391 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); |
9f42c2b6 FF |
392 | if (!time_left) { |
393 | ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | |
394 | "Timeout waiting for paprd training on " | |
395 | "TX chain %d\n", | |
396 | chain); | |
ca369eb4 | 397 | goto fail_paprd; |
9f42c2b6 FF |
398 | } |
399 | ||
400 | if (!ar9003_paprd_is_done(ah)) | |
401 | break; | |
402 | ||
20bd2a09 | 403 | if (ar9003_paprd_create_curve(ah, caldata, chain) != 0) |
9f42c2b6 FF |
404 | break; |
405 | ||
406 | chain_ok = 1; | |
407 | } | |
408 | kfree_skb(skb); | |
409 | ||
410 | if (chain_ok) { | |
20bd2a09 | 411 | caldata->paprd_done = true; |
9f42c2b6 FF |
412 | ath_paprd_activate(sc); |
413 | } | |
414 | ||
ca369eb4 | 415 | fail_paprd: |
9f42c2b6 FF |
416 | ath9k_ps_restore(sc); |
417 | } | |
418 | ||
ff37e337 S |
419 | /* |
420 | * This routine performs the periodic noise floor calibration function | |
421 | * that is used to adjust and optimize the chip performance. This | |
422 | * takes environmental changes (location, temperature) into account. | |
423 | * When the task is complete, it reschedules itself depending on the | |
424 | * appropriate interval that was calculated. | |
425 | */ | |
55624204 | 426 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 427 | { |
20977d3e S |
428 | struct ath_softc *sc = (struct ath_softc *)data; |
429 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 430 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
431 | bool longcal = false; |
432 | bool shortcal = false; | |
433 | bool aniflag = false; | |
434 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e | 435 | u32 cal_interval, short_cal_interval, long_cal_interval; |
b5bfc568 | 436 | unsigned long flags; |
6044474e FF |
437 | |
438 | if (ah->caldata && ah->caldata->nfcal_interference) | |
439 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
440 | else | |
441 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 442 | |
20977d3e S |
443 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
444 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 445 | |
1ffc1c61 JM |
446 | /* Only calibrate if awake */ |
447 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
448 | goto set_timer; | |
449 | ||
450 | ath9k_ps_wakeup(sc); | |
451 | ||
ff37e337 | 452 | /* Long calibration runs independently of short calibration. */ |
6044474e | 453 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 454 | longcal = true; |
c46917bb | 455 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 456 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
457 | } |
458 | ||
17d7904d | 459 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
460 | if (!common->ani.caldone) { |
461 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 462 | shortcal = true; |
c46917bb LR |
463 | ath_print(common, ATH_DBG_ANI, |
464 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
465 | common->ani.shortcal_timer = timestamp; |
466 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
467 | } |
468 | } else { | |
3d536acf | 469 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 470 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
471 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
472 | if (common->ani.caldone) | |
473 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
474 | } |
475 | } | |
476 | ||
477 | /* Verify whether we must check ANI */ | |
e36b27af LR |
478 | if ((timestamp - common->ani.checkani_timer) >= |
479 | ah->config.ani_poll_interval) { | |
ff37e337 | 480 | aniflag = true; |
3d536acf | 481 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
482 | } |
483 | ||
484 | /* Skip all processing if there's nothing to do. */ | |
485 | if (longcal || shortcal || aniflag) { | |
486 | /* Call ANI routine if necessary */ | |
b5bfc568 FF |
487 | if (aniflag) { |
488 | spin_lock_irqsave(&common->cc_lock, flags); | |
22e66a4c | 489 | ath9k_hw_ani_monitor(ah, ah->curchan); |
3430098a | 490 | ath_update_survey_stats(sc); |
b5bfc568 FF |
491 | spin_unlock_irqrestore(&common->cc_lock, flags); |
492 | } | |
ff37e337 S |
493 | |
494 | /* Perform calibration if necessary */ | |
495 | if (longcal || shortcal) { | |
3d536acf | 496 | common->ani.caldone = |
43c27613 LR |
497 | ath9k_hw_calibrate(ah, |
498 | ah->curchan, | |
499 | common->rx_chainmask, | |
500 | longcal); | |
ff37e337 S |
501 | } |
502 | } | |
503 | ||
1ffc1c61 JM |
504 | ath9k_ps_restore(sc); |
505 | ||
20977d3e | 506 | set_timer: |
ff37e337 S |
507 | /* |
508 | * Set timer interval based on previous results. | |
509 | * The interval must be the shortest necessary to satisfy ANI, | |
510 | * short calibration and long calibration. | |
511 | */ | |
aac9207e | 512 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 513 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
514 | cal_interval = min(cal_interval, |
515 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 516 | if (!common->ani.caldone) |
20977d3e | 517 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 518 | |
3d536acf | 519 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
520 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
521 | if (!ah->caldata->paprd_done) | |
9f42c2b6 FF |
522 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
523 | else | |
524 | ath_paprd_activate(sc); | |
525 | } | |
ff37e337 S |
526 | } |
527 | ||
528 | /* | |
529 | * Update tx/rx chainmask. For legacy association, | |
530 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
531 | * the chainmask configuration, for bt coexistence, use |
532 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 533 | */ |
0e2dedf9 | 534 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 535 | { |
af03abec | 536 | struct ath_hw *ah = sc->sc_ah; |
43c27613 | 537 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 538 | |
5ee08656 | 539 | if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht || |
766ec4a9 | 540 | (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { |
43c27613 LR |
541 | common->tx_chainmask = ah->caps.tx_chainmask; |
542 | common->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 | 543 | } else { |
43c27613 LR |
544 | common->tx_chainmask = 1; |
545 | common->rx_chainmask = 1; | |
ff37e337 S |
546 | } |
547 | ||
43c27613 | 548 | ath_print(common, ATH_DBG_CONFIG, |
c46917bb | 549 | "tx chmask: %d, rx chmask: %d\n", |
43c27613 LR |
550 | common->tx_chainmask, |
551 | common->rx_chainmask); | |
ff37e337 S |
552 | } |
553 | ||
554 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
555 | { | |
556 | struct ath_node *an; | |
557 | ||
558 | an = (struct ath_node *)sta->drv_priv; | |
559 | ||
87792efc | 560 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 561 | ath_tx_node_init(sc, an); |
9e98ac65 | 562 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
563 | sta->ht_cap.ampdu_factor); |
564 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 565 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 566 | } |
ff37e337 S |
567 | } |
568 | ||
569 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
570 | { | |
571 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
572 | ||
573 | if (sc->sc_flags & SC_OP_TXAGGR) | |
574 | ath_tx_node_cleanup(sc, an); | |
575 | } | |
576 | ||
347809fc FF |
577 | void ath_hw_check(struct work_struct *work) |
578 | { | |
579 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
580 | int i; | |
581 | ||
582 | ath9k_ps_wakeup(sc); | |
583 | ||
584 | for (i = 0; i < 3; i++) { | |
585 | if (ath9k_hw_check_alive(sc->sc_ah)) | |
586 | goto out; | |
587 | ||
588 | msleep(1); | |
589 | } | |
fac6b6a0 | 590 | ath_reset(sc, true); |
347809fc FF |
591 | |
592 | out: | |
593 | ath9k_ps_restore(sc); | |
594 | } | |
595 | ||
55624204 | 596 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
597 | { |
598 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 599 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 600 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 601 | |
17d7904d | 602 | u32 status = sc->intrstatus; |
b5c80475 | 603 | u32 rxmask; |
ff37e337 | 604 | |
153e080d VT |
605 | ath9k_ps_wakeup(sc); |
606 | ||
347809fc | 607 | if (status & ATH9K_INT_FATAL) { |
fac6b6a0 | 608 | ath_reset(sc, true); |
153e080d | 609 | ath9k_ps_restore(sc); |
ff37e337 | 610 | return; |
063d8be3 | 611 | } |
ff37e337 | 612 | |
347809fc FF |
613 | if (!ath9k_hw_check_alive(ah)) |
614 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); | |
615 | ||
b5c80475 FF |
616 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
617 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
618 | ATH9K_INT_RXORN); | |
619 | else | |
620 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
621 | ||
622 | if (status & rxmask) { | |
b79b33c4 | 623 | spin_lock_bh(&sc->rx.pcu_lock); |
b5c80475 FF |
624 | |
625 | /* Check for high priority Rx first */ | |
626 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
627 | (status & ATH9K_INT_RXHP)) | |
628 | ath_rx_tasklet(sc, 0, true); | |
629 | ||
630 | ath_rx_tasklet(sc, 0, false); | |
b79b33c4 | 631 | spin_unlock_bh(&sc->rx.pcu_lock); |
ff37e337 S |
632 | } |
633 | ||
e5003249 VT |
634 | if (status & ATH9K_INT_TX) { |
635 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
636 | ath_tx_edma_tasklet(sc); | |
637 | else | |
638 | ath_tx_tasklet(sc); | |
639 | } | |
063d8be3 | 640 | |
96148326 | 641 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
642 | /* |
643 | * TSF sync does not look correct; remain awake to sync with | |
644 | * the next Beacon. | |
645 | */ | |
c46917bb LR |
646 | ath_print(common, ATH_DBG_PS, |
647 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 648 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
649 | } |
650 | ||
766ec4a9 | 651 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
652 | if (status & ATH9K_INT_GENTIMER) |
653 | ath_gen_timer_isr(sc->sc_ah); | |
654 | ||
ff37e337 | 655 | /* re-enable hardware interrupt */ |
3069168c | 656 | ath9k_hw_set_interrupts(ah, ah->imask); |
153e080d | 657 | ath9k_ps_restore(sc); |
ff37e337 S |
658 | } |
659 | ||
6baff7f9 | 660 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 661 | { |
063d8be3 S |
662 | #define SCHED_INTR ( \ |
663 | ATH9K_INT_FATAL | \ | |
664 | ATH9K_INT_RXORN | \ | |
665 | ATH9K_INT_RXEOL | \ | |
666 | ATH9K_INT_RX | \ | |
b5c80475 FF |
667 | ATH9K_INT_RXLP | \ |
668 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
669 | ATH9K_INT_TX | \ |
670 | ATH9K_INT_BMISS | \ | |
671 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
672 | ATH9K_INT_TSFOOR | \ |
673 | ATH9K_INT_GENTIMER) | |
063d8be3 | 674 | |
ff37e337 | 675 | struct ath_softc *sc = dev; |
cbe61d8a | 676 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 677 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
678 | enum ath9k_int status; |
679 | bool sched = false; | |
680 | ||
063d8be3 S |
681 | /* |
682 | * The hardware is not ready/present, don't | |
683 | * touch anything. Note this can happen early | |
684 | * on if the IRQ is shared. | |
685 | */ | |
686 | if (sc->sc_flags & SC_OP_INVALID) | |
687 | return IRQ_NONE; | |
ff37e337 | 688 | |
063d8be3 S |
689 | |
690 | /* shared irq, not for us */ | |
691 | ||
153e080d | 692 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 693 | return IRQ_NONE; |
063d8be3 S |
694 | |
695 | /* | |
696 | * Figure out the reason(s) for the interrupt. Note | |
697 | * that the hal returns a pseudo-ISR that may include | |
698 | * bits we haven't explicitly enabled so we mask the | |
699 | * value to insure we only process bits we requested. | |
700 | */ | |
701 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 702 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 703 | |
063d8be3 S |
704 | /* |
705 | * If there are no status bits set, then this interrupt was not | |
706 | * for me (should have been caught above). | |
707 | */ | |
153e080d | 708 | if (!status) |
063d8be3 | 709 | return IRQ_NONE; |
ff37e337 | 710 | |
063d8be3 S |
711 | /* Cache the status */ |
712 | sc->intrstatus = status; | |
713 | ||
714 | if (status & SCHED_INTR) | |
715 | sched = true; | |
716 | ||
717 | /* | |
718 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
719 | * chip immediately. | |
720 | */ | |
b5c80475 FF |
721 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
722 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
723 | goto chip_reset; |
724 | ||
08578b8f LR |
725 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
726 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
727 | |
728 | spin_lock(&common->cc_lock); | |
729 | ath_hw_cycle_counters_update(common); | |
08578b8f | 730 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
731 | spin_unlock(&common->cc_lock); |
732 | ||
08578b8f LR |
733 | goto chip_reset; |
734 | } | |
735 | ||
063d8be3 S |
736 | if (status & ATH9K_INT_SWBA) |
737 | tasklet_schedule(&sc->bcon_tasklet); | |
738 | ||
739 | if (status & ATH9K_INT_TXURN) | |
740 | ath9k_hw_updatetxtriglevel(ah, true); | |
741 | ||
b5c80475 FF |
742 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
743 | if (status & ATH9K_INT_RXEOL) { | |
744 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
745 | ath9k_hw_set_interrupts(ah, ah->imask); | |
746 | } | |
747 | } | |
748 | ||
063d8be3 | 749 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 750 | /* |
063d8be3 S |
751 | * Disable interrupts until we service the MIB |
752 | * interrupt; otherwise it will continue to | |
753 | * fire. | |
ff37e337 | 754 | */ |
063d8be3 S |
755 | ath9k_hw_set_interrupts(ah, 0); |
756 | /* | |
757 | * Let the hal handle the event. We assume | |
758 | * it will clear whatever condition caused | |
759 | * the interrupt. | |
760 | */ | |
88eac2da | 761 | spin_lock(&common->cc_lock); |
bfc472bb | 762 | ath9k_hw_proc_mib_event(ah); |
88eac2da | 763 | spin_unlock(&common->cc_lock); |
3069168c | 764 | ath9k_hw_set_interrupts(ah, ah->imask); |
063d8be3 | 765 | } |
ff37e337 | 766 | |
153e080d VT |
767 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
768 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
769 | /* Clear RxAbort bit so that we can |
770 | * receive frames */ | |
9ecdef4b | 771 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 772 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 773 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 774 | } |
063d8be3 S |
775 | |
776 | chip_reset: | |
ff37e337 | 777 | |
817e11de S |
778 | ath_debug_stat_interrupt(sc, status); |
779 | ||
ff37e337 S |
780 | if (sched) { |
781 | /* turn off every interrupt except SWBA */ | |
3069168c | 782 | ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
783 | tasklet_schedule(&sc->intr_tq); |
784 | } | |
785 | ||
786 | return IRQ_HANDLED; | |
063d8be3 S |
787 | |
788 | #undef SCHED_INTR | |
ff37e337 S |
789 | } |
790 | ||
f078f209 | 791 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 792 | struct ieee80211_channel *chan, |
094d05dc | 793 | enum nl80211_channel_type channel_type) |
f078f209 LR |
794 | { |
795 | u32 chanmode = 0; | |
f078f209 LR |
796 | |
797 | switch (chan->band) { | |
798 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
799 | switch(channel_type) { |
800 | case NL80211_CHAN_NO_HT: | |
801 | case NL80211_CHAN_HT20: | |
f078f209 | 802 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
803 | break; |
804 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 805 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
806 | break; |
807 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 808 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
809 | break; |
810 | } | |
f078f209 LR |
811 | break; |
812 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
813 | switch(channel_type) { |
814 | case NL80211_CHAN_NO_HT: | |
815 | case NL80211_CHAN_HT20: | |
f078f209 | 816 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
817 | break; |
818 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 819 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
820 | break; |
821 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 822 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
823 | break; |
824 | } | |
f078f209 LR |
825 | break; |
826 | default: | |
827 | break; | |
828 | } | |
829 | ||
830 | return chanmode; | |
831 | } | |
832 | ||
8feceb67 | 833 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 834 | struct ieee80211_vif *vif, |
8feceb67 | 835 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 836 | { |
f2b2143e | 837 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 838 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 839 | |
8feceb67 | 840 | if (bss_conf->assoc) { |
c46917bb LR |
841 | ath_print(common, ATH_DBG_CONFIG, |
842 | "Bss Info ASSOC %d, bssid: %pM\n", | |
843 | bss_conf->aid, common->curbssid); | |
f078f209 | 844 | |
8feceb67 | 845 | /* New association, store aid */ |
1510718d | 846 | common->curaid = bss_conf->aid; |
f2b2143e | 847 | ath9k_hw_write_associd(ah); |
2664f201 SB |
848 | |
849 | /* | |
850 | * Request a re-configuration of Beacon related timers | |
851 | * on the receipt of the first Beacon frame (i.e., | |
852 | * after time sync with the AP). | |
853 | */ | |
1b04b930 | 854 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 855 | |
8feceb67 | 856 | /* Configure the beacon */ |
2c3db3d5 | 857 | ath_beacon_config(sc, vif); |
f078f209 | 858 | |
8feceb67 | 859 | /* Reset rssi stats */ |
22e66a4c | 860 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 861 | |
6c3118e2 | 862 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 863 | ath_start_ani(common); |
8feceb67 | 864 | } else { |
c46917bb | 865 | ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 866 | common->curaid = 0; |
f38faa31 | 867 | /* Stop ANI */ |
6c3118e2 | 868 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 869 | del_timer_sync(&common->ani.timer); |
f078f209 | 870 | } |
8feceb67 | 871 | } |
f078f209 | 872 | |
68a89116 | 873 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 874 | { |
cbe61d8a | 875 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 876 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 877 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 878 | int r; |
500c064d | 879 | |
3cbb5dd7 | 880 | ath9k_ps_wakeup(sc); |
93b1b37f | 881 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 882 | |
159cd468 VT |
883 | if (!ah->curchan) |
884 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
885 | ||
5e848f78 | 886 | spin_lock_bh(&sc->rx.pcu_lock); |
d2f5b3a6 | 887 | spin_lock_bh(&sc->sc_resetlock); |
20bd2a09 | 888 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 889 | if (r) { |
c46917bb | 890 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 891 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
892 | "reset status %d\n", |
893 | channel->center_freq, r); | |
500c064d VT |
894 | } |
895 | spin_unlock_bh(&sc->sc_resetlock); | |
896 | ||
897 | ath_update_txpow(sc); | |
898 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
899 | ath_print(common, ATH_DBG_FATAL, |
900 | "Unable to restart recv logic\n"); | |
5e848f78 | 901 | spin_unlock_bh(&sc->rx.pcu_lock); |
500c064d VT |
902 | return; |
903 | } | |
5e848f78 | 904 | spin_unlock_bh(&sc->rx.pcu_lock); |
500c064d VT |
905 | |
906 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 907 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
908 | |
909 | /* Re-Enable interrupts */ | |
3069168c | 910 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
911 | |
912 | /* Enable LED */ | |
08fc5c1b | 913 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 914 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 915 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 916 | |
68a89116 | 917 | ieee80211_wake_queues(hw); |
3cbb5dd7 | 918 | ath9k_ps_restore(sc); |
500c064d VT |
919 | } |
920 | ||
68a89116 | 921 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 922 | { |
cbe61d8a | 923 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 924 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 925 | int r; |
500c064d | 926 | |
3cbb5dd7 | 927 | ath9k_ps_wakeup(sc); |
68a89116 | 928 | ieee80211_stop_queues(hw); |
500c064d | 929 | |
982723df VN |
930 | /* |
931 | * Keep the LED on when the radio is disabled | |
932 | * during idle unassociated state. | |
933 | */ | |
934 | if (!sc->ps_idle) { | |
935 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
936 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
937 | } | |
500c064d VT |
938 | |
939 | /* Disable interrupts */ | |
940 | ath9k_hw_set_interrupts(ah, 0); | |
941 | ||
043a0405 | 942 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
5e848f78 LR |
943 | |
944 | spin_lock_bh(&sc->rx.pcu_lock); | |
945 | ||
500c064d VT |
946 | ath_stoprecv(sc); /* turn off frame recv */ |
947 | ath_flushrecv(sc); /* flush recv queue */ | |
948 | ||
159cd468 | 949 | if (!ah->curchan) |
68a89116 | 950 | ah->curchan = ath_get_curchannel(sc, hw); |
159cd468 | 951 | |
500c064d | 952 | spin_lock_bh(&sc->sc_resetlock); |
20bd2a09 | 953 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 954 | if (r) { |
c46917bb | 955 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
f643e51d | 956 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
957 | "reset status %d\n", |
958 | channel->center_freq, r); | |
500c064d VT |
959 | } |
960 | spin_unlock_bh(&sc->sc_resetlock); | |
961 | ||
962 | ath9k_hw_phy_disable(ah); | |
5e848f78 LR |
963 | |
964 | spin_unlock_bh(&sc->rx.pcu_lock); | |
965 | ||
93b1b37f | 966 | ath9k_hw_configpcipowersave(ah, 1, 1); |
3cbb5dd7 | 967 | ath9k_ps_restore(sc); |
9ecdef4b | 968 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
969 | } |
970 | ||
ff37e337 S |
971 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
972 | { | |
cbe61d8a | 973 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 974 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 975 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 976 | int r; |
ff37e337 | 977 | |
2ab81d4a S |
978 | /* Stop ANI */ |
979 | del_timer_sync(&common->ani.timer); | |
980 | ||
cc9c378a S |
981 | ieee80211_stop_queues(hw); |
982 | ||
ff37e337 | 983 | ath9k_hw_set_interrupts(ah, 0); |
043a0405 | 984 | ath_drain_all_txq(sc, retry_tx); |
5e848f78 LR |
985 | |
986 | spin_lock_bh(&sc->rx.pcu_lock); | |
987 | ||
ff37e337 S |
988 | ath_stoprecv(sc); |
989 | ath_flushrecv(sc); | |
990 | ||
991 | spin_lock_bh(&sc->sc_resetlock); | |
20bd2a09 | 992 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); |
ae8d2858 | 993 | if (r) |
c46917bb LR |
994 | ath_print(common, ATH_DBG_FATAL, |
995 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
996 | spin_unlock_bh(&sc->sc_resetlock); |
997 | ||
998 | if (ath_startrecv(sc) != 0) | |
c46917bb LR |
999 | ath_print(common, ATH_DBG_FATAL, |
1000 | "Unable to start recv logic\n"); | |
ff37e337 | 1001 | |
5e848f78 LR |
1002 | spin_unlock_bh(&sc->rx.pcu_lock); |
1003 | ||
ff37e337 S |
1004 | /* |
1005 | * We may be doing a reset in response to a request | |
1006 | * that changes the channel so update any state that | |
1007 | * might change as a result. | |
1008 | */ | |
ff37e337 S |
1009 | ath_update_txpow(sc); |
1010 | ||
52b8ac92 | 1011 | if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL))) |
2c3db3d5 | 1012 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 1013 | |
3069168c | 1014 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
1015 | |
1016 | if (retry_tx) { | |
1017 | int i; | |
1018 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1019 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
1020 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
1021 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
1022 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
1023 | } |
1024 | } | |
1025 | } | |
1026 | ||
cc9c378a S |
1027 | ieee80211_wake_queues(hw); |
1028 | ||
2ab81d4a S |
1029 | /* Start ANI */ |
1030 | ath_start_ani(common); | |
1031 | ||
ae8d2858 | 1032 | return r; |
ff37e337 S |
1033 | } |
1034 | ||
ebe297c3 | 1035 | static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) |
ff37e337 S |
1036 | { |
1037 | int qnum; | |
1038 | ||
1039 | switch (queue) { | |
1040 | case 0: | |
1d2231e2 | 1041 | qnum = sc->tx.hwq_map[WME_AC_VO]; |
ff37e337 S |
1042 | break; |
1043 | case 1: | |
1d2231e2 | 1044 | qnum = sc->tx.hwq_map[WME_AC_VI]; |
ff37e337 S |
1045 | break; |
1046 | case 2: | |
1d2231e2 | 1047 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
1048 | break; |
1049 | case 3: | |
1d2231e2 | 1050 | qnum = sc->tx.hwq_map[WME_AC_BK]; |
ff37e337 S |
1051 | break; |
1052 | default: | |
1d2231e2 | 1053 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
1054 | break; |
1055 | } | |
1056 | ||
1057 | return qnum; | |
1058 | } | |
1059 | ||
1060 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
1061 | { | |
1062 | int qnum; | |
1063 | ||
1064 | switch (queue) { | |
1d2231e2 | 1065 | case WME_AC_VO: |
ff37e337 S |
1066 | qnum = 0; |
1067 | break; | |
1d2231e2 | 1068 | case WME_AC_VI: |
ff37e337 S |
1069 | qnum = 1; |
1070 | break; | |
1d2231e2 | 1071 | case WME_AC_BE: |
ff37e337 S |
1072 | qnum = 2; |
1073 | break; | |
1d2231e2 | 1074 | case WME_AC_BK: |
ff37e337 S |
1075 | qnum = 3; |
1076 | break; | |
1077 | default: | |
1078 | qnum = -1; | |
1079 | break; | |
1080 | } | |
1081 | ||
1082 | return qnum; | |
1083 | } | |
1084 | ||
5f8e077c LR |
1085 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
1086 | * this redundant data */ | |
0e2dedf9 JM |
1087 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
1088 | struct ath9k_channel *ichan) | |
5f8e077c | 1089 | { |
5f8e077c LR |
1090 | struct ieee80211_channel *chan = hw->conf.channel; |
1091 | struct ieee80211_conf *conf = &hw->conf; | |
1092 | ||
1093 | ichan->channel = chan->center_freq; | |
1094 | ichan->chan = chan; | |
1095 | ||
1096 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
1097 | ichan->chanmode = CHANNEL_G; | |
8813262e | 1098 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
1099 | } else { |
1100 | ichan->chanmode = CHANNEL_A; | |
1101 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
1102 | } | |
1103 | ||
25c56eec | 1104 | if (conf_is_ht(conf)) |
5f8e077c LR |
1105 | ichan->chanmode = ath_get_extchanmode(sc, chan, |
1106 | conf->channel_type); | |
5f8e077c LR |
1107 | } |
1108 | ||
ff37e337 S |
1109 | /**********************/ |
1110 | /* mac80211 callbacks */ | |
1111 | /**********************/ | |
1112 | ||
8feceb67 | 1113 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1114 | { |
bce048d7 JM |
1115 | struct ath_wiphy *aphy = hw->priv; |
1116 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1117 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1118 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1119 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1120 | struct ath9k_channel *init_channel; |
82880a7c | 1121 | int r; |
f078f209 | 1122 | |
c46917bb LR |
1123 | ath_print(common, ATH_DBG_CONFIG, |
1124 | "Starting driver with initial channel: %d MHz\n", | |
1125 | curchan->center_freq); | |
f078f209 | 1126 | |
141b38b6 S |
1127 | mutex_lock(&sc->mutex); |
1128 | ||
9580a222 JM |
1129 | if (ath9k_wiphy_started(sc)) { |
1130 | if (sc->chan_idx == curchan->hw_value) { | |
1131 | /* | |
1132 | * Already on the operational channel, the new wiphy | |
1133 | * can be marked active. | |
1134 | */ | |
1135 | aphy->state = ATH_WIPHY_ACTIVE; | |
1136 | ieee80211_wake_queues(hw); | |
1137 | } else { | |
1138 | /* | |
1139 | * Another wiphy is on another channel, start the new | |
1140 | * wiphy in paused state. | |
1141 | */ | |
1142 | aphy->state = ATH_WIPHY_PAUSED; | |
1143 | ieee80211_stop_queues(hw); | |
1144 | } | |
1145 | mutex_unlock(&sc->mutex); | |
1146 | return 0; | |
1147 | } | |
1148 | aphy->state = ATH_WIPHY_ACTIVE; | |
1149 | ||
8feceb67 | 1150 | /* setup initial channel */ |
f078f209 | 1151 | |
82880a7c | 1152 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1153 | |
82880a7c | 1154 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
1155 | |
1156 | /* Reset SERDES registers */ | |
af03abec | 1157 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1158 | |
1159 | /* | |
1160 | * The basic interface to setting the hardware in a good | |
1161 | * state is ``reset''. On return the hardware is known to | |
1162 | * be powered up and with interrupts disabled. This must | |
1163 | * be followed by initialization of the appropriate bits | |
1164 | * and then setup of the interrupt mask. | |
1165 | */ | |
5e848f78 | 1166 | spin_lock_bh(&sc->rx.pcu_lock); |
ff37e337 | 1167 | spin_lock_bh(&sc->sc_resetlock); |
20bd2a09 | 1168 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1169 | if (r) { |
c46917bb LR |
1170 | ath_print(common, ATH_DBG_FATAL, |
1171 | "Unable to reset hardware; reset status %d " | |
1172 | "(freq %u MHz)\n", r, | |
1173 | curchan->center_freq); | |
ff37e337 | 1174 | spin_unlock_bh(&sc->sc_resetlock); |
5e848f78 | 1175 | spin_unlock_bh(&sc->rx.pcu_lock); |
141b38b6 | 1176 | goto mutex_unlock; |
ff37e337 S |
1177 | } |
1178 | spin_unlock_bh(&sc->sc_resetlock); | |
1179 | ||
1180 | /* | |
1181 | * This is needed only to setup initial state | |
1182 | * but it's best done after a reset. | |
1183 | */ | |
1184 | ath_update_txpow(sc); | |
8feceb67 | 1185 | |
ff37e337 S |
1186 | /* |
1187 | * Setup the hardware after reset: | |
1188 | * The receive engine is set going. | |
1189 | * Frame transmit is handled entirely | |
1190 | * in the frame output path; there's nothing to do | |
1191 | * here except setup the interrupt mask. | |
1192 | */ | |
1193 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
1194 | ath_print(common, ATH_DBG_FATAL, |
1195 | "Unable to start recv logic\n"); | |
141b38b6 | 1196 | r = -EIO; |
5e848f78 | 1197 | spin_unlock_bh(&sc->rx.pcu_lock); |
141b38b6 | 1198 | goto mutex_unlock; |
f078f209 | 1199 | } |
5e848f78 | 1200 | spin_unlock_bh(&sc->rx.pcu_lock); |
8feceb67 | 1201 | |
ff37e337 | 1202 | /* Setup our intr mask. */ |
b5c80475 FF |
1203 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1204 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1205 | ATH9K_INT_GLOBAL; | |
1206 | ||
1207 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1208 | ah->imask |= ATH9K_INT_RXHP | |
1209 | ATH9K_INT_RXLP | | |
1210 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1211 | else |
1212 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1213 | |
364734fa | 1214 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1215 | |
af03abec | 1216 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1217 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1218 | |
ff37e337 S |
1219 | sc->sc_flags &= ~SC_OP_INVALID; |
1220 | ||
1221 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
1222 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1223 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 1224 | |
bce048d7 | 1225 | ieee80211_wake_queues(hw); |
ff37e337 | 1226 | |
42935eca | 1227 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1228 | |
766ec4a9 LR |
1229 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1230 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1231 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1232 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1233 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1234 | |
5bb12791 LR |
1235 | if (common->bus_ops->bt_coex_prep) |
1236 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1237 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1238 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1239 | } |
1240 | ||
141b38b6 S |
1241 | mutex_unlock: |
1242 | mutex_unlock(&sc->mutex); | |
1243 | ||
ae8d2858 | 1244 | return r; |
f078f209 LR |
1245 | } |
1246 | ||
8feceb67 VT |
1247 | static int ath9k_tx(struct ieee80211_hw *hw, |
1248 | struct sk_buff *skb) | |
f078f209 | 1249 | { |
528f0c6b | 1250 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
1251 | struct ath_wiphy *aphy = hw->priv; |
1252 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1253 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1254 | struct ath_tx_control txctl; |
1bc14880 BP |
1255 | int padpos, padsize; |
1256 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
84642d6b | 1257 | int qnum; |
528f0c6b | 1258 | |
8089cc47 | 1259 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
c46917bb LR |
1260 | ath_print(common, ATH_DBG_XMIT, |
1261 | "ath9k: %s: TX in unexpected wiphy state " | |
1262 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
ee166a0e JM |
1263 | goto exit; |
1264 | } | |
1265 | ||
96148326 | 1266 | if (sc->ps_enabled) { |
dc8c4585 JM |
1267 | /* |
1268 | * mac80211 does not set PM field for normal data frames, so we | |
1269 | * need to update that based on the current PS mode. | |
1270 | */ | |
1271 | if (ieee80211_is_data(hdr->frame_control) && | |
1272 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1273 | !ieee80211_has_pm(hdr->frame_control)) { | |
c46917bb LR |
1274 | ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " |
1275 | "while in PS mode\n"); | |
dc8c4585 JM |
1276 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1277 | } | |
1278 | } | |
1279 | ||
9a23f9ca JM |
1280 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1281 | /* | |
1282 | * We are using PS-Poll and mac80211 can request TX while in | |
1283 | * power save mode. Need to wake up hardware for the TX to be | |
1284 | * completed and if needed, also for RX of buffered frames. | |
1285 | */ | |
9a23f9ca | 1286 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1287 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1288 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1289 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
c46917bb LR |
1290 | ath_print(common, ATH_DBG_PS, |
1291 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1292 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1293 | } else { |
c46917bb LR |
1294 | ath_print(common, ATH_DBG_PS, |
1295 | "Wake up to complete TX\n"); | |
1b04b930 | 1296 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1297 | } |
1298 | /* | |
1299 | * The actual restore operation will happen only after | |
1300 | * the sc_flags bit is cleared. We are just dropping | |
1301 | * the ps_usecount here. | |
1302 | */ | |
1303 | ath9k_ps_restore(sc); | |
1304 | } | |
1305 | ||
528f0c6b | 1306 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 1307 | |
8feceb67 VT |
1308 | /* |
1309 | * As a temporary workaround, assign seq# here; this will likely need | |
1310 | * to be cleaned up to work better with Beacon transmission and virtual | |
1311 | * BSSes. | |
1312 | */ | |
1313 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
8feceb67 | 1314 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
b77f483f | 1315 | sc->tx.seq_no += 0x10; |
8feceb67 | 1316 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 1317 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 1318 | } |
f078f209 | 1319 | |
8feceb67 | 1320 | /* Add the padding after the header if this is not already done */ |
1bc14880 BP |
1321 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1322 | padsize = padpos & 3; | |
1323 | if (padsize && skb->len>padpos) { | |
8feceb67 VT |
1324 | if (skb_headroom(skb) < padsize) |
1325 | return -1; | |
1326 | skb_push(skb, padsize); | |
1bc14880 | 1327 | memmove(skb->data, skb->data + padsize, padpos); |
8feceb67 VT |
1328 | } |
1329 | ||
84642d6b FF |
1330 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
1331 | txctl.txq = &sc->tx.txq[qnum]; | |
528f0c6b | 1332 | |
c46917bb | 1333 | ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1334 | |
c52f33d0 | 1335 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1336 | ath_print(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1337 | goto exit; |
8feceb67 VT |
1338 | } |
1339 | ||
528f0c6b S |
1340 | return 0; |
1341 | exit: | |
1342 | dev_kfree_skb_any(skb); | |
8feceb67 | 1343 | return 0; |
f078f209 LR |
1344 | } |
1345 | ||
8feceb67 | 1346 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1347 | { |
bce048d7 JM |
1348 | struct ath_wiphy *aphy = hw->priv; |
1349 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1350 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1351 | struct ath_common *common = ath9k_hw_common(ah); |
447a42c2 | 1352 | int i; |
f078f209 | 1353 | |
4c483817 S |
1354 | mutex_lock(&sc->mutex); |
1355 | ||
9580a222 JM |
1356 | aphy->state = ATH_WIPHY_INACTIVE; |
1357 | ||
9a75c2ff VN |
1358 | if (led_blink) |
1359 | cancel_delayed_work_sync(&sc->ath_led_blink_work); | |
1360 | ||
c94dbff7 | 1361 | cancel_delayed_work_sync(&sc->tx_complete_work); |
9f42c2b6 | 1362 | cancel_work_sync(&sc->paprd_work); |
347809fc | 1363 | cancel_work_sync(&sc->hw_check_work); |
c94dbff7 | 1364 | |
447a42c2 RM |
1365 | for (i = 0; i < sc->num_sec_wiphy; i++) { |
1366 | if (sc->sec_wiphy[i]) | |
1367 | break; | |
1368 | } | |
1369 | ||
1370 | if (i == sc->num_sec_wiphy) { | |
c94dbff7 LR |
1371 | cancel_delayed_work_sync(&sc->wiphy_work); |
1372 | cancel_work_sync(&sc->chan_work); | |
1373 | } | |
1374 | ||
9c84b797 | 1375 | if (sc->sc_flags & SC_OP_INVALID) { |
c46917bb | 1376 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1377 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1378 | return; |
1379 | } | |
8feceb67 | 1380 | |
9580a222 JM |
1381 | if (ath9k_wiphy_started(sc)) { |
1382 | mutex_unlock(&sc->mutex); | |
1383 | return; /* another wiphy still in use */ | |
1384 | } | |
1385 | ||
3867cf6a S |
1386 | /* Ensure HW is awake when we try to shut it down. */ |
1387 | ath9k_ps_wakeup(sc); | |
1388 | ||
766ec4a9 | 1389 | if (ah->btcoex_hw.enabled) { |
af03abec | 1390 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1391 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1392 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1393 | } |
1394 | ||
ff37e337 S |
1395 | /* make sure h/w will not generate any interrupt |
1396 | * before setting the invalid flag. */ | |
af03abec | 1397 | ath9k_hw_set_interrupts(ah, 0); |
ff37e337 | 1398 | |
5e848f78 | 1399 | spin_lock_bh(&sc->rx.pcu_lock); |
ff37e337 | 1400 | if (!(sc->sc_flags & SC_OP_INVALID)) { |
043a0405 | 1401 | ath_drain_all_txq(sc, false); |
ff37e337 | 1402 | ath_stoprecv(sc); |
af03abec | 1403 | ath9k_hw_phy_disable(ah); |
ff37e337 | 1404 | } else |
b77f483f | 1405 | sc->rx.rxlink = NULL; |
5e848f78 | 1406 | spin_unlock_bh(&sc->rx.pcu_lock); |
ff37e337 | 1407 | |
ff37e337 | 1408 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1409 | ath9k_hw_disable(ah); |
1410 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
3867cf6a S |
1411 | ath9k_ps_restore(sc); |
1412 | ||
1413 | /* Finally, put the chip in FULL SLEEP mode */ | |
9ecdef4b | 1414 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
ff37e337 S |
1415 | |
1416 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1417 | |
141b38b6 S |
1418 | mutex_unlock(&sc->mutex); |
1419 | ||
c46917bb | 1420 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1421 | } |
1422 | ||
8feceb67 | 1423 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1424 | struct ieee80211_vif *vif) |
f078f209 | 1425 | { |
bce048d7 JM |
1426 | struct ath_wiphy *aphy = hw->priv; |
1427 | struct ath_softc *sc = aphy->sc; | |
3069168c PR |
1428 | struct ath_hw *ah = sc->sc_ah; |
1429 | struct ath_common *common = ath9k_hw_common(ah); | |
1ed32e4f | 1430 | struct ath_vif *avp = (void *)vif->drv_priv; |
d97809db | 1431 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 1432 | int ret = 0; |
8feceb67 | 1433 | |
141b38b6 S |
1434 | mutex_lock(&sc->mutex); |
1435 | ||
1ed32e4f | 1436 | switch (vif->type) { |
05c914fe | 1437 | case NL80211_IFTYPE_STATION: |
d97809db | 1438 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 1439 | break; |
e51f3eff BJ |
1440 | case NL80211_IFTYPE_WDS: |
1441 | ic_opmode = NL80211_IFTYPE_WDS; | |
1442 | break; | |
05c914fe | 1443 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 1444 | case NL80211_IFTYPE_AP: |
9cb5412b | 1445 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
1446 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1447 | ret = -ENOBUFS; | |
1448 | goto out; | |
1449 | } | |
1ed32e4f | 1450 | ic_opmode = vif->type; |
f078f209 LR |
1451 | break; |
1452 | default: | |
c46917bb | 1453 | ath_print(common, ATH_DBG_FATAL, |
1ed32e4f | 1454 | "Interface type %d not yet supported\n", vif->type); |
2c3db3d5 JM |
1455 | ret = -EOPNOTSUPP; |
1456 | goto out; | |
f078f209 LR |
1457 | } |
1458 | ||
c46917bb LR |
1459 | ath_print(common, ATH_DBG_CONFIG, |
1460 | "Attach a VIF of type: %d\n", ic_opmode); | |
8feceb67 | 1461 | |
17d7904d | 1462 | /* Set the VIF opmode */ |
5640b08e S |
1463 | avp->av_opmode = ic_opmode; |
1464 | avp->av_bslot = -1; | |
1465 | ||
2c3db3d5 | 1466 | sc->nvifs++; |
8ca21f01 | 1467 | |
364734fa | 1468 | ath9k_set_bssid_mask(hw, vif); |
8ca21f01 | 1469 | |
2c3db3d5 JM |
1470 | if (sc->nvifs > 1) |
1471 | goto out; /* skip global settings for secondary vif */ | |
1472 | ||
b238e90e | 1473 | if (ic_opmode == NL80211_IFTYPE_AP) { |
3069168c | 1474 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e S |
1475 | sc->sc_flags |= SC_OP_TSF_RESET; |
1476 | } | |
5640b08e | 1477 | |
5640b08e | 1478 | /* Set the device opmode */ |
3069168c | 1479 | ah->opmode = ic_opmode; |
5640b08e | 1480 | |
4e30ffa2 VN |
1481 | /* |
1482 | * Enable MIB interrupts when there are hardware phy counters. | |
1483 | * Note we only do this (at the moment) for station mode. | |
1484 | */ | |
1ed32e4f JB |
1485 | if ((vif->type == NL80211_IFTYPE_STATION) || |
1486 | (vif->type == NL80211_IFTYPE_ADHOC) || | |
1487 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
3448f912 LR |
1488 | if (ah->config.enable_ani) |
1489 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1490 | ah->imask |= ATH9K_INT_TSFOOR; |
4af9cf4f S |
1491 | } |
1492 | ||
3069168c | 1493 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1494 | |
1ed32e4f JB |
1495 | if (vif->type == NL80211_IFTYPE_AP || |
1496 | vif->type == NL80211_IFTYPE_ADHOC || | |
6c3118e2 VT |
1497 | vif->type == NL80211_IFTYPE_MONITOR) { |
1498 | sc->sc_flags |= SC_OP_ANI_RUN; | |
3d536acf | 1499 | ath_start_ani(common); |
6c3118e2 | 1500 | } |
6f255425 | 1501 | |
2c3db3d5 | 1502 | out: |
141b38b6 | 1503 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 1504 | return ret; |
f078f209 LR |
1505 | } |
1506 | ||
8feceb67 | 1507 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1508 | struct ieee80211_vif *vif) |
f078f209 | 1509 | { |
bce048d7 JM |
1510 | struct ath_wiphy *aphy = hw->priv; |
1511 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1512 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1ed32e4f | 1513 | struct ath_vif *avp = (void *)vif->drv_priv; |
2c3db3d5 | 1514 | int i; |
f078f209 | 1515 | |
c46917bb | 1516 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1517 | |
141b38b6 S |
1518 | mutex_lock(&sc->mutex); |
1519 | ||
6f255425 | 1520 | /* Stop ANI */ |
6c3118e2 | 1521 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 1522 | del_timer_sync(&common->ani.timer); |
580f0b8a | 1523 | |
8feceb67 | 1524 | /* Reclaim beacon resources */ |
9cb5412b PE |
1525 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
1526 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
1527 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
5f70a88f | 1528 | ath9k_ps_wakeup(sc); |
b77f483f | 1529 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
5f70a88f | 1530 | ath9k_ps_restore(sc); |
580f0b8a | 1531 | } |
f078f209 | 1532 | |
74401773 | 1533 | ath_beacon_return(sc, avp); |
8feceb67 | 1534 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 1535 | |
2c3db3d5 | 1536 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
1ed32e4f | 1537 | if (sc->beacon.bslot[i] == vif) { |
2c3db3d5 JM |
1538 | printk(KERN_DEBUG "%s: vif had allocated beacon " |
1539 | "slot\n", __func__); | |
1540 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 1541 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
1542 | } |
1543 | } | |
1544 | ||
17d7904d | 1545 | sc->nvifs--; |
141b38b6 S |
1546 | |
1547 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1548 | } |
1549 | ||
fbab7390 | 1550 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1551 | { |
3069168c PR |
1552 | struct ath_hw *ah = sc->sc_ah; |
1553 | ||
3f7c5c10 | 1554 | sc->ps_enabled = true; |
3069168c PR |
1555 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1556 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1557 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1558 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1559 | } |
fdf76622 | 1560 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1561 | } |
3f7c5c10 SB |
1562 | } |
1563 | ||
845d708e SB |
1564 | static void ath9k_disable_ps(struct ath_softc *sc) |
1565 | { | |
1566 | struct ath_hw *ah = sc->sc_ah; | |
1567 | ||
1568 | sc->ps_enabled = false; | |
1569 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1570 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1571 | ath9k_hw_setrxabort(ah, 0); | |
1572 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1573 | PS_WAIT_FOR_CAB | | |
1574 | PS_WAIT_FOR_PSPOLL_DATA | | |
1575 | PS_WAIT_FOR_TX_ACK); | |
1576 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1577 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
1578 | ath9k_hw_set_interrupts(ah, ah->imask); | |
1579 | } | |
1580 | } | |
1581 | ||
1582 | } | |
1583 | ||
e8975581 | 1584 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1585 | { |
bce048d7 JM |
1586 | struct ath_wiphy *aphy = hw->priv; |
1587 | struct ath_softc *sc = aphy->sc; | |
3430098a FF |
1588 | struct ath_hw *ah = sc->sc_ah; |
1589 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1590 | struct ieee80211_conf *conf = &hw->conf; |
194b7c13 | 1591 | bool disable_radio; |
f078f209 | 1592 | |
aa33de09 | 1593 | mutex_lock(&sc->mutex); |
141b38b6 | 1594 | |
194b7c13 LR |
1595 | /* |
1596 | * Leave this as the first check because we need to turn on the | |
1597 | * radio if it was disabled before prior to processing the rest | |
1598 | * of the changes. Likewise we must only disable the radio towards | |
1599 | * the end. | |
1600 | */ | |
64839170 | 1601 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
194b7c13 LR |
1602 | bool enable_radio; |
1603 | bool all_wiphys_idle; | |
1604 | bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); | |
64839170 LR |
1605 | |
1606 | spin_lock_bh(&sc->wiphy_lock); | |
1607 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
194b7c13 LR |
1608 | ath9k_set_wiphy_idle(aphy, idle); |
1609 | ||
11446011 | 1610 | enable_radio = (!idle && all_wiphys_idle); |
194b7c13 LR |
1611 | |
1612 | /* | |
1613 | * After we unlock here its possible another wiphy | |
1614 | * can be re-renabled so to account for that we will | |
1615 | * only disable the radio toward the end of this routine | |
1616 | * if by then all wiphys are still idle. | |
1617 | */ | |
64839170 LR |
1618 | spin_unlock_bh(&sc->wiphy_lock); |
1619 | ||
194b7c13 | 1620 | if (enable_radio) { |
1dbfd9d4 | 1621 | sc->ps_idle = false; |
68a89116 | 1622 | ath_radio_enable(sc, hw); |
c46917bb LR |
1623 | ath_print(common, ATH_DBG_CONFIG, |
1624 | "not-idle: enabling radio\n"); | |
64839170 LR |
1625 | } |
1626 | } | |
1627 | ||
e7824a50 LR |
1628 | /* |
1629 | * We just prepare to enable PS. We have to wait until our AP has | |
1630 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1631 | * those ACKs and end up retransmitting the same null data frames. | |
1632 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1633 | */ | |
3cbb5dd7 | 1634 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1635 | unsigned long flags; |
1636 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1637 | if (conf->flags & IEEE80211_CONF_PS) |
1638 | ath9k_enable_ps(sc); | |
845d708e SB |
1639 | else |
1640 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1641 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1642 | } |
1643 | ||
199afd9d S |
1644 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1645 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
1646 | ath_print(common, ATH_DBG_CONFIG, | |
1647 | "HW opmode set to Monitor mode\n"); | |
1648 | sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; | |
1649 | } | |
1650 | } | |
1651 | ||
4797938c | 1652 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1653 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1654 | int pos = curchan->hw_value; |
3430098a FF |
1655 | int old_pos = -1; |
1656 | unsigned long flags; | |
1657 | ||
1658 | if (ah->curchan) | |
1659 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1660 | |
0e2dedf9 JM |
1661 | aphy->chan_idx = pos; |
1662 | aphy->chan_is_ht = conf_is_ht(conf); | |
5ee08656 FF |
1663 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1664 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1665 | else | |
1666 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1667 | |
8089cc47 JM |
1668 | if (aphy->state == ATH_WIPHY_SCAN || |
1669 | aphy->state == ATH_WIPHY_ACTIVE) | |
1670 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
1671 | else { | |
1672 | /* | |
1673 | * Do not change operational channel based on a paused | |
1674 | * wiphy changes. | |
1675 | */ | |
1676 | goto skip_chan_change; | |
1677 | } | |
0e2dedf9 | 1678 | |
c46917bb LR |
1679 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1680 | curchan->center_freq); | |
f078f209 | 1681 | |
5f8e077c | 1682 | /* XXX: remove me eventualy */ |
0e2dedf9 | 1683 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 1684 | |
ecf70441 | 1685 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 1686 | |
3430098a FF |
1687 | /* update survey stats for the old channel before switching */ |
1688 | spin_lock_irqsave(&common->cc_lock, flags); | |
1689 | ath_update_survey_stats(sc); | |
1690 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1691 | ||
1692 | /* | |
1693 | * If the operating channel changes, change the survey in-use flags | |
1694 | * along with it. | |
1695 | * Reset the survey data for the new channel, unless we're switching | |
1696 | * back to the operating channel from an off-channel operation. | |
1697 | */ | |
1698 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1699 | sc->cur_survey != &sc->survey[pos]) { | |
1700 | ||
1701 | if (sc->cur_survey) | |
1702 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1703 | ||
1704 | sc->cur_survey = &sc->survey[pos]; | |
1705 | ||
1706 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1707 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1708 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1709 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1710 | } | |
1711 | ||
0e2dedf9 | 1712 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
c46917bb LR |
1713 | ath_print(common, ATH_DBG_FATAL, |
1714 | "Unable to set channel\n"); | |
aa33de09 | 1715 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1716 | return -EINVAL; |
1717 | } | |
3430098a FF |
1718 | |
1719 | /* | |
1720 | * The most recent snapshot of channel->noisefloor for the old | |
1721 | * channel is only available after the hardware reset. Copy it to | |
1722 | * the survey stats now. | |
1723 | */ | |
1724 | if (old_pos >= 0) | |
1725 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1726 | } |
f078f209 | 1727 | |
8089cc47 | 1728 | skip_chan_change: |
c9f6a656 | 1729 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
17d7904d | 1730 | sc->config.txpowlimit = 2 * conf->power_level; |
c9f6a656 LR |
1731 | ath_update_txpow(sc); |
1732 | } | |
f078f209 | 1733 | |
194b7c13 LR |
1734 | spin_lock_bh(&sc->wiphy_lock); |
1735 | disable_radio = ath9k_all_wiphys_idle(sc); | |
1736 | spin_unlock_bh(&sc->wiphy_lock); | |
1737 | ||
64839170 | 1738 | if (disable_radio) { |
c46917bb | 1739 | ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
1dbfd9d4 | 1740 | sc->ps_idle = true; |
68a89116 | 1741 | ath_radio_disable(sc, hw); |
64839170 LR |
1742 | } |
1743 | ||
aa33de09 | 1744 | mutex_unlock(&sc->mutex); |
141b38b6 | 1745 | |
f078f209 LR |
1746 | return 0; |
1747 | } | |
1748 | ||
8feceb67 VT |
1749 | #define SUPPORTED_FILTERS \ |
1750 | (FIF_PROMISC_IN_BSS | \ | |
1751 | FIF_ALLMULTI | \ | |
1752 | FIF_CONTROL | \ | |
af6a3fc7 | 1753 | FIF_PSPOLL | \ |
8feceb67 VT |
1754 | FIF_OTHER_BSS | \ |
1755 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1756 | FIF_PROBE_REQ | \ |
8feceb67 | 1757 | FIF_FCSFAIL) |
c83be688 | 1758 | |
8feceb67 VT |
1759 | /* FIXME: sc->sc_full_reset ? */ |
1760 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1761 | unsigned int changed_flags, | |
1762 | unsigned int *total_flags, | |
3ac64bee | 1763 | u64 multicast) |
8feceb67 | 1764 | { |
bce048d7 JM |
1765 | struct ath_wiphy *aphy = hw->priv; |
1766 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1767 | u32 rfilt; |
f078f209 | 1768 | |
8feceb67 VT |
1769 | changed_flags &= SUPPORTED_FILTERS; |
1770 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1771 | |
b77f483f | 1772 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1773 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1774 | rfilt = ath_calcrxfilter(sc); |
1775 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1776 | ath9k_ps_restore(sc); |
f078f209 | 1777 | |
c46917bb LR |
1778 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1779 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1780 | } |
f078f209 | 1781 | |
4ca77860 JB |
1782 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1783 | struct ieee80211_vif *vif, | |
1784 | struct ieee80211_sta *sta) | |
8feceb67 | 1785 | { |
bce048d7 JM |
1786 | struct ath_wiphy *aphy = hw->priv; |
1787 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1788 | |
4ca77860 JB |
1789 | ath_node_attach(sc, sta); |
1790 | ||
1791 | return 0; | |
1792 | } | |
1793 | ||
1794 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1795 | struct ieee80211_vif *vif, | |
1796 | struct ieee80211_sta *sta) | |
1797 | { | |
1798 | struct ath_wiphy *aphy = hw->priv; | |
1799 | struct ath_softc *sc = aphy->sc; | |
1800 | ||
1801 | ath_node_detach(sc, sta); | |
1802 | ||
1803 | return 0; | |
f078f209 LR |
1804 | } |
1805 | ||
141b38b6 | 1806 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1807 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1808 | { |
bce048d7 JM |
1809 | struct ath_wiphy *aphy = hw->priv; |
1810 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1811 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 VT |
1812 | struct ath9k_tx_queue_info qi; |
1813 | int ret = 0, qnum; | |
f078f209 | 1814 | |
8feceb67 VT |
1815 | if (queue >= WME_NUM_AC) |
1816 | return 0; | |
f078f209 | 1817 | |
141b38b6 S |
1818 | mutex_lock(&sc->mutex); |
1819 | ||
1ffb0610 S |
1820 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1821 | ||
8feceb67 VT |
1822 | qi.tqi_aifs = params->aifs; |
1823 | qi.tqi_cwmin = params->cw_min; | |
1824 | qi.tqi_cwmax = params->cw_max; | |
1825 | qi.tqi_burstTime = params->txop; | |
1826 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 1827 | |
c46917bb LR |
1828 | ath_print(common, ATH_DBG_CONFIG, |
1829 | "Configure tx [queue/halq] [%d/%d], " | |
1830 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1831 | queue, qnum, params->aifs, params->cw_min, | |
1832 | params->cw_max, params->txop); | |
f078f209 | 1833 | |
8feceb67 VT |
1834 | ret = ath_txq_update(sc, qnum, &qi); |
1835 | if (ret) | |
c46917bb | 1836 | ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 1837 | |
94db2936 | 1838 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
1d2231e2 | 1839 | if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret) |
94db2936 VN |
1840 | ath_beaconq_config(sc); |
1841 | ||
141b38b6 S |
1842 | mutex_unlock(&sc->mutex); |
1843 | ||
8feceb67 VT |
1844 | return ret; |
1845 | } | |
f078f209 | 1846 | |
8feceb67 VT |
1847 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1848 | enum set_key_cmd cmd, | |
dc822b5d JB |
1849 | struct ieee80211_vif *vif, |
1850 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1851 | struct ieee80211_key_conf *key) |
1852 | { | |
bce048d7 JM |
1853 | struct ath_wiphy *aphy = hw->priv; |
1854 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1855 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1856 | int ret = 0; |
f078f209 | 1857 | |
b3bd89ce JM |
1858 | if (modparam_nohwcrypt) |
1859 | return -ENOSPC; | |
1860 | ||
141b38b6 | 1861 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1862 | ath9k_ps_wakeup(sc); |
c46917bb | 1863 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1864 | |
8feceb67 VT |
1865 | switch (cmd) { |
1866 | case SET_KEY: | |
040e539e | 1867 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1868 | if (ret >= 0) { |
1869 | key->hw_key_idx = ret; | |
8feceb67 VT |
1870 | /* push IV and Michael MIC generation to stack */ |
1871 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1872 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1873 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1874 | if (sc->sc_ah->sw_mgmt_crypto && |
1875 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1876 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1877 | ret = 0; |
8feceb67 VT |
1878 | } |
1879 | break; | |
1880 | case DISABLE_KEY: | |
040e539e | 1881 | ath_key_delete(common, key); |
8feceb67 VT |
1882 | break; |
1883 | default: | |
1884 | ret = -EINVAL; | |
1885 | } | |
f078f209 | 1886 | |
3cbb5dd7 | 1887 | ath9k_ps_restore(sc); |
141b38b6 S |
1888 | mutex_unlock(&sc->mutex); |
1889 | ||
8feceb67 VT |
1890 | return ret; |
1891 | } | |
f078f209 | 1892 | |
8feceb67 VT |
1893 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1894 | struct ieee80211_vif *vif, | |
1895 | struct ieee80211_bss_conf *bss_conf, | |
1896 | u32 changed) | |
1897 | { | |
bce048d7 JM |
1898 | struct ath_wiphy *aphy = hw->priv; |
1899 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 | 1900 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1901 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1902 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1903 | int slottime; |
c6089ccc | 1904 | int error; |
f078f209 | 1905 | |
141b38b6 S |
1906 | mutex_lock(&sc->mutex); |
1907 | ||
c6089ccc S |
1908 | if (changed & BSS_CHANGED_BSSID) { |
1909 | /* Set BSSID */ | |
1910 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1911 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1912 | common->curaid = 0; |
f2b2143e | 1913 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1914 | |
c6089ccc S |
1915 | /* Set aggregation protection mode parameters */ |
1916 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1917 | |
c6089ccc S |
1918 | /* Only legacy IBSS for now */ |
1919 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
1920 | ath_update_chainmask(sc, 0); | |
2d0ddec5 | 1921 | |
c6089ccc S |
1922 | ath_print(common, ATH_DBG_CONFIG, |
1923 | "BSSID: %pM aid: 0x%x\n", | |
1924 | common->curbssid, common->curaid); | |
2d0ddec5 | 1925 | |
c6089ccc S |
1926 | /* need to reconfigure the beacon */ |
1927 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1928 | } | |
2d0ddec5 | 1929 | |
c6089ccc S |
1930 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1931 | if ((changed & BSS_CHANGED_BEACON) || | |
1932 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1933 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1934 | error = ath_beacon_alloc(aphy, vif); | |
1935 | if (!error) | |
1936 | ath_beacon_config(sc, vif); | |
0005baf4 FF |
1937 | } |
1938 | ||
1939 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1940 | if (bss_conf->use_short_slot) | |
1941 | slottime = 9; | |
1942 | else | |
1943 | slottime = 20; | |
1944 | if (vif->type == NL80211_IFTYPE_AP) { | |
1945 | /* | |
1946 | * Defer update, so that connected stations can adjust | |
1947 | * their settings at the same time. | |
1948 | * See beacon.c for more details | |
1949 | */ | |
1950 | sc->beacon.slottime = slottime; | |
1951 | sc->beacon.updateslot = UPDATE; | |
1952 | } else { | |
1953 | ah->slottime = slottime; | |
1954 | ath9k_hw_init_global_settings(ah); | |
1955 | } | |
2d0ddec5 JB |
1956 | } |
1957 | ||
c6089ccc S |
1958 | /* Disable transmission of beacons */ |
1959 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1960 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1961 | |
c6089ccc S |
1962 | if (changed & BSS_CHANGED_BEACON_INT) { |
1963 | sc->beacon_interval = bss_conf->beacon_int; | |
1964 | /* | |
1965 | * In case of AP mode, the HW TSF has to be reset | |
1966 | * when the beacon interval changes. | |
1967 | */ | |
1968 | if (vif->type == NL80211_IFTYPE_AP) { | |
1969 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1970 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 JB |
1971 | error = ath_beacon_alloc(aphy, vif); |
1972 | if (!error) | |
1973 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1974 | } else { |
1975 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1976 | } |
1977 | } | |
1978 | ||
8feceb67 | 1979 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
c46917bb LR |
1980 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1981 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1982 | if (bss_conf->use_short_preamble) |
1983 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1984 | else | |
1985 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1986 | } | |
f078f209 | 1987 | |
8feceb67 | 1988 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
c46917bb LR |
1989 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1990 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1991 | if (bss_conf->use_cts_prot && |
1992 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1993 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1994 | else | |
1995 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1996 | } | |
f078f209 | 1997 | |
8feceb67 | 1998 | if (changed & BSS_CHANGED_ASSOC) { |
c46917bb | 1999 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 2000 | bss_conf->assoc); |
5640b08e | 2001 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 2002 | } |
141b38b6 S |
2003 | |
2004 | mutex_unlock(&sc->mutex); | |
8feceb67 | 2005 | } |
f078f209 | 2006 | |
8feceb67 VT |
2007 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
2008 | { | |
2009 | u64 tsf; | |
bce048d7 JM |
2010 | struct ath_wiphy *aphy = hw->priv; |
2011 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 2012 | |
141b38b6 S |
2013 | mutex_lock(&sc->mutex); |
2014 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
2015 | mutex_unlock(&sc->mutex); | |
f078f209 | 2016 | |
8feceb67 VT |
2017 | return tsf; |
2018 | } | |
f078f209 | 2019 | |
3b5d665b AF |
2020 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
2021 | { | |
bce048d7 JM |
2022 | struct ath_wiphy *aphy = hw->priv; |
2023 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 2024 | |
141b38b6 S |
2025 | mutex_lock(&sc->mutex); |
2026 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
2027 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
2028 | } |
2029 | ||
8feceb67 VT |
2030 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
2031 | { | |
bce048d7 JM |
2032 | struct ath_wiphy *aphy = hw->priv; |
2033 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 2034 | |
141b38b6 | 2035 | mutex_lock(&sc->mutex); |
21526d57 LR |
2036 | |
2037 | ath9k_ps_wakeup(sc); | |
141b38b6 | 2038 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
2039 | ath9k_ps_restore(sc); |
2040 | ||
141b38b6 | 2041 | mutex_unlock(&sc->mutex); |
8feceb67 | 2042 | } |
f078f209 | 2043 | |
8feceb67 | 2044 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2045 | struct ieee80211_vif *vif, |
141b38b6 S |
2046 | enum ieee80211_ampdu_mlme_action action, |
2047 | struct ieee80211_sta *sta, | |
2048 | u16 tid, u16 *ssn) | |
8feceb67 | 2049 | { |
bce048d7 JM |
2050 | struct ath_wiphy *aphy = hw->priv; |
2051 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2052 | int ret = 0; |
f078f209 | 2053 | |
85ad181e JB |
2054 | local_bh_disable(); |
2055 | ||
8feceb67 VT |
2056 | switch (action) { |
2057 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2058 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2059 | ret = -ENOTSUPP; | |
8feceb67 VT |
2060 | break; |
2061 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2062 | break; |
2063 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 2064 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
2065 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
2066 | if (!ret) | |
2067 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 2068 | ath9k_ps_restore(sc); |
8feceb67 VT |
2069 | break; |
2070 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 2071 | ath9k_ps_wakeup(sc); |
f83da965 | 2072 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 2073 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2074 | ath9k_ps_restore(sc); |
8feceb67 | 2075 | break; |
b1720231 | 2076 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 2077 | ath9k_ps_wakeup(sc); |
8469cdef | 2078 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 2079 | ath9k_ps_restore(sc); |
8469cdef | 2080 | break; |
8feceb67 | 2081 | default: |
c46917bb LR |
2082 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
2083 | "Unknown AMPDU action\n"); | |
8feceb67 VT |
2084 | } |
2085 | ||
85ad181e JB |
2086 | local_bh_enable(); |
2087 | ||
8feceb67 | 2088 | return ret; |
f078f209 LR |
2089 | } |
2090 | ||
62dad5b0 BP |
2091 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2092 | struct survey_info *survey) | |
2093 | { | |
2094 | struct ath_wiphy *aphy = hw->priv; | |
2095 | struct ath_softc *sc = aphy->sc; | |
3430098a | 2096 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 2097 | struct ieee80211_supported_band *sband; |
3430098a FF |
2098 | struct ieee80211_channel *chan; |
2099 | unsigned long flags; | |
2100 | int pos; | |
2101 | ||
2102 | spin_lock_irqsave(&common->cc_lock, flags); | |
2103 | if (idx == 0) | |
2104 | ath_update_survey_stats(sc); | |
39162dbe FF |
2105 | |
2106 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
2107 | if (sband && idx >= sband->n_channels) { | |
2108 | idx -= sband->n_channels; | |
2109 | sband = NULL; | |
2110 | } | |
62dad5b0 | 2111 | |
39162dbe FF |
2112 | if (!sband) |
2113 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 2114 | |
3430098a FF |
2115 | if (!sband || idx >= sband->n_channels) { |
2116 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2117 | return -ENOENT; | |
4f1a5a4b | 2118 | } |
62dad5b0 | 2119 | |
3430098a FF |
2120 | chan = &sband->channels[idx]; |
2121 | pos = chan->hw_value; | |
2122 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
2123 | survey->channel = chan; | |
2124 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2125 | ||
62dad5b0 BP |
2126 | return 0; |
2127 | } | |
2128 | ||
0c98de65 S |
2129 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2130 | { | |
bce048d7 JM |
2131 | struct ath_wiphy *aphy = hw->priv; |
2132 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2133 | |
3d832611 | 2134 | mutex_lock(&sc->mutex); |
8089cc47 | 2135 | if (ath9k_wiphy_scanning(sc)) { |
8089cc47 | 2136 | /* |
30888338 LR |
2137 | * There is a race here in mac80211 but fixing it requires |
2138 | * we revisit how we handle the scan complete callback. | |
2139 | * After mac80211 fixes we will not have configured hardware | |
2140 | * to the home channel nor would we have configured the RX | |
2141 | * filter yet. | |
8089cc47 | 2142 | */ |
3d832611 | 2143 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
2144 | return; |
2145 | } | |
2146 | ||
2147 | aphy->state = ATH_WIPHY_SCAN; | |
2148 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
3d832611 | 2149 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2150 | } |
2151 | ||
30888338 LR |
2152 | /* |
2153 | * XXX: this requires a revisit after the driver | |
2154 | * scan_complete gets moved to another place/removed in mac80211. | |
2155 | */ | |
0c98de65 S |
2156 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) |
2157 | { | |
bce048d7 JM |
2158 | struct ath_wiphy *aphy = hw->priv; |
2159 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2160 | |
3d832611 | 2161 | mutex_lock(&sc->mutex); |
8089cc47 | 2162 | aphy->state = ATH_WIPHY_ACTIVE; |
3d832611 | 2163 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2164 | } |
2165 | ||
e239d859 FF |
2166 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2167 | { | |
2168 | struct ath_wiphy *aphy = hw->priv; | |
2169 | struct ath_softc *sc = aphy->sc; | |
2170 | struct ath_hw *ah = sc->sc_ah; | |
2171 | ||
2172 | mutex_lock(&sc->mutex); | |
2173 | ah->coverage_class = coverage_class; | |
2174 | ath9k_hw_init_global_settings(ah); | |
2175 | mutex_unlock(&sc->mutex); | |
2176 | } | |
2177 | ||
6baff7f9 | 2178 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2179 | .tx = ath9k_tx, |
2180 | .start = ath9k_start, | |
2181 | .stop = ath9k_stop, | |
2182 | .add_interface = ath9k_add_interface, | |
2183 | .remove_interface = ath9k_remove_interface, | |
2184 | .config = ath9k_config, | |
8feceb67 | 2185 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2186 | .sta_add = ath9k_sta_add, |
2187 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 2188 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2189 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2190 | .set_key = ath9k_set_key, |
8feceb67 | 2191 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2192 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2193 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2194 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2195 | .get_survey = ath9k_get_survey, |
0c98de65 S |
2196 | .sw_scan_start = ath9k_sw_scan_start, |
2197 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 2198 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2199 | .set_coverage_class = ath9k_set_coverage_class, |
8feceb67 | 2200 | }; |