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Commit | Line | Data |
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f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
6dcc3444 SM |
22 | static void ath9k_set_assoc_state(struct ath_softc *sc, |
23 | struct ieee80211_vif *vif); | |
24 | ||
313eb87f | 25 | u8 ath9k_parse_mpdudensity(u8 mpdudensity) |
ff37e337 S |
26 | { |
27 | /* | |
28 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
29 | * 0 for no restriction | |
30 | * 1 for 1/4 us | |
31 | * 2 for 1/2 us | |
32 | * 3 for 1 us | |
33 | * 4 for 2 us | |
34 | * 5 for 4 us | |
35 | * 6 for 8 us | |
36 | * 7 for 16 us | |
37 | */ | |
38 | switch (mpdudensity) { | |
39 | case 0: | |
40 | return 0; | |
41 | case 1: | |
42 | case 2: | |
43 | case 3: | |
44 | /* Our lower layer calculations limit our precision to | |
45 | 1 microsecond */ | |
46 | return 1; | |
47 | case 4: | |
48 | return 2; | |
49 | case 5: | |
50 | return 4; | |
51 | case 6: | |
52 | return 8; | |
53 | case 7: | |
54 | return 16; | |
55 | default: | |
56 | return 0; | |
57 | } | |
58 | } | |
59 | ||
69081624 VT |
60 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
61 | { | |
62 | bool pending = false; | |
63 | ||
64 | spin_lock_bh(&txq->axq_lock); | |
65 | ||
66 | if (txq->axq_depth || !list_empty(&txq->axq_acq)) | |
67 | pending = true; | |
69081624 VT |
68 | |
69 | spin_unlock_bh(&txq->axq_lock); | |
70 | return pending; | |
71 | } | |
72 | ||
6d79cb4c | 73 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
74 | { |
75 | unsigned long flags; | |
76 | bool ret; | |
77 | ||
9ecdef4b LR |
78 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
79 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
80 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
81 | |
82 | return ret; | |
83 | } | |
84 | ||
a91d75ae LR |
85 | void ath9k_ps_wakeup(struct ath_softc *sc) |
86 | { | |
898c914a | 87 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 88 | unsigned long flags; |
fbb078fc | 89 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
90 | |
91 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
92 | if (++sc->ps_usecount != 1) | |
93 | goto unlock; | |
94 | ||
fbb078fc | 95 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 96 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 97 | |
898c914a FF |
98 | /* |
99 | * While the hardware is asleep, the cycle counters contain no | |
100 | * useful data. Better clear them now so that they don't mess up | |
101 | * survey data results. | |
102 | */ | |
fbb078fc FF |
103 | if (power_mode != ATH9K_PM_AWAKE) { |
104 | spin_lock(&common->cc_lock); | |
105 | ath_hw_cycle_counters_update(common); | |
106 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
c9ae6ab4 | 107 | memset(&common->cc_ani, 0, sizeof(common->cc_ani)); |
fbb078fc FF |
108 | spin_unlock(&common->cc_lock); |
109 | } | |
898c914a | 110 | |
a91d75ae LR |
111 | unlock: |
112 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
113 | } | |
114 | ||
115 | void ath9k_ps_restore(struct ath_softc *sc) | |
116 | { | |
898c914a | 117 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c6c539f0 | 118 | enum ath9k_power_mode mode; |
a91d75ae | 119 | unsigned long flags; |
ad128860 | 120 | bool reset; |
a91d75ae LR |
121 | |
122 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
123 | if (--sc->ps_usecount != 0) | |
124 | goto unlock; | |
125 | ||
ad128860 SM |
126 | if (sc->ps_idle) { |
127 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
128 | ath9k_hw_stopdmarecv(sc->sc_ah, &reset); | |
c6c539f0 | 129 | mode = ATH9K_PM_FULL_SLEEP; |
ad128860 SM |
130 | } else if (sc->ps_enabled && |
131 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
132 | PS_WAIT_FOR_CAB | | |
133 | PS_WAIT_FOR_PSPOLL_DATA | | |
134 | PS_WAIT_FOR_TX_ACK))) { | |
c6c539f0 | 135 | mode = ATH9K_PM_NETWORK_SLEEP; |
08d4df41 RM |
136 | if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) |
137 | ath9k_btcoex_stop_gen_timer(sc); | |
ad128860 | 138 | } else { |
c6c539f0 | 139 | goto unlock; |
ad128860 | 140 | } |
c6c539f0 FF |
141 | |
142 | spin_lock(&common->cc_lock); | |
143 | ath_hw_cycle_counters_update(common); | |
144 | spin_unlock(&common->cc_lock); | |
145 | ||
1a8f0d39 | 146 | ath9k_hw_setpower(sc->sc_ah, mode); |
a91d75ae LR |
147 | |
148 | unlock: | |
149 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
150 | } | |
151 | ||
9adcf440 | 152 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 153 | { |
5ee08656 FF |
154 | cancel_work_sync(&sc->paprd_work); |
155 | cancel_work_sync(&sc->hw_check_work); | |
156 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
181fb18d | 157 | cancel_delayed_work_sync(&sc->hw_pll_work); |
fad29cd2 | 158 | |
bf52592f | 159 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
fad29cd2 SM |
160 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
161 | cancel_work_sync(&sc->mci_work); | |
bf52592f | 162 | #endif |
9adcf440 | 163 | } |
5ee08656 | 164 | |
9adcf440 FF |
165 | static void ath_cancel_work(struct ath_softc *sc) |
166 | { | |
167 | __ath_cancel_work(sc); | |
168 | cancel_work_sync(&sc->hw_reset_work); | |
169 | } | |
3cbb5dd7 | 170 | |
af68abad SM |
171 | static void ath_restart_work(struct ath_softc *sc) |
172 | { | |
af68abad SM |
173 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
174 | ||
c12b6021 GJ |
175 | if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) || |
176 | AR_SREV_9550(sc->sc_ah)) | |
af68abad SM |
177 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, |
178 | msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); | |
179 | ||
180 | ath_start_rx_poll(sc, 3); | |
da0d45f7 | 181 | ath_start_ani(sc); |
af68abad SM |
182 | } |
183 | ||
9adcf440 FF |
184 | static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) |
185 | { | |
186 | struct ath_hw *ah = sc->sc_ah; | |
ceea2a51 | 187 | bool ret = true; |
6a6733f2 | 188 | |
9adcf440 | 189 | ieee80211_stop_queues(sc->hw); |
5e848f78 | 190 | |
9adcf440 | 191 | sc->hw_busy_count = 0; |
da0d45f7 | 192 | ath_stop_ani(sc); |
01e18918 | 193 | del_timer_sync(&sc->rx_poll_timer); |
ff37e337 | 194 | |
9adcf440 FF |
195 | ath9k_debug_samp_bb_mac(sc); |
196 | ath9k_hw_disable_interrupts(ah); | |
8b3f4616 | 197 | |
9adcf440 FF |
198 | if (!ath_stoprecv(sc)) |
199 | ret = false; | |
c0d7c7af | 200 | |
ceea2a51 FF |
201 | if (!ath_drain_all_txq(sc, retry_tx)) |
202 | ret = false; | |
203 | ||
9adcf440 FF |
204 | if (!flush) { |
205 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
3483288c FF |
206 | ath_rx_tasklet(sc, 1, true); |
207 | ath_rx_tasklet(sc, 1, false); | |
9adcf440 FF |
208 | } else { |
209 | ath_flushrecv(sc); | |
210 | } | |
20bd2a09 | 211 | |
9adcf440 FF |
212 | return ret; |
213 | } | |
ff37e337 | 214 | |
9adcf440 FF |
215 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
216 | { | |
217 | struct ath_hw *ah = sc->sc_ah; | |
218 | struct ath_common *common = ath9k_hw_common(ah); | |
196fb860 | 219 | unsigned long flags; |
c0d7c7af | 220 | |
c0d7c7af | 221 | if (ath_startrecv(sc) != 0) { |
3800276a | 222 | ath_err(common, "Unable to restart recv logic\n"); |
9adcf440 | 223 | return false; |
c0d7c7af LR |
224 | } |
225 | ||
5048e8c3 RM |
226 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
227 | sc->config.txpowlimit, &sc->curtxpow); | |
b74713d0 SM |
228 | |
229 | clear_bit(SC_OP_HW_RESET, &sc->sc_flags); | |
72d874c6 | 230 | ath9k_hw_set_interrupts(ah); |
b037b693 | 231 | ath9k_hw_enable_interrupts(ah); |
3989279c | 232 | |
4cb54fa3 | 233 | if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { |
196fb860 SM |
234 | if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) |
235 | goto work; | |
236 | ||
ef4ad633 | 237 | ath9k_set_beacon(sc); |
196fb860 SM |
238 | |
239 | if (ah->opmode == NL80211_IFTYPE_STATION && | |
240 | test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
241 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
242 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
243 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
244 | } | |
245 | work: | |
af68abad | 246 | ath_restart_work(sc); |
5ee08656 FF |
247 | } |
248 | ||
8da07830 SM |
249 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) |
250 | ath_ant_comb_update(sc); | |
43c35284 | 251 | |
9adcf440 FF |
252 | ieee80211_wake_queues(sc->hw); |
253 | ||
254 | return true; | |
255 | } | |
256 | ||
257 | static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, | |
258 | bool retry_tx) | |
259 | { | |
260 | struct ath_hw *ah = sc->sc_ah; | |
261 | struct ath_common *common = ath9k_hw_common(ah); | |
262 | struct ath9k_hw_cal_data *caldata = NULL; | |
263 | bool fastcc = true; | |
264 | bool flush = false; | |
265 | int r; | |
266 | ||
267 | __ath_cancel_work(sc); | |
268 | ||
269 | spin_lock_bh(&sc->sc_pcu_lock); | |
92460412 | 270 | |
4cb54fa3 | 271 | if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { |
9adcf440 FF |
272 | fastcc = false; |
273 | caldata = &sc->caldata; | |
274 | } | |
275 | ||
276 | if (!hchan) { | |
277 | fastcc = false; | |
278 | flush = true; | |
279 | hchan = ah->curchan; | |
280 | } | |
281 | ||
9adcf440 FF |
282 | if (!ath_prepare_reset(sc, retry_tx, flush)) |
283 | fastcc = false; | |
284 | ||
d2182b69 | 285 | ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", |
feced201 | 286 | hchan->channel, IS_CHAN_HT40(hchan), fastcc); |
9adcf440 FF |
287 | |
288 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
289 | if (r) { | |
290 | ath_err(common, | |
291 | "Unable to reset channel, reset status %d\n", r); | |
292 | goto out; | |
293 | } | |
294 | ||
295 | if (!ath_complete_reset(sc, true)) | |
296 | r = -EIO; | |
297 | ||
298 | out: | |
6a6733f2 | 299 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 FF |
300 | return r; |
301 | } | |
302 | ||
303 | ||
304 | /* | |
305 | * Set/change channels. If the channel is really being changed, it's done | |
306 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
307 | * DMA, then restart stuff. | |
308 | */ | |
309 | static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
310 | struct ath9k_channel *hchan) | |
311 | { | |
312 | int r; | |
313 | ||
781b14a3 | 314 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) |
9adcf440 FF |
315 | return -EIO; |
316 | ||
9adcf440 | 317 | r = ath_reset_internal(sc, hchan, false); |
6a6733f2 | 318 | |
3989279c | 319 | return r; |
ff37e337 S |
320 | } |
321 | ||
7e1e3864 BG |
322 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, |
323 | struct ieee80211_vif *vif) | |
ff37e337 S |
324 | { |
325 | struct ath_node *an; | |
313eb87f | 326 | u8 density; |
ff37e337 S |
327 | an = (struct ath_node *)sta->drv_priv; |
328 | ||
7f010c93 BG |
329 | #ifdef CONFIG_ATH9K_DEBUGFS |
330 | spin_lock(&sc->nodes_lock); | |
331 | list_add(&an->list, &sc->nodes); | |
332 | spin_unlock(&sc->nodes_lock); | |
156369fa | 333 | #endif |
7f010c93 | 334 | an->sta = sta; |
7e1e3864 | 335 | an->vif = vif; |
3d4e20f2 | 336 | |
a4d6367f | 337 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
ff37e337 | 338 | ath_tx_node_init(sc, an); |
9e98ac65 | 339 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc | 340 | sta->ht_cap.ampdu_factor); |
313eb87f SE |
341 | density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); |
342 | an->mpdudensity = density; | |
87792efc | 343 | } |
ff37e337 S |
344 | } |
345 | ||
346 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
347 | { | |
348 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
349 | ||
7f010c93 BG |
350 | #ifdef CONFIG_ATH9K_DEBUGFS |
351 | spin_lock(&sc->nodes_lock); | |
352 | list_del(&an->list); | |
353 | spin_unlock(&sc->nodes_lock); | |
354 | an->sta = NULL; | |
355 | #endif | |
356 | ||
a4d6367f | 357 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
ff37e337 S |
358 | ath_tx_node_cleanup(sc, an); |
359 | } | |
360 | ||
55624204 | 361 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
362 | { |
363 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 364 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 365 | struct ath_common *common = ath9k_hw_common(ah); |
124b979b | 366 | enum ath_reset_type type; |
07c15a3f | 367 | unsigned long flags; |
17d7904d | 368 | u32 status = sc->intrstatus; |
b5c80475 | 369 | u32 rxmask; |
ff37e337 | 370 | |
e3927007 FF |
371 | ath9k_ps_wakeup(sc); |
372 | spin_lock(&sc->sc_pcu_lock); | |
373 | ||
a4d86d95 RM |
374 | if ((status & ATH9K_INT_FATAL) || |
375 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
030d6294 FF |
376 | |
377 | if (status & ATH9K_INT_FATAL) | |
378 | type = RESET_TYPE_FATAL_INT; | |
379 | else | |
380 | type = RESET_TYPE_BB_WATCHDOG; | |
381 | ||
124b979b | 382 | ath9k_queue_reset(sc, type); |
e3927007 | 383 | goto out; |
063d8be3 | 384 | } |
ff37e337 | 385 | |
07c15a3f | 386 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
4105f807 RM |
387 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
388 | /* | |
389 | * TSF sync does not look correct; remain awake to sync with | |
390 | * the next Beacon. | |
391 | */ | |
d2182b69 | 392 | ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); |
e8fe7336 | 393 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 | 394 | } |
07c15a3f | 395 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
4105f807 | 396 | |
b5c80475 FF |
397 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
398 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
399 | ATH9K_INT_RXORN); | |
400 | else | |
401 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
402 | ||
403 | if (status & rxmask) { | |
b5c80475 FF |
404 | /* Check for high priority Rx first */ |
405 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
406 | (status & ATH9K_INT_RXHP)) | |
407 | ath_rx_tasklet(sc, 0, true); | |
408 | ||
409 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
410 | } |
411 | ||
e5003249 VT |
412 | if (status & ATH9K_INT_TX) { |
413 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
414 | ath_tx_edma_tasklet(sc); | |
415 | else | |
416 | ath_tx_tasklet(sc); | |
417 | } | |
063d8be3 | 418 | |
56ca0dba | 419 | ath9k_btcoex_handle_interrupt(sc, status); |
19686ddf | 420 | |
e3927007 | 421 | out: |
ff37e337 | 422 | /* re-enable hardware interrupt */ |
4df3071e | 423 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 424 | |
52671e43 | 425 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 426 | ath9k_ps_restore(sc); |
ff37e337 S |
427 | } |
428 | ||
6baff7f9 | 429 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 430 | { |
063d8be3 S |
431 | #define SCHED_INTR ( \ |
432 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 433 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
434 | ATH9K_INT_RXORN | \ |
435 | ATH9K_INT_RXEOL | \ | |
436 | ATH9K_INT_RX | \ | |
b5c80475 FF |
437 | ATH9K_INT_RXLP | \ |
438 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
439 | ATH9K_INT_TX | \ |
440 | ATH9K_INT_BMISS | \ | |
441 | ATH9K_INT_CST | \ | |
ebb8e1d7 | 442 | ATH9K_INT_TSFOOR | \ |
40dc5392 MSS |
443 | ATH9K_INT_GENTIMER | \ |
444 | ATH9K_INT_MCI) | |
063d8be3 | 445 | |
ff37e337 | 446 | struct ath_softc *sc = dev; |
cbe61d8a | 447 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 448 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
449 | enum ath9k_int status; |
450 | bool sched = false; | |
451 | ||
063d8be3 S |
452 | /* |
453 | * The hardware is not ready/present, don't | |
454 | * touch anything. Note this can happen early | |
455 | * on if the IRQ is shared. | |
456 | */ | |
781b14a3 | 457 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) |
063d8be3 | 458 | return IRQ_NONE; |
ff37e337 | 459 | |
063d8be3 S |
460 | /* shared irq, not for us */ |
461 | ||
153e080d | 462 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 463 | return IRQ_NONE; |
063d8be3 | 464 | |
f41a9b3b FF |
465 | if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) { |
466 | ath9k_hw_kill_interrupts(ah); | |
b74713d0 | 467 | return IRQ_HANDLED; |
f41a9b3b | 468 | } |
b74713d0 | 469 | |
063d8be3 S |
470 | /* |
471 | * Figure out the reason(s) for the interrupt. Note | |
472 | * that the hal returns a pseudo-ISR that may include | |
473 | * bits we haven't explicitly enabled so we mask the | |
474 | * value to insure we only process bits we requested. | |
475 | */ | |
476 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 477 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 478 | |
063d8be3 S |
479 | /* |
480 | * If there are no status bits set, then this interrupt was not | |
481 | * for me (should have been caught above). | |
482 | */ | |
153e080d | 483 | if (!status) |
063d8be3 | 484 | return IRQ_NONE; |
ff37e337 | 485 | |
063d8be3 S |
486 | /* Cache the status */ |
487 | sc->intrstatus = status; | |
488 | ||
489 | if (status & SCHED_INTR) | |
490 | sched = true; | |
491 | ||
b11e640a MSS |
492 | #ifdef CONFIG_PM_SLEEP |
493 | if (status & ATH9K_INT_BMISS) { | |
494 | if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { | |
495 | ath_dbg(common, ANY, "during WoW we got a BMISS\n"); | |
496 | atomic_inc(&sc->wow_got_bmiss_intr); | |
497 | atomic_dec(&sc->wow_sleep_proc_intr); | |
498 | } | |
499 | ath_dbg(common, INTERRUPT, "beacon miss interrupt\n"); | |
500 | } | |
501 | #endif | |
502 | ||
063d8be3 S |
503 | /* |
504 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
505 | * chip immediately. | |
506 | */ | |
b5c80475 FF |
507 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
508 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
509 | goto chip_reset; |
510 | ||
08578b8f LR |
511 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
512 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
513 | |
514 | spin_lock(&common->cc_lock); | |
515 | ath_hw_cycle_counters_update(common); | |
08578b8f | 516 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
517 | spin_unlock(&common->cc_lock); |
518 | ||
08578b8f LR |
519 | goto chip_reset; |
520 | } | |
521 | ||
063d8be3 S |
522 | if (status & ATH9K_INT_SWBA) |
523 | tasklet_schedule(&sc->bcon_tasklet); | |
524 | ||
525 | if (status & ATH9K_INT_TXURN) | |
526 | ath9k_hw_updatetxtriglevel(ah, true); | |
527 | ||
0682c9b5 RM |
528 | if (status & ATH9K_INT_RXEOL) { |
529 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 530 | ath9k_hw_set_interrupts(ah); |
b5c80475 FF |
531 | } |
532 | ||
153e080d VT |
533 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
534 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
535 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
536 | goto chip_reset; | |
063d8be3 S |
537 | /* Clear RxAbort bit so that we can |
538 | * receive frames */ | |
9ecdef4b | 539 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
07c15a3f | 540 | spin_lock(&sc->sc_pm_lock); |
153e080d | 541 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 542 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
07c15a3f | 543 | spin_unlock(&sc->sc_pm_lock); |
ff37e337 | 544 | } |
063d8be3 S |
545 | |
546 | chip_reset: | |
ff37e337 | 547 | |
817e11de S |
548 | ath_debug_stat_interrupt(sc, status); |
549 | ||
ff37e337 | 550 | if (sched) { |
4df3071e FF |
551 | /* turn off every interrupt */ |
552 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
553 | tasklet_schedule(&sc->intr_tq); |
554 | } | |
555 | ||
556 | return IRQ_HANDLED; | |
063d8be3 S |
557 | |
558 | #undef SCHED_INTR | |
ff37e337 S |
559 | } |
560 | ||
236de514 | 561 | static int ath_reset(struct ath_softc *sc, bool retry_tx) |
ff37e337 | 562 | { |
ae8d2858 | 563 | int r; |
ff37e337 | 564 | |
783cd01e | 565 | ath9k_ps_wakeup(sc); |
6a6733f2 | 566 | |
9adcf440 | 567 | r = ath_reset_internal(sc, NULL, retry_tx); |
ff37e337 S |
568 | |
569 | if (retry_tx) { | |
570 | int i; | |
571 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
572 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
573 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
574 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
575 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
576 | } |
577 | } | |
578 | } | |
579 | ||
783cd01e | 580 | ath9k_ps_restore(sc); |
2ab81d4a | 581 | |
ae8d2858 | 582 | return r; |
ff37e337 S |
583 | } |
584 | ||
124b979b RM |
585 | void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) |
586 | { | |
587 | #ifdef CONFIG_ATH9K_DEBUGFS | |
588 | RESET_STAT_INC(sc, type); | |
589 | #endif | |
590 | set_bit(SC_OP_HW_RESET, &sc->sc_flags); | |
591 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | |
592 | } | |
593 | ||
236de514 FF |
594 | void ath_reset_work(struct work_struct *work) |
595 | { | |
596 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
597 | ||
236de514 | 598 | ath_reset(sc, true); |
236de514 FF |
599 | } |
600 | ||
ff37e337 S |
601 | /**********************/ |
602 | /* mac80211 callbacks */ | |
603 | /**********************/ | |
604 | ||
8feceb67 | 605 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 606 | { |
9ac58615 | 607 | struct ath_softc *sc = hw->priv; |
af03abec | 608 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 609 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 610 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 611 | struct ath9k_channel *init_channel; |
82880a7c | 612 | int r; |
f078f209 | 613 | |
d2182b69 | 614 | ath_dbg(common, CONFIG, |
226afe68 JP |
615 | "Starting driver with initial channel: %d MHz\n", |
616 | curchan->center_freq); | |
f078f209 | 617 | |
f62d816f | 618 | ath9k_ps_wakeup(sc); |
141b38b6 S |
619 | mutex_lock(&sc->mutex); |
620 | ||
c344c9cb | 621 | init_channel = ath9k_cmn_get_curchannel(hw, ah); |
ff37e337 S |
622 | |
623 | /* Reset SERDES registers */ | |
84c87dc8 | 624 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
625 | |
626 | /* | |
627 | * The basic interface to setting the hardware in a good | |
628 | * state is ``reset''. On return the hardware is known to | |
629 | * be powered up and with interrupts disabled. This must | |
630 | * be followed by initialization of the appropriate bits | |
631 | * and then setup of the interrupt mask. | |
632 | */ | |
4bdd1e97 | 633 | spin_lock_bh(&sc->sc_pcu_lock); |
c0c11741 FF |
634 | |
635 | atomic_set(&ah->intr_ref_cnt, -1); | |
636 | ||
20bd2a09 | 637 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 638 | if (r) { |
3800276a JP |
639 | ath_err(common, |
640 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
641 | r, curchan->center_freq); | |
ceb26a60 | 642 | ah->reset_power_on = false; |
ff37e337 | 643 | } |
ff37e337 | 644 | |
ff37e337 | 645 | /* Setup our intr mask. */ |
b5c80475 FF |
646 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
647 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
648 | ATH9K_INT_GLOBAL; | |
649 | ||
650 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
651 | ah->imask |= ATH9K_INT_RXHP | |
652 | ATH9K_INT_RXLP | | |
653 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
654 | else |
655 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 656 | |
364734fa | 657 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 658 | |
af03abec | 659 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 660 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 661 | |
e270e776 | 662 | ath_mci_enable(sc); |
40dc5392 | 663 | |
781b14a3 | 664 | clear_bit(SC_OP_INVALID, &sc->sc_flags); |
5f841b41 | 665 | sc->sc_ah->is_monitoring = false; |
ff37e337 | 666 | |
ceb26a60 FF |
667 | if (!ath_complete_reset(sc, false)) |
668 | ah->reset_power_on = false; | |
ff37e337 | 669 | |
c0c11741 FF |
670 | if (ah->led_pin >= 0) { |
671 | ath9k_hw_cfg_output(ah, ah->led_pin, | |
672 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
673 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); | |
674 | } | |
675 | ||
676 | /* | |
677 | * Reset key cache to sane defaults (all entries cleared) instead of | |
678 | * semi-random values after suspend/resume. | |
679 | */ | |
680 | ath9k_cmn_init_crypto(sc->sc_ah); | |
681 | ||
9adcf440 | 682 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 683 | |
8060e169 VT |
684 | if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) |
685 | common->bus_ops->extn_synch_en(common); | |
686 | ||
141b38b6 S |
687 | mutex_unlock(&sc->mutex); |
688 | ||
f62d816f FF |
689 | ath9k_ps_restore(sc); |
690 | ||
ceb26a60 | 691 | return 0; |
f078f209 LR |
692 | } |
693 | ||
36323f81 TH |
694 | static void ath9k_tx(struct ieee80211_hw *hw, |
695 | struct ieee80211_tx_control *control, | |
696 | struct sk_buff *skb) | |
f078f209 | 697 | { |
9ac58615 | 698 | struct ath_softc *sc = hw->priv; |
c46917bb | 699 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 700 | struct ath_tx_control txctl; |
1bc14880 | 701 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
07c15a3f | 702 | unsigned long flags; |
528f0c6b | 703 | |
96148326 | 704 | if (sc->ps_enabled) { |
dc8c4585 JM |
705 | /* |
706 | * mac80211 does not set PM field for normal data frames, so we | |
707 | * need to update that based on the current PS mode. | |
708 | */ | |
709 | if (ieee80211_is_data(hdr->frame_control) && | |
710 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
711 | !ieee80211_has_pm(hdr->frame_control)) { | |
d2182b69 | 712 | ath_dbg(common, PS, |
226afe68 | 713 | "Add PM=1 for a TX frame while in PS mode\n"); |
dc8c4585 JM |
714 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
715 | } | |
716 | } | |
717 | ||
ad128860 | 718 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { |
9a23f9ca JM |
719 | /* |
720 | * We are using PS-Poll and mac80211 can request TX while in | |
721 | * power save mode. Need to wake up hardware for the TX to be | |
722 | * completed and if needed, also for RX of buffered frames. | |
723 | */ | |
9a23f9ca | 724 | ath9k_ps_wakeup(sc); |
07c15a3f | 725 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
fdf76622 VT |
726 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
727 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 728 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
d2182b69 | 729 | ath_dbg(common, PS, |
226afe68 | 730 | "Sending PS-Poll to pick a buffered frame\n"); |
1b04b930 | 731 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 732 | } else { |
d2182b69 | 733 | ath_dbg(common, PS, "Wake up to complete TX\n"); |
1b04b930 | 734 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
735 | } |
736 | /* | |
737 | * The actual restore operation will happen only after | |
ad128860 | 738 | * the ps_flags bit is cleared. We are just dropping |
9a23f9ca JM |
739 | * the ps_usecount here. |
740 | */ | |
07c15a3f | 741 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
9a23f9ca JM |
742 | ath9k_ps_restore(sc); |
743 | } | |
744 | ||
ad128860 SM |
745 | /* |
746 | * Cannot tx while the hardware is in full sleep, it first needs a full | |
747 | * chip reset to recover from that | |
748 | */ | |
749 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { | |
750 | ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); | |
751 | goto exit; | |
752 | } | |
753 | ||
528f0c6b | 754 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 755 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
36323f81 | 756 | txctl.sta = control->sta; |
528f0c6b | 757 | |
d2182b69 | 758 | ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 759 | |
c52f33d0 | 760 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
d2182b69 | 761 | ath_dbg(common, XMIT, "TX failed\n"); |
a5a0bca1 | 762 | TX_STAT_INC(txctl.txq->axq_qnum, txfailed); |
528f0c6b | 763 | goto exit; |
8feceb67 VT |
764 | } |
765 | ||
7bb45683 | 766 | return; |
528f0c6b S |
767 | exit: |
768 | dev_kfree_skb_any(skb); | |
f078f209 LR |
769 | } |
770 | ||
8feceb67 | 771 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 772 | { |
9ac58615 | 773 | struct ath_softc *sc = hw->priv; |
af03abec | 774 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 775 | struct ath_common *common = ath9k_hw_common(ah); |
c0c11741 | 776 | bool prev_idle; |
f078f209 | 777 | |
4c483817 S |
778 | mutex_lock(&sc->mutex); |
779 | ||
9adcf440 | 780 | ath_cancel_work(sc); |
01e18918 | 781 | del_timer_sync(&sc->rx_poll_timer); |
c94dbff7 | 782 | |
781b14a3 | 783 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { |
d2182b69 | 784 | ath_dbg(common, ANY, "Device not present\n"); |
4c483817 | 785 | mutex_unlock(&sc->mutex); |
9c84b797 S |
786 | return; |
787 | } | |
8feceb67 | 788 | |
3867cf6a S |
789 | /* Ensure HW is awake when we try to shut it down. */ |
790 | ath9k_ps_wakeup(sc); | |
791 | ||
6a6733f2 LR |
792 | spin_lock_bh(&sc->sc_pcu_lock); |
793 | ||
203043f5 SG |
794 | /* prevent tasklets to enable interrupts once we disable them */ |
795 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
796 | ||
ff37e337 S |
797 | /* make sure h/w will not generate any interrupt |
798 | * before setting the invalid flag. */ | |
4df3071e | 799 | ath9k_hw_disable_interrupts(ah); |
ff37e337 | 800 | |
c0c11741 FF |
801 | spin_unlock_bh(&sc->sc_pcu_lock); |
802 | ||
803 | /* we can now sync irq and kill any running tasklets, since we already | |
804 | * disabled interrupts and not holding a spin lock */ | |
805 | synchronize_irq(sc->irq); | |
806 | tasklet_kill(&sc->intr_tq); | |
807 | tasklet_kill(&sc->bcon_tasklet); | |
808 | ||
809 | prev_idle = sc->ps_idle; | |
810 | sc->ps_idle = true; | |
811 | ||
812 | spin_lock_bh(&sc->sc_pcu_lock); | |
813 | ||
814 | if (ah->led_pin >= 0) { | |
815 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
816 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
817 | } | |
818 | ||
819 | ath_prepare_reset(sc, false, true); | |
ff37e337 | 820 | |
0d95521e FF |
821 | if (sc->rx.frag) { |
822 | dev_kfree_skb_any(sc->rx.frag); | |
823 | sc->rx.frag = NULL; | |
824 | } | |
825 | ||
c0c11741 FF |
826 | if (!ah->curchan) |
827 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); | |
6a6733f2 | 828 | |
c0c11741 FF |
829 | ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
830 | ath9k_hw_phy_disable(ah); | |
6a6733f2 | 831 | |
c0c11741 | 832 | ath9k_hw_configpcipowersave(ah, true); |
203043f5 | 833 | |
c0c11741 | 834 | spin_unlock_bh(&sc->sc_pcu_lock); |
3867cf6a | 835 | |
c0c11741 | 836 | ath9k_ps_restore(sc); |
ff37e337 | 837 | |
781b14a3 | 838 | set_bit(SC_OP_INVALID, &sc->sc_flags); |
c0c11741 | 839 | sc->ps_idle = prev_idle; |
500c064d | 840 | |
141b38b6 S |
841 | mutex_unlock(&sc->mutex); |
842 | ||
d2182b69 | 843 | ath_dbg(common, CONFIG, "Driver halt\n"); |
f078f209 LR |
844 | } |
845 | ||
4801416c BG |
846 | bool ath9k_uses_beacons(int type) |
847 | { | |
848 | switch (type) { | |
849 | case NL80211_IFTYPE_AP: | |
850 | case NL80211_IFTYPE_ADHOC: | |
851 | case NL80211_IFTYPE_MESH_POINT: | |
852 | return true; | |
853 | default: | |
854 | return false; | |
855 | } | |
856 | } | |
857 | ||
4801416c BG |
858 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
859 | { | |
860 | struct ath9k_vif_iter_data *iter_data = data; | |
861 | int i; | |
862 | ||
863 | if (iter_data->hw_macaddr) | |
864 | for (i = 0; i < ETH_ALEN; i++) | |
865 | iter_data->mask[i] &= | |
866 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
141b38b6 | 867 | |
1ed32e4f | 868 | switch (vif->type) { |
4801416c BG |
869 | case NL80211_IFTYPE_AP: |
870 | iter_data->naps++; | |
f078f209 | 871 | break; |
4801416c BG |
872 | case NL80211_IFTYPE_STATION: |
873 | iter_data->nstations++; | |
e51f3eff | 874 | break; |
05c914fe | 875 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
876 | iter_data->nadhocs++; |
877 | break; | |
9cb5412b | 878 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
879 | iter_data->nmeshes++; |
880 | break; | |
881 | case NL80211_IFTYPE_WDS: | |
882 | iter_data->nwds++; | |
f078f209 LR |
883 | break; |
884 | default: | |
4801416c | 885 | break; |
f078f209 | 886 | } |
4801416c | 887 | } |
f078f209 | 888 | |
6dcc3444 SM |
889 | static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
890 | { | |
891 | struct ath_softc *sc = data; | |
892 | struct ath_vif *avp = (void *)vif->drv_priv; | |
893 | ||
894 | if (vif->type != NL80211_IFTYPE_STATION) | |
895 | return; | |
896 | ||
897 | if (avp->primary_sta_vif) | |
898 | ath9k_set_assoc_state(sc, vif); | |
899 | } | |
900 | ||
4801416c BG |
901 | /* Called with sc->mutex held. */ |
902 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
903 | struct ieee80211_vif *vif, | |
904 | struct ath9k_vif_iter_data *iter_data) | |
905 | { | |
9ac58615 | 906 | struct ath_softc *sc = hw->priv; |
4801416c BG |
907 | struct ath_hw *ah = sc->sc_ah; |
908 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 909 | |
4801416c BG |
910 | /* |
911 | * Use the hardware MAC address as reference, the hardware uses it | |
912 | * together with the BSSID mask when matching addresses. | |
913 | */ | |
914 | memset(iter_data, 0, sizeof(*iter_data)); | |
915 | iter_data->hw_macaddr = common->macaddr; | |
916 | memset(&iter_data->mask, 0xff, ETH_ALEN); | |
5640b08e | 917 | |
4801416c BG |
918 | if (vif) |
919 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
920 | ||
921 | /* Get list of all active MAC addresses */ | |
4801416c BG |
922 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, |
923 | iter_data); | |
4801416c | 924 | } |
8ca21f01 | 925 | |
4801416c BG |
926 | /* Called with sc->mutex held. */ |
927 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
928 | struct ieee80211_vif *vif) | |
929 | { | |
9ac58615 | 930 | struct ath_softc *sc = hw->priv; |
4801416c BG |
931 | struct ath_hw *ah = sc->sc_ah; |
932 | struct ath_common *common = ath9k_hw_common(ah); | |
933 | struct ath9k_vif_iter_data iter_data; | |
6dcc3444 | 934 | enum nl80211_iftype old_opmode = ah->opmode; |
8ca21f01 | 935 | |
4801416c | 936 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 937 | |
4801416c BG |
938 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); |
939 | ath_hw_setbssidmask(common); | |
940 | ||
4801416c | 941 | if (iter_data.naps > 0) { |
60ca9f87 | 942 | ath9k_hw_set_tsfadjust(ah, true); |
4801416c BG |
943 | ah->opmode = NL80211_IFTYPE_AP; |
944 | } else { | |
60ca9f87 | 945 | ath9k_hw_set_tsfadjust(ah, false); |
5640b08e | 946 | |
fd5999cf JC |
947 | if (iter_data.nmeshes) |
948 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
949 | else if (iter_data.nwds) | |
4801416c BG |
950 | ah->opmode = NL80211_IFTYPE_AP; |
951 | else if (iter_data.nadhocs) | |
952 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
953 | else | |
954 | ah->opmode = NL80211_IFTYPE_STATION; | |
955 | } | |
5640b08e | 956 | |
df35d29e SM |
957 | ath9k_hw_setopmode(ah); |
958 | ||
198823fd | 959 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) |
3069168c | 960 | ah->imask |= ATH9K_INT_TSFOOR; |
198823fd | 961 | else |
4801416c | 962 | ah->imask &= ~ATH9K_INT_TSFOOR; |
4af9cf4f | 963 | |
72d874c6 | 964 | ath9k_hw_set_interrupts(ah); |
6dcc3444 SM |
965 | |
966 | /* | |
967 | * If we are changing the opmode to STATION, | |
968 | * a beacon sync needs to be done. | |
969 | */ | |
970 | if (ah->opmode == NL80211_IFTYPE_STATION && | |
971 | old_opmode == NL80211_IFTYPE_AP && | |
972 | test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
973 | ieee80211_iterate_active_interfaces_atomic(sc->hw, | |
974 | ath9k_sta_vif_iter, sc); | |
975 | } | |
4801416c | 976 | } |
6f255425 | 977 | |
4801416c BG |
978 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
979 | struct ieee80211_vif *vif) | |
6b3b991d | 980 | { |
9ac58615 | 981 | struct ath_softc *sc = hw->priv; |
4801416c BG |
982 | struct ath_hw *ah = sc->sc_ah; |
983 | struct ath_common *common = ath9k_hw_common(ah); | |
6b3b991d | 984 | |
4801416c | 985 | mutex_lock(&sc->mutex); |
6b3b991d | 986 | |
d2182b69 | 987 | ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); |
4801416c BG |
988 | sc->nvifs++; |
989 | ||
327967cb | 990 | ath9k_ps_wakeup(sc); |
130ef6e9 | 991 | ath9k_calculate_summary_state(hw, vif); |
327967cb MSS |
992 | ath9k_ps_restore(sc); |
993 | ||
130ef6e9 SM |
994 | if (ath9k_uses_beacons(vif->type)) |
995 | ath9k_beacon_assign_slot(sc, vif); | |
996 | ||
4801416c | 997 | mutex_unlock(&sc->mutex); |
327967cb | 998 | return 0; |
6b3b991d RM |
999 | } |
1000 | ||
1001 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1002 | struct ieee80211_vif *vif, | |
1003 | enum nl80211_iftype new_type, | |
1004 | bool p2p) | |
1005 | { | |
9ac58615 | 1006 | struct ath_softc *sc = hw->priv; |
6b3b991d RM |
1007 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1008 | ||
d2182b69 | 1009 | ath_dbg(common, CONFIG, "Change Interface\n"); |
6b3b991d | 1010 | mutex_lock(&sc->mutex); |
4801416c | 1011 | |
4801416c | 1012 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1013 | ath9k_beacon_remove_slot(sc, vif); |
4801416c | 1014 | |
6b3b991d RM |
1015 | vif->type = new_type; |
1016 | vif->p2p = p2p; | |
1017 | ||
327967cb | 1018 | ath9k_ps_wakeup(sc); |
130ef6e9 | 1019 | ath9k_calculate_summary_state(hw, vif); |
327967cb MSS |
1020 | ath9k_ps_restore(sc); |
1021 | ||
130ef6e9 SM |
1022 | if (ath9k_uses_beacons(vif->type)) |
1023 | ath9k_beacon_assign_slot(sc, vif); | |
1024 | ||
6b3b991d | 1025 | mutex_unlock(&sc->mutex); |
327967cb | 1026 | return 0; |
6b3b991d RM |
1027 | } |
1028 | ||
8feceb67 | 1029 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1030 | struct ieee80211_vif *vif) |
f078f209 | 1031 | { |
9ac58615 | 1032 | struct ath_softc *sc = hw->priv; |
c46917bb | 1033 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1034 | |
d2182b69 | 1035 | ath_dbg(common, CONFIG, "Detach Interface\n"); |
f078f209 | 1036 | |
141b38b6 S |
1037 | mutex_lock(&sc->mutex); |
1038 | ||
4801416c | 1039 | sc->nvifs--; |
580f0b8a | 1040 | |
4801416c | 1041 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1042 | ath9k_beacon_remove_slot(sc, vif); |
2c3db3d5 | 1043 | |
327967cb | 1044 | ath9k_ps_wakeup(sc); |
4801416c | 1045 | ath9k_calculate_summary_state(hw, NULL); |
327967cb | 1046 | ath9k_ps_restore(sc); |
141b38b6 S |
1047 | |
1048 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1049 | } |
1050 | ||
fbab7390 | 1051 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1052 | { |
3069168c | 1053 | struct ath_hw *ah = sc->sc_ah; |
ad128860 | 1054 | struct ath_common *common = ath9k_hw_common(ah); |
3069168c | 1055 | |
3f7c5c10 | 1056 | sc->ps_enabled = true; |
3069168c PR |
1057 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1058 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1059 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1060 | ath9k_hw_set_interrupts(ah); |
3f7c5c10 | 1061 | } |
fdf76622 | 1062 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1063 | } |
ad128860 | 1064 | ath_dbg(common, PS, "PowerSave enabled\n"); |
3f7c5c10 SB |
1065 | } |
1066 | ||
845d708e SB |
1067 | static void ath9k_disable_ps(struct ath_softc *sc) |
1068 | { | |
1069 | struct ath_hw *ah = sc->sc_ah; | |
ad128860 | 1070 | struct ath_common *common = ath9k_hw_common(ah); |
845d708e SB |
1071 | |
1072 | sc->ps_enabled = false; | |
1073 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1074 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1075 | ath9k_hw_setrxabort(ah, 0); | |
1076 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1077 | PS_WAIT_FOR_CAB | | |
1078 | PS_WAIT_FOR_PSPOLL_DATA | | |
1079 | PS_WAIT_FOR_TX_ACK); | |
1080 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1081 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1082 | ath9k_hw_set_interrupts(ah); |
845d708e SB |
1083 | } |
1084 | } | |
ad128860 | 1085 | ath_dbg(common, PS, "PowerSave disabled\n"); |
845d708e SB |
1086 | } |
1087 | ||
e8975581 | 1088 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1089 | { |
9ac58615 | 1090 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1091 | struct ath_hw *ah = sc->sc_ah; |
1092 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1093 | struct ieee80211_conf *conf = &hw->conf; |
75600abf | 1094 | bool reset_channel = false; |
f078f209 | 1095 | |
c0c11741 | 1096 | ath9k_ps_wakeup(sc); |
aa33de09 | 1097 | mutex_lock(&sc->mutex); |
141b38b6 | 1098 | |
daa1b6ee | 1099 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 | 1100 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
b73f3e78 | 1101 | if (sc->ps_idle) { |
daa1b6ee | 1102 | ath_cancel_work(sc); |
b73f3e78 RM |
1103 | ath9k_stop_btcoex(sc); |
1104 | } else { | |
1105 | ath9k_start_btcoex(sc); | |
75600abf FF |
1106 | /* |
1107 | * The chip needs a reset to properly wake up from | |
1108 | * full sleep | |
1109 | */ | |
1110 | reset_channel = ah->chip_fullsleep; | |
b73f3e78 | 1111 | } |
daa1b6ee | 1112 | } |
64839170 | 1113 | |
e7824a50 LR |
1114 | /* |
1115 | * We just prepare to enable PS. We have to wait until our AP has | |
1116 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1117 | * those ACKs and end up retransmitting the same null data frames. | |
1118 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1119 | */ | |
3cbb5dd7 | 1120 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1121 | unsigned long flags; |
1122 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1123 | if (conf->flags & IEEE80211_CONF_PS) |
1124 | ath9k_enable_ps(sc); | |
845d708e SB |
1125 | else |
1126 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1127 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1128 | } |
1129 | ||
199afd9d S |
1130 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1131 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
d2182b69 | 1132 | ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); |
5f841b41 RM |
1133 | sc->sc_ah->is_monitoring = true; |
1134 | } else { | |
d2182b69 | 1135 | ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); |
5f841b41 | 1136 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1137 | } |
1138 | } | |
1139 | ||
75600abf | 1140 | if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { |
99405f93 | 1141 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1142 | int pos = curchan->hw_value; |
3430098a FF |
1143 | int old_pos = -1; |
1144 | unsigned long flags; | |
1145 | ||
1146 | if (ah->curchan) | |
1147 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1148 | |
d2182b69 | 1149 | ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", |
8c79a610 | 1150 | curchan->center_freq, conf->channel_type); |
f078f209 | 1151 | |
3430098a FF |
1152 | /* update survey stats for the old channel before switching */ |
1153 | spin_lock_irqsave(&common->cc_lock, flags); | |
1154 | ath_update_survey_stats(sc); | |
1155 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1156 | ||
e338a85e RM |
1157 | /* |
1158 | * Preserve the current channel values, before updating | |
1159 | * the same channel | |
1160 | */ | |
1a19f77f RM |
1161 | if (ah->curchan && (old_pos == pos)) |
1162 | ath9k_hw_getnf(ah, ah->curchan); | |
e338a85e RM |
1163 | |
1164 | ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], | |
1165 | curchan, conf->channel_type); | |
1166 | ||
3430098a FF |
1167 | /* |
1168 | * If the operating channel changes, change the survey in-use flags | |
1169 | * along with it. | |
1170 | * Reset the survey data for the new channel, unless we're switching | |
1171 | * back to the operating channel from an off-channel operation. | |
1172 | */ | |
1173 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1174 | sc->cur_survey != &sc->survey[pos]) { | |
1175 | ||
1176 | if (sc->cur_survey) | |
1177 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1178 | ||
1179 | sc->cur_survey = &sc->survey[pos]; | |
1180 | ||
1181 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1182 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1183 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1184 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1185 | } | |
1186 | ||
0e2dedf9 | 1187 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1188 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1189 | mutex_unlock(&sc->mutex); |
8389fb3f | 1190 | ath9k_ps_restore(sc); |
e11602b7 S |
1191 | return -EINVAL; |
1192 | } | |
3430098a FF |
1193 | |
1194 | /* | |
1195 | * The most recent snapshot of channel->noisefloor for the old | |
1196 | * channel is only available after the hardware reset. Copy it to | |
1197 | * the survey stats now. | |
1198 | */ | |
1199 | if (old_pos >= 0) | |
1200 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1201 | } |
f078f209 | 1202 | |
c9f6a656 | 1203 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
d2182b69 | 1204 | ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); |
17d7904d | 1205 | sc->config.txpowlimit = 2 * conf->power_level; |
5048e8c3 RM |
1206 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1207 | sc->config.txpowlimit, &sc->curtxpow); | |
64839170 LR |
1208 | } |
1209 | ||
aa33de09 | 1210 | mutex_unlock(&sc->mutex); |
c0c11741 | 1211 | ath9k_ps_restore(sc); |
141b38b6 | 1212 | |
f078f209 LR |
1213 | return 0; |
1214 | } | |
1215 | ||
8feceb67 VT |
1216 | #define SUPPORTED_FILTERS \ |
1217 | (FIF_PROMISC_IN_BSS | \ | |
1218 | FIF_ALLMULTI | \ | |
1219 | FIF_CONTROL | \ | |
af6a3fc7 | 1220 | FIF_PSPOLL | \ |
8feceb67 VT |
1221 | FIF_OTHER_BSS | \ |
1222 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1223 | FIF_PROBE_REQ | \ |
8feceb67 | 1224 | FIF_FCSFAIL) |
c83be688 | 1225 | |
8feceb67 VT |
1226 | /* FIXME: sc->sc_full_reset ? */ |
1227 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1228 | unsigned int changed_flags, | |
1229 | unsigned int *total_flags, | |
3ac64bee | 1230 | u64 multicast) |
8feceb67 | 1231 | { |
9ac58615 | 1232 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1233 | u32 rfilt; |
f078f209 | 1234 | |
8feceb67 VT |
1235 | changed_flags &= SUPPORTED_FILTERS; |
1236 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1237 | |
b77f483f | 1238 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1239 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1240 | rfilt = ath_calcrxfilter(sc); |
1241 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1242 | ath9k_ps_restore(sc); |
f078f209 | 1243 | |
d2182b69 JP |
1244 | ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", |
1245 | rfilt); | |
8feceb67 | 1246 | } |
f078f209 | 1247 | |
4ca77860 JB |
1248 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1249 | struct ieee80211_vif *vif, | |
1250 | struct ieee80211_sta *sta) | |
8feceb67 | 1251 | { |
9ac58615 | 1252 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1253 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1254 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1255 | struct ieee80211_key_conf ps_key = { }; | |
f078f209 | 1256 | |
7e1e3864 | 1257 | ath_node_attach(sc, sta, vif); |
f59a59fe FF |
1258 | |
1259 | if (vif->type != NL80211_IFTYPE_AP && | |
1260 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1261 | return 0; | |
1262 | ||
93ae2dd2 | 1263 | an->ps_key = ath_key_config(common, vif, sta, &ps_key); |
4ca77860 JB |
1264 | |
1265 | return 0; | |
1266 | } | |
1267 | ||
93ae2dd2 FF |
1268 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1269 | struct ieee80211_vif *vif, | |
1270 | struct ieee80211_sta *sta) | |
1271 | { | |
1272 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1273 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1274 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1275 | ||
1276 | if (!an->ps_key) | |
1277 | return; | |
1278 | ||
1279 | ath_key_delete(common, &ps_key); | |
1280 | } | |
1281 | ||
4ca77860 JB |
1282 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1283 | struct ieee80211_vif *vif, | |
1284 | struct ieee80211_sta *sta) | |
1285 | { | |
9ac58615 | 1286 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1287 | |
93ae2dd2 | 1288 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1289 | ath_node_detach(sc, sta); |
1290 | ||
1291 | return 0; | |
f078f209 LR |
1292 | } |
1293 | ||
5519541d FF |
1294 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1295 | struct ieee80211_vif *vif, | |
1296 | enum sta_notify_cmd cmd, | |
1297 | struct ieee80211_sta *sta) | |
1298 | { | |
1299 | struct ath_softc *sc = hw->priv; | |
1300 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1301 | ||
3d4e20f2 | 1302 | if (!sta->ht_cap.ht_supported) |
b25bfda3 MSS |
1303 | return; |
1304 | ||
5519541d FF |
1305 | switch (cmd) { |
1306 | case STA_NOTIFY_SLEEP: | |
1307 | an->sleeping = true; | |
042ec453 | 1308 | ath_tx_aggr_sleep(sta, sc, an); |
5519541d FF |
1309 | break; |
1310 | case STA_NOTIFY_AWAKE: | |
1311 | an->sleeping = false; | |
1312 | ath_tx_aggr_wakeup(sc, an); | |
1313 | break; | |
1314 | } | |
1315 | } | |
1316 | ||
8a3a3c85 EP |
1317 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
1318 | struct ieee80211_vif *vif, u16 queue, | |
8feceb67 | 1319 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1320 | { |
9ac58615 | 1321 | struct ath_softc *sc = hw->priv; |
c46917bb | 1322 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1323 | struct ath_txq *txq; |
8feceb67 | 1324 | struct ath9k_tx_queue_info qi; |
066dae93 | 1325 | int ret = 0; |
f078f209 | 1326 | |
8feceb67 VT |
1327 | if (queue >= WME_NUM_AC) |
1328 | return 0; | |
f078f209 | 1329 | |
066dae93 FF |
1330 | txq = sc->tx.txq_map[queue]; |
1331 | ||
96f372c9 | 1332 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1333 | mutex_lock(&sc->mutex); |
1334 | ||
1ffb0610 S |
1335 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1336 | ||
8feceb67 VT |
1337 | qi.tqi_aifs = params->aifs; |
1338 | qi.tqi_cwmin = params->cw_min; | |
1339 | qi.tqi_cwmax = params->cw_max; | |
531bd079 | 1340 | qi.tqi_burstTime = params->txop * 32; |
f078f209 | 1341 | |
d2182b69 | 1342 | ath_dbg(common, CONFIG, |
226afe68 JP |
1343 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1344 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1345 | params->cw_max, params->txop); | |
f078f209 | 1346 | |
aa5955c3 | 1347 | ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); |
066dae93 | 1348 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1349 | if (ret) |
3800276a | 1350 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1351 | |
141b38b6 | 1352 | mutex_unlock(&sc->mutex); |
96f372c9 | 1353 | ath9k_ps_restore(sc); |
141b38b6 | 1354 | |
8feceb67 VT |
1355 | return ret; |
1356 | } | |
f078f209 | 1357 | |
8feceb67 VT |
1358 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1359 | enum set_key_cmd cmd, | |
dc822b5d JB |
1360 | struct ieee80211_vif *vif, |
1361 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1362 | struct ieee80211_key_conf *key) |
1363 | { | |
9ac58615 | 1364 | struct ath_softc *sc = hw->priv; |
c46917bb | 1365 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1366 | int ret = 0; |
f078f209 | 1367 | |
3e6109c5 | 1368 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1369 | return -ENOSPC; |
1370 | ||
5bd5e9a6 CYY |
1371 | if ((vif->type == NL80211_IFTYPE_ADHOC || |
1372 | vif->type == NL80211_IFTYPE_MESH_POINT) && | |
cfdc9a8b JM |
1373 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || |
1374 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1375 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1376 | /* | |
1377 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1378 | * could be optimized in the future to use a modified key cache | |
1379 | * design to support per-STA RX GTK, but until that gets | |
1380 | * implemented, use of software crypto for group addressed | |
1381 | * frames is a acceptable to allow RSN IBSS to be used. | |
1382 | */ | |
1383 | return -EOPNOTSUPP; | |
1384 | } | |
1385 | ||
141b38b6 | 1386 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1387 | ath9k_ps_wakeup(sc); |
d2182b69 | 1388 | ath_dbg(common, CONFIG, "Set HW Key\n"); |
f078f209 | 1389 | |
8feceb67 VT |
1390 | switch (cmd) { |
1391 | case SET_KEY: | |
93ae2dd2 FF |
1392 | if (sta) |
1393 | ath9k_del_ps_key(sc, vif, sta); | |
1394 | ||
040e539e | 1395 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1396 | if (ret >= 0) { |
1397 | key->hw_key_idx = ret; | |
8feceb67 VT |
1398 | /* push IV and Michael MIC generation to stack */ |
1399 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1400 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1401 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1402 | if (sc->sc_ah->sw_mgmt_crypto && |
1403 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
e548c49e | 1404 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; |
6ace2891 | 1405 | ret = 0; |
8feceb67 VT |
1406 | } |
1407 | break; | |
1408 | case DISABLE_KEY: | |
040e539e | 1409 | ath_key_delete(common, key); |
8feceb67 VT |
1410 | break; |
1411 | default: | |
1412 | ret = -EINVAL; | |
1413 | } | |
f078f209 | 1414 | |
3cbb5dd7 | 1415 | ath9k_ps_restore(sc); |
141b38b6 S |
1416 | mutex_unlock(&sc->mutex); |
1417 | ||
8feceb67 VT |
1418 | return ret; |
1419 | } | |
6c43c090 SM |
1420 | |
1421 | static void ath9k_set_assoc_state(struct ath_softc *sc, | |
1422 | struct ieee80211_vif *vif) | |
4f5ef75b | 1423 | { |
4f5ef75b | 1424 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4f5ef75b | 1425 | struct ath_vif *avp = (void *)vif->drv_priv; |
6c43c090 | 1426 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; |
07c15a3f | 1427 | unsigned long flags; |
6c43c090 SM |
1428 | |
1429 | set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); | |
1430 | avp->primary_sta_vif = true; | |
1431 | ||
2e5ef459 | 1432 | /* |
6c43c090 SM |
1433 | * Set the AID, BSSID and do beacon-sync only when |
1434 | * the HW opmode is STATION. | |
1435 | * | |
1436 | * But the primary bit is set above in any case. | |
2e5ef459 | 1437 | */ |
6c43c090 | 1438 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
2e5ef459 RM |
1439 | return; |
1440 | ||
6c43c090 SM |
1441 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1442 | common->curaid = bss_conf->aid; | |
1443 | ath9k_hw_write_associd(sc->sc_ah); | |
07c15a3f | 1444 | |
6c43c090 SM |
1445 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
1446 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
99e4d43a | 1447 | |
6c43c090 SM |
1448 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
1449 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
1450 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
05c0be2f | 1451 | |
6c43c090 SM |
1452 | ath_dbg(common, CONFIG, |
1453 | "Primary Station interface: %pM, BSSID: %pM\n", | |
1454 | vif->addr, common->curbssid); | |
4f5ef75b RM |
1455 | } |
1456 | ||
6c43c090 | 1457 | static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
4f5ef75b | 1458 | { |
6c43c090 | 1459 | struct ath_softc *sc = data; |
4f5ef75b | 1460 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; |
4f5ef75b | 1461 | |
6c43c090 | 1462 | if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) |
2e5ef459 RM |
1463 | return; |
1464 | ||
6c43c090 SM |
1465 | if (bss_conf->assoc) |
1466 | ath9k_set_assoc_state(sc, vif); | |
4f5ef75b | 1467 | } |
f078f209 | 1468 | |
8feceb67 VT |
1469 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1470 | struct ieee80211_vif *vif, | |
1471 | struct ieee80211_bss_conf *bss_conf, | |
1472 | u32 changed) | |
1473 | { | |
da0d45f7 SM |
1474 | #define CHECK_ANI \ |
1475 | (BSS_CHANGED_ASSOC | \ | |
1476 | BSS_CHANGED_IBSS | \ | |
1477 | BSS_CHANGED_BEACON_ENABLED) | |
1478 | ||
9ac58615 | 1479 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 1480 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1481 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1482 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1483 | int slottime; |
f078f209 | 1484 | |
96f372c9 | 1485 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1486 | mutex_lock(&sc->mutex); |
1487 | ||
9f61903c | 1488 | if (changed & BSS_CHANGED_ASSOC) { |
6c43c090 SM |
1489 | ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", |
1490 | bss_conf->bssid, bss_conf->assoc); | |
1491 | ||
1492 | if (avp->primary_sta_vif && !bss_conf->assoc) { | |
1493 | clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); | |
1494 | avp->primary_sta_vif = false; | |
1495 | ||
1496 | if (ah->opmode == NL80211_IFTYPE_STATION) | |
1497 | clear_bit(SC_OP_BEACONS, &sc->sc_flags); | |
1498 | } | |
1499 | ||
1500 | ieee80211_iterate_active_interfaces_atomic(sc->hw, | |
1501 | ath9k_bss_assoc_iter, sc); | |
2d0ddec5 | 1502 | |
6c43c090 SM |
1503 | if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && |
1504 | ah->opmode == NL80211_IFTYPE_STATION) { | |
1505 | memset(common->curbssid, 0, ETH_ALEN); | |
1506 | common->curaid = 0; | |
1507 | ath9k_hw_write_associd(sc->sc_ah); | |
1508 | } | |
c6089ccc | 1509 | } |
2d0ddec5 | 1510 | |
2e5ef459 | 1511 | if (changed & BSS_CHANGED_IBSS) { |
2e5ef459 RM |
1512 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1513 | common->curaid = bss_conf->aid; | |
1514 | ath9k_hw_write_associd(sc->sc_ah); | |
2e5ef459 RM |
1515 | } |
1516 | ||
ef4ad633 SM |
1517 | if ((changed & BSS_CHANGED_BEACON_ENABLED) || |
1518 | (changed & BSS_CHANGED_BEACON_INT)) { | |
2f8e82e8 SM |
1519 | if (ah->opmode == NL80211_IFTYPE_AP && |
1520 | bss_conf->enable_beacon) | |
1521 | ath9k_set_tsfadjust(sc, vif); | |
ef4ad633 SM |
1522 | if (ath9k_allow_beacon_config(sc, vif)) |
1523 | ath9k_beacon_config(sc, vif, changed); | |
0005baf4 FF |
1524 | } |
1525 | ||
1526 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1527 | if (bss_conf->use_short_slot) | |
1528 | slottime = 9; | |
1529 | else | |
1530 | slottime = 20; | |
1531 | if (vif->type == NL80211_IFTYPE_AP) { | |
1532 | /* | |
1533 | * Defer update, so that connected stations can adjust | |
1534 | * their settings at the same time. | |
1535 | * See beacon.c for more details | |
1536 | */ | |
1537 | sc->beacon.slottime = slottime; | |
1538 | sc->beacon.updateslot = UPDATE; | |
1539 | } else { | |
1540 | ah->slottime = slottime; | |
1541 | ath9k_hw_init_global_settings(ah); | |
1542 | } | |
2d0ddec5 JB |
1543 | } |
1544 | ||
da0d45f7 SM |
1545 | if (changed & CHECK_ANI) |
1546 | ath_check_ani(sc); | |
1547 | ||
141b38b6 | 1548 | mutex_unlock(&sc->mutex); |
96f372c9 | 1549 | ath9k_ps_restore(sc); |
da0d45f7 SM |
1550 | |
1551 | #undef CHECK_ANI | |
8feceb67 | 1552 | } |
f078f209 | 1553 | |
37a41b4a | 1554 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1555 | { |
9ac58615 | 1556 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1557 | u64 tsf; |
f078f209 | 1558 | |
141b38b6 | 1559 | mutex_lock(&sc->mutex); |
9abbfb27 | 1560 | ath9k_ps_wakeup(sc); |
141b38b6 | 1561 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 1562 | ath9k_ps_restore(sc); |
141b38b6 | 1563 | mutex_unlock(&sc->mutex); |
f078f209 | 1564 | |
8feceb67 VT |
1565 | return tsf; |
1566 | } | |
f078f209 | 1567 | |
37a41b4a EP |
1568 | static void ath9k_set_tsf(struct ieee80211_hw *hw, |
1569 | struct ieee80211_vif *vif, | |
1570 | u64 tsf) | |
3b5d665b | 1571 | { |
9ac58615 | 1572 | struct ath_softc *sc = hw->priv; |
3b5d665b | 1573 | |
141b38b6 | 1574 | mutex_lock(&sc->mutex); |
9abbfb27 | 1575 | ath9k_ps_wakeup(sc); |
141b38b6 | 1576 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 1577 | ath9k_ps_restore(sc); |
141b38b6 | 1578 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
1579 | } |
1580 | ||
37a41b4a | 1581 | static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1582 | { |
9ac58615 | 1583 | struct ath_softc *sc = hw->priv; |
c83be688 | 1584 | |
141b38b6 | 1585 | mutex_lock(&sc->mutex); |
21526d57 LR |
1586 | |
1587 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1588 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1589 | ath9k_ps_restore(sc); |
1590 | ||
141b38b6 | 1591 | mutex_unlock(&sc->mutex); |
8feceb67 | 1592 | } |
f078f209 | 1593 | |
8feceb67 | 1594 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1595 | struct ieee80211_vif *vif, |
141b38b6 S |
1596 | enum ieee80211_ampdu_mlme_action action, |
1597 | struct ieee80211_sta *sta, | |
0b01f030 | 1598 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 1599 | { |
9ac58615 | 1600 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1601 | int ret = 0; |
f078f209 | 1602 | |
85ad181e JB |
1603 | local_bh_disable(); |
1604 | ||
8feceb67 VT |
1605 | switch (action) { |
1606 | case IEEE80211_AMPDU_RX_START: | |
8feceb67 VT |
1607 | break; |
1608 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1609 | break; |
1610 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1611 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
1612 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
1613 | if (!ret) | |
1614 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 1615 | ath9k_ps_restore(sc); |
8feceb67 VT |
1616 | break; |
1617 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 1618 | ath9k_ps_wakeup(sc); |
f83da965 | 1619 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 1620 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1621 | ath9k_ps_restore(sc); |
8feceb67 | 1622 | break; |
b1720231 | 1623 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1624 | ath9k_ps_wakeup(sc); |
8469cdef | 1625 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1626 | ath9k_ps_restore(sc); |
8469cdef | 1627 | break; |
8feceb67 | 1628 | default: |
3800276a | 1629 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
1630 | } |
1631 | ||
85ad181e JB |
1632 | local_bh_enable(); |
1633 | ||
8feceb67 | 1634 | return ret; |
f078f209 LR |
1635 | } |
1636 | ||
62dad5b0 BP |
1637 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1638 | struct survey_info *survey) | |
1639 | { | |
9ac58615 | 1640 | struct ath_softc *sc = hw->priv; |
3430098a | 1641 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 1642 | struct ieee80211_supported_band *sband; |
3430098a FF |
1643 | struct ieee80211_channel *chan; |
1644 | unsigned long flags; | |
1645 | int pos; | |
1646 | ||
1647 | spin_lock_irqsave(&common->cc_lock, flags); | |
1648 | if (idx == 0) | |
1649 | ath_update_survey_stats(sc); | |
39162dbe FF |
1650 | |
1651 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
1652 | if (sband && idx >= sband->n_channels) { | |
1653 | idx -= sband->n_channels; | |
1654 | sband = NULL; | |
1655 | } | |
62dad5b0 | 1656 | |
39162dbe FF |
1657 | if (!sband) |
1658 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 1659 | |
3430098a FF |
1660 | if (!sband || idx >= sband->n_channels) { |
1661 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1662 | return -ENOENT; | |
4f1a5a4b | 1663 | } |
62dad5b0 | 1664 | |
3430098a FF |
1665 | chan = &sband->channels[idx]; |
1666 | pos = chan->hw_value; | |
1667 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
1668 | survey->channel = chan; | |
1669 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1670 | ||
62dad5b0 BP |
1671 | return 0; |
1672 | } | |
1673 | ||
e239d859 FF |
1674 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
1675 | { | |
9ac58615 | 1676 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
1677 | struct ath_hw *ah = sc->sc_ah; |
1678 | ||
1679 | mutex_lock(&sc->mutex); | |
1680 | ah->coverage_class = coverage_class; | |
8b2a3827 MSS |
1681 | |
1682 | ath9k_ps_wakeup(sc); | |
e239d859 | 1683 | ath9k_hw_init_global_settings(ah); |
8b2a3827 MSS |
1684 | ath9k_ps_restore(sc); |
1685 | ||
e239d859 FF |
1686 | mutex_unlock(&sc->mutex); |
1687 | } | |
1688 | ||
69081624 VT |
1689 | static void ath9k_flush(struct ieee80211_hw *hw, bool drop) |
1690 | { | |
69081624 | 1691 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
1692 | struct ath_hw *ah = sc->sc_ah; |
1693 | struct ath_common *common = ath9k_hw_common(ah); | |
86271e46 FF |
1694 | int timeout = 200; /* ms */ |
1695 | int i, j; | |
2f6fc351 | 1696 | bool drain_txq; |
69081624 VT |
1697 | |
1698 | mutex_lock(&sc->mutex); | |
69081624 VT |
1699 | cancel_delayed_work_sync(&sc->tx_complete_work); |
1700 | ||
6a6b3f3e | 1701 | if (ah->ah_flags & AH_UNPLUGGED) { |
d2182b69 | 1702 | ath_dbg(common, ANY, "Device has been unplugged!\n"); |
6a6b3f3e MSS |
1703 | mutex_unlock(&sc->mutex); |
1704 | return; | |
1705 | } | |
1706 | ||
781b14a3 | 1707 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { |
d2182b69 | 1708 | ath_dbg(common, ANY, "Device not present\n"); |
99aa55b6 MSS |
1709 | mutex_unlock(&sc->mutex); |
1710 | return; | |
1711 | } | |
1712 | ||
86271e46 | 1713 | for (j = 0; j < timeout; j++) { |
108697c4 | 1714 | bool npend = false; |
86271e46 FF |
1715 | |
1716 | if (j) | |
1717 | usleep_range(1000, 2000); | |
69081624 | 1718 | |
86271e46 FF |
1719 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
1720 | if (!ATH_TXQ_SETUP(sc, i)) | |
1721 | continue; | |
1722 | ||
108697c4 MSS |
1723 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); |
1724 | ||
1725 | if (npend) | |
1726 | break; | |
69081624 | 1727 | } |
86271e46 FF |
1728 | |
1729 | if (!npend) | |
9df0d6a2 | 1730 | break; |
69081624 VT |
1731 | } |
1732 | ||
9df0d6a2 FF |
1733 | if (drop) { |
1734 | ath9k_ps_wakeup(sc); | |
1735 | spin_lock_bh(&sc->sc_pcu_lock); | |
1736 | drain_txq = ath_drain_all_txq(sc, false); | |
1737 | spin_unlock_bh(&sc->sc_pcu_lock); | |
9adcf440 | 1738 | |
9df0d6a2 FF |
1739 | if (!drain_txq) |
1740 | ath_reset(sc, false); | |
9adcf440 | 1741 | |
9df0d6a2 FF |
1742 | ath9k_ps_restore(sc); |
1743 | ieee80211_wake_queues(hw); | |
1744 | } | |
d78f4b3e | 1745 | |
69081624 VT |
1746 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
1747 | mutex_unlock(&sc->mutex); | |
1748 | } | |
1749 | ||
15b91e83 VN |
1750 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
1751 | { | |
1752 | struct ath_softc *sc = hw->priv; | |
1753 | int i; | |
1754 | ||
1755 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1756 | if (!ATH_TXQ_SETUP(sc, i)) | |
1757 | continue; | |
1758 | ||
1759 | if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) | |
1760 | return true; | |
1761 | } | |
1762 | return false; | |
1763 | } | |
1764 | ||
5595f119 | 1765 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
1766 | { |
1767 | struct ath_softc *sc = hw->priv; | |
1768 | struct ath_hw *ah = sc->sc_ah; | |
1769 | struct ieee80211_vif *vif; | |
1770 | struct ath_vif *avp; | |
1771 | struct ath_buf *bf; | |
1772 | struct ath_tx_status ts; | |
4286df60 | 1773 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
ba4903f9 FF |
1774 | int status; |
1775 | ||
1776 | vif = sc->beacon.bslot[0]; | |
1777 | if (!vif) | |
1778 | return 0; | |
1779 | ||
aa45fe96 | 1780 | if (!vif->bss_conf.enable_beacon) |
ba4903f9 FF |
1781 | return 0; |
1782 | ||
aa45fe96 SM |
1783 | avp = (void *)vif->drv_priv; |
1784 | ||
4286df60 | 1785 | if (!sc->beacon.tx_processed && !edma) { |
ba4903f9 FF |
1786 | tasklet_disable(&sc->bcon_tasklet); |
1787 | ||
1788 | bf = avp->av_bcbuf; | |
1789 | if (!bf || !bf->bf_mpdu) | |
1790 | goto skip; | |
1791 | ||
1792 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
1793 | if (status == -EINPROGRESS) | |
1794 | goto skip; | |
1795 | ||
1796 | sc->beacon.tx_processed = true; | |
1797 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
1798 | ||
1799 | skip: | |
1800 | tasklet_enable(&sc->bcon_tasklet); | |
1801 | } | |
1802 | ||
1803 | return sc->beacon.tx_last; | |
1804 | } | |
1805 | ||
52c94f41 MSS |
1806 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
1807 | struct ieee80211_low_level_stats *stats) | |
1808 | { | |
1809 | struct ath_softc *sc = hw->priv; | |
1810 | struct ath_hw *ah = sc->sc_ah; | |
1811 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
1812 | ||
1813 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
1814 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
1815 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
1816 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
1817 | return 0; | |
1818 | } | |
1819 | ||
43c35284 FF |
1820 | static u32 fill_chainmask(u32 cap, u32 new) |
1821 | { | |
1822 | u32 filled = 0; | |
1823 | int i; | |
1824 | ||
1825 | for (i = 0; cap && new; i++, cap >>= 1) { | |
1826 | if (!(cap & BIT(0))) | |
1827 | continue; | |
1828 | ||
1829 | if (new & BIT(0)) | |
1830 | filled |= BIT(i); | |
1831 | ||
1832 | new >>= 1; | |
1833 | } | |
1834 | ||
1835 | return filled; | |
1836 | } | |
1837 | ||
5d9c7e3c FF |
1838 | static bool validate_antenna_mask(struct ath_hw *ah, u32 val) |
1839 | { | |
1840 | switch (val & 0x7) { | |
1841 | case 0x1: | |
1842 | case 0x3: | |
1843 | case 0x7: | |
1844 | return true; | |
1845 | case 0x2: | |
1846 | return (ah->caps.rx_chainmask == 1); | |
1847 | default: | |
1848 | return false; | |
1849 | } | |
1850 | } | |
1851 | ||
43c35284 FF |
1852 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) |
1853 | { | |
1854 | struct ath_softc *sc = hw->priv; | |
1855 | struct ath_hw *ah = sc->sc_ah; | |
1856 | ||
5d9c7e3c FF |
1857 | if (ah->caps.rx_chainmask != 1) |
1858 | rx_ant |= tx_ant; | |
1859 | ||
1860 | if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) | |
43c35284 FF |
1861 | return -EINVAL; |
1862 | ||
1863 | sc->ant_rx = rx_ant; | |
1864 | sc->ant_tx = tx_ant; | |
1865 | ||
1866 | if (ah->caps.rx_chainmask == 1) | |
1867 | return 0; | |
1868 | ||
1869 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | |
1870 | if (AR_SREV_9100(ah)) | |
1871 | ah->rxchainmask = 0x7; | |
1872 | else | |
1873 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | |
1874 | ||
1875 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | |
1876 | ath9k_reload_chainmask_settings(sc); | |
1877 | ||
1878 | return 0; | |
1879 | } | |
1880 | ||
1881 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
1882 | { | |
1883 | struct ath_softc *sc = hw->priv; | |
1884 | ||
1885 | *tx_ant = sc->ant_tx; | |
1886 | *rx_ant = sc->ant_rx; | |
1887 | return 0; | |
1888 | } | |
1889 | ||
b90bd9d1 BG |
1890 | #ifdef CONFIG_ATH9K_DEBUGFS |
1891 | ||
1892 | /* Ethtool support for get-stats */ | |
1893 | ||
1894 | #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO" | |
1895 | static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = { | |
1896 | "tx_pkts_nic", | |
1897 | "tx_bytes_nic", | |
1898 | "rx_pkts_nic", | |
1899 | "rx_bytes_nic", | |
1900 | AMKSTR(d_tx_pkts), | |
1901 | AMKSTR(d_tx_bytes), | |
1902 | AMKSTR(d_tx_mpdus_queued), | |
1903 | AMKSTR(d_tx_mpdus_completed), | |
1904 | AMKSTR(d_tx_mpdu_xretries), | |
1905 | AMKSTR(d_tx_aggregates), | |
1906 | AMKSTR(d_tx_ampdus_queued_hw), | |
1907 | AMKSTR(d_tx_ampdus_queued_sw), | |
1908 | AMKSTR(d_tx_ampdus_completed), | |
1909 | AMKSTR(d_tx_ampdu_retries), | |
1910 | AMKSTR(d_tx_ampdu_xretries), | |
1911 | AMKSTR(d_tx_fifo_underrun), | |
1912 | AMKSTR(d_tx_op_exceeded), | |
1913 | AMKSTR(d_tx_timer_expiry), | |
1914 | AMKSTR(d_tx_desc_cfg_err), | |
1915 | AMKSTR(d_tx_data_underrun), | |
1916 | AMKSTR(d_tx_delim_underrun), | |
1917 | ||
1918 | "d_rx_decrypt_crc_err", | |
1919 | "d_rx_phy_err", | |
1920 | "d_rx_mic_err", | |
1921 | "d_rx_pre_delim_crc_err", | |
1922 | "d_rx_post_delim_crc_err", | |
1923 | "d_rx_decrypt_busy_err", | |
1924 | ||
1925 | "d_rx_phyerr_radar", | |
1926 | "d_rx_phyerr_ofdm_timing", | |
1927 | "d_rx_phyerr_cck_timing", | |
1928 | ||
1929 | }; | |
1930 | #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats) | |
1931 | ||
1932 | static void ath9k_get_et_strings(struct ieee80211_hw *hw, | |
1933 | struct ieee80211_vif *vif, | |
1934 | u32 sset, u8 *data) | |
1935 | { | |
1936 | if (sset == ETH_SS_STATS) | |
1937 | memcpy(data, *ath9k_gstrings_stats, | |
1938 | sizeof(ath9k_gstrings_stats)); | |
1939 | } | |
1940 | ||
1941 | static int ath9k_get_et_sset_count(struct ieee80211_hw *hw, | |
1942 | struct ieee80211_vif *vif, int sset) | |
1943 | { | |
1944 | if (sset == ETH_SS_STATS) | |
1945 | return ATH9K_SSTATS_LEN; | |
1946 | return 0; | |
1947 | } | |
1948 | ||
1949 | #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum) | |
1950 | #define AWDATA(elem) \ | |
1951 | do { \ | |
1952 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \ | |
1953 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \ | |
1954 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \ | |
1955 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \ | |
1956 | } while (0) | |
1957 | ||
1958 | #define AWDATA_RX(elem) \ | |
1959 | do { \ | |
1960 | data[i++] = sc->debug.stats.rxstats.elem; \ | |
1961 | } while (0) | |
1962 | ||
1963 | static void ath9k_get_et_stats(struct ieee80211_hw *hw, | |
1964 | struct ieee80211_vif *vif, | |
1965 | struct ethtool_stats *stats, u64 *data) | |
1966 | { | |
1967 | struct ath_softc *sc = hw->priv; | |
1968 | int i = 0; | |
1969 | ||
1970 | data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all + | |
1971 | sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all + | |
1972 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all + | |
1973 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all); | |
1974 | data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all + | |
1975 | sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all + | |
1976 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all + | |
1977 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all); | |
1978 | AWDATA_RX(rx_pkts_all); | |
1979 | AWDATA_RX(rx_bytes_all); | |
1980 | ||
1981 | AWDATA(tx_pkts_all); | |
1982 | AWDATA(tx_bytes_all); | |
1983 | AWDATA(queued); | |
1984 | AWDATA(completed); | |
1985 | AWDATA(xretries); | |
1986 | AWDATA(a_aggr); | |
1987 | AWDATA(a_queued_hw); | |
1988 | AWDATA(a_queued_sw); | |
1989 | AWDATA(a_completed); | |
1990 | AWDATA(a_retries); | |
1991 | AWDATA(a_xretries); | |
1992 | AWDATA(fifo_underrun); | |
1993 | AWDATA(xtxop); | |
1994 | AWDATA(timer_exp); | |
1995 | AWDATA(desc_cfg_err); | |
1996 | AWDATA(data_underrun); | |
1997 | AWDATA(delim_underrun); | |
1998 | ||
1999 | AWDATA_RX(decrypt_crc_err); | |
2000 | AWDATA_RX(phy_err); | |
2001 | AWDATA_RX(mic_err); | |
2002 | AWDATA_RX(pre_delim_crc_err); | |
2003 | AWDATA_RX(post_delim_crc_err); | |
2004 | AWDATA_RX(decrypt_busy_err); | |
2005 | ||
2006 | AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]); | |
2007 | AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]); | |
2008 | AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]); | |
2009 | ||
2010 | WARN_ON(i != ATH9K_SSTATS_LEN); | |
2011 | } | |
2012 | ||
2013 | /* End of ethtool get-stats functions */ | |
2014 | ||
2015 | #endif | |
2016 | ||
2017 | ||
b11e640a MSS |
2018 | #ifdef CONFIG_PM_SLEEP |
2019 | ||
2020 | static void ath9k_wow_map_triggers(struct ath_softc *sc, | |
2021 | struct cfg80211_wowlan *wowlan, | |
2022 | u32 *wow_triggers) | |
2023 | { | |
2024 | if (wowlan->disconnect) | |
2025 | *wow_triggers |= AH_WOW_LINK_CHANGE | | |
2026 | AH_WOW_BEACON_MISS; | |
2027 | if (wowlan->magic_pkt) | |
2028 | *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN; | |
2029 | ||
2030 | if (wowlan->n_patterns) | |
2031 | *wow_triggers |= AH_WOW_USER_PATTERN_EN; | |
2032 | ||
2033 | sc->wow_enabled = *wow_triggers; | |
2034 | ||
2035 | } | |
2036 | ||
2037 | static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc) | |
2038 | { | |
2039 | struct ath_hw *ah = sc->sc_ah; | |
2040 | struct ath_common *common = ath9k_hw_common(ah); | |
2041 | struct ath9k_hw_capabilities *pcaps = &ah->caps; | |
2042 | int pattern_count = 0; | |
2043 | int i, byte_cnt; | |
2044 | u8 dis_deauth_pattern[MAX_PATTERN_SIZE]; | |
2045 | u8 dis_deauth_mask[MAX_PATTERN_SIZE]; | |
2046 | ||
2047 | memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE); | |
2048 | memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE); | |
2049 | ||
2050 | /* | |
2051 | * Create Dissassociate / Deauthenticate packet filter | |
2052 | * | |
2053 | * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes | |
2054 | * +--------------+----------+---------+--------+--------+---- | |
2055 | * + Frame Control+ Duration + DA + SA + BSSID + | |
2056 | * +--------------+----------+---------+--------+--------+---- | |
2057 | * | |
2058 | * The above is the management frame format for disassociate/ | |
2059 | * deauthenticate pattern, from this we need to match the first byte | |
2060 | * of 'Frame Control' and DA, SA, and BSSID fields | |
2061 | * (skipping 2nd byte of FC and Duration feild. | |
2062 | * | |
2063 | * Disassociate pattern | |
2064 | * -------------------- | |
2065 | * Frame control = 00 00 1010 | |
2066 | * DA, SA, BSSID = x:x:x:x:x:x | |
2067 | * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x | |
2068 | * | x:x:x:x:x:x -- 22 bytes | |
2069 | * | |
2070 | * Deauthenticate pattern | |
2071 | * ---------------------- | |
2072 | * Frame control = 00 00 1100 | |
2073 | * DA, SA, BSSID = x:x:x:x:x:x | |
2074 | * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x | |
2075 | * | x:x:x:x:x:x -- 22 bytes | |
2076 | */ | |
2077 | ||
2078 | /* Create Disassociate Pattern first */ | |
2079 | ||
2080 | byte_cnt = 0; | |
2081 | ||
2082 | /* Fill out the mask with all FF's */ | |
2083 | ||
2084 | for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++) | |
2085 | dis_deauth_mask[i] = 0xff; | |
2086 | ||
2087 | /* copy the first byte of frame control field */ | |
2088 | dis_deauth_pattern[byte_cnt] = 0xa0; | |
2089 | byte_cnt++; | |
2090 | ||
2091 | /* skip 2nd byte of frame control and Duration field */ | |
2092 | byte_cnt += 3; | |
2093 | ||
2094 | /* | |
2095 | * need not match the destination mac address, it can be a broadcast | |
2096 | * mac address or an unicast to this station | |
2097 | */ | |
2098 | byte_cnt += 6; | |
2099 | ||
2100 | /* copy the source mac address */ | |
2101 | memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); | |
2102 | ||
2103 | byte_cnt += 6; | |
2104 | ||
2105 | /* copy the bssid, its same as the source mac address */ | |
2106 | ||
2107 | memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); | |
2108 | ||
2109 | /* Create Disassociate pattern mask */ | |
2110 | ||
2111 | if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) { | |
2112 | ||
2113 | if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) { | |
2114 | /* | |
2115 | * for AR9280, because of hardware limitation, the | |
2116 | * first 4 bytes have to be matched for all patterns. | |
2117 | * the mask for disassociation and de-auth pattern | |
2118 | * matching need to enable the first 4 bytes. | |
2119 | * also the duration field needs to be filled. | |
2120 | */ | |
2121 | dis_deauth_mask[0] = 0xf0; | |
2122 | ||
2123 | /* | |
2124 | * fill in duration field | |
2125 | FIXME: what is the exact value ? | |
2126 | */ | |
2127 | dis_deauth_pattern[2] = 0xff; | |
2128 | dis_deauth_pattern[3] = 0xff; | |
2129 | } else { | |
2130 | dis_deauth_mask[0] = 0xfe; | |
2131 | } | |
2132 | ||
2133 | dis_deauth_mask[1] = 0x03; | |
2134 | dis_deauth_mask[2] = 0xc0; | |
2135 | } else { | |
2136 | dis_deauth_mask[0] = 0xef; | |
2137 | dis_deauth_mask[1] = 0x3f; | |
2138 | dis_deauth_mask[2] = 0x00; | |
2139 | dis_deauth_mask[3] = 0xfc; | |
2140 | } | |
2141 | ||
2142 | ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n"); | |
2143 | ||
2144 | ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, | |
2145 | pattern_count, byte_cnt); | |
2146 | ||
2147 | pattern_count++; | |
2148 | /* | |
2149 | * for de-authenticate pattern, only the first byte of the frame | |
2150 | * control field gets changed from 0xA0 to 0xC0 | |
2151 | */ | |
2152 | dis_deauth_pattern[0] = 0xC0; | |
2153 | ||
2154 | ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, | |
2155 | pattern_count, byte_cnt); | |
2156 | ||
2157 | } | |
2158 | ||
2159 | static void ath9k_wow_add_pattern(struct ath_softc *sc, | |
2160 | struct cfg80211_wowlan *wowlan) | |
2161 | { | |
2162 | struct ath_hw *ah = sc->sc_ah; | |
2163 | struct ath9k_wow_pattern *wow_pattern = NULL; | |
2164 | struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns; | |
2165 | int mask_len; | |
2166 | s8 i = 0; | |
2167 | ||
2168 | if (!wowlan->n_patterns) | |
2169 | return; | |
2170 | ||
2171 | /* | |
2172 | * Add the new user configured patterns | |
2173 | */ | |
2174 | for (i = 0; i < wowlan->n_patterns; i++) { | |
2175 | ||
2176 | wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL); | |
2177 | ||
2178 | if (!wow_pattern) | |
2179 | return; | |
2180 | ||
2181 | /* | |
2182 | * TODO: convert the generic user space pattern to | |
2183 | * appropriate chip specific/802.11 pattern. | |
2184 | */ | |
2185 | ||
2186 | mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8); | |
2187 | memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE); | |
2188 | memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE); | |
2189 | memcpy(wow_pattern->pattern_bytes, patterns[i].pattern, | |
2190 | patterns[i].pattern_len); | |
2191 | memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len); | |
2192 | wow_pattern->pattern_len = patterns[i].pattern_len; | |
2193 | ||
2194 | /* | |
2195 | * just need to take care of deauth and disssoc pattern, | |
2196 | * make sure we don't overwrite them. | |
2197 | */ | |
2198 | ||
2199 | ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes, | |
2200 | wow_pattern->mask_bytes, | |
2201 | i + 2, | |
2202 | wow_pattern->pattern_len); | |
2203 | kfree(wow_pattern); | |
2204 | ||
2205 | } | |
2206 | ||
2207 | } | |
2208 | ||
2209 | static int ath9k_suspend(struct ieee80211_hw *hw, | |
2210 | struct cfg80211_wowlan *wowlan) | |
2211 | { | |
2212 | struct ath_softc *sc = hw->priv; | |
2213 | struct ath_hw *ah = sc->sc_ah; | |
2214 | struct ath_common *common = ath9k_hw_common(ah); | |
2215 | u32 wow_triggers_enabled = 0; | |
2216 | int ret = 0; | |
2217 | ||
2218 | mutex_lock(&sc->mutex); | |
2219 | ||
2220 | ath_cancel_work(sc); | |
5686cac5 | 2221 | ath_stop_ani(sc); |
b11e640a MSS |
2222 | del_timer_sync(&sc->rx_poll_timer); |
2223 | ||
2224 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { | |
2225 | ath_dbg(common, ANY, "Device not present\n"); | |
2226 | ret = -EINVAL; | |
2227 | goto fail_wow; | |
2228 | } | |
2229 | ||
2230 | if (WARN_ON(!wowlan)) { | |
2231 | ath_dbg(common, WOW, "None of the WoW triggers enabled\n"); | |
2232 | ret = -EINVAL; | |
2233 | goto fail_wow; | |
2234 | } | |
2235 | ||
2236 | if (!device_can_wakeup(sc->dev)) { | |
2237 | ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n"); | |
2238 | ret = 1; | |
2239 | goto fail_wow; | |
2240 | } | |
2241 | ||
2242 | /* | |
2243 | * none of the sta vifs are associated | |
2244 | * and we are not currently handling multivif | |
2245 | * cases, for instance we have to seperately | |
2246 | * configure 'keep alive frame' for each | |
2247 | * STA. | |
2248 | */ | |
2249 | ||
2250 | if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
2251 | ath_dbg(common, WOW, "None of the STA vifs are associated\n"); | |
2252 | ret = 1; | |
2253 | goto fail_wow; | |
2254 | } | |
2255 | ||
2256 | if (sc->nvifs > 1) { | |
2257 | ath_dbg(common, WOW, "WoW for multivif is not yet supported\n"); | |
2258 | ret = 1; | |
2259 | goto fail_wow; | |
2260 | } | |
2261 | ||
2262 | ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled); | |
2263 | ||
2264 | ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n", | |
2265 | wow_triggers_enabled); | |
2266 | ||
2267 | ath9k_ps_wakeup(sc); | |
2268 | ||
2269 | ath9k_stop_btcoex(sc); | |
2270 | ||
2271 | /* | |
2272 | * Enable wake up on recieving disassoc/deauth | |
2273 | * frame by default. | |
2274 | */ | |
2275 | ath9k_wow_add_disassoc_deauth_pattern(sc); | |
2276 | ||
2277 | if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN) | |
2278 | ath9k_wow_add_pattern(sc, wowlan); | |
2279 | ||
2280 | spin_lock_bh(&sc->sc_pcu_lock); | |
2281 | /* | |
2282 | * To avoid false wake, we enable beacon miss interrupt only | |
2283 | * when we go to sleep. We save the current interrupt mask | |
2284 | * so we can restore it after the system wakes up | |
2285 | */ | |
2286 | sc->wow_intr_before_sleep = ah->imask; | |
2287 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
2288 | ath9k_hw_disable_interrupts(ah); | |
2289 | ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL; | |
2290 | ath9k_hw_set_interrupts(ah); | |
2291 | ath9k_hw_enable_interrupts(ah); | |
2292 | ||
2293 | spin_unlock_bh(&sc->sc_pcu_lock); | |
2294 | ||
2295 | /* | |
2296 | * we can now sync irq and kill any running tasklets, since we already | |
2297 | * disabled interrupts and not holding a spin lock | |
2298 | */ | |
2299 | synchronize_irq(sc->irq); | |
2300 | tasklet_kill(&sc->intr_tq); | |
2301 | ||
2302 | ath9k_hw_wow_enable(ah, wow_triggers_enabled); | |
2303 | ||
2304 | ath9k_ps_restore(sc); | |
2305 | ath_dbg(common, ANY, "WoW enabled in ath9k\n"); | |
2306 | atomic_inc(&sc->wow_sleep_proc_intr); | |
2307 | ||
2308 | fail_wow: | |
2309 | mutex_unlock(&sc->mutex); | |
2310 | return ret; | |
2311 | } | |
2312 | ||
2313 | static int ath9k_resume(struct ieee80211_hw *hw) | |
2314 | { | |
2315 | struct ath_softc *sc = hw->priv; | |
2316 | struct ath_hw *ah = sc->sc_ah; | |
2317 | struct ath_common *common = ath9k_hw_common(ah); | |
2318 | u32 wow_status; | |
2319 | ||
2320 | mutex_lock(&sc->mutex); | |
2321 | ||
2322 | ath9k_ps_wakeup(sc); | |
2323 | ||
2324 | spin_lock_bh(&sc->sc_pcu_lock); | |
2325 | ||
2326 | ath9k_hw_disable_interrupts(ah); | |
2327 | ah->imask = sc->wow_intr_before_sleep; | |
2328 | ath9k_hw_set_interrupts(ah); | |
2329 | ath9k_hw_enable_interrupts(ah); | |
2330 | ||
2331 | spin_unlock_bh(&sc->sc_pcu_lock); | |
2332 | ||
2333 | wow_status = ath9k_hw_wow_wakeup(ah); | |
2334 | ||
2335 | if (atomic_read(&sc->wow_got_bmiss_intr) == 0) { | |
2336 | /* | |
2337 | * some devices may not pick beacon miss | |
2338 | * as the reason they woke up so we add | |
2339 | * that here for that shortcoming. | |
2340 | */ | |
2341 | wow_status |= AH_WOW_BEACON_MISS; | |
2342 | atomic_dec(&sc->wow_got_bmiss_intr); | |
2343 | ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n"); | |
2344 | } | |
2345 | ||
2346 | atomic_dec(&sc->wow_sleep_proc_intr); | |
2347 | ||
2348 | if (wow_status) { | |
2349 | ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n", | |
2350 | ath9k_hw_wow_event_to_string(wow_status), wow_status); | |
2351 | } | |
2352 | ||
2353 | ath_restart_work(sc); | |
2354 | ath9k_start_btcoex(sc); | |
2355 | ||
2356 | ath9k_ps_restore(sc); | |
2357 | mutex_unlock(&sc->mutex); | |
2358 | ||
2359 | return 0; | |
2360 | } | |
2361 | ||
2362 | static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) | |
2363 | { | |
2364 | struct ath_softc *sc = hw->priv; | |
2365 | ||
2366 | mutex_lock(&sc->mutex); | |
2367 | device_init_wakeup(sc->dev, 1); | |
2368 | device_set_wakeup_enable(sc->dev, enabled); | |
2369 | mutex_unlock(&sc->mutex); | |
2370 | } | |
2371 | ||
2372 | #endif | |
2373 | ||
6baff7f9 | 2374 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2375 | .tx = ath9k_tx, |
2376 | .start = ath9k_start, | |
2377 | .stop = ath9k_stop, | |
2378 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2379 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2380 | .remove_interface = ath9k_remove_interface, |
2381 | .config = ath9k_config, | |
8feceb67 | 2382 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2383 | .sta_add = ath9k_sta_add, |
2384 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2385 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2386 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2387 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2388 | .set_key = ath9k_set_key, |
8feceb67 | 2389 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2390 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2391 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2392 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2393 | .get_survey = ath9k_get_survey, |
3b319aae | 2394 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2395 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2396 | .flush = ath9k_flush, |
15b91e83 | 2397 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 MSS |
2398 | .tx_last_beacon = ath9k_tx_last_beacon, |
2399 | .get_stats = ath9k_get_stats, | |
43c35284 FF |
2400 | .set_antenna = ath9k_set_antenna, |
2401 | .get_antenna = ath9k_get_antenna, | |
b90bd9d1 | 2402 | |
b11e640a MSS |
2403 | #ifdef CONFIG_PM_SLEEP |
2404 | .suspend = ath9k_suspend, | |
2405 | .resume = ath9k_resume, | |
2406 | .set_wakeup = ath9k_set_wakeup, | |
2407 | #endif | |
2408 | ||
b90bd9d1 BG |
2409 | #ifdef CONFIG_ATH9K_DEBUGFS |
2410 | .get_et_sset_count = ath9k_get_et_sset_count, | |
2411 | .get_et_stats = ath9k_get_et_stats, | |
2412 | .get_et_strings = ath9k_get_et_strings, | |
2413 | #endif | |
8feceb67 | 2414 | }; |