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Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
313eb87f | 22 | u8 ath9k_parse_mpdudensity(u8 mpdudensity) |
ff37e337 S |
23 | { |
24 | /* | |
25 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
26 | * 0 for no restriction | |
27 | * 1 for 1/4 us | |
28 | * 2 for 1/2 us | |
29 | * 3 for 1 us | |
30 | * 4 for 2 us | |
31 | * 5 for 4 us | |
32 | * 6 for 8 us | |
33 | * 7 for 16 us | |
34 | */ | |
35 | switch (mpdudensity) { | |
36 | case 0: | |
37 | return 0; | |
38 | case 1: | |
39 | case 2: | |
40 | case 3: | |
41 | /* Our lower layer calculations limit our precision to | |
42 | 1 microsecond */ | |
43 | return 1; | |
44 | case 4: | |
45 | return 2; | |
46 | case 5: | |
47 | return 4; | |
48 | case 6: | |
49 | return 8; | |
50 | case 7: | |
51 | return 16; | |
52 | default: | |
53 | return 0; | |
54 | } | |
55 | } | |
56 | ||
69081624 VT |
57 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
58 | { | |
59 | bool pending = false; | |
60 | ||
61 | spin_lock_bh(&txq->axq_lock); | |
62 | ||
b7367285 | 63 | if (txq->axq_depth) { |
69081624 | 64 | pending = true; |
b7367285 SM |
65 | goto out; |
66 | } | |
69081624 | 67 | |
0453531e FF |
68 | if (txq->mac80211_qnum >= 0) { |
69 | struct list_head *list; | |
70 | ||
71 | list = &sc->cur_chan->acq[txq->mac80211_qnum]; | |
72 | if (!list_empty(list)) | |
73 | pending = true; | |
74 | } | |
b7367285 | 75 | out: |
69081624 VT |
76 | spin_unlock_bh(&txq->axq_lock); |
77 | return pending; | |
78 | } | |
79 | ||
6d79cb4c | 80 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
81 | { |
82 | unsigned long flags; | |
83 | bool ret; | |
84 | ||
9ecdef4b LR |
85 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
86 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
87 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
88 | |
89 | return ret; | |
90 | } | |
91 | ||
bf3dac5a FF |
92 | void ath_ps_full_sleep(unsigned long data) |
93 | { | |
94 | struct ath_softc *sc = (struct ath_softc *) data; | |
95 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
96 | bool reset; | |
97 | ||
98 | spin_lock(&common->cc_lock); | |
99 | ath_hw_cycle_counters_update(common); | |
100 | spin_unlock(&common->cc_lock); | |
101 | ||
102 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
103 | ath9k_hw_stopdmarecv(sc->sc_ah, &reset); | |
104 | ||
105 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
106 | } | |
107 | ||
a91d75ae LR |
108 | void ath9k_ps_wakeup(struct ath_softc *sc) |
109 | { | |
898c914a | 110 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 111 | unsigned long flags; |
fbb078fc | 112 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
113 | |
114 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
115 | if (++sc->ps_usecount != 1) | |
116 | goto unlock; | |
117 | ||
bf3dac5a | 118 | del_timer_sync(&sc->sleep_timer); |
fbb078fc | 119 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 120 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 121 | |
898c914a FF |
122 | /* |
123 | * While the hardware is asleep, the cycle counters contain no | |
124 | * useful data. Better clear them now so that they don't mess up | |
125 | * survey data results. | |
126 | */ | |
fbb078fc FF |
127 | if (power_mode != ATH9K_PM_AWAKE) { |
128 | spin_lock(&common->cc_lock); | |
129 | ath_hw_cycle_counters_update(common); | |
130 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
c9ae6ab4 | 131 | memset(&common->cc_ani, 0, sizeof(common->cc_ani)); |
fbb078fc FF |
132 | spin_unlock(&common->cc_lock); |
133 | } | |
898c914a | 134 | |
a91d75ae LR |
135 | unlock: |
136 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
137 | } | |
138 | ||
139 | void ath9k_ps_restore(struct ath_softc *sc) | |
140 | { | |
898c914a | 141 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c6c539f0 | 142 | enum ath9k_power_mode mode; |
a91d75ae LR |
143 | unsigned long flags; |
144 | ||
145 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
146 | if (--sc->ps_usecount != 0) | |
147 | goto unlock; | |
148 | ||
ad128860 | 149 | if (sc->ps_idle) { |
bf3dac5a FF |
150 | mod_timer(&sc->sleep_timer, jiffies + HZ / 10); |
151 | goto unlock; | |
152 | } | |
153 | ||
154 | if (sc->ps_enabled && | |
ad128860 SM |
155 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | |
156 | PS_WAIT_FOR_CAB | | |
157 | PS_WAIT_FOR_PSPOLL_DATA | | |
424749c7 RM |
158 | PS_WAIT_FOR_TX_ACK | |
159 | PS_WAIT_FOR_ANI))) { | |
c6c539f0 | 160 | mode = ATH9K_PM_NETWORK_SLEEP; |
08d4df41 RM |
161 | if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) |
162 | ath9k_btcoex_stop_gen_timer(sc); | |
ad128860 | 163 | } else { |
c6c539f0 | 164 | goto unlock; |
ad128860 | 165 | } |
c6c539f0 FF |
166 | |
167 | spin_lock(&common->cc_lock); | |
168 | ath_hw_cycle_counters_update(common); | |
169 | spin_unlock(&common->cc_lock); | |
170 | ||
1a8f0d39 | 171 | ath9k_hw_setpower(sc->sc_ah, mode); |
a91d75ae LR |
172 | |
173 | unlock: | |
174 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
175 | } | |
176 | ||
9adcf440 | 177 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 178 | { |
5ee08656 | 179 | cancel_work_sync(&sc->paprd_work); |
5ee08656 | 180 | cancel_delayed_work_sync(&sc->tx_complete_work); |
181fb18d | 181 | cancel_delayed_work_sync(&sc->hw_pll_work); |
fad29cd2 | 182 | |
bf52592f | 183 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
fad29cd2 SM |
184 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
185 | cancel_work_sync(&sc->mci_work); | |
bf52592f | 186 | #endif |
9adcf440 | 187 | } |
5ee08656 | 188 | |
e60001e7 | 189 | void ath_cancel_work(struct ath_softc *sc) |
9adcf440 FF |
190 | { |
191 | __ath_cancel_work(sc); | |
192 | cancel_work_sync(&sc->hw_reset_work); | |
193 | } | |
3cbb5dd7 | 194 | |
e60001e7 | 195 | void ath_restart_work(struct ath_softc *sc) |
af68abad | 196 | { |
af68abad SM |
197 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
198 | ||
19c36160 | 199 | if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) |
af68abad SM |
200 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, |
201 | msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); | |
202 | ||
da0d45f7 | 203 | ath_start_ani(sc); |
af68abad SM |
204 | } |
205 | ||
9ebea382 | 206 | static bool ath_prepare_reset(struct ath_softc *sc) |
9adcf440 FF |
207 | { |
208 | struct ath_hw *ah = sc->sc_ah; | |
ceea2a51 | 209 | bool ret = true; |
6a6733f2 | 210 | |
9adcf440 | 211 | ieee80211_stop_queues(sc->hw); |
da0d45f7 | 212 | ath_stop_ani(sc); |
9adcf440 | 213 | ath9k_hw_disable_interrupts(ah); |
8b3f4616 | 214 | |
1381559b | 215 | if (!ath_drain_all_txq(sc)) |
9adcf440 | 216 | ret = false; |
c0d7c7af | 217 | |
0a62acb1 | 218 | if (!ath_stoprecv(sc)) |
ceea2a51 FF |
219 | ret = false; |
220 | ||
9adcf440 FF |
221 | return ret; |
222 | } | |
ff37e337 | 223 | |
9adcf440 FF |
224 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
225 | { | |
226 | struct ath_hw *ah = sc->sc_ah; | |
227 | struct ath_common *common = ath9k_hw_common(ah); | |
196fb860 | 228 | unsigned long flags; |
c0d7c7af | 229 | |
9019f646 | 230 | ath9k_calculate_summary_state(sc, sc->cur_chan); |
19ec477f | 231 | ath_startrecv(sc); |
5048e8c3 | 232 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
bc7e1be7 | 233 | sc->cur_chan->txpower, &sc->curtxpow); |
eefa01dd | 234 | clear_bit(ATH_OP_HW_RESET, &common->op_flags); |
3989279c | 235 | |
fbbcd146 | 236 | if (!sc->cur_chan->offchannel && start) { |
8d7e09dd FF |
237 | /* restore per chanctx TSF timer */ |
238 | if (sc->cur_chan->tsf_val) { | |
239 | u32 offset; | |
240 | ||
241 | offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, | |
242 | NULL); | |
243 | ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset); | |
244 | } | |
245 | ||
246 | ||
eefa01dd | 247 | if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) |
196fb860 SM |
248 | goto work; |
249 | ||
196fb860 | 250 | if (ah->opmode == NL80211_IFTYPE_STATION && |
eefa01dd | 251 | test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { |
196fb860 SM |
252 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
253 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
254 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
a6768280 SM |
255 | } else { |
256 | ath9k_set_beacon(sc); | |
196fb860 SM |
257 | } |
258 | work: | |
af68abad | 259 | ath_restart_work(sc); |
0453531e | 260 | ath_txq_schedule_all(sc); |
5ee08656 FF |
261 | } |
262 | ||
071aa9a8 | 263 | sc->gtt_cnt = 0; |
9a9c4fbc RM |
264 | |
265 | ath9k_hw_set_interrupts(ah); | |
266 | ath9k_hw_enable_interrupts(ah); | |
5ba8d9d2 | 267 | ieee80211_wake_queues(sc->hw); |
d463af4a FF |
268 | ath9k_p2p_ps_timer(sc); |
269 | ||
9adcf440 FF |
270 | return true; |
271 | } | |
272 | ||
fbbcd146 | 273 | int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) |
9adcf440 FF |
274 | { |
275 | struct ath_hw *ah = sc->sc_ah; | |
276 | struct ath_common *common = ath9k_hw_common(ah); | |
277 | struct ath9k_hw_cal_data *caldata = NULL; | |
278 | bool fastcc = true; | |
9adcf440 FF |
279 | int r; |
280 | ||
281 | __ath_cancel_work(sc); | |
282 | ||
4668cce5 | 283 | tasklet_disable(&sc->intr_tq); |
9adcf440 | 284 | spin_lock_bh(&sc->sc_pcu_lock); |
92460412 | 285 | |
fbbcd146 | 286 | if (!sc->cur_chan->offchannel) { |
9adcf440 | 287 | fastcc = false; |
b01459e8 | 288 | caldata = &sc->cur_chan->caldata; |
9adcf440 FF |
289 | } |
290 | ||
291 | if (!hchan) { | |
292 | fastcc = false; | |
9adcf440 FF |
293 | hchan = ah->curchan; |
294 | } | |
295 | ||
9ebea382 | 296 | if (!ath_prepare_reset(sc)) |
9adcf440 FF |
297 | fastcc = false; |
298 | ||
9ea3598b SM |
299 | if (ath9k_is_chanctx_enabled()) |
300 | fastcc = false; | |
301 | ||
d6067f0e RM |
302 | spin_lock_bh(&sc->chan_lock); |
303 | sc->cur_chandef = sc->cur_chan->chandef; | |
304 | spin_unlock_bh(&sc->chan_lock); | |
bff11766 | 305 | |
d2182b69 | 306 | ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", |
feced201 | 307 | hchan->channel, IS_CHAN_HT40(hchan), fastcc); |
9adcf440 FF |
308 | |
309 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
310 | if (r) { | |
311 | ath_err(common, | |
312 | "Unable to reset channel, reset status %d\n", r); | |
f50b1cd3 RS |
313 | |
314 | ath9k_hw_enable_interrupts(ah); | |
315 | ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); | |
316 | ||
9adcf440 FF |
317 | goto out; |
318 | } | |
319 | ||
e82cb03f | 320 | if (ath9k_hw_mci_is_enabled(sc->sc_ah) && |
fbbcd146 | 321 | sc->cur_chan->offchannel) |
e82cb03f RM |
322 | ath9k_mci_set_txpower(sc, true, false); |
323 | ||
9adcf440 FF |
324 | if (!ath_complete_reset(sc, true)) |
325 | r = -EIO; | |
326 | ||
327 | out: | |
6a6733f2 | 328 | spin_unlock_bh(&sc->sc_pcu_lock); |
4668cce5 FF |
329 | tasklet_enable(&sc->intr_tq); |
330 | ||
9adcf440 FF |
331 | return r; |
332 | } | |
333 | ||
7e1e3864 BG |
334 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, |
335 | struct ieee80211_vif *vif) | |
ff37e337 S |
336 | { |
337 | struct ath_node *an; | |
ff37e337 S |
338 | an = (struct ath_node *)sta->drv_priv; |
339 | ||
a145daf7 | 340 | an->sc = sc; |
7f010c93 | 341 | an->sta = sta; |
7e1e3864 | 342 | an->vif = vif; |
4bbf4414 | 343 | memset(&an->key_idx, 0, sizeof(an->key_idx)); |
3d4e20f2 | 344 | |
dd5ee59b | 345 | ath_tx_node_init(sc, an); |
44b47a7d LB |
346 | |
347 | ath_dynack_node_init(sc->sc_ah, an); | |
ff37e337 S |
348 | } |
349 | ||
350 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
351 | { | |
352 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
dd5ee59b | 353 | ath_tx_node_cleanup(sc, an); |
44b47a7d LB |
354 | |
355 | ath_dynack_node_deinit(sc->sc_ah, an); | |
ff37e337 S |
356 | } |
357 | ||
55624204 | 358 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
359 | { |
360 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 361 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 362 | struct ath_common *common = ath9k_hw_common(ah); |
124b979b | 363 | enum ath_reset_type type; |
07c15a3f | 364 | unsigned long flags; |
17d7904d | 365 | u32 status = sc->intrstatus; |
b5c80475 | 366 | u32 rxmask; |
ff37e337 | 367 | |
e3927007 FF |
368 | ath9k_ps_wakeup(sc); |
369 | spin_lock(&sc->sc_pcu_lock); | |
370 | ||
6549a860 SM |
371 | if (status & ATH9K_INT_FATAL) { |
372 | type = RESET_TYPE_FATAL_INT; | |
124b979b | 373 | ath9k_queue_reset(sc, type); |
c6cc47b1 SM |
374 | |
375 | /* | |
376 | * Increment the ref. counter here so that | |
377 | * interrupts are enabled in the reset routine. | |
378 | */ | |
379 | atomic_inc(&ah->intr_ref_cnt); | |
affad456 | 380 | ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); |
e3927007 | 381 | goto out; |
063d8be3 | 382 | } |
ff37e337 | 383 | |
6549a860 SM |
384 | if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && |
385 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
0c759977 SM |
386 | spin_lock(&common->cc_lock); |
387 | ath_hw_cycle_counters_update(common); | |
388 | ar9003_hw_bb_watchdog_dbg_info(ah); | |
389 | spin_unlock(&common->cc_lock); | |
390 | ||
6549a860 SM |
391 | if (ar9003_hw_bb_watchdog_check(ah)) { |
392 | type = RESET_TYPE_BB_WATCHDOG; | |
393 | ath9k_queue_reset(sc, type); | |
394 | ||
395 | /* | |
396 | * Increment the ref. counter here so that | |
397 | * interrupts are enabled in the reset routine. | |
398 | */ | |
399 | atomic_inc(&ah->intr_ref_cnt); | |
affad456 | 400 | ath_dbg(common, RESET, |
6549a860 SM |
401 | "BB_WATCHDOG: Skipping interrupts\n"); |
402 | goto out; | |
403 | } | |
404 | } | |
405 | ||
071aa9a8 SM |
406 | if (status & ATH9K_INT_GTT) { |
407 | sc->gtt_cnt++; | |
408 | ||
409 | if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { | |
410 | type = RESET_TYPE_TX_GTT; | |
411 | ath9k_queue_reset(sc, type); | |
412 | atomic_inc(&ah->intr_ref_cnt); | |
affad456 | 413 | ath_dbg(common, RESET, |
071aa9a8 SM |
414 | "GTT: Skipping interrupts\n"); |
415 | goto out; | |
416 | } | |
417 | } | |
418 | ||
07c15a3f | 419 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
4105f807 RM |
420 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
421 | /* | |
422 | * TSF sync does not look correct; remain awake to sync with | |
423 | * the next Beacon. | |
424 | */ | |
d2182b69 | 425 | ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); |
e8fe7336 | 426 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 | 427 | } |
07c15a3f | 428 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
4105f807 | 429 | |
b5c80475 FF |
430 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
431 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
432 | ATH9K_INT_RXORN); | |
433 | else | |
434 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
435 | ||
436 | if (status & rxmask) { | |
b5c80475 FF |
437 | /* Check for high priority Rx first */ |
438 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
439 | (status & ATH9K_INT_RXHP)) | |
440 | ath_rx_tasklet(sc, 0, true); | |
441 | ||
442 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
443 | } |
444 | ||
e5003249 | 445 | if (status & ATH9K_INT_TX) { |
071aa9a8 SM |
446 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
447 | /* | |
448 | * For EDMA chips, TX completion is enabled for the | |
449 | * beacon queue, so if a beacon has been transmitted | |
450 | * successfully after a GTT interrupt, the GTT counter | |
451 | * gets reset to zero here. | |
452 | */ | |
3b745c7b | 453 | sc->gtt_cnt = 0; |
071aa9a8 | 454 | |
e5003249 | 455 | ath_tx_edma_tasklet(sc); |
071aa9a8 | 456 | } else { |
e5003249 | 457 | ath_tx_tasklet(sc); |
071aa9a8 | 458 | } |
10e23181 FF |
459 | |
460 | wake_up(&sc->tx_wait); | |
e5003249 | 461 | } |
063d8be3 | 462 | |
c67ce339 FF |
463 | if (status & ATH9K_INT_GENTIMER) |
464 | ath_gen_timer_isr(sc->sc_ah); | |
465 | ||
56ca0dba | 466 | ath9k_btcoex_handle_interrupt(sc, status); |
19686ddf | 467 | |
ff37e337 | 468 | /* re-enable hardware interrupt */ |
4df3071e | 469 | ath9k_hw_enable_interrupts(ah); |
c6cc47b1 | 470 | out: |
52671e43 | 471 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 472 | ath9k_ps_restore(sc); |
ff37e337 S |
473 | } |
474 | ||
6baff7f9 | 475 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 476 | { |
063d8be3 S |
477 | #define SCHED_INTR ( \ |
478 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 479 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
480 | ATH9K_INT_RXORN | \ |
481 | ATH9K_INT_RXEOL | \ | |
482 | ATH9K_INT_RX | \ | |
b5c80475 FF |
483 | ATH9K_INT_RXLP | \ |
484 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
485 | ATH9K_INT_TX | \ |
486 | ATH9K_INT_BMISS | \ | |
487 | ATH9K_INT_CST | \ | |
071aa9a8 | 488 | ATH9K_INT_GTT | \ |
ebb8e1d7 | 489 | ATH9K_INT_TSFOOR | \ |
40dc5392 MSS |
490 | ATH9K_INT_GENTIMER | \ |
491 | ATH9K_INT_MCI) | |
063d8be3 | 492 | |
ff37e337 | 493 | struct ath_softc *sc = dev; |
cbe61d8a | 494 | struct ath_hw *ah = sc->sc_ah; |
eefa01dd | 495 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 | 496 | enum ath9k_int status; |
78c8a950 | 497 | u32 sync_cause = 0; |
ff37e337 S |
498 | bool sched = false; |
499 | ||
063d8be3 S |
500 | /* |
501 | * The hardware is not ready/present, don't | |
502 | * touch anything. Note this can happen early | |
503 | * on if the IRQ is shared. | |
504 | */ | |
2ba7d144 | 505 | if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags)) |
063d8be3 | 506 | return IRQ_NONE; |
ff37e337 | 507 | |
063d8be3 S |
508 | /* shared irq, not for us */ |
509 | ||
153e080d | 510 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 511 | return IRQ_NONE; |
063d8be3 | 512 | |
eefa01dd | 513 | if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) { |
f41a9b3b | 514 | ath9k_hw_kill_interrupts(ah); |
b74713d0 | 515 | return IRQ_HANDLED; |
f41a9b3b | 516 | } |
b74713d0 | 517 | |
063d8be3 S |
518 | /* |
519 | * Figure out the reason(s) for the interrupt. Note | |
520 | * that the hal returns a pseudo-ISR that may include | |
521 | * bits we haven't explicitly enabled so we mask the | |
522 | * value to insure we only process bits we requested. | |
523 | */ | |
6a4d05dc FF |
524 | ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ |
525 | ath9k_debug_sync_cause(sc, sync_cause); | |
3069168c | 526 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 527 | |
063d8be3 S |
528 | /* |
529 | * If there are no status bits set, then this interrupt was not | |
530 | * for me (should have been caught above). | |
531 | */ | |
153e080d | 532 | if (!status) |
063d8be3 | 533 | return IRQ_NONE; |
ff37e337 | 534 | |
063d8be3 S |
535 | /* Cache the status */ |
536 | sc->intrstatus = status; | |
537 | ||
538 | if (status & SCHED_INTR) | |
539 | sched = true; | |
540 | ||
541 | /* | |
542 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
543 | * chip immediately. | |
544 | */ | |
b5c80475 FF |
545 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
546 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
547 | goto chip_reset; |
548 | ||
a6bb860b | 549 | if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && |
0c759977 | 550 | (status & ATH9K_INT_BB_WATCHDOG)) |
08578b8f | 551 | goto chip_reset; |
e60001e7 SM |
552 | |
553 | #ifdef CONFIG_ATH9K_WOW | |
ca90ef44 RM |
554 | if (status & ATH9K_INT_BMISS) { |
555 | if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { | |
ca90ef44 RM |
556 | atomic_inc(&sc->wow_got_bmiss_intr); |
557 | atomic_dec(&sc->wow_sleep_proc_intr); | |
558 | } | |
559 | } | |
560 | #endif | |
e60001e7 | 561 | |
063d8be3 S |
562 | if (status & ATH9K_INT_SWBA) |
563 | tasklet_schedule(&sc->bcon_tasklet); | |
564 | ||
565 | if (status & ATH9K_INT_TXURN) | |
566 | ath9k_hw_updatetxtriglevel(ah, true); | |
567 | ||
0682c9b5 RM |
568 | if (status & ATH9K_INT_RXEOL) { |
569 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 570 | ath9k_hw_set_interrupts(ah); |
b5c80475 FF |
571 | } |
572 | ||
153e080d VT |
573 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
574 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
575 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
576 | goto chip_reset; | |
063d8be3 S |
577 | /* Clear RxAbort bit so that we can |
578 | * receive frames */ | |
9ecdef4b | 579 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
07c15a3f | 580 | spin_lock(&sc->sc_pm_lock); |
153e080d | 581 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 582 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
07c15a3f | 583 | spin_unlock(&sc->sc_pm_lock); |
ff37e337 | 584 | } |
063d8be3 S |
585 | |
586 | chip_reset: | |
ff37e337 | 587 | |
817e11de S |
588 | ath_debug_stat_interrupt(sc, status); |
589 | ||
ff37e337 | 590 | if (sched) { |
4df3071e FF |
591 | /* turn off every interrupt */ |
592 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
593 | tasklet_schedule(&sc->intr_tq); |
594 | } | |
595 | ||
596 | return IRQ_HANDLED; | |
063d8be3 S |
597 | |
598 | #undef SCHED_INTR | |
ff37e337 S |
599 | } |
600 | ||
ef6b19e4 | 601 | int ath_reset(struct ath_softc *sc) |
ff37e337 | 602 | { |
ec30326e | 603 | int r; |
ff37e337 | 604 | |
783cd01e | 605 | ath9k_ps_wakeup(sc); |
1381559b | 606 | r = ath_reset_internal(sc, NULL); |
783cd01e | 607 | ath9k_ps_restore(sc); |
2ab81d4a | 608 | |
ae8d2858 | 609 | return r; |
ff37e337 S |
610 | } |
611 | ||
124b979b RM |
612 | void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) |
613 | { | |
eefa01dd | 614 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
124b979b RM |
615 | #ifdef CONFIG_ATH9K_DEBUGFS |
616 | RESET_STAT_INC(sc, type); | |
617 | #endif | |
eefa01dd | 618 | set_bit(ATH_OP_HW_RESET, &common->op_flags); |
124b979b RM |
619 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
620 | } | |
621 | ||
236de514 FF |
622 | void ath_reset_work(struct work_struct *work) |
623 | { | |
624 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
625 | ||
1381559b | 626 | ath_reset(sc); |
236de514 FF |
627 | } |
628 | ||
ff37e337 S |
629 | /**********************/ |
630 | /* mac80211 callbacks */ | |
631 | /**********************/ | |
632 | ||
8feceb67 | 633 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 634 | { |
9ac58615 | 635 | struct ath_softc *sc = hw->priv; |
af03abec | 636 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 637 | struct ath_common *common = ath9k_hw_common(ah); |
39305635 | 638 | struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; |
fbbcd146 | 639 | struct ath_chanctx *ctx = sc->cur_chan; |
ff37e337 | 640 | struct ath9k_channel *init_channel; |
82880a7c | 641 | int r; |
f078f209 | 642 | |
d2182b69 | 643 | ath_dbg(common, CONFIG, |
226afe68 JP |
644 | "Starting driver with initial channel: %d MHz\n", |
645 | curchan->center_freq); | |
f078f209 | 646 | |
f62d816f | 647 | ath9k_ps_wakeup(sc); |
141b38b6 S |
648 | mutex_lock(&sc->mutex); |
649 | ||
fbbcd146 | 650 | init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef); |
bff11766 | 651 | sc->cur_chandef = hw->conf.chandef; |
ff37e337 S |
652 | |
653 | /* Reset SERDES registers */ | |
84c87dc8 | 654 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
655 | |
656 | /* | |
657 | * The basic interface to setting the hardware in a good | |
658 | * state is ``reset''. On return the hardware is known to | |
659 | * be powered up and with interrupts disabled. This must | |
660 | * be followed by initialization of the appropriate bits | |
661 | * and then setup of the interrupt mask. | |
662 | */ | |
4bdd1e97 | 663 | spin_lock_bh(&sc->sc_pcu_lock); |
c0c11741 FF |
664 | |
665 | atomic_set(&ah->intr_ref_cnt, -1); | |
666 | ||
20bd2a09 | 667 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 668 | if (r) { |
3800276a JP |
669 | ath_err(common, |
670 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
671 | r, curchan->center_freq); | |
ceb26a60 | 672 | ah->reset_power_on = false; |
ff37e337 | 673 | } |
ff37e337 | 674 | |
ff37e337 | 675 | /* Setup our intr mask. */ |
b5c80475 FF |
676 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
677 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
678 | ATH9K_INT_GLOBAL; | |
679 | ||
680 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f | 681 | ah->imask |= ATH9K_INT_RXHP | |
a6bb860b | 682 | ATH9K_INT_RXLP; |
b5c80475 FF |
683 | else |
684 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 685 | |
a6bb860b SM |
686 | if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) |
687 | ah->imask |= ATH9K_INT_BB_WATCHDOG; | |
688 | ||
071aa9a8 SM |
689 | /* |
690 | * Enable GTT interrupts only for AR9003/AR9004 chips | |
691 | * for now. | |
692 | */ | |
693 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
694 | ah->imask |= ATH9K_INT_GTT; | |
ff37e337 | 695 | |
af03abec | 696 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 697 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 698 | |
e270e776 | 699 | ath_mci_enable(sc); |
40dc5392 | 700 | |
eefa01dd | 701 | clear_bit(ATH_OP_INVALID, &common->op_flags); |
5f841b41 | 702 | sc->sc_ah->is_monitoring = false; |
ff37e337 | 703 | |
ceb26a60 FF |
704 | if (!ath_complete_reset(sc, false)) |
705 | ah->reset_power_on = false; | |
ff37e337 | 706 | |
c0c11741 FF |
707 | if (ah->led_pin >= 0) { |
708 | ath9k_hw_cfg_output(ah, ah->led_pin, | |
709 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
710 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); | |
711 | } | |
712 | ||
713 | /* | |
714 | * Reset key cache to sane defaults (all entries cleared) instead of | |
715 | * semi-random values after suspend/resume. | |
716 | */ | |
717 | ath9k_cmn_init_crypto(sc->sc_ah); | |
718 | ||
a35051ce FF |
719 | ath9k_hw_reset_tsf(ah); |
720 | ||
9adcf440 | 721 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 722 | |
141b38b6 S |
723 | mutex_unlock(&sc->mutex); |
724 | ||
f62d816f FF |
725 | ath9k_ps_restore(sc); |
726 | ||
ceb26a60 | 727 | return 0; |
f078f209 LR |
728 | } |
729 | ||
36323f81 TH |
730 | static void ath9k_tx(struct ieee80211_hw *hw, |
731 | struct ieee80211_tx_control *control, | |
732 | struct sk_buff *skb) | |
f078f209 | 733 | { |
9ac58615 | 734 | struct ath_softc *sc = hw->priv; |
c46917bb | 735 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 736 | struct ath_tx_control txctl; |
1bc14880 | 737 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
07c15a3f | 738 | unsigned long flags; |
528f0c6b | 739 | |
96148326 | 740 | if (sc->ps_enabled) { |
dc8c4585 JM |
741 | /* |
742 | * mac80211 does not set PM field for normal data frames, so we | |
743 | * need to update that based on the current PS mode. | |
744 | */ | |
745 | if (ieee80211_is_data(hdr->frame_control) && | |
746 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
747 | !ieee80211_has_pm(hdr->frame_control)) { | |
d2182b69 | 748 | ath_dbg(common, PS, |
226afe68 | 749 | "Add PM=1 for a TX frame while in PS mode\n"); |
dc8c4585 JM |
750 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
751 | } | |
752 | } | |
753 | ||
ad128860 | 754 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { |
9a23f9ca JM |
755 | /* |
756 | * We are using PS-Poll and mac80211 can request TX while in | |
757 | * power save mode. Need to wake up hardware for the TX to be | |
758 | * completed and if needed, also for RX of buffered frames. | |
759 | */ | |
9a23f9ca | 760 | ath9k_ps_wakeup(sc); |
07c15a3f | 761 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
fdf76622 VT |
762 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
763 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 764 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
d2182b69 | 765 | ath_dbg(common, PS, |
226afe68 | 766 | "Sending PS-Poll to pick a buffered frame\n"); |
1b04b930 | 767 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 768 | } else { |
d2182b69 | 769 | ath_dbg(common, PS, "Wake up to complete TX\n"); |
1b04b930 | 770 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
771 | } |
772 | /* | |
773 | * The actual restore operation will happen only after | |
ad128860 | 774 | * the ps_flags bit is cleared. We are just dropping |
9a23f9ca JM |
775 | * the ps_usecount here. |
776 | */ | |
07c15a3f | 777 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
9a23f9ca JM |
778 | ath9k_ps_restore(sc); |
779 | } | |
780 | ||
ad128860 SM |
781 | /* |
782 | * Cannot tx while the hardware is in full sleep, it first needs a full | |
783 | * chip reset to recover from that | |
784 | */ | |
785 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { | |
786 | ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); | |
787 | goto exit; | |
788 | } | |
789 | ||
528f0c6b | 790 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 791 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
36323f81 | 792 | txctl.sta = control->sta; |
528f0c6b | 793 | |
d2182b69 | 794 | ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 795 | |
c52f33d0 | 796 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
d2182b69 | 797 | ath_dbg(common, XMIT, "TX failed\n"); |
a5a0bca1 | 798 | TX_STAT_INC(txctl.txq->axq_qnum, txfailed); |
528f0c6b | 799 | goto exit; |
8feceb67 VT |
800 | } |
801 | ||
7bb45683 | 802 | return; |
528f0c6b | 803 | exit: |
249ee722 | 804 | ieee80211_free_txskb(hw, skb); |
f078f209 LR |
805 | } |
806 | ||
8feceb67 | 807 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 808 | { |
9ac58615 | 809 | struct ath_softc *sc = hw->priv; |
af03abec | 810 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 811 | struct ath_common *common = ath9k_hw_common(ah); |
c0c11741 | 812 | bool prev_idle; |
f078f209 | 813 | |
ea22df29 SM |
814 | ath9k_deinit_channel_context(sc); |
815 | ||
4c483817 S |
816 | mutex_lock(&sc->mutex); |
817 | ||
9adcf440 | 818 | ath_cancel_work(sc); |
c94dbff7 | 819 | |
eefa01dd | 820 | if (test_bit(ATH_OP_INVALID, &common->op_flags)) { |
d2182b69 | 821 | ath_dbg(common, ANY, "Device not present\n"); |
4c483817 | 822 | mutex_unlock(&sc->mutex); |
9c84b797 S |
823 | return; |
824 | } | |
8feceb67 | 825 | |
3867cf6a S |
826 | /* Ensure HW is awake when we try to shut it down. */ |
827 | ath9k_ps_wakeup(sc); | |
828 | ||
6a6733f2 LR |
829 | spin_lock_bh(&sc->sc_pcu_lock); |
830 | ||
203043f5 SG |
831 | /* prevent tasklets to enable interrupts once we disable them */ |
832 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
833 | ||
ff37e337 S |
834 | /* make sure h/w will not generate any interrupt |
835 | * before setting the invalid flag. */ | |
4df3071e | 836 | ath9k_hw_disable_interrupts(ah); |
ff37e337 | 837 | |
c0c11741 FF |
838 | spin_unlock_bh(&sc->sc_pcu_lock); |
839 | ||
840 | /* we can now sync irq and kill any running tasklets, since we already | |
841 | * disabled interrupts and not holding a spin lock */ | |
842 | synchronize_irq(sc->irq); | |
843 | tasklet_kill(&sc->intr_tq); | |
844 | tasklet_kill(&sc->bcon_tasklet); | |
845 | ||
846 | prev_idle = sc->ps_idle; | |
847 | sc->ps_idle = true; | |
848 | ||
849 | spin_lock_bh(&sc->sc_pcu_lock); | |
850 | ||
851 | if (ah->led_pin >= 0) { | |
852 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
853 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
854 | } | |
855 | ||
9ebea382 | 856 | ath_prepare_reset(sc); |
ff37e337 | 857 | |
0d95521e FF |
858 | if (sc->rx.frag) { |
859 | dev_kfree_skb_any(sc->rx.frag); | |
860 | sc->rx.frag = NULL; | |
861 | } | |
862 | ||
c0c11741 | 863 | if (!ah->curchan) |
fbbcd146 FF |
864 | ah->curchan = ath9k_cmn_get_channel(hw, ah, |
865 | &sc->cur_chan->chandef); | |
6a6733f2 | 866 | |
c0c11741 FF |
867 | ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
868 | ath9k_hw_phy_disable(ah); | |
6a6733f2 | 869 | |
c0c11741 | 870 | ath9k_hw_configpcipowersave(ah, true); |
203043f5 | 871 | |
c0c11741 | 872 | spin_unlock_bh(&sc->sc_pcu_lock); |
3867cf6a | 873 | |
c0c11741 | 874 | ath9k_ps_restore(sc); |
ff37e337 | 875 | |
eefa01dd | 876 | set_bit(ATH_OP_INVALID, &common->op_flags); |
c0c11741 | 877 | sc->ps_idle = prev_idle; |
500c064d | 878 | |
141b38b6 S |
879 | mutex_unlock(&sc->mutex); |
880 | ||
d2182b69 | 881 | ath_dbg(common, CONFIG, "Driver halt\n"); |
f078f209 LR |
882 | } |
883 | ||
c648ecb0 | 884 | static bool ath9k_uses_beacons(int type) |
4801416c BG |
885 | { |
886 | switch (type) { | |
887 | case NL80211_IFTYPE_AP: | |
888 | case NL80211_IFTYPE_ADHOC: | |
889 | case NL80211_IFTYPE_MESH_POINT: | |
890 | return true; | |
891 | default: | |
892 | return false; | |
893 | } | |
894 | } | |
895 | ||
4b93fd29 SM |
896 | static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data, |
897 | u8 *mac, struct ieee80211_vif *vif) | |
4801416c | 898 | { |
cb35582a | 899 | struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; |
4801416c BG |
900 | int i; |
901 | ||
ab11bb28 | 902 | if (iter_data->has_hw_macaddr) { |
4801416c BG |
903 | for (i = 0; i < ETH_ALEN; i++) |
904 | iter_data->mask[i] &= | |
905 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
ab11bb28 FF |
906 | } else { |
907 | memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); | |
908 | iter_data->has_hw_macaddr = true; | |
909 | } | |
141b38b6 | 910 | |
9a9c4fbc RM |
911 | if (!vif->bss_conf.use_short_slot) |
912 | iter_data->slottime = ATH9K_SLOT_TIME_20; | |
913 | ||
1ed32e4f | 914 | switch (vif->type) { |
4801416c BG |
915 | case NL80211_IFTYPE_AP: |
916 | iter_data->naps++; | |
f078f209 | 917 | break; |
4801416c BG |
918 | case NL80211_IFTYPE_STATION: |
919 | iter_data->nstations++; | |
cb35582a | 920 | if (avp->assoc && !iter_data->primary_sta) |
9a9c4fbc | 921 | iter_data->primary_sta = vif; |
e51f3eff | 922 | break; |
05c914fe | 923 | case NL80211_IFTYPE_ADHOC: |
4801416c | 924 | iter_data->nadhocs++; |
9a9c4fbc RM |
925 | if (vif->bss_conf.enable_beacon) |
926 | iter_data->beacons = true; | |
4801416c | 927 | break; |
9cb5412b | 928 | case NL80211_IFTYPE_MESH_POINT: |
4801416c | 929 | iter_data->nmeshes++; |
9a9c4fbc RM |
930 | if (vif->bss_conf.enable_beacon) |
931 | iter_data->beacons = true; | |
4801416c BG |
932 | break; |
933 | case NL80211_IFTYPE_WDS: | |
934 | iter_data->nwds++; | |
f078f209 LR |
935 | break; |
936 | default: | |
4801416c | 937 | break; |
f078f209 | 938 | } |
4801416c | 939 | } |
f078f209 | 940 | |
2ce73c02 SM |
941 | static void ath9k_update_bssid_mask(struct ath_softc *sc, |
942 | struct ath_chanctx *ctx, | |
943 | struct ath9k_vif_iter_data *iter_data) | |
944 | { | |
945 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
946 | struct ath_vif *avp; | |
947 | int i; | |
948 | ||
949 | if (!ath9k_is_chanctx_enabled()) | |
950 | return; | |
951 | ||
952 | list_for_each_entry(avp, &ctx->vifs, list) { | |
953 | if (ctx->nvifs_assigned != 1) | |
954 | continue; | |
955 | ||
956 | if (!avp->vif->p2p || !iter_data->has_hw_macaddr) | |
957 | continue; | |
958 | ||
959 | ether_addr_copy(common->curbssid, avp->bssid); | |
960 | ||
961 | /* perm_addr will be used as the p2p device address. */ | |
962 | for (i = 0; i < ETH_ALEN; i++) | |
963 | iter_data->mask[i] &= | |
964 | ~(iter_data->hw_macaddr[i] ^ | |
965 | sc->hw->wiphy->perm_addr[i]); | |
966 | } | |
967 | } | |
968 | ||
4801416c | 969 | /* Called with sc->mutex held. */ |
9a9c4fbc RM |
970 | void ath9k_calculate_iter_data(struct ath_softc *sc, |
971 | struct ath_chanctx *ctx, | |
4801416c BG |
972 | struct ath9k_vif_iter_data *iter_data) |
973 | { | |
9a9c4fbc | 974 | struct ath_vif *avp; |
8feceb67 | 975 | |
4801416c | 976 | /* |
daad1660 BG |
977 | * The hardware will use primary station addr together with the |
978 | * BSSID mask when matching addresses. | |
4801416c BG |
979 | */ |
980 | memset(iter_data, 0, sizeof(*iter_data)); | |
4801416c | 981 | memset(&iter_data->mask, 0xff, ETH_ALEN); |
9a9c4fbc RM |
982 | iter_data->slottime = ATH9K_SLOT_TIME_9; |
983 | ||
984 | list_for_each_entry(avp, &ctx->vifs, list) | |
985 | ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif); | |
2ce73c02 SM |
986 | |
987 | ath9k_update_bssid_mask(sc, ctx, iter_data); | |
9a9c4fbc RM |
988 | } |
989 | ||
990 | static void ath9k_set_assoc_state(struct ath_softc *sc, | |
991 | struct ieee80211_vif *vif, bool changed) | |
992 | { | |
993 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
cb35582a | 994 | struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; |
9a9c4fbc RM |
995 | unsigned long flags; |
996 | ||
997 | set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); | |
9a9c4fbc | 998 | |
cb35582a SM |
999 | ether_addr_copy(common->curbssid, avp->bssid); |
1000 | common->curaid = avp->aid; | |
9a9c4fbc RM |
1001 | ath9k_hw_write_associd(sc->sc_ah); |
1002 | ||
1003 | if (changed) { | |
1004 | common->last_rssi = ATH_RSSI_DUMMY_MARKER; | |
1005 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
5640b08e | 1006 | |
9a9c4fbc RM |
1007 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
1008 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
1009 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
1010 | } | |
4801416c | 1011 | |
9a9c4fbc RM |
1012 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
1013 | ath9k_mci_update_wlan_channels(sc, false); | |
ab11bb28 | 1014 | |
9a9c4fbc RM |
1015 | ath_dbg(common, CONFIG, |
1016 | "Primary Station interface: %pM, BSSID: %pM\n", | |
1017 | vif->addr, common->curbssid); | |
4801416c | 1018 | } |
8ca21f01 | 1019 | |
4ee26de1 SM |
1020 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
1021 | static void ath9k_set_offchannel_state(struct ath_softc *sc) | |
1022 | { | |
1023 | struct ath_hw *ah = sc->sc_ah; | |
1024 | struct ath_common *common = ath9k_hw_common(ah); | |
1025 | struct ieee80211_vif *vif = NULL; | |
1026 | ||
1027 | ath9k_ps_wakeup(sc); | |
1028 | ||
1029 | if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START) | |
1030 | vif = sc->offchannel.scan_vif; | |
1031 | else | |
1032 | vif = sc->offchannel.roc_vif; | |
1033 | ||
1034 | if (WARN_ON(!vif)) | |
1035 | goto exit; | |
1036 | ||
1037 | eth_zero_addr(common->curbssid); | |
1038 | eth_broadcast_addr(common->bssidmask); | |
1039 | ether_addr_copy(common->macaddr, vif->addr); | |
1040 | common->curaid = 0; | |
1041 | ah->opmode = vif->type; | |
1042 | ah->imask &= ~ATH9K_INT_SWBA; | |
1043 | ah->imask &= ~ATH9K_INT_TSFOOR; | |
1044 | ah->slottime = ATH9K_SLOT_TIME_9; | |
1045 | ||
1046 | ath_hw_setbssidmask(common); | |
1047 | ath9k_hw_setopmode(ah); | |
1048 | ath9k_hw_write_associd(sc->sc_ah); | |
1049 | ath9k_hw_set_interrupts(ah); | |
1050 | ath9k_hw_init_global_settings(ah); | |
1051 | ||
1052 | exit: | |
1053 | ath9k_ps_restore(sc); | |
1054 | } | |
1055 | #endif | |
1056 | ||
4801416c | 1057 | /* Called with sc->mutex held. */ |
9a9c4fbc RM |
1058 | void ath9k_calculate_summary_state(struct ath_softc *sc, |
1059 | struct ath_chanctx *ctx) | |
4801416c | 1060 | { |
4801416c BG |
1061 | struct ath_hw *ah = sc->sc_ah; |
1062 | struct ath_common *common = ath9k_hw_common(ah); | |
1063 | struct ath9k_vif_iter_data iter_data; | |
9bf30ff9 | 1064 | struct ath_beacon_config *cur_conf; |
8ca21f01 | 1065 | |
9a9c4fbc RM |
1066 | ath_chanctx_check_active(sc, ctx); |
1067 | ||
1068 | if (ctx != sc->cur_chan) | |
1069 | return; | |
1070 | ||
4ee26de1 SM |
1071 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
1072 | if (ctx == &sc->offchannel.chan) | |
1073 | return ath9k_set_offchannel_state(sc); | |
1074 | #endif | |
1075 | ||
9a9c4fbc RM |
1076 | ath9k_ps_wakeup(sc); |
1077 | ath9k_calculate_iter_data(sc, ctx, &iter_data); | |
1078 | ||
1079 | if (iter_data.has_hw_macaddr) | |
1080 | ether_addr_copy(common->macaddr, iter_data.hw_macaddr); | |
2c3db3d5 | 1081 | |
4801416c BG |
1082 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); |
1083 | ath_hw_setbssidmask(common); | |
1084 | ||
4801416c | 1085 | if (iter_data.naps > 0) { |
9bf30ff9 | 1086 | cur_conf = &ctx->beacon; |
60ca9f87 | 1087 | ath9k_hw_set_tsfadjust(ah, true); |
4801416c | 1088 | ah->opmode = NL80211_IFTYPE_AP; |
9bf30ff9 SM |
1089 | if (cur_conf->enable_beacon) |
1090 | iter_data.beacons = true; | |
4801416c | 1091 | } else { |
60ca9f87 | 1092 | ath9k_hw_set_tsfadjust(ah, false); |
5640b08e | 1093 | |
fd5999cf JC |
1094 | if (iter_data.nmeshes) |
1095 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
1096 | else if (iter_data.nwds) | |
4801416c BG |
1097 | ah->opmode = NL80211_IFTYPE_AP; |
1098 | else if (iter_data.nadhocs) | |
1099 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
1100 | else | |
1101 | ah->opmode = NL80211_IFTYPE_STATION; | |
1102 | } | |
5640b08e | 1103 | |
df35d29e SM |
1104 | ath9k_hw_setopmode(ah); |
1105 | ||
748299f2 | 1106 | ctx->switch_after_beacon = false; |
198823fd | 1107 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) |
3069168c | 1108 | ah->imask |= ATH9K_INT_TSFOOR; |
748299f2 | 1109 | else { |
4801416c | 1110 | ah->imask &= ~ATH9K_INT_TSFOOR; |
748299f2 FF |
1111 | if (iter_data.naps == 1 && iter_data.beacons) |
1112 | ctx->switch_after_beacon = true; | |
1113 | } | |
4af9cf4f | 1114 | |
9a9c4fbc RM |
1115 | ah->imask &= ~ATH9K_INT_SWBA; |
1116 | if (ah->opmode == NL80211_IFTYPE_STATION) { | |
1117 | bool changed = (iter_data.primary_sta != ctx->primary_sta); | |
1118 | ||
9a9c4fbc | 1119 | if (iter_data.primary_sta) { |
602607b6 | 1120 | iter_data.beacons = true; |
9a9c4fbc RM |
1121 | ath9k_set_assoc_state(sc, iter_data.primary_sta, |
1122 | changed); | |
1030f9fe | 1123 | ctx->primary_sta = iter_data.primary_sta; |
9a9c4fbc RM |
1124 | } else { |
1125 | ctx->primary_sta = NULL; | |
1126 | memset(common->curbssid, 0, ETH_ALEN); | |
1127 | common->curaid = 0; | |
1128 | ath9k_hw_write_associd(sc->sc_ah); | |
1129 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) | |
1130 | ath9k_mci_update_wlan_channels(sc, true); | |
1131 | } | |
1132 | } else if (iter_data.beacons) { | |
1133 | ah->imask |= ATH9K_INT_SWBA; | |
1134 | } | |
72d874c6 | 1135 | ath9k_hw_set_interrupts(ah); |
6dcc3444 | 1136 | |
9a9c4fbc RM |
1137 | if (iter_data.beacons) |
1138 | set_bit(ATH_OP_BEACONS, &common->op_flags); | |
1139 | else | |
1140 | clear_bit(ATH_OP_BEACONS, &common->op_flags); | |
1141 | ||
1142 | if (ah->slottime != iter_data.slottime) { | |
1143 | ah->slottime = iter_data.slottime; | |
1144 | ath9k_hw_init_global_settings(ah); | |
6dcc3444 | 1145 | } |
9a9c4fbc RM |
1146 | |
1147 | if (iter_data.primary_sta) | |
1148 | set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); | |
1149 | else | |
1150 | clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); | |
1151 | ||
2ce73c02 SM |
1152 | ath_dbg(common, CONFIG, |
1153 | "macaddr: %pM, bssid: %pM, bssidmask: %pM\n", | |
1154 | common->macaddr, common->curbssid, common->bssidmask); | |
1155 | ||
9a9c4fbc | 1156 | ath9k_ps_restore(sc); |
4801416c | 1157 | } |
6f255425 | 1158 | |
a4027644 SM |
1159 | static void ath9k_assign_hw_queues(struct ieee80211_hw *hw, |
1160 | struct ieee80211_vif *vif) | |
1161 | { | |
1162 | int i; | |
1163 | ||
868caae3 SM |
1164 | if (!ath9k_is_chanctx_enabled()) |
1165 | return; | |
1166 | ||
a4027644 SM |
1167 | for (i = 0; i < IEEE80211_NUM_ACS; i++) |
1168 | vif->hw_queue[i] = i; | |
1169 | ||
1170 | if (vif->type == NL80211_IFTYPE_AP) | |
1171 | vif->cab_queue = hw->queues - 2; | |
1172 | else | |
1173 | vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; | |
1174 | } | |
1175 | ||
4801416c BG |
1176 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1177 | struct ieee80211_vif *vif) | |
6b3b991d | 1178 | { |
9ac58615 | 1179 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1180 | struct ath_hw *ah = sc->sc_ah; |
1181 | struct ath_common *common = ath9k_hw_common(ah); | |
f89d1bc4 FF |
1182 | struct ath_vif *avp = (void *)vif->drv_priv; |
1183 | struct ath_node *an = &avp->mcast_node; | |
6b3b991d | 1184 | |
4801416c | 1185 | mutex_lock(&sc->mutex); |
6b3b991d | 1186 | |
89f927af | 1187 | if (config_enabled(CONFIG_ATH9K_TX99)) { |
ca529c93 | 1188 | if (sc->cur_chan->nvifs >= 1) { |
89f927af LR |
1189 | mutex_unlock(&sc->mutex); |
1190 | return -EOPNOTSUPP; | |
1191 | } | |
1192 | sc->tx99_vif = vif; | |
1193 | } | |
1194 | ||
d2182b69 | 1195 | ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); |
ca529c93 | 1196 | sc->cur_chan->nvifs++; |
4801416c | 1197 | |
130ef6e9 SM |
1198 | if (ath9k_uses_beacons(vif->type)) |
1199 | ath9k_beacon_assign_slot(sc, vif); | |
1200 | ||
d463af4a | 1201 | avp->vif = vif; |
499afacc | 1202 | if (!ath9k_is_chanctx_enabled()) { |
39305635 | 1203 | avp->chanctx = sc->cur_chan; |
9a9c4fbc RM |
1204 | list_add_tail(&avp->list, &avp->chanctx->vifs); |
1205 | } | |
a4027644 | 1206 | |
daad1660 BG |
1207 | ath9k_calculate_summary_state(sc, avp->chanctx); |
1208 | ||
a4027644 | 1209 | ath9k_assign_hw_queues(hw, vif); |
0453531e | 1210 | |
f89d1bc4 FF |
1211 | an->sc = sc; |
1212 | an->sta = NULL; | |
1213 | an->vif = vif; | |
1214 | an->no_ps_filter = true; | |
1215 | ath_tx_node_init(sc, an); | |
1216 | ||
4801416c | 1217 | mutex_unlock(&sc->mutex); |
327967cb | 1218 | return 0; |
6b3b991d RM |
1219 | } |
1220 | ||
1221 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1222 | struct ieee80211_vif *vif, | |
1223 | enum nl80211_iftype new_type, | |
1224 | bool p2p) | |
1225 | { | |
9ac58615 | 1226 | struct ath_softc *sc = hw->priv; |
6b3b991d | 1227 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c083ce99 | 1228 | struct ath_vif *avp = (void *)vif->drv_priv; |
6b3b991d | 1229 | |
6b3b991d | 1230 | mutex_lock(&sc->mutex); |
4801416c | 1231 | |
89f927af LR |
1232 | if (config_enabled(CONFIG_ATH9K_TX99)) { |
1233 | mutex_unlock(&sc->mutex); | |
1234 | return -EOPNOTSUPP; | |
1235 | } | |
1236 | ||
1237 | ath_dbg(common, CONFIG, "Change Interface\n"); | |
1238 | ||
4801416c | 1239 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1240 | ath9k_beacon_remove_slot(sc, vif); |
4801416c | 1241 | |
6b3b991d RM |
1242 | vif->type = new_type; |
1243 | vif->p2p = p2p; | |
1244 | ||
130ef6e9 SM |
1245 | if (ath9k_uses_beacons(vif->type)) |
1246 | ath9k_beacon_assign_slot(sc, vif); | |
9a9c4fbc | 1247 | |
a4027644 | 1248 | ath9k_assign_hw_queues(hw, vif); |
9a9c4fbc | 1249 | ath9k_calculate_summary_state(sc, avp->chanctx); |
130ef6e9 | 1250 | |
6b3b991d | 1251 | mutex_unlock(&sc->mutex); |
327967cb | 1252 | return 0; |
6b3b991d RM |
1253 | } |
1254 | ||
8feceb67 | 1255 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1256 | struct ieee80211_vif *vif) |
f078f209 | 1257 | { |
9ac58615 | 1258 | struct ath_softc *sc = hw->priv; |
c46917bb | 1259 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f89d1bc4 | 1260 | struct ath_vif *avp = (void *)vif->drv_priv; |
f078f209 | 1261 | |
d2182b69 | 1262 | ath_dbg(common, CONFIG, "Detach Interface\n"); |
f078f209 | 1263 | |
141b38b6 S |
1264 | mutex_lock(&sc->mutex); |
1265 | ||
c7dd40c9 | 1266 | ath9k_p2p_remove_vif(sc, vif); |
d463af4a | 1267 | |
ca529c93 | 1268 | sc->cur_chan->nvifs--; |
89f927af | 1269 | sc->tx99_vif = NULL; |
499afacc | 1270 | if (!ath9k_is_chanctx_enabled()) |
9a9c4fbc | 1271 | list_del(&avp->list); |
580f0b8a | 1272 | |
4801416c | 1273 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1274 | ath9k_beacon_remove_slot(sc, vif); |
2c3db3d5 | 1275 | |
f89d1bc4 FF |
1276 | ath_tx_node_cleanup(sc, &avp->mcast_node); |
1277 | ||
daad1660 BG |
1278 | ath9k_calculate_summary_state(sc, avp->chanctx); |
1279 | ||
141b38b6 | 1280 | mutex_unlock(&sc->mutex); |
f078f209 LR |
1281 | } |
1282 | ||
fbab7390 | 1283 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1284 | { |
3069168c | 1285 | struct ath_hw *ah = sc->sc_ah; |
ad128860 | 1286 | struct ath_common *common = ath9k_hw_common(ah); |
3069168c | 1287 | |
89f927af LR |
1288 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1289 | return; | |
1290 | ||
3f7c5c10 | 1291 | sc->ps_enabled = true; |
3069168c PR |
1292 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1293 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1294 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1295 | ath9k_hw_set_interrupts(ah); |
3f7c5c10 | 1296 | } |
fdf76622 | 1297 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1298 | } |
ad128860 | 1299 | ath_dbg(common, PS, "PowerSave enabled\n"); |
3f7c5c10 SB |
1300 | } |
1301 | ||
845d708e SB |
1302 | static void ath9k_disable_ps(struct ath_softc *sc) |
1303 | { | |
1304 | struct ath_hw *ah = sc->sc_ah; | |
ad128860 | 1305 | struct ath_common *common = ath9k_hw_common(ah); |
845d708e | 1306 | |
89f927af LR |
1307 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1308 | return; | |
1309 | ||
845d708e SB |
1310 | sc->ps_enabled = false; |
1311 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1312 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1313 | ath9k_hw_setrxabort(ah, 0); | |
1314 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1315 | PS_WAIT_FOR_CAB | | |
1316 | PS_WAIT_FOR_PSPOLL_DATA | | |
1317 | PS_WAIT_FOR_TX_ACK); | |
1318 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1319 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1320 | ath9k_hw_set_interrupts(ah); |
845d708e SB |
1321 | } |
1322 | } | |
ad128860 | 1323 | ath_dbg(common, PS, "PowerSave disabled\n"); |
845d708e SB |
1324 | } |
1325 | ||
e93d083f SW |
1326 | void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) |
1327 | { | |
1328 | struct ath_softc *sc = hw->priv; | |
1329 | struct ath_hw *ah = sc->sc_ah; | |
1330 | struct ath_common *common = ath9k_hw_common(ah); | |
1331 | u32 rxfilter; | |
1332 | ||
89f927af LR |
1333 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1334 | return; | |
1335 | ||
e93d083f SW |
1336 | if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { |
1337 | ath_err(common, "spectrum analyzer not implemented on this hardware\n"); | |
1338 | return; | |
1339 | } | |
1340 | ||
1341 | ath9k_ps_wakeup(sc); | |
1342 | rxfilter = ath9k_hw_getrxfilter(ah); | |
1343 | ath9k_hw_setrxfilter(ah, rxfilter | | |
1344 | ATH9K_RX_FILTER_PHYRADAR | | |
1345 | ATH9K_RX_FILTER_PHYERR); | |
1346 | ||
1347 | /* TODO: usually this should not be neccesary, but for some reason | |
1348 | * (or in some mode?) the trigger must be called after the | |
1349 | * configuration, otherwise the register will have its values reset | |
1350 | * (on my ar9220 to value 0x01002310) | |
1351 | */ | |
1352 | ath9k_spectral_scan_config(hw, sc->spectral_mode); | |
1353 | ath9k_hw_ops(ah)->spectral_scan_trigger(ah); | |
1354 | ath9k_ps_restore(sc); | |
1355 | } | |
1356 | ||
1357 | int ath9k_spectral_scan_config(struct ieee80211_hw *hw, | |
1358 | enum spectral_mode spectral_mode) | |
1359 | { | |
1360 | struct ath_softc *sc = hw->priv; | |
1361 | struct ath_hw *ah = sc->sc_ah; | |
1362 | struct ath_common *common = ath9k_hw_common(ah); | |
e93d083f SW |
1363 | |
1364 | if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { | |
1365 | ath_err(common, "spectrum analyzer not implemented on this hardware\n"); | |
1366 | return -1; | |
1367 | } | |
1368 | ||
e93d083f SW |
1369 | switch (spectral_mode) { |
1370 | case SPECTRAL_DISABLED: | |
04ccd4a1 | 1371 | sc->spec_config.enabled = 0; |
e93d083f SW |
1372 | break; |
1373 | case SPECTRAL_BACKGROUND: | |
1374 | /* send endless samples. | |
1375 | * TODO: is this really useful for "background"? | |
1376 | */ | |
04ccd4a1 SW |
1377 | sc->spec_config.endless = 1; |
1378 | sc->spec_config.enabled = 1; | |
e93d083f SW |
1379 | break; |
1380 | case SPECTRAL_CHANSCAN: | |
e93d083f | 1381 | case SPECTRAL_MANUAL: |
04ccd4a1 SW |
1382 | sc->spec_config.endless = 0; |
1383 | sc->spec_config.enabled = 1; | |
e93d083f SW |
1384 | break; |
1385 | default: | |
1386 | return -1; | |
1387 | } | |
1388 | ||
1389 | ath9k_ps_wakeup(sc); | |
04ccd4a1 | 1390 | ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); |
e93d083f SW |
1391 | ath9k_ps_restore(sc); |
1392 | ||
1393 | sc->spectral_mode = spectral_mode; | |
1394 | ||
1395 | return 0; | |
1396 | } | |
1397 | ||
e8975581 | 1398 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1399 | { |
9ac58615 | 1400 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1401 | struct ath_hw *ah = sc->sc_ah; |
1402 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1403 | struct ieee80211_conf *conf = &hw->conf; |
fbbcd146 | 1404 | struct ath_chanctx *ctx = sc->cur_chan; |
f078f209 | 1405 | |
c0c11741 | 1406 | ath9k_ps_wakeup(sc); |
aa33de09 | 1407 | mutex_lock(&sc->mutex); |
141b38b6 | 1408 | |
daa1b6ee | 1409 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 | 1410 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
b73f3e78 | 1411 | if (sc->ps_idle) { |
daa1b6ee | 1412 | ath_cancel_work(sc); |
b73f3e78 RM |
1413 | ath9k_stop_btcoex(sc); |
1414 | } else { | |
1415 | ath9k_start_btcoex(sc); | |
75600abf FF |
1416 | /* |
1417 | * The chip needs a reset to properly wake up from | |
1418 | * full sleep | |
1419 | */ | |
39305635 | 1420 | ath_chanctx_set_channel(sc, ctx, &ctx->chandef); |
b73f3e78 | 1421 | } |
daa1b6ee | 1422 | } |
64839170 | 1423 | |
e7824a50 LR |
1424 | /* |
1425 | * We just prepare to enable PS. We have to wait until our AP has | |
1426 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1427 | * those ACKs and end up retransmitting the same null data frames. | |
1428 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1429 | */ | |
3cbb5dd7 | 1430 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1431 | unsigned long flags; |
1432 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1433 | if (conf->flags & IEEE80211_CONF_PS) |
1434 | ath9k_enable_ps(sc); | |
845d708e SB |
1435 | else |
1436 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1437 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1438 | } |
1439 | ||
199afd9d S |
1440 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1441 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
d2182b69 | 1442 | ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); |
5f841b41 RM |
1443 | sc->sc_ah->is_monitoring = true; |
1444 | } else { | |
d2182b69 | 1445 | ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); |
5f841b41 | 1446 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1447 | } |
1448 | } | |
1449 | ||
499afacc | 1450 | if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { |
fbbcd146 | 1451 | ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL); |
bff11766 | 1452 | ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); |
094d05dc | 1453 | } |
f078f209 | 1454 | |
c9f6a656 | 1455 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
d2182b69 | 1456 | ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); |
bc7e1be7 | 1457 | sc->cur_chan->txpower = 2 * conf->power_level; |
5048e8c3 | 1458 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
bc7e1be7 | 1459 | sc->cur_chan->txpower, &sc->curtxpow); |
64839170 LR |
1460 | } |
1461 | ||
aa33de09 | 1462 | mutex_unlock(&sc->mutex); |
c0c11741 | 1463 | ath9k_ps_restore(sc); |
141b38b6 | 1464 | |
f078f209 LR |
1465 | return 0; |
1466 | } | |
1467 | ||
8feceb67 VT |
1468 | #define SUPPORTED_FILTERS \ |
1469 | (FIF_PROMISC_IN_BSS | \ | |
1470 | FIF_ALLMULTI | \ | |
1471 | FIF_CONTROL | \ | |
af6a3fc7 | 1472 | FIF_PSPOLL | \ |
8feceb67 VT |
1473 | FIF_OTHER_BSS | \ |
1474 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1475 | FIF_PROBE_REQ | \ |
8feceb67 | 1476 | FIF_FCSFAIL) |
c83be688 | 1477 | |
8feceb67 VT |
1478 | /* FIXME: sc->sc_full_reset ? */ |
1479 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1480 | unsigned int changed_flags, | |
1481 | unsigned int *total_flags, | |
3ac64bee | 1482 | u64 multicast) |
8feceb67 | 1483 | { |
9ac58615 | 1484 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1485 | u32 rfilt; |
f078f209 | 1486 | |
8feceb67 VT |
1487 | changed_flags &= SUPPORTED_FILTERS; |
1488 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1489 | |
fce34430 SM |
1490 | spin_lock_bh(&sc->chan_lock); |
1491 | sc->cur_chan->rxfilter = *total_flags; | |
1492 | spin_unlock_bh(&sc->chan_lock); | |
1493 | ||
aa68aeaa | 1494 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1495 | rfilt = ath_calcrxfilter(sc); |
1496 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1497 | ath9k_ps_restore(sc); |
f078f209 | 1498 | |
d2182b69 JP |
1499 | ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", |
1500 | rfilt); | |
8feceb67 | 1501 | } |
f078f209 | 1502 | |
4ca77860 JB |
1503 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1504 | struct ieee80211_vif *vif, | |
1505 | struct ieee80211_sta *sta) | |
8feceb67 | 1506 | { |
9ac58615 | 1507 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1508 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1509 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1510 | struct ieee80211_key_conf ps_key = { }; | |
4ef69d03 | 1511 | int key; |
f078f209 | 1512 | |
7e1e3864 | 1513 | ath_node_attach(sc, sta, vif); |
f59a59fe FF |
1514 | |
1515 | if (vif->type != NL80211_IFTYPE_AP && | |
1516 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1517 | return 0; | |
1518 | ||
4ef69d03 | 1519 | key = ath_key_config(common, vif, sta, &ps_key); |
4bbf4414 | 1520 | if (key > 0) { |
4ef69d03 | 1521 | an->ps_key = key; |
4bbf4414 RM |
1522 | an->key_idx[0] = key; |
1523 | } | |
4ca77860 JB |
1524 | |
1525 | return 0; | |
1526 | } | |
1527 | ||
93ae2dd2 FF |
1528 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1529 | struct ieee80211_vif *vif, | |
1530 | struct ieee80211_sta *sta) | |
1531 | { | |
1532 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1533 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1534 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1535 | ||
1536 | if (!an->ps_key) | |
1537 | return; | |
1538 | ||
1539 | ath_key_delete(common, &ps_key); | |
4ef69d03 | 1540 | an->ps_key = 0; |
4bbf4414 | 1541 | an->key_idx[0] = 0; |
93ae2dd2 FF |
1542 | } |
1543 | ||
4ca77860 JB |
1544 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1545 | struct ieee80211_vif *vif, | |
1546 | struct ieee80211_sta *sta) | |
1547 | { | |
9ac58615 | 1548 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1549 | |
93ae2dd2 | 1550 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1551 | ath_node_detach(sc, sta); |
1552 | ||
1553 | return 0; | |
f078f209 LR |
1554 | } |
1555 | ||
4bbf4414 RM |
1556 | static void ath9k_sta_set_tx_filter(struct ath_hw *ah, |
1557 | struct ath_node *an, | |
1558 | bool set) | |
1559 | { | |
1560 | int i; | |
1561 | ||
1562 | for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { | |
1563 | if (!an->key_idx[i]) | |
1564 | continue; | |
1565 | ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); | |
1566 | } | |
1567 | } | |
1568 | ||
5519541d FF |
1569 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1570 | struct ieee80211_vif *vif, | |
1571 | enum sta_notify_cmd cmd, | |
1572 | struct ieee80211_sta *sta) | |
1573 | { | |
1574 | struct ath_softc *sc = hw->priv; | |
1575 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1576 | ||
1577 | switch (cmd) { | |
1578 | case STA_NOTIFY_SLEEP: | |
1579 | an->sleeping = true; | |
042ec453 | 1580 | ath_tx_aggr_sleep(sta, sc, an); |
4bbf4414 | 1581 | ath9k_sta_set_tx_filter(sc->sc_ah, an, true); |
5519541d FF |
1582 | break; |
1583 | case STA_NOTIFY_AWAKE: | |
4bbf4414 | 1584 | ath9k_sta_set_tx_filter(sc->sc_ah, an, false); |
5519541d FF |
1585 | an->sleeping = false; |
1586 | ath_tx_aggr_wakeup(sc, an); | |
1587 | break; | |
1588 | } | |
1589 | } | |
1590 | ||
8a3a3c85 EP |
1591 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
1592 | struct ieee80211_vif *vif, u16 queue, | |
8feceb67 | 1593 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1594 | { |
9ac58615 | 1595 | struct ath_softc *sc = hw->priv; |
c46917bb | 1596 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1597 | struct ath_txq *txq; |
8feceb67 | 1598 | struct ath9k_tx_queue_info qi; |
066dae93 | 1599 | int ret = 0; |
f078f209 | 1600 | |
bea843c7 | 1601 | if (queue >= IEEE80211_NUM_ACS) |
8feceb67 | 1602 | return 0; |
f078f209 | 1603 | |
066dae93 FF |
1604 | txq = sc->tx.txq_map[queue]; |
1605 | ||
96f372c9 | 1606 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1607 | mutex_lock(&sc->mutex); |
1608 | ||
1ffb0610 S |
1609 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1610 | ||
8feceb67 VT |
1611 | qi.tqi_aifs = params->aifs; |
1612 | qi.tqi_cwmin = params->cw_min; | |
1613 | qi.tqi_cwmax = params->cw_max; | |
531bd079 | 1614 | qi.tqi_burstTime = params->txop * 32; |
f078f209 | 1615 | |
d2182b69 | 1616 | ath_dbg(common, CONFIG, |
226afe68 JP |
1617 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1618 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1619 | params->cw_max, params->txop); | |
f078f209 | 1620 | |
aa5955c3 | 1621 | ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); |
066dae93 | 1622 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1623 | if (ret) |
3800276a | 1624 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1625 | |
141b38b6 | 1626 | mutex_unlock(&sc->mutex); |
96f372c9 | 1627 | ath9k_ps_restore(sc); |
141b38b6 | 1628 | |
8feceb67 VT |
1629 | return ret; |
1630 | } | |
f078f209 | 1631 | |
8feceb67 VT |
1632 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1633 | enum set_key_cmd cmd, | |
dc822b5d JB |
1634 | struct ieee80211_vif *vif, |
1635 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1636 | struct ieee80211_key_conf *key) |
1637 | { | |
9ac58615 | 1638 | struct ath_softc *sc = hw->priv; |
c46917bb | 1639 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4bbf4414 RM |
1640 | struct ath_node *an = NULL; |
1641 | int ret = 0, i; | |
f078f209 | 1642 | |
3e6109c5 | 1643 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1644 | return -ENOSPC; |
1645 | ||
5bd5e9a6 CYY |
1646 | if ((vif->type == NL80211_IFTYPE_ADHOC || |
1647 | vif->type == NL80211_IFTYPE_MESH_POINT) && | |
cfdc9a8b JM |
1648 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || |
1649 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1650 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1651 | /* | |
1652 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1653 | * could be optimized in the future to use a modified key cache | |
1654 | * design to support per-STA RX GTK, but until that gets | |
1655 | * implemented, use of software crypto for group addressed | |
1656 | * frames is a acceptable to allow RSN IBSS to be used. | |
1657 | */ | |
1658 | return -EOPNOTSUPP; | |
1659 | } | |
1660 | ||
141b38b6 | 1661 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1662 | ath9k_ps_wakeup(sc); |
4bbf4414 RM |
1663 | ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); |
1664 | if (sta) | |
1665 | an = (struct ath_node *)sta->drv_priv; | |
f078f209 | 1666 | |
8feceb67 VT |
1667 | switch (cmd) { |
1668 | case SET_KEY: | |
93ae2dd2 FF |
1669 | if (sta) |
1670 | ath9k_del_ps_key(sc, vif, sta); | |
1671 | ||
4bbf4414 | 1672 | key->hw_key_idx = 0; |
040e539e | 1673 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1674 | if (ret >= 0) { |
1675 | key->hw_key_idx = ret; | |
8feceb67 VT |
1676 | /* push IV and Michael MIC generation to stack */ |
1677 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1678 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1679 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1680 | if (sc->sc_ah->sw_mgmt_crypto && |
1681 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
e548c49e | 1682 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; |
6ace2891 | 1683 | ret = 0; |
8feceb67 | 1684 | } |
4bbf4414 RM |
1685 | if (an && key->hw_key_idx) { |
1686 | for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { | |
1687 | if (an->key_idx[i]) | |
1688 | continue; | |
1689 | an->key_idx[i] = key->hw_key_idx; | |
1690 | break; | |
1691 | } | |
1692 | WARN_ON(i == ARRAY_SIZE(an->key_idx)); | |
1693 | } | |
8feceb67 VT |
1694 | break; |
1695 | case DISABLE_KEY: | |
040e539e | 1696 | ath_key_delete(common, key); |
4bbf4414 RM |
1697 | if (an) { |
1698 | for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { | |
1699 | if (an->key_idx[i] != key->hw_key_idx) | |
1700 | continue; | |
1701 | an->key_idx[i] = 0; | |
1702 | break; | |
1703 | } | |
1704 | } | |
1705 | key->hw_key_idx = 0; | |
8feceb67 VT |
1706 | break; |
1707 | default: | |
1708 | ret = -EINVAL; | |
1709 | } | |
f078f209 | 1710 | |
3cbb5dd7 | 1711 | ath9k_ps_restore(sc); |
141b38b6 S |
1712 | mutex_unlock(&sc->mutex); |
1713 | ||
8feceb67 VT |
1714 | return ret; |
1715 | } | |
6c43c090 | 1716 | |
8feceb67 VT |
1717 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1718 | struct ieee80211_vif *vif, | |
1719 | struct ieee80211_bss_conf *bss_conf, | |
1720 | u32 changed) | |
1721 | { | |
da0d45f7 SM |
1722 | #define CHECK_ANI \ |
1723 | (BSS_CHANGED_ASSOC | \ | |
1724 | BSS_CHANGED_IBSS | \ | |
1725 | BSS_CHANGED_BEACON_ENABLED) | |
1726 | ||
9ac58615 | 1727 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 1728 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1729 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1730 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1731 | int slottime; |
f078f209 | 1732 | |
96f372c9 | 1733 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1734 | mutex_lock(&sc->mutex); |
1735 | ||
9f61903c | 1736 | if (changed & BSS_CHANGED_ASSOC) { |
6c43c090 SM |
1737 | ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", |
1738 | bss_conf->bssid, bss_conf->assoc); | |
1739 | ||
cb35582a SM |
1740 | ether_addr_copy(avp->bssid, bss_conf->bssid); |
1741 | avp->aid = bss_conf->aid; | |
1742 | avp->assoc = bss_conf->assoc; | |
1743 | ||
9a9c4fbc | 1744 | ath9k_calculate_summary_state(sc, avp->chanctx); |
27babf9f SM |
1745 | |
1746 | if (ath9k_is_chanctx_enabled()) { | |
1747 | if (bss_conf->assoc) | |
1748 | ath_chanctx_event(sc, vif, | |
1749 | ATH_CHANCTX_EVENT_ASSOC); | |
1750 | } | |
c6089ccc | 1751 | } |
2d0ddec5 | 1752 | |
2e5ef459 | 1753 | if (changed & BSS_CHANGED_IBSS) { |
2e5ef459 RM |
1754 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1755 | common->curaid = bss_conf->aid; | |
1756 | ath9k_hw_write_associd(sc->sc_ah); | |
2e5ef459 RM |
1757 | } |
1758 | ||
ef4ad633 | 1759 | if ((changed & BSS_CHANGED_BEACON_ENABLED) || |
9198cf4a RM |
1760 | (changed & BSS_CHANGED_BEACON_INT) || |
1761 | (changed & BSS_CHANGED_BEACON_INFO)) { | |
9bf30ff9 | 1762 | ath9k_beacon_config(sc, vif, changed); |
9a9c4fbc RM |
1763 | if (changed & BSS_CHANGED_BEACON_ENABLED) |
1764 | ath9k_calculate_summary_state(sc, avp->chanctx); | |
9a9c4fbc | 1765 | } |
0005baf4 | 1766 | |
9a9c4fbc RM |
1767 | if ((avp->chanctx == sc->cur_chan) && |
1768 | (changed & BSS_CHANGED_ERP_SLOT)) { | |
0005baf4 FF |
1769 | if (bss_conf->use_short_slot) |
1770 | slottime = 9; | |
1771 | else | |
1772 | slottime = 20; | |
1773 | if (vif->type == NL80211_IFTYPE_AP) { | |
1774 | /* | |
1775 | * Defer update, so that connected stations can adjust | |
1776 | * their settings at the same time. | |
1777 | * See beacon.c for more details | |
1778 | */ | |
1779 | sc->beacon.slottime = slottime; | |
1780 | sc->beacon.updateslot = UPDATE; | |
1781 | } else { | |
1782 | ah->slottime = slottime; | |
1783 | ath9k_hw_init_global_settings(ah); | |
1784 | } | |
2d0ddec5 JB |
1785 | } |
1786 | ||
c7dd40c9 SM |
1787 | if (changed & BSS_CHANGED_P2P_PS) |
1788 | ath9k_p2p_bss_info_changed(sc, vif); | |
d463af4a | 1789 | |
da0d45f7 SM |
1790 | if (changed & CHECK_ANI) |
1791 | ath_check_ani(sc); | |
1792 | ||
141b38b6 | 1793 | mutex_unlock(&sc->mutex); |
96f372c9 | 1794 | ath9k_ps_restore(sc); |
da0d45f7 SM |
1795 | |
1796 | #undef CHECK_ANI | |
8feceb67 | 1797 | } |
f078f209 | 1798 | |
37a41b4a | 1799 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1800 | { |
9ac58615 | 1801 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1802 | u64 tsf; |
f078f209 | 1803 | |
141b38b6 | 1804 | mutex_lock(&sc->mutex); |
9abbfb27 | 1805 | ath9k_ps_wakeup(sc); |
141b38b6 | 1806 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 1807 | ath9k_ps_restore(sc); |
141b38b6 | 1808 | mutex_unlock(&sc->mutex); |
f078f209 | 1809 | |
8feceb67 VT |
1810 | return tsf; |
1811 | } | |
f078f209 | 1812 | |
37a41b4a EP |
1813 | static void ath9k_set_tsf(struct ieee80211_hw *hw, |
1814 | struct ieee80211_vif *vif, | |
1815 | u64 tsf) | |
3b5d665b | 1816 | { |
9ac58615 | 1817 | struct ath_softc *sc = hw->priv; |
3b5d665b | 1818 | |
141b38b6 | 1819 | mutex_lock(&sc->mutex); |
9abbfb27 | 1820 | ath9k_ps_wakeup(sc); |
141b38b6 | 1821 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 1822 | ath9k_ps_restore(sc); |
141b38b6 | 1823 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
1824 | } |
1825 | ||
37a41b4a | 1826 | static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1827 | { |
9ac58615 | 1828 | struct ath_softc *sc = hw->priv; |
c83be688 | 1829 | |
141b38b6 | 1830 | mutex_lock(&sc->mutex); |
21526d57 LR |
1831 | |
1832 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1833 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1834 | ath9k_ps_restore(sc); |
1835 | ||
141b38b6 | 1836 | mutex_unlock(&sc->mutex); |
8feceb67 | 1837 | } |
f078f209 | 1838 | |
8feceb67 | 1839 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1840 | struct ieee80211_vif *vif, |
141b38b6 S |
1841 | enum ieee80211_ampdu_mlme_action action, |
1842 | struct ieee80211_sta *sta, | |
0b01f030 | 1843 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 1844 | { |
9ac58615 | 1845 | struct ath_softc *sc = hw->priv; |
16e23428 | 1846 | bool flush = false; |
8feceb67 | 1847 | int ret = 0; |
f078f209 | 1848 | |
7ca7c776 | 1849 | mutex_lock(&sc->mutex); |
85ad181e | 1850 | |
8feceb67 VT |
1851 | switch (action) { |
1852 | case IEEE80211_AMPDU_RX_START: | |
8feceb67 VT |
1853 | break; |
1854 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1855 | break; |
1856 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1857 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
1858 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
1859 | if (!ret) | |
1860 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 1861 | ath9k_ps_restore(sc); |
8feceb67 | 1862 | break; |
18b559d5 JB |
1863 | case IEEE80211_AMPDU_TX_STOP_FLUSH: |
1864 | case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: | |
16e23428 FF |
1865 | flush = true; |
1866 | case IEEE80211_AMPDU_TX_STOP_CONT: | |
8b685ba9 | 1867 | ath9k_ps_wakeup(sc); |
f83da965 | 1868 | ath_tx_aggr_stop(sc, sta, tid); |
08c96abd | 1869 | if (!flush) |
16e23428 | 1870 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1871 | ath9k_ps_restore(sc); |
8feceb67 | 1872 | break; |
b1720231 | 1873 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1874 | ath9k_ps_wakeup(sc); |
8469cdef | 1875 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1876 | ath9k_ps_restore(sc); |
8469cdef | 1877 | break; |
8feceb67 | 1878 | default: |
3800276a | 1879 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
1880 | } |
1881 | ||
7ca7c776 | 1882 | mutex_unlock(&sc->mutex); |
85ad181e | 1883 | |
8feceb67 | 1884 | return ret; |
f078f209 LR |
1885 | } |
1886 | ||
62dad5b0 BP |
1887 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1888 | struct survey_info *survey) | |
1889 | { | |
9ac58615 | 1890 | struct ath_softc *sc = hw->priv; |
3430098a | 1891 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 1892 | struct ieee80211_supported_band *sband; |
3430098a | 1893 | struct ieee80211_channel *chan; |
3430098a FF |
1894 | int pos; |
1895 | ||
89f927af LR |
1896 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1897 | return -EOPNOTSUPP; | |
1898 | ||
b7cc9b97 | 1899 | spin_lock_bh(&common->cc_lock); |
3430098a FF |
1900 | if (idx == 0) |
1901 | ath_update_survey_stats(sc); | |
39162dbe FF |
1902 | |
1903 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
1904 | if (sband && idx >= sband->n_channels) { | |
1905 | idx -= sband->n_channels; | |
1906 | sband = NULL; | |
1907 | } | |
62dad5b0 | 1908 | |
39162dbe FF |
1909 | if (!sband) |
1910 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 1911 | |
3430098a | 1912 | if (!sband || idx >= sband->n_channels) { |
b7cc9b97 | 1913 | spin_unlock_bh(&common->cc_lock); |
3430098a | 1914 | return -ENOENT; |
4f1a5a4b | 1915 | } |
62dad5b0 | 1916 | |
3430098a FF |
1917 | chan = &sband->channels[idx]; |
1918 | pos = chan->hw_value; | |
1919 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
1920 | survey->channel = chan; | |
b7cc9b97 | 1921 | spin_unlock_bh(&common->cc_lock); |
3430098a | 1922 | |
62dad5b0 BP |
1923 | return 0; |
1924 | } | |
1925 | ||
24a1936b LB |
1926 | static void ath9k_enable_dynack(struct ath_softc *sc) |
1927 | { | |
1928 | #ifdef CONFIG_ATH9K_DYNACK | |
1929 | u32 rfilt; | |
1930 | struct ath_hw *ah = sc->sc_ah; | |
1931 | ||
1932 | ath_dynack_reset(ah); | |
1933 | ||
1934 | ah->dynack.enabled = true; | |
1935 | rfilt = ath_calcrxfilter(sc); | |
1936 | ath9k_hw_setrxfilter(ah, rfilt); | |
1937 | #endif | |
1938 | } | |
1939 | ||
a4bcaf55 LB |
1940 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, |
1941 | s16 coverage_class) | |
e239d859 | 1942 | { |
9ac58615 | 1943 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
1944 | struct ath_hw *ah = sc->sc_ah; |
1945 | ||
89f927af LR |
1946 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1947 | return; | |
1948 | ||
e239d859 | 1949 | mutex_lock(&sc->mutex); |
8b2a3827 | 1950 | |
24a1936b LB |
1951 | if (coverage_class >= 0) { |
1952 | ah->coverage_class = coverage_class; | |
1953 | if (ah->dynack.enabled) { | |
1954 | u32 rfilt; | |
1955 | ||
1956 | ah->dynack.enabled = false; | |
1957 | rfilt = ath_calcrxfilter(sc); | |
1958 | ath9k_hw_setrxfilter(ah, rfilt); | |
1959 | } | |
1960 | ath9k_ps_wakeup(sc); | |
1961 | ath9k_hw_init_global_settings(ah); | |
1962 | ath9k_ps_restore(sc); | |
1963 | } else if (!ah->dynack.enabled) { | |
1964 | ath9k_enable_dynack(sc); | |
1965 | } | |
8b2a3827 | 1966 | |
e239d859 FF |
1967 | mutex_unlock(&sc->mutex); |
1968 | } | |
1969 | ||
10e23181 FF |
1970 | static bool ath9k_has_tx_pending(struct ath_softc *sc) |
1971 | { | |
f7838073 | 1972 | int i, npend = 0; |
10e23181 FF |
1973 | |
1974 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1975 | if (!ATH_TXQ_SETUP(sc, i)) | |
1976 | continue; | |
1977 | ||
10e23181 FF |
1978 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); |
1979 | if (npend) | |
1980 | break; | |
1981 | } | |
1982 | ||
1983 | return !!npend; | |
1984 | } | |
1985 | ||
77be2c54 EG |
1986 | static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
1987 | u32 queues, bool drop) | |
bff11766 FF |
1988 | { |
1989 | struct ath_softc *sc = hw->priv; | |
1990 | ||
1991 | mutex_lock(&sc->mutex); | |
1992 | __ath9k_flush(hw, queues, drop); | |
1993 | mutex_unlock(&sc->mutex); | |
1994 | } | |
1995 | ||
1996 | void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop) | |
69081624 | 1997 | { |
69081624 | 1998 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
1999 | struct ath_hw *ah = sc->sc_ah; |
2000 | struct ath_common *common = ath9k_hw_common(ah); | |
10e23181 | 2001 | int timeout = HZ / 5; /* 200 ms */ |
2f6fc351 | 2002 | bool drain_txq; |
69081624 | 2003 | |
69081624 VT |
2004 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2005 | ||
6a6b3f3e | 2006 | if (ah->ah_flags & AH_UNPLUGGED) { |
d2182b69 | 2007 | ath_dbg(common, ANY, "Device has been unplugged!\n"); |
6a6b3f3e MSS |
2008 | return; |
2009 | } | |
2010 | ||
eefa01dd | 2011 | if (test_bit(ATH_OP_INVALID, &common->op_flags)) { |
d2182b69 | 2012 | ath_dbg(common, ANY, "Device not present\n"); |
99aa55b6 MSS |
2013 | return; |
2014 | } | |
2015 | ||
10e23181 FF |
2016 | if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc), |
2017 | timeout) > 0) | |
2018 | drop = false; | |
69081624 | 2019 | |
9df0d6a2 FF |
2020 | if (drop) { |
2021 | ath9k_ps_wakeup(sc); | |
2022 | spin_lock_bh(&sc->sc_pcu_lock); | |
1381559b | 2023 | drain_txq = ath_drain_all_txq(sc); |
9df0d6a2 | 2024 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 | 2025 | |
9df0d6a2 | 2026 | if (!drain_txq) |
1381559b | 2027 | ath_reset(sc); |
9adcf440 | 2028 | |
9df0d6a2 | 2029 | ath9k_ps_restore(sc); |
9df0d6a2 | 2030 | } |
d78f4b3e | 2031 | |
69081624 | 2032 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
69081624 VT |
2033 | } |
2034 | ||
15b91e83 VN |
2035 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
2036 | { | |
2037 | struct ath_softc *sc = hw->priv; | |
15b91e83 | 2038 | |
60913f4d | 2039 | return ath9k_has_tx_pending(sc); |
15b91e83 VN |
2040 | } |
2041 | ||
5595f119 | 2042 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
2043 | { |
2044 | struct ath_softc *sc = hw->priv; | |
2045 | struct ath_hw *ah = sc->sc_ah; | |
2046 | struct ieee80211_vif *vif; | |
2047 | struct ath_vif *avp; | |
2048 | struct ath_buf *bf; | |
2049 | struct ath_tx_status ts; | |
4286df60 | 2050 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
ba4903f9 FF |
2051 | int status; |
2052 | ||
2053 | vif = sc->beacon.bslot[0]; | |
2054 | if (!vif) | |
2055 | return 0; | |
2056 | ||
aa45fe96 | 2057 | if (!vif->bss_conf.enable_beacon) |
ba4903f9 FF |
2058 | return 0; |
2059 | ||
aa45fe96 SM |
2060 | avp = (void *)vif->drv_priv; |
2061 | ||
4286df60 | 2062 | if (!sc->beacon.tx_processed && !edma) { |
ba4903f9 FF |
2063 | tasklet_disable(&sc->bcon_tasklet); |
2064 | ||
2065 | bf = avp->av_bcbuf; | |
2066 | if (!bf || !bf->bf_mpdu) | |
2067 | goto skip; | |
2068 | ||
2069 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
2070 | if (status == -EINPROGRESS) | |
2071 | goto skip; | |
2072 | ||
2073 | sc->beacon.tx_processed = true; | |
2074 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
2075 | ||
2076 | skip: | |
2077 | tasklet_enable(&sc->bcon_tasklet); | |
2078 | } | |
2079 | ||
2080 | return sc->beacon.tx_last; | |
2081 | } | |
2082 | ||
52c94f41 MSS |
2083 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
2084 | struct ieee80211_low_level_stats *stats) | |
2085 | { | |
2086 | struct ath_softc *sc = hw->priv; | |
2087 | struct ath_hw *ah = sc->sc_ah; | |
2088 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
2089 | ||
2090 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
2091 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
2092 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
2093 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
2094 | return 0; | |
2095 | } | |
2096 | ||
43c35284 FF |
2097 | static u32 fill_chainmask(u32 cap, u32 new) |
2098 | { | |
2099 | u32 filled = 0; | |
2100 | int i; | |
2101 | ||
2102 | for (i = 0; cap && new; i++, cap >>= 1) { | |
2103 | if (!(cap & BIT(0))) | |
2104 | continue; | |
2105 | ||
2106 | if (new & BIT(0)) | |
2107 | filled |= BIT(i); | |
2108 | ||
2109 | new >>= 1; | |
2110 | } | |
2111 | ||
2112 | return filled; | |
2113 | } | |
2114 | ||
5d9c7e3c FF |
2115 | static bool validate_antenna_mask(struct ath_hw *ah, u32 val) |
2116 | { | |
fea92cbf FF |
2117 | if (AR_SREV_9300_20_OR_LATER(ah)) |
2118 | return true; | |
2119 | ||
5d9c7e3c FF |
2120 | switch (val & 0x7) { |
2121 | case 0x1: | |
2122 | case 0x3: | |
2123 | case 0x7: | |
2124 | return true; | |
2125 | case 0x2: | |
2126 | return (ah->caps.rx_chainmask == 1); | |
2127 | default: | |
2128 | return false; | |
2129 | } | |
2130 | } | |
2131 | ||
43c35284 FF |
2132 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) |
2133 | { | |
2134 | struct ath_softc *sc = hw->priv; | |
2135 | struct ath_hw *ah = sc->sc_ah; | |
2136 | ||
5d9c7e3c FF |
2137 | if (ah->caps.rx_chainmask != 1) |
2138 | rx_ant |= tx_ant; | |
2139 | ||
2140 | if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) | |
43c35284 FF |
2141 | return -EINVAL; |
2142 | ||
2143 | sc->ant_rx = rx_ant; | |
2144 | sc->ant_tx = tx_ant; | |
2145 | ||
2146 | if (ah->caps.rx_chainmask == 1) | |
2147 | return 0; | |
2148 | ||
2149 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | |
2150 | if (AR_SREV_9100(ah)) | |
2151 | ah->rxchainmask = 0x7; | |
2152 | else | |
2153 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | |
2154 | ||
2155 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | |
b57ba3b2 | 2156 | ath9k_cmn_reload_chainmask(ah); |
43c35284 FF |
2157 | |
2158 | return 0; | |
2159 | } | |
2160 | ||
2161 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
2162 | { | |
2163 | struct ath_softc *sc = hw->priv; | |
2164 | ||
2165 | *tx_ant = sc->ant_tx; | |
2166 | *rx_ant = sc->ant_rx; | |
2167 | return 0; | |
2168 | } | |
2169 | ||
e93d083f SW |
2170 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2171 | { | |
2172 | struct ath_softc *sc = hw->priv; | |
eefa01dd OR |
2173 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2174 | set_bit(ATH_OP_SCANNING, &common->op_flags); | |
e93d083f SW |
2175 | } |
2176 | ||
2177 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
2178 | { | |
2179 | struct ath_softc *sc = hw->priv; | |
eefa01dd OR |
2180 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2181 | clear_bit(ATH_OP_SCANNING, &common->op_flags); | |
e93d083f | 2182 | } |
b11e640a | 2183 | |
499afacc SM |
2184 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
2185 | ||
78b21949 | 2186 | static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
855df36d | 2187 | struct ieee80211_scan_request *hw_req) |
78b21949 | 2188 | { |
855df36d | 2189 | struct cfg80211_scan_request *req = &hw_req->req; |
78b21949 FF |
2190 | struct ath_softc *sc = hw->priv; |
2191 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
2192 | int ret = 0; | |
2193 | ||
2194 | mutex_lock(&sc->mutex); | |
2195 | ||
2196 | if (WARN_ON(sc->offchannel.scan_req)) { | |
2197 | ret = -EBUSY; | |
2198 | goto out; | |
2199 | } | |
2200 | ||
2201 | ath9k_ps_wakeup(sc); | |
2202 | set_bit(ATH_OP_SCANNING, &common->op_flags); | |
2203 | sc->offchannel.scan_vif = vif; | |
2204 | sc->offchannel.scan_req = req; | |
2205 | sc->offchannel.scan_idx = 0; | |
78b21949 | 2206 | |
bc81d43a SM |
2207 | ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n", |
2208 | vif->addr); | |
2209 | ||
2210 | if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { | |
2211 | ath_dbg(common, CHAN_CTX, "Starting HW scan\n"); | |
405393cf | 2212 | ath_offchannel_next(sc); |
bc81d43a | 2213 | } |
78b21949 FF |
2214 | |
2215 | out: | |
2216 | mutex_unlock(&sc->mutex); | |
2217 | ||
2218 | return ret; | |
2219 | } | |
2220 | ||
2221 | static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw, | |
2222 | struct ieee80211_vif *vif) | |
2223 | { | |
2224 | struct ath_softc *sc = hw->priv; | |
bc81d43a SM |
2225 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2226 | ||
2227 | ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr); | |
78b21949 FF |
2228 | |
2229 | mutex_lock(&sc->mutex); | |
2230 | del_timer_sync(&sc->offchannel.timer); | |
2231 | ath_scan_complete(sc, true); | |
2232 | mutex_unlock(&sc->mutex); | |
2233 | } | |
2234 | ||
405393cf FF |
2235 | static int ath9k_remain_on_channel(struct ieee80211_hw *hw, |
2236 | struct ieee80211_vif *vif, | |
2237 | struct ieee80211_channel *chan, int duration, | |
2238 | enum ieee80211_roc_type type) | |
2239 | { | |
2240 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2241 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
405393cf FF |
2242 | int ret = 0; |
2243 | ||
2244 | mutex_lock(&sc->mutex); | |
2245 | ||
2246 | if (WARN_ON(sc->offchannel.roc_vif)) { | |
2247 | ret = -EBUSY; | |
2248 | goto out; | |
2249 | } | |
2250 | ||
2251 | ath9k_ps_wakeup(sc); | |
2252 | sc->offchannel.roc_vif = vif; | |
2253 | sc->offchannel.roc_chan = chan; | |
2254 | sc->offchannel.roc_duration = duration; | |
2255 | ||
bc81d43a SM |
2256 | ath_dbg(common, CHAN_CTX, |
2257 | "RoC request on vif: %pM, type: %d duration: %d\n", | |
2258 | vif->addr, type, duration); | |
2259 | ||
2260 | if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { | |
2261 | ath_dbg(common, CHAN_CTX, "Starting RoC period\n"); | |
405393cf | 2262 | ath_offchannel_next(sc); |
bc81d43a | 2263 | } |
405393cf FF |
2264 | |
2265 | out: | |
2266 | mutex_unlock(&sc->mutex); | |
2267 | ||
2268 | return ret; | |
2269 | } | |
2270 | ||
2271 | static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw) | |
2272 | { | |
2273 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2274 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
405393cf FF |
2275 | |
2276 | mutex_lock(&sc->mutex); | |
2277 | ||
bc81d43a | 2278 | ath_dbg(common, CHAN_CTX, "Cancel RoC\n"); |
405393cf FF |
2279 | del_timer_sync(&sc->offchannel.timer); |
2280 | ||
2281 | if (sc->offchannel.roc_vif) { | |
2282 | if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) | |
2283 | ath_roc_complete(sc, true); | |
2284 | } | |
2285 | ||
2286 | mutex_unlock(&sc->mutex); | |
2287 | ||
2288 | return 0; | |
2289 | } | |
2290 | ||
39305635 FF |
2291 | static int ath9k_add_chanctx(struct ieee80211_hw *hw, |
2292 | struct ieee80211_chanctx_conf *conf) | |
2293 | { | |
2294 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2295 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 | 2296 | struct ath_chanctx *ctx, **ptr; |
3ad9c386 | 2297 | int pos; |
39305635 FF |
2298 | |
2299 | mutex_lock(&sc->mutex); | |
c4dc0d04 RM |
2300 | |
2301 | ath_for_each_chanctx(sc, ctx) { | |
2302 | if (ctx->assigned) | |
2303 | continue; | |
2304 | ||
2305 | ptr = (void *) conf->drv_priv; | |
2306 | *ptr = ctx; | |
2307 | ctx->assigned = true; | |
3ad9c386 RM |
2308 | pos = ctx - &sc->chanctx[0]; |
2309 | ctx->hw_queue_base = pos * IEEE80211_NUM_ACS; | |
bc81d43a SM |
2310 | |
2311 | ath_dbg(common, CHAN_CTX, | |
2312 | "Add channel context: %d MHz\n", | |
2313 | conf->def.chan->center_freq); | |
2314 | ||
c4dc0d04 | 2315 | ath_chanctx_set_channel(sc, ctx, &conf->def); |
4c7e9aee SM |
2316 | ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_ASSIGN); |
2317 | ||
39305635 | 2318 | mutex_unlock(&sc->mutex); |
c4dc0d04 | 2319 | return 0; |
39305635 | 2320 | } |
bc81d43a | 2321 | |
39305635 | 2322 | mutex_unlock(&sc->mutex); |
c4dc0d04 | 2323 | return -ENOSPC; |
39305635 FF |
2324 | } |
2325 | ||
2326 | ||
2327 | static void ath9k_remove_chanctx(struct ieee80211_hw *hw, | |
2328 | struct ieee80211_chanctx_conf *conf) | |
2329 | { | |
2330 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2331 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2332 | struct ath_chanctx *ctx = ath_chanctx_get(conf); |
2333 | ||
2334 | mutex_lock(&sc->mutex); | |
bc81d43a SM |
2335 | |
2336 | ath_dbg(common, CHAN_CTX, | |
2337 | "Remove channel context: %d MHz\n", | |
2338 | conf->def.chan->center_freq); | |
2339 | ||
39305635 | 2340 | ctx->assigned = false; |
b18111d9 | 2341 | ctx->hw_queue_base = 0; |
73fa2f26 | 2342 | ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN); |
bc81d43a | 2343 | |
39305635 FF |
2344 | mutex_unlock(&sc->mutex); |
2345 | } | |
2346 | ||
2347 | static void ath9k_change_chanctx(struct ieee80211_hw *hw, | |
2348 | struct ieee80211_chanctx_conf *conf, | |
2349 | u32 changed) | |
2350 | { | |
2351 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2352 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2353 | struct ath_chanctx *ctx = ath_chanctx_get(conf); |
2354 | ||
2355 | mutex_lock(&sc->mutex); | |
bc81d43a SM |
2356 | ath_dbg(common, CHAN_CTX, |
2357 | "Change channel context: %d MHz\n", | |
2358 | conf->def.chan->center_freq); | |
39305635 FF |
2359 | ath_chanctx_set_channel(sc, ctx, &conf->def); |
2360 | mutex_unlock(&sc->mutex); | |
2361 | } | |
2362 | ||
2363 | static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw, | |
2364 | struct ieee80211_vif *vif, | |
2365 | struct ieee80211_chanctx_conf *conf) | |
2366 | { | |
2367 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2368 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2369 | struct ath_vif *avp = (void *)vif->drv_priv; |
2370 | struct ath_chanctx *ctx = ath_chanctx_get(conf); | |
3ad9c386 | 2371 | int i; |
39305635 FF |
2372 | |
2373 | mutex_lock(&sc->mutex); | |
bc81d43a SM |
2374 | |
2375 | ath_dbg(common, CHAN_CTX, | |
2376 | "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n", | |
2377 | vif->addr, vif->type, vif->p2p, | |
2378 | conf->def.chan->center_freq); | |
2379 | ||
39305635 | 2380 | avp->chanctx = ctx; |
2ce73c02 | 2381 | ctx->nvifs_assigned++; |
39305635 | 2382 | list_add_tail(&avp->list, &ctx->vifs); |
9a9c4fbc | 2383 | ath9k_calculate_summary_state(sc, ctx); |
3ad9c386 RM |
2384 | for (i = 0; i < IEEE80211_NUM_ACS; i++) |
2385 | vif->hw_queue[i] = ctx->hw_queue_base + i; | |
bc81d43a | 2386 | |
39305635 FF |
2387 | mutex_unlock(&sc->mutex); |
2388 | ||
2389 | return 0; | |
2390 | } | |
2391 | ||
2392 | static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw, | |
2393 | struct ieee80211_vif *vif, | |
2394 | struct ieee80211_chanctx_conf *conf) | |
2395 | { | |
2396 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2397 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2398 | struct ath_vif *avp = (void *)vif->drv_priv; |
2399 | struct ath_chanctx *ctx = ath_chanctx_get(conf); | |
3ad9c386 | 2400 | int ac; |
39305635 FF |
2401 | |
2402 | mutex_lock(&sc->mutex); | |
bc81d43a SM |
2403 | |
2404 | ath_dbg(common, CHAN_CTX, | |
2405 | "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n", | |
2406 | vif->addr, vif->type, vif->p2p, | |
2407 | conf->def.chan->center_freq); | |
2408 | ||
39305635 | 2409 | avp->chanctx = NULL; |
2ce73c02 | 2410 | ctx->nvifs_assigned--; |
39305635 | 2411 | list_del(&avp->list); |
9a9c4fbc | 2412 | ath9k_calculate_summary_state(sc, ctx); |
3ad9c386 RM |
2413 | for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) |
2414 | vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE; | |
bc81d43a | 2415 | |
39305635 FF |
2416 | mutex_unlock(&sc->mutex); |
2417 | } | |
2418 | ||
e20a854e SM |
2419 | static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw, |
2420 | struct ieee80211_vif *vif) | |
2421 | { | |
2422 | struct ath_softc *sc = hw->priv; | |
2423 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
2424 | struct ath_vif *avp = (struct ath_vif *) vif->drv_priv; | |
2425 | bool changed = false; | |
2426 | ||
2427 | if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) | |
2428 | return; | |
2429 | ||
2430 | if (!avp->chanctx) | |
2431 | return; | |
2432 | ||
2433 | mutex_lock(&sc->mutex); | |
2434 | ||
2435 | spin_lock_bh(&sc->chan_lock); | |
2436 | if (sc->next_chan || (sc->cur_chan != avp->chanctx)) { | |
2437 | sc->next_chan = avp->chanctx; | |
2438 | changed = true; | |
2439 | } | |
878066e7 SM |
2440 | ath_dbg(common, CHAN_CTX, |
2441 | "%s: Set chanctx state to FORCE_ACTIVE, changed: %d\n", | |
2442 | __func__, changed); | |
e20a854e SM |
2443 | sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE; |
2444 | spin_unlock_bh(&sc->chan_lock); | |
2445 | ||
2446 | if (changed) | |
2447 | ath_chanctx_set_next(sc, true); | |
2448 | ||
2449 | mutex_unlock(&sc->mutex); | |
2450 | } | |
2451 | ||
78b21949 FF |
2452 | void ath9k_fill_chanctx_ops(void) |
2453 | { | |
499afacc | 2454 | if (!ath9k_is_chanctx_enabled()) |
78b21949 FF |
2455 | return; |
2456 | ||
bc81d43a SM |
2457 | ath9k_ops.hw_scan = ath9k_hw_scan; |
2458 | ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan; | |
2459 | ath9k_ops.remain_on_channel = ath9k_remain_on_channel; | |
405393cf | 2460 | ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel; |
bc81d43a SM |
2461 | ath9k_ops.add_chanctx = ath9k_add_chanctx; |
2462 | ath9k_ops.remove_chanctx = ath9k_remove_chanctx; | |
2463 | ath9k_ops.change_chanctx = ath9k_change_chanctx; | |
2464 | ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx; | |
2465 | ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx; | |
e20a854e | 2466 | ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx; |
78b21949 FF |
2467 | } |
2468 | ||
499afacc SM |
2469 | #endif |
2470 | ||
6baff7f9 | 2471 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2472 | .tx = ath9k_tx, |
2473 | .start = ath9k_start, | |
2474 | .stop = ath9k_stop, | |
2475 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2476 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2477 | .remove_interface = ath9k_remove_interface, |
2478 | .config = ath9k_config, | |
8feceb67 | 2479 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2480 | .sta_add = ath9k_sta_add, |
2481 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2482 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2483 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2484 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2485 | .set_key = ath9k_set_key, |
8feceb67 | 2486 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2487 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2488 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2489 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2490 | .get_survey = ath9k_get_survey, |
3b319aae | 2491 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2492 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2493 | .flush = ath9k_flush, |
15b91e83 | 2494 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 | 2495 | .tx_last_beacon = ath9k_tx_last_beacon, |
86a22acf | 2496 | .release_buffered_frames = ath9k_release_buffered_frames, |
52c94f41 | 2497 | .get_stats = ath9k_get_stats, |
43c35284 FF |
2498 | .set_antenna = ath9k_set_antenna, |
2499 | .get_antenna = ath9k_get_antenna, | |
b90bd9d1 | 2500 | |
e60001e7 | 2501 | #ifdef CONFIG_ATH9K_WOW |
b11e640a MSS |
2502 | .suspend = ath9k_suspend, |
2503 | .resume = ath9k_resume, | |
2504 | .set_wakeup = ath9k_set_wakeup, | |
2505 | #endif | |
2506 | ||
b90bd9d1 BG |
2507 | #ifdef CONFIG_ATH9K_DEBUGFS |
2508 | .get_et_sset_count = ath9k_get_et_sset_count, | |
a145daf7 SM |
2509 | .get_et_stats = ath9k_get_et_stats, |
2510 | .get_et_strings = ath9k_get_et_strings, | |
2511 | #endif | |
2512 | ||
1cdbaf0d | 2513 | #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) |
a145daf7 | 2514 | .sta_add_debugfs = ath9k_sta_add_debugfs, |
b90bd9d1 | 2515 | #endif |
e93d083f SW |
2516 | .sw_scan_start = ath9k_sw_scan_start, |
2517 | .sw_scan_complete = ath9k_sw_scan_complete, | |
8feceb67 | 2518 | }; |