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ath: make gcc check format arguments of ath_print(), fix all misuses
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CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
ce111bad
LR
21static void ath_cache_conf_rate(struct ath_softc *sc,
22 struct ieee80211_conf *conf)
ff37e337 23{
030bb495
LR
24 switch (conf->channel->band) {
25 case IEEE80211_BAND_2GHZ:
26 if (conf_is_ht20(conf))
545750d3 27 sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
030bb495 28 else if (conf_is_ht40_minus(conf))
545750d3 29 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
030bb495 30 else if (conf_is_ht40_plus(conf))
545750d3 31 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
96742256 32 else
545750d3 33 sc->cur_rate_mode = ATH9K_MODE_11G;
030bb495
LR
34 break;
35 case IEEE80211_BAND_5GHZ:
36 if (conf_is_ht20(conf))
545750d3 37 sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
030bb495 38 else if (conf_is_ht40_minus(conf))
545750d3 39 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
030bb495 40 else if (conf_is_ht40_plus(conf))
545750d3 41 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
030bb495 42 else
545750d3 43 sc->cur_rate_mode = ATH9K_MODE_11A;
030bb495
LR
44 break;
45 default:
ce111bad 46 BUG_ON(1);
030bb495
LR
47 break;
48 }
ff37e337
S
49}
50
51static void ath_update_txpow(struct ath_softc *sc)
52{
cbe61d8a 53 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
54 u32 txpow;
55
17d7904d
S
56 if (sc->curtxpow != sc->config.txpowlimit) {
57 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S
58 /* read back in case value is clamped */
59 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 60 sc->curtxpow = txpow;
ff37e337
S
61 }
62}
63
64static u8 parse_mpdudensity(u8 mpdudensity)
65{
66 /*
67 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
68 * 0 for no restriction
69 * 1 for 1/4 us
70 * 2 for 1/2 us
71 * 3 for 1 us
72 * 4 for 2 us
73 * 5 for 4 us
74 * 6 for 8 us
75 * 7 for 16 us
76 */
77 switch (mpdudensity) {
78 case 0:
79 return 0;
80 case 1:
81 case 2:
82 case 3:
83 /* Our lower layer calculations limit our precision to
84 1 microsecond */
85 return 1;
86 case 4:
87 return 2;
88 case 5:
89 return 4;
90 case 6:
91 return 8;
92 case 7:
93 return 16;
94 default:
95 return 0;
96 }
97}
98
82880a7c
VT
99static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
100 struct ieee80211_hw *hw)
101{
102 struct ieee80211_channel *curchan = hw->conf.channel;
103 struct ath9k_channel *channel;
104 u8 chan_idx;
105
106 chan_idx = curchan->hw_value;
107 channel = &sc->sc_ah->channels[chan_idx];
108 ath9k_update_ichannel(sc, hw, channel);
109 return channel;
110}
111
55624204 112bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
113{
114 unsigned long flags;
115 bool ret;
116
9ecdef4b
LR
117 spin_lock_irqsave(&sc->sc_pm_lock, flags);
118 ret = ath9k_hw_setpower(sc->sc_ah, mode);
119 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
120
121 return ret;
122}
123
a91d75ae
LR
124void ath9k_ps_wakeup(struct ath_softc *sc)
125{
126 unsigned long flags;
127
128 spin_lock_irqsave(&sc->sc_pm_lock, flags);
129 if (++sc->ps_usecount != 1)
130 goto unlock;
131
9ecdef4b 132 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae
LR
133
134 unlock:
135 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
136}
137
138void ath9k_ps_restore(struct ath_softc *sc)
139{
140 unsigned long flags;
141
142 spin_lock_irqsave(&sc->sc_pm_lock, flags);
143 if (--sc->ps_usecount != 0)
144 goto unlock;
145
1dbfd9d4
VN
146 if (sc->ps_idle)
147 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
148 else if (sc->ps_enabled &&
149 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
150 PS_WAIT_FOR_CAB |
151 PS_WAIT_FOR_PSPOLL_DATA |
152 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 153 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
154
155 unlock:
156 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
157}
158
ff37e337
S
159/*
160 * Set/change channels. If the channel is really being changed, it's done
161 * by reseting the chip. To accomplish this we must first cleanup any pending
162 * DMA, then restart stuff.
163*/
0e2dedf9
JM
164int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
165 struct ath9k_channel *hchan)
ff37e337 166{
cbe61d8a 167 struct ath_hw *ah = sc->sc_ah;
c46917bb 168 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 169 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 170 bool fastcc = true, stopped;
ae8d2858
LR
171 struct ieee80211_channel *channel = hw->conf.channel;
172 int r;
ff37e337
S
173
174 if (sc->sc_flags & SC_OP_INVALID)
175 return -EIO;
176
3cbb5dd7
VN
177 ath9k_ps_wakeup(sc);
178
c0d7c7af
LR
179 /*
180 * This is only performed if the channel settings have
181 * actually changed.
182 *
183 * To switch channels clear any pending DMA operations;
184 * wait long enough for the RX fifo to drain, reset the
185 * hardware at the new frequency, and then re-enable
186 * the relevant bits of the h/w.
187 */
188 ath9k_hw_set_interrupts(ah, 0);
043a0405 189 ath_drain_all_txq(sc, false);
c0d7c7af 190 stopped = ath_stoprecv(sc);
ff37e337 191
c0d7c7af
LR
192 /* XXX: do not flush receive queue here. We don't want
193 * to flush data frames already in queue because of
194 * changing channel. */
ff37e337 195
c0d7c7af
LR
196 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
197 fastcc = false;
198
c46917bb 199 ath_print(common, ATH_DBG_CONFIG,
25c56eec 200 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
c46917bb 201 sc->sc_ah->curchan->channel,
25c56eec 202 channel->center_freq, conf_is_ht40(conf));
ff37e337 203
c0d7c7af
LR
204 spin_lock_bh(&sc->sc_resetlock);
205
206 r = ath9k_hw_reset(ah, hchan, fastcc);
207 if (r) {
c46917bb 208 ath_print(common, ATH_DBG_FATAL,
f643e51d 209 "Unable to reset channel (%u MHz), "
c46917bb
LR
210 "reset status %d\n",
211 channel->center_freq, r);
c0d7c7af 212 spin_unlock_bh(&sc->sc_resetlock);
3989279c 213 goto ps_restore;
ff37e337 214 }
c0d7c7af
LR
215 spin_unlock_bh(&sc->sc_resetlock);
216
c0d7c7af
LR
217 sc->sc_flags &= ~SC_OP_FULL_RESET;
218
219 if (ath_startrecv(sc) != 0) {
c46917bb
LR
220 ath_print(common, ATH_DBG_FATAL,
221 "Unable to restart recv logic\n");
3989279c
GJ
222 r = -EIO;
223 goto ps_restore;
c0d7c7af
LR
224 }
225
226 ath_cache_conf_rate(sc, &hw->conf);
227 ath_update_txpow(sc);
17d7904d 228 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ
229
230 ps_restore:
3cbb5dd7 231 ath9k_ps_restore(sc);
3989279c 232 return r;
ff37e337
S
233}
234
235/*
236 * This routine performs the periodic noise floor calibration function
237 * that is used to adjust and optimize the chip performance. This
238 * takes environmental changes (location, temperature) into account.
239 * When the task is complete, it reschedules itself depending on the
240 * appropriate interval that was calculated.
241 */
55624204 242void ath_ani_calibrate(unsigned long data)
ff37e337 243{
20977d3e
S
244 struct ath_softc *sc = (struct ath_softc *)data;
245 struct ath_hw *ah = sc->sc_ah;
c46917bb 246 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
247 bool longcal = false;
248 bool shortcal = false;
249 bool aniflag = false;
250 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 251 u32 cal_interval, short_cal_interval;
ff37e337 252
20977d3e
S
253 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
254 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 255
1ffc1c61
JM
256 /* Only calibrate if awake */
257 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
258 goto set_timer;
259
260 ath9k_ps_wakeup(sc);
261
ff37e337 262 /* Long calibration runs independently of short calibration. */
3d536acf 263 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 264 longcal = true;
c46917bb 265 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 266 common->ani.longcal_timer = timestamp;
ff37e337
S
267 }
268
17d7904d 269 /* Short calibration applies only while caldone is false */
3d536acf
LR
270 if (!common->ani.caldone) {
271 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 272 shortcal = true;
c46917bb
LR
273 ath_print(common, ATH_DBG_ANI,
274 "shortcal @%lu\n", jiffies);
3d536acf
LR
275 common->ani.shortcal_timer = timestamp;
276 common->ani.resetcal_timer = timestamp;
ff37e337
S
277 }
278 } else {
3d536acf 279 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 280 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
281 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
282 if (common->ani.caldone)
283 common->ani.resetcal_timer = timestamp;
ff37e337
S
284 }
285 }
286
287 /* Verify whether we must check ANI */
3d536acf 288 if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 289 aniflag = true;
3d536acf 290 common->ani.checkani_timer = timestamp;
ff37e337
S
291 }
292
293 /* Skip all processing if there's nothing to do. */
294 if (longcal || shortcal || aniflag) {
295 /* Call ANI routine if necessary */
296 if (aniflag)
22e66a4c 297 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S
298
299 /* Perform calibration if necessary */
300 if (longcal || shortcal) {
3d536acf 301 common->ani.caldone =
43c27613
LR
302 ath9k_hw_calibrate(ah,
303 ah->curchan,
304 common->rx_chainmask,
305 longcal);
379f0440
S
306
307 if (longcal)
3d536acf 308 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
379f0440
S
309 ah->curchan);
310
c46917bb
LR
311 ath_print(common, ATH_DBG_ANI,
312 " calibrate chan %u/%x nf: %d\n",
313 ah->curchan->channel,
314 ah->curchan->channelFlags,
3d536acf 315 common->ani.noise_floor);
ff37e337
S
316 }
317 }
318
1ffc1c61
JM
319 ath9k_ps_restore(sc);
320
20977d3e 321set_timer:
ff37e337
S
322 /*
323 * Set timer interval based on previous results.
324 * The interval must be the shortest necessary to satisfy ANI,
325 * short calibration and long calibration.
326 */
aac9207e 327 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 328 if (sc->sc_ah->config.enable_ani)
aac9207e 329 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
3d536acf 330 if (!common->ani.caldone)
20977d3e 331 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 332
3d536acf 333 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S
334}
335
3d536acf 336static void ath_start_ani(struct ath_common *common)
415f738e
S
337{
338 unsigned long timestamp = jiffies_to_msecs(jiffies);
339
3d536acf
LR
340 common->ani.longcal_timer = timestamp;
341 common->ani.shortcal_timer = timestamp;
342 common->ani.checkani_timer = timestamp;
415f738e 343
3d536acf 344 mod_timer(&common->ani.timer,
415f738e
S
345 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
346}
347
ff37e337
S
348/*
349 * Update tx/rx chainmask. For legacy association,
350 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT
351 * the chainmask configuration, for bt coexistence, use
352 * the chainmask configuration even in legacy mode.
ff37e337 353 */
0e2dedf9 354void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 355{
af03abec 356 struct ath_hw *ah = sc->sc_ah;
43c27613 357 struct ath_common *common = ath9k_hw_common(ah);
af03abec 358
3d832611 359 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
766ec4a9 360 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR
361 common->tx_chainmask = ah->caps.tx_chainmask;
362 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 363 } else {
43c27613
LR
364 common->tx_chainmask = 1;
365 common->rx_chainmask = 1;
ff37e337
S
366 }
367
43c27613 368 ath_print(common, ATH_DBG_CONFIG,
c46917bb 369 "tx chmask: %d, rx chmask: %d\n",
43c27613
LR
370 common->tx_chainmask,
371 common->rx_chainmask);
ff37e337
S
372}
373
374static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
375{
376 struct ath_node *an;
377
378 an = (struct ath_node *)sta->drv_priv;
379
87792efc 380 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 381 ath_tx_node_init(sc, an);
9e98ac65 382 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
383 sta->ht_cap.ampdu_factor);
384 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 385 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 386 }
ff37e337
S
387}
388
389static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
390{
391 struct ath_node *an = (struct ath_node *)sta->drv_priv;
392
393 if (sc->sc_flags & SC_OP_TXAGGR)
394 ath_tx_node_cleanup(sc, an);
395}
396
55624204 397void ath9k_tasklet(unsigned long data)
ff37e337
S
398{
399 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 400 struct ath_hw *ah = sc->sc_ah;
c46917bb 401 struct ath_common *common = ath9k_hw_common(ah);
af03abec 402
17d7904d 403 u32 status = sc->intrstatus;
ff37e337 404
153e080d
VT
405 ath9k_ps_wakeup(sc);
406
ff37e337 407 if (status & ATH9K_INT_FATAL) {
ff37e337 408 ath_reset(sc, false);
153e080d 409 ath9k_ps_restore(sc);
ff37e337 410 return;
063d8be3 411 }
ff37e337 412
063d8be3
S
413 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
414 spin_lock_bh(&sc->rx.rxflushlock);
415 ath_rx_tasklet(sc, 0);
416 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S
417 }
418
063d8be3
S
419 if (status & ATH9K_INT_TX)
420 ath_tx_tasklet(sc);
421
96148326 422 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM
423 /*
424 * TSF sync does not look correct; remain awake to sync with
425 * the next Beacon.
426 */
c46917bb
LR
427 ath_print(common, ATH_DBG_PS,
428 "TSFOOR - Sync with next Beacon\n");
1b04b930 429 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
54ce846e
JM
430 }
431
766ec4a9 432 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
433 if (status & ATH9K_INT_GENTIMER)
434 ath_gen_timer_isr(sc->sc_ah);
435
ff37e337 436 /* re-enable hardware interrupt */
af03abec 437 ath9k_hw_set_interrupts(ah, sc->imask);
153e080d 438 ath9k_ps_restore(sc);
ff37e337
S
439}
440
6baff7f9 441irqreturn_t ath_isr(int irq, void *dev)
ff37e337 442{
063d8be3
S
443#define SCHED_INTR ( \
444 ATH9K_INT_FATAL | \
445 ATH9K_INT_RXORN | \
446 ATH9K_INT_RXEOL | \
447 ATH9K_INT_RX | \
448 ATH9K_INT_TX | \
449 ATH9K_INT_BMISS | \
450 ATH9K_INT_CST | \
ebb8e1d7
VT
451 ATH9K_INT_TSFOOR | \
452 ATH9K_INT_GENTIMER)
063d8be3 453
ff37e337 454 struct ath_softc *sc = dev;
cbe61d8a 455 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
456 enum ath9k_int status;
457 bool sched = false;
458
063d8be3
S
459 /*
460 * The hardware is not ready/present, don't
461 * touch anything. Note this can happen early
462 * on if the IRQ is shared.
463 */
464 if (sc->sc_flags & SC_OP_INVALID)
465 return IRQ_NONE;
ff37e337 466
063d8be3
S
467
468 /* shared irq, not for us */
469
153e080d 470 if (!ath9k_hw_intrpend(ah))
063d8be3 471 return IRQ_NONE;
063d8be3
S
472
473 /*
474 * Figure out the reason(s) for the interrupt. Note
475 * that the hal returns a pseudo-ISR that may include
476 * bits we haven't explicitly enabled so we mask the
477 * value to insure we only process bits we requested.
478 */
479 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
480 status &= sc->imask; /* discard unasked-for bits */
ff37e337 481
063d8be3
S
482 /*
483 * If there are no status bits set, then this interrupt was not
484 * for me (should have been caught above).
485 */
153e080d 486 if (!status)
063d8be3 487 return IRQ_NONE;
ff37e337 488
063d8be3
S
489 /* Cache the status */
490 sc->intrstatus = status;
491
492 if (status & SCHED_INTR)
493 sched = true;
494
495 /*
496 * If a FATAL or RXORN interrupt is received, we have to reset the
497 * chip immediately.
498 */
499 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
500 goto chip_reset;
501
502 if (status & ATH9K_INT_SWBA)
503 tasklet_schedule(&sc->bcon_tasklet);
504
505 if (status & ATH9K_INT_TXURN)
506 ath9k_hw_updatetxtriglevel(ah, true);
507
508 if (status & ATH9K_INT_MIB) {
ff37e337 509 /*
063d8be3
S
510 * Disable interrupts until we service the MIB
511 * interrupt; otherwise it will continue to
512 * fire.
ff37e337 513 */
063d8be3
S
514 ath9k_hw_set_interrupts(ah, 0);
515 /*
516 * Let the hal handle the event. We assume
517 * it will clear whatever condition caused
518 * the interrupt.
519 */
22e66a4c 520 ath9k_hw_procmibevent(ah);
063d8be3
S
521 ath9k_hw_set_interrupts(ah, sc->imask);
522 }
ff37e337 523
153e080d
VT
524 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
525 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S
526 /* Clear RxAbort bit so that we can
527 * receive frames */
9ecdef4b 528 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 529 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 530 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 531 }
063d8be3
S
532
533chip_reset:
ff37e337 534
817e11de
S
535 ath_debug_stat_interrupt(sc, status);
536
ff37e337
S
537 if (sched) {
538 /* turn off every interrupt except SWBA */
17d7904d 539 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S
540 tasklet_schedule(&sc->intr_tq);
541 }
542
543 return IRQ_HANDLED;
063d8be3
S
544
545#undef SCHED_INTR
ff37e337
S
546}
547
f078f209 548static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 549 struct ieee80211_channel *chan,
094d05dc 550 enum nl80211_channel_type channel_type)
f078f209
LR
551{
552 u32 chanmode = 0;
f078f209
LR
553
554 switch (chan->band) {
555 case IEEE80211_BAND_2GHZ:
094d05dc
S
556 switch(channel_type) {
557 case NL80211_CHAN_NO_HT:
558 case NL80211_CHAN_HT20:
f078f209 559 chanmode = CHANNEL_G_HT20;
094d05dc
S
560 break;
561 case NL80211_CHAN_HT40PLUS:
f078f209 562 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S
563 break;
564 case NL80211_CHAN_HT40MINUS:
f078f209 565 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S
566 break;
567 }
f078f209
LR
568 break;
569 case IEEE80211_BAND_5GHZ:
094d05dc
S
570 switch(channel_type) {
571 case NL80211_CHAN_NO_HT:
572 case NL80211_CHAN_HT20:
f078f209 573 chanmode = CHANNEL_A_HT20;
094d05dc
S
574 break;
575 case NL80211_CHAN_HT40PLUS:
f078f209 576 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S
577 break;
578 case NL80211_CHAN_HT40MINUS:
f078f209 579 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S
580 break;
581 }
f078f209
LR
582 break;
583 default:
584 break;
585 }
586
587 return chanmode;
588}
589
7e86c104 590static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
3f53dd64
JM
591 struct ath9k_keyval *hk, const u8 *addr,
592 bool authenticator)
f078f209 593{
7e86c104 594 struct ath_hw *ah = common->ah;
6ace2891
JM
595 const u8 *key_rxmic;
596 const u8 *key_txmic;
f078f209 597
6ace2891
JM
598 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
599 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR
600
601 if (addr == NULL) {
d216aaa6
JM
602 /*
603 * Group key installation - only two key cache entries are used
604 * regardless of splitmic capability since group key is only
605 * used either for TX or RX.
606 */
3f53dd64
JM
607 if (authenticator) {
608 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
609 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
610 } else {
611 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
612 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
613 }
7e86c104 614 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
f078f209 615 }
7e86c104 616 if (!common->splitmic) {
d216aaa6 617 /* TX and RX keys share the same key cache entry. */
f078f209
LR
618 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
619 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
7e86c104 620 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
f078f209 621 }
d216aaa6
JM
622
623 /* Separate key cache entries for TX and RX */
624
625 /* TX key goes at first index, RX key at +32. */
f078f209 626 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
7e86c104 627 if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
d216aaa6 628 /* TX MIC entry failed. No need to proceed further */
7e86c104 629 ath_print(common, ATH_DBG_FATAL,
c46917bb 630 "Setting TX MIC Key Failed\n");
f078f209
LR
631 return 0;
632 }
633
634 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
635 /* XXX delete tx key on failure? */
7e86c104 636 return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
6ace2891
JM
637}
638
7e86c104 639static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
6ace2891
JM
640{
641 int i;
642
7e86c104
LR
643 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
644 if (test_bit(i, common->keymap) ||
645 test_bit(i + 64, common->keymap))
6ace2891 646 continue; /* At least one part of TKIP key allocated */
7e86c104
LR
647 if (common->splitmic &&
648 (test_bit(i + 32, common->keymap) ||
649 test_bit(i + 64 + 32, common->keymap)))
6ace2891
JM
650 continue; /* At least one part of TKIP key allocated */
651
652 /* Found a free slot for a TKIP key */
653 return i;
654 }
655 return -1;
656}
657
7e86c104 658static int ath_reserve_key_cache_slot(struct ath_common *common)
6ace2891
JM
659{
660 int i;
661
662 /* First, try to find slots that would not be available for TKIP. */
7e86c104
LR
663 if (common->splitmic) {
664 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
665 if (!test_bit(i, common->keymap) &&
666 (test_bit(i + 32, common->keymap) ||
667 test_bit(i + 64, common->keymap) ||
668 test_bit(i + 64 + 32, common->keymap)))
6ace2891 669 return i;
7e86c104
LR
670 if (!test_bit(i + 32, common->keymap) &&
671 (test_bit(i, common->keymap) ||
672 test_bit(i + 64, common->keymap) ||
673 test_bit(i + 64 + 32, common->keymap)))
6ace2891 674 return i + 32;
7e86c104
LR
675 if (!test_bit(i + 64, common->keymap) &&
676 (test_bit(i , common->keymap) ||
677 test_bit(i + 32, common->keymap) ||
678 test_bit(i + 64 + 32, common->keymap)))
ea612132 679 return i + 64;
7e86c104
LR
680 if (!test_bit(i + 64 + 32, common->keymap) &&
681 (test_bit(i, common->keymap) ||
682 test_bit(i + 32, common->keymap) ||
683 test_bit(i + 64, common->keymap)))
ea612132 684 return i + 64 + 32;
6ace2891
JM
685 }
686 } else {
7e86c104
LR
687 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
688 if (!test_bit(i, common->keymap) &&
689 test_bit(i + 64, common->keymap))
6ace2891 690 return i;
7e86c104
LR
691 if (test_bit(i, common->keymap) &&
692 !test_bit(i + 64, common->keymap))
6ace2891
JM
693 return i + 64;
694 }
695 }
696
697 /* No partially used TKIP slots, pick any available slot */
7e86c104 698 for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
be2864cf
JM
699 /* Do not allow slots that could be needed for TKIP group keys
700 * to be used. This limitation could be removed if we know that
701 * TKIP will not be used. */
702 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
703 continue;
7e86c104 704 if (common->splitmic) {
be2864cf
JM
705 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
706 continue;
707 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
708 continue;
709 }
710
7e86c104 711 if (!test_bit(i, common->keymap))
6ace2891
JM
712 return i; /* Found a free slot for a key */
713 }
714
715 /* No free slot found */
716 return -1;
f078f209
LR
717}
718
7e86c104 719static int ath_key_config(struct ath_common *common,
3f53dd64 720 struct ieee80211_vif *vif,
dc822b5d 721 struct ieee80211_sta *sta,
f078f209
LR
722 struct ieee80211_key_conf *key)
723{
7e86c104 724 struct ath_hw *ah = common->ah;
f078f209
LR
725 struct ath9k_keyval hk;
726 const u8 *mac = NULL;
727 int ret = 0;
6ace2891 728 int idx;
f078f209
LR
729
730 memset(&hk, 0, sizeof(hk));
731
732 switch (key->alg) {
733 case ALG_WEP:
734 hk.kv_type = ATH9K_CIPHER_WEP;
735 break;
736 case ALG_TKIP:
737 hk.kv_type = ATH9K_CIPHER_TKIP;
738 break;
739 case ALG_CCMP:
740 hk.kv_type = ATH9K_CIPHER_AES_CCM;
741 break;
742 default:
ca470b29 743 return -EOPNOTSUPP;
f078f209
LR
744 }
745
6ace2891 746 hk.kv_len = key->keylen;
f078f209
LR
747 memcpy(hk.kv_val, key->key, key->keylen);
748
6ace2891
JM
749 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
750 /* For now, use the default keys for broadcast keys. This may
751 * need to change with virtual interfaces. */
752 idx = key->keyidx;
753 } else if (key->keyidx) {
dc822b5d
JB
754 if (WARN_ON(!sta))
755 return -EOPNOTSUPP;
756 mac = sta->addr;
757
6ace2891
JM
758 if (vif->type != NL80211_IFTYPE_AP) {
759 /* Only keyidx 0 should be used with unicast key, but
760 * allow this for client mode for now. */
761 idx = key->keyidx;
762 } else
763 return -EIO;
f078f209 764 } else {
dc822b5d
JB
765 if (WARN_ON(!sta))
766 return -EOPNOTSUPP;
767 mac = sta->addr;
768
6ace2891 769 if (key->alg == ALG_TKIP)
7e86c104 770 idx = ath_reserve_key_cache_slot_tkip(common);
6ace2891 771 else
7e86c104 772 idx = ath_reserve_key_cache_slot(common);
6ace2891 773 if (idx < 0)
ca470b29 774 return -ENOSPC; /* no free key cache entries */
f078f209
LR
775 }
776
777 if (key->alg == ALG_TKIP)
7e86c104 778 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
3f53dd64 779 vif->type == NL80211_IFTYPE_AP);
f078f209 780 else
7e86c104 781 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
f078f209
LR
782
783 if (!ret)
784 return -EIO;
785
7e86c104 786 set_bit(idx, common->keymap);
6ace2891 787 if (key->alg == ALG_TKIP) {
7e86c104
LR
788 set_bit(idx + 64, common->keymap);
789 if (common->splitmic) {
790 set_bit(idx + 32, common->keymap);
791 set_bit(idx + 64 + 32, common->keymap);
6ace2891
JM
792 }
793 }
794
795 return idx;
f078f209
LR
796}
797
7e86c104 798static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
f078f209 799{
7e86c104
LR
800 struct ath_hw *ah = common->ah;
801
802 ath9k_hw_keyreset(ah, key->hw_key_idx);
6ace2891
JM
803 if (key->hw_key_idx < IEEE80211_WEP_NKID)
804 return;
805
7e86c104 806 clear_bit(key->hw_key_idx, common->keymap);
6ace2891
JM
807 if (key->alg != ALG_TKIP)
808 return;
f078f209 809
7e86c104
LR
810 clear_bit(key->hw_key_idx + 64, common->keymap);
811 if (common->splitmic) {
812 clear_bit(key->hw_key_idx + 32, common->keymap);
813 clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
6ace2891 814 }
f078f209
LR
815}
816
8feceb67 817static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 818 struct ieee80211_vif *vif,
8feceb67 819 struct ieee80211_bss_conf *bss_conf)
f078f209 820{
f2b2143e 821 struct ath_hw *ah = sc->sc_ah;
1510718d 822 struct ath_common *common = ath9k_hw_common(ah);
f078f209 823
8feceb67 824 if (bss_conf->assoc) {
c46917bb
LR
825 ath_print(common, ATH_DBG_CONFIG,
826 "Bss Info ASSOC %d, bssid: %pM\n",
827 bss_conf->aid, common->curbssid);
f078f209 828
8feceb67 829 /* New association, store aid */
1510718d 830 common->curaid = bss_conf->aid;
f2b2143e 831 ath9k_hw_write_associd(ah);
2664f201
SB
832
833 /*
834 * Request a re-configuration of Beacon related timers
835 * on the receipt of the first Beacon frame (i.e.,
836 * after time sync with the AP).
837 */
1b04b930 838 sc->ps_flags |= PS_BEACON_SYNC;
f078f209 839
8feceb67 840 /* Configure the beacon */
2c3db3d5 841 ath_beacon_config(sc, vif);
f078f209 842
8feceb67 843 /* Reset rssi stats */
22e66a4c 844 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 845
3d536acf 846 ath_start_ani(common);
8feceb67 847 } else {
c46917bb 848 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 849 common->curaid = 0;
f38faa31 850 /* Stop ANI */
3d536acf 851 del_timer_sync(&common->ani.timer);
f078f209 852 }
8feceb67 853}
f078f209 854
68a89116 855void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 856{
cbe61d8a 857 struct ath_hw *ah = sc->sc_ah;
c46917bb 858 struct ath_common *common = ath9k_hw_common(ah);
68a89116 859 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 860 int r;
500c064d 861
3cbb5dd7 862 ath9k_ps_wakeup(sc);
93b1b37f 863 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 864
159cd468
VT
865 if (!ah->curchan)
866 ah->curchan = ath_get_curchannel(sc, sc->hw);
867
d2f5b3a6 868 spin_lock_bh(&sc->sc_resetlock);
2660b81a 869 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 870 if (r) {
c46917bb 871 ath_print(common, ATH_DBG_FATAL,
f643e51d 872 "Unable to reset channel (%u MHz), "
c46917bb
LR
873 "reset status %d\n",
874 channel->center_freq, r);
500c064d
VT
875 }
876 spin_unlock_bh(&sc->sc_resetlock);
877
878 ath_update_txpow(sc);
879 if (ath_startrecv(sc) != 0) {
c46917bb
LR
880 ath_print(common, ATH_DBG_FATAL,
881 "Unable to restart recv logic\n");
500c064d
VT
882 return;
883 }
884
885 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 886 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT
887
888 /* Re-Enable interrupts */
17d7904d 889 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT
890
891 /* Enable LED */
08fc5c1b 892 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 893 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 894 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 895
68a89116 896 ieee80211_wake_queues(hw);
3cbb5dd7 897 ath9k_ps_restore(sc);
500c064d
VT
898}
899
68a89116 900void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 901{
cbe61d8a 902 struct ath_hw *ah = sc->sc_ah;
68a89116 903 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 904 int r;
500c064d 905
3cbb5dd7 906 ath9k_ps_wakeup(sc);
68a89116 907 ieee80211_stop_queues(hw);
500c064d
VT
908
909 /* Disable LED */
08fc5c1b
VN
910 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
911 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT
912
913 /* Disable interrupts */
914 ath9k_hw_set_interrupts(ah, 0);
915
043a0405 916 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT
917 ath_stoprecv(sc); /* turn off frame recv */
918 ath_flushrecv(sc); /* flush recv queue */
919
159cd468 920 if (!ah->curchan)
68a89116 921 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 922
500c064d 923 spin_lock_bh(&sc->sc_resetlock);
2660b81a 924 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 925 if (r) {
c46917bb 926 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
f643e51d 927 "Unable to reset channel (%u MHz), "
c46917bb
LR
928 "reset status %d\n",
929 channel->center_freq, r);
500c064d
VT
930 }
931 spin_unlock_bh(&sc->sc_resetlock);
932
933 ath9k_hw_phy_disable(ah);
93b1b37f 934 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 935 ath9k_ps_restore(sc);
9ecdef4b 936 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT
937}
938
ff37e337
S
939int ath_reset(struct ath_softc *sc, bool retry_tx)
940{
cbe61d8a 941 struct ath_hw *ah = sc->sc_ah;
c46917bb 942 struct ath_common *common = ath9k_hw_common(ah);
030bb495 943 struct ieee80211_hw *hw = sc->hw;
ae8d2858 944 int r;
ff37e337 945
2ab81d4a
S
946 /* Stop ANI */
947 del_timer_sync(&common->ani.timer);
948
cc9c378a
S
949 ieee80211_stop_queues(hw);
950
ff37e337 951 ath9k_hw_set_interrupts(ah, 0);
043a0405 952 ath_drain_all_txq(sc, retry_tx);
ff37e337
S
953 ath_stoprecv(sc);
954 ath_flushrecv(sc);
955
956 spin_lock_bh(&sc->sc_resetlock);
2660b81a 957 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 958 if (r)
c46917bb
LR
959 ath_print(common, ATH_DBG_FATAL,
960 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
961 spin_unlock_bh(&sc->sc_resetlock);
962
963 if (ath_startrecv(sc) != 0)
c46917bb
LR
964 ath_print(common, ATH_DBG_FATAL,
965 "Unable to start recv logic\n");
ff37e337
S
966
967 /*
968 * We may be doing a reset in response to a request
969 * that changes the channel so update any state that
970 * might change as a result.
971 */
ce111bad 972 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
973
974 ath_update_txpow(sc);
975
976 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 977 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 978
17d7904d 979 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S
980
981 if (retry_tx) {
982 int i;
983 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
984 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
985 spin_lock_bh(&sc->tx.txq[i].axq_lock);
986 ath_txq_schedule(sc, &sc->tx.txq[i]);
987 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
988 }
989 }
990 }
991
cc9c378a
S
992 ieee80211_wake_queues(hw);
993
2ab81d4a
S
994 /* Start ANI */
995 ath_start_ani(common);
996
ae8d2858 997 return r;
ff37e337
S
998}
999
ff37e337
S
1000int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1001{
1002 int qnum;
1003
1004 switch (queue) {
1005 case 0:
b77f483f 1006 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S
1007 break;
1008 case 1:
b77f483f 1009 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S
1010 break;
1011 case 2:
b77f483f 1012 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S
1013 break;
1014 case 3:
b77f483f 1015 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S
1016 break;
1017 default:
b77f483f 1018 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S
1019 break;
1020 }
1021
1022 return qnum;
1023}
1024
1025int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1026{
1027 int qnum;
1028
1029 switch (queue) {
1030 case ATH9K_WME_AC_VO:
1031 qnum = 0;
1032 break;
1033 case ATH9K_WME_AC_VI:
1034 qnum = 1;
1035 break;
1036 case ATH9K_WME_AC_BE:
1037 qnum = 2;
1038 break;
1039 case ATH9K_WME_AC_BK:
1040 qnum = 3;
1041 break;
1042 default:
1043 qnum = -1;
1044 break;
1045 }
1046
1047 return qnum;
1048}
1049
5f8e077c
LR
1050/* XXX: Remove me once we don't depend on ath9k_channel for all
1051 * this redundant data */
0e2dedf9
JM
1052void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1053 struct ath9k_channel *ichan)
5f8e077c 1054{
5f8e077c
LR
1055 struct ieee80211_channel *chan = hw->conf.channel;
1056 struct ieee80211_conf *conf = &hw->conf;
1057
1058 ichan->channel = chan->center_freq;
1059 ichan->chan = chan;
1060
1061 if (chan->band == IEEE80211_BAND_2GHZ) {
1062 ichan->chanmode = CHANNEL_G;
8813262e 1063 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR
1064 } else {
1065 ichan->chanmode = CHANNEL_A;
1066 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1067 }
1068
25c56eec 1069 if (conf_is_ht(conf))
5f8e077c
LR
1070 ichan->chanmode = ath_get_extchanmode(sc, chan,
1071 conf->channel_type);
5f8e077c
LR
1072}
1073
ff37e337
S
1074/**********************/
1075/* mac80211 callbacks */
1076/**********************/
1077
8feceb67 1078static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1079{
bce048d7
JM
1080 struct ath_wiphy *aphy = hw->priv;
1081 struct ath_softc *sc = aphy->sc;
af03abec 1082 struct ath_hw *ah = sc->sc_ah;
c46917bb 1083 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1084 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1085 struct ath9k_channel *init_channel;
82880a7c 1086 int r;
f078f209 1087
c46917bb
LR
1088 ath_print(common, ATH_DBG_CONFIG,
1089 "Starting driver with initial channel: %d MHz\n",
1090 curchan->center_freq);
f078f209 1091
141b38b6
S
1092 mutex_lock(&sc->mutex);
1093
9580a222
JM
1094 if (ath9k_wiphy_started(sc)) {
1095 if (sc->chan_idx == curchan->hw_value) {
1096 /*
1097 * Already on the operational channel, the new wiphy
1098 * can be marked active.
1099 */
1100 aphy->state = ATH_WIPHY_ACTIVE;
1101 ieee80211_wake_queues(hw);
1102 } else {
1103 /*
1104 * Another wiphy is on another channel, start the new
1105 * wiphy in paused state.
1106 */
1107 aphy->state = ATH_WIPHY_PAUSED;
1108 ieee80211_stop_queues(hw);
1109 }
1110 mutex_unlock(&sc->mutex);
1111 return 0;
1112 }
1113 aphy->state = ATH_WIPHY_ACTIVE;
1114
8feceb67 1115 /* setup initial channel */
f078f209 1116
82880a7c 1117 sc->chan_idx = curchan->hw_value;
f078f209 1118
82880a7c 1119 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S
1120
1121 /* Reset SERDES registers */
af03abec 1122 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S
1123
1124 /*
1125 * The basic interface to setting the hardware in a good
1126 * state is ``reset''. On return the hardware is known to
1127 * be powered up and with interrupts disabled. This must
1128 * be followed by initialization of the appropriate bits
1129 * and then setup of the interrupt mask.
1130 */
1131 spin_lock_bh(&sc->sc_resetlock);
af03abec 1132 r = ath9k_hw_reset(ah, init_channel, false);
ae8d2858 1133 if (r) {
c46917bb
LR
1134 ath_print(common, ATH_DBG_FATAL,
1135 "Unable to reset hardware; reset status %d "
1136 "(freq %u MHz)\n", r,
1137 curchan->center_freq);
ff37e337 1138 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1139 goto mutex_unlock;
ff37e337
S
1140 }
1141 spin_unlock_bh(&sc->sc_resetlock);
1142
1143 /*
1144 * This is needed only to setup initial state
1145 * but it's best done after a reset.
1146 */
1147 ath_update_txpow(sc);
8feceb67 1148
ff37e337
S
1149 /*
1150 * Setup the hardware after reset:
1151 * The receive engine is set going.
1152 * Frame transmit is handled entirely
1153 * in the frame output path; there's nothing to do
1154 * here except setup the interrupt mask.
1155 */
1156 if (ath_startrecv(sc) != 0) {
c46917bb
LR
1157 ath_print(common, ATH_DBG_FATAL,
1158 "Unable to start recv logic\n");
141b38b6
S
1159 r = -EIO;
1160 goto mutex_unlock;
f078f209 1161 }
8feceb67 1162
ff37e337 1163 /* Setup our intr mask. */
17d7904d 1164 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S
1165 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1166 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1167
af03abec 1168 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 1169 sc->imask |= ATH9K_INT_GTT;
ff37e337 1170
af03abec 1171 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 1172 sc->imask |= ATH9K_INT_CST;
ff37e337 1173
ce111bad 1174 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
1175
1176 sc->sc_flags &= ~SC_OP_INVALID;
1177
1178 /* Disable BMISS interrupt when we're not associated */
17d7904d 1179 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
af03abec 1180 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337 1181
bce048d7 1182 ieee80211_wake_queues(hw);
ff37e337 1183
42935eca 1184 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1185
766ec4a9
LR
1186 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1187 !ah->btcoex_hw.enabled) {
5e197292
LR
1188 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1189 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1190 ath9k_hw_btcoex_enable(ah);
f985ad12 1191
5bb12791
LR
1192 if (common->bus_ops->bt_coex_prep)
1193 common->bus_ops->bt_coex_prep(common);
766ec4a9 1194 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1195 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1196 }
1197
141b38b6
S
1198mutex_unlock:
1199 mutex_unlock(&sc->mutex);
1200
ae8d2858 1201 return r;
f078f209
LR
1202}
1203
8feceb67
VT
1204static int ath9k_tx(struct ieee80211_hw *hw,
1205 struct sk_buff *skb)
f078f209 1206{
528f0c6b 1207 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM
1208 struct ath_wiphy *aphy = hw->priv;
1209 struct ath_softc *sc = aphy->sc;
c46917bb 1210 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1211 struct ath_tx_control txctl;
1bc14880
BP
1212 int padpos, padsize;
1213 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1214
8089cc47 1215 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
c46917bb
LR
1216 ath_print(common, ATH_DBG_XMIT,
1217 "ath9k: %s: TX in unexpected wiphy state "
1218 "%d\n", wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM
1219 goto exit;
1220 }
1221
96148326 1222 if (sc->ps_enabled) {
dc8c4585
JM
1223 /*
1224 * mac80211 does not set PM field for normal data frames, so we
1225 * need to update that based on the current PS mode.
1226 */
1227 if (ieee80211_is_data(hdr->frame_control) &&
1228 !ieee80211_is_nullfunc(hdr->frame_control) &&
1229 !ieee80211_has_pm(hdr->frame_control)) {
c46917bb
LR
1230 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
1231 "while in PS mode\n");
dc8c4585
JM
1232 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1233 }
1234 }
1235
9a23f9ca
JM
1236 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1237 /*
1238 * We are using PS-Poll and mac80211 can request TX while in
1239 * power save mode. Need to wake up hardware for the TX to be
1240 * completed and if needed, also for RX of buffered frames.
1241 */
9a23f9ca
JM
1242 ath9k_ps_wakeup(sc);
1243 ath9k_hw_setrxabort(sc->sc_ah, 0);
1244 if (ieee80211_is_pspoll(hdr->frame_control)) {
c46917bb
LR
1245 ath_print(common, ATH_DBG_PS,
1246 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1247 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1248 } else {
c46917bb
LR
1249 ath_print(common, ATH_DBG_PS,
1250 "Wake up to complete TX\n");
1b04b930 1251 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1252 }
1253 /*
1254 * The actual restore operation will happen only after
1255 * the sc_flags bit is cleared. We are just dropping
1256 * the ps_usecount here.
1257 */
1258 ath9k_ps_restore(sc);
1259 }
1260
528f0c6b 1261 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1262
8feceb67
VT
1263 /*
1264 * As a temporary workaround, assign seq# here; this will likely need
1265 * to be cleaned up to work better with Beacon transmission and virtual
1266 * BSSes.
1267 */
1268 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
8feceb67 1269 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1270 sc->tx.seq_no += 0x10;
8feceb67 1271 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1272 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1273 }
f078f209 1274
8feceb67 1275 /* Add the padding after the header if this is not already done */
1bc14880
BP
1276 padpos = ath9k_cmn_padpos(hdr->frame_control);
1277 padsize = padpos & 3;
1278 if (padsize && skb->len>padpos) {
8feceb67
VT
1279 if (skb_headroom(skb) < padsize)
1280 return -1;
1281 skb_push(skb, padsize);
1bc14880 1282 memmove(skb->data, skb->data + padsize, padpos);
8feceb67
VT
1283 }
1284
528f0c6b
S
1285 /* Check if a tx queue is available */
1286
1287 txctl.txq = ath_test_get_txq(sc, skb);
1288 if (!txctl.txq)
1289 goto exit;
1290
c46917bb 1291 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1292
c52f33d0 1293 if (ath_tx_start(hw, skb, &txctl) != 0) {
c46917bb 1294 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1295 goto exit;
8feceb67
VT
1296 }
1297
528f0c6b
S
1298 return 0;
1299exit:
1300 dev_kfree_skb_any(skb);
8feceb67 1301 return 0;
f078f209
LR
1302}
1303
8feceb67 1304static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1305{
bce048d7
JM
1306 struct ath_wiphy *aphy = hw->priv;
1307 struct ath_softc *sc = aphy->sc;
af03abec 1308 struct ath_hw *ah = sc->sc_ah;
c46917bb 1309 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1310
4c483817
S
1311 mutex_lock(&sc->mutex);
1312
9580a222
JM
1313 aphy->state = ATH_WIPHY_INACTIVE;
1314
c94dbff7
LR
1315 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1316 cancel_delayed_work_sync(&sc->tx_complete_work);
1317
1318 if (!sc->num_sec_wiphy) {
1319 cancel_delayed_work_sync(&sc->wiphy_work);
1320 cancel_work_sync(&sc->chan_work);
1321 }
1322
9c84b797 1323 if (sc->sc_flags & SC_OP_INVALID) {
c46917bb 1324 ath_print(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1325 mutex_unlock(&sc->mutex);
9c84b797
S
1326 return;
1327 }
8feceb67 1328
9580a222
JM
1329 if (ath9k_wiphy_started(sc)) {
1330 mutex_unlock(&sc->mutex);
1331 return; /* another wiphy still in use */
1332 }
1333
3867cf6a
S
1334 /* Ensure HW is awake when we try to shut it down. */
1335 ath9k_ps_wakeup(sc);
1336
766ec4a9 1337 if (ah->btcoex_hw.enabled) {
af03abec 1338 ath9k_hw_btcoex_disable(ah);
766ec4a9 1339 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1340 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1341 }
1342
ff37e337
S
1343 /* make sure h/w will not generate any interrupt
1344 * before setting the invalid flag. */
af03abec 1345 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S
1346
1347 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1348 ath_drain_all_txq(sc, false);
ff37e337 1349 ath_stoprecv(sc);
af03abec 1350 ath9k_hw_phy_disable(ah);
ff37e337 1351 } else
b77f483f 1352 sc->rx.rxlink = NULL;
ff37e337 1353
ff37e337 1354 /* disable HAL and put h/w to sleep */
af03abec
LR
1355 ath9k_hw_disable(ah);
1356 ath9k_hw_configpcipowersave(ah, 1, 1);
3867cf6a
S
1357 ath9k_ps_restore(sc);
1358
1359 /* Finally, put the chip in FULL SLEEP mode */
9ecdef4b 1360 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S
1361
1362 sc->sc_flags |= SC_OP_INVALID;
500c064d 1363
141b38b6
S
1364 mutex_unlock(&sc->mutex);
1365
c46917bb 1366 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1367}
1368
8feceb67 1369static int ath9k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 1370 struct ieee80211_vif *vif)
f078f209 1371{
bce048d7
JM
1372 struct ath_wiphy *aphy = hw->priv;
1373 struct ath_softc *sc = aphy->sc;
c46917bb 1374 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1ed32e4f 1375 struct ath_vif *avp = (void *)vif->drv_priv;
d97809db 1376 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 1377 int ret = 0;
8feceb67 1378
141b38b6
S
1379 mutex_lock(&sc->mutex);
1380
8ca21f01
JM
1381 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
1382 sc->nvifs > 0) {
1383 ret = -ENOBUFS;
1384 goto out;
1385 }
1386
1ed32e4f 1387 switch (vif->type) {
05c914fe 1388 case NL80211_IFTYPE_STATION:
d97809db 1389 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 1390 break;
05c914fe 1391 case NL80211_IFTYPE_ADHOC:
05c914fe 1392 case NL80211_IFTYPE_AP:
9cb5412b 1393 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM
1394 if (sc->nbcnvifs >= ATH_BCBUF) {
1395 ret = -ENOBUFS;
1396 goto out;
1397 }
1ed32e4f 1398 ic_opmode = vif->type;
f078f209
LR
1399 break;
1400 default:
c46917bb 1401 ath_print(common, ATH_DBG_FATAL,
1ed32e4f 1402 "Interface type %d not yet supported\n", vif->type);
2c3db3d5
JM
1403 ret = -EOPNOTSUPP;
1404 goto out;
f078f209
LR
1405 }
1406
c46917bb
LR
1407 ath_print(common, ATH_DBG_CONFIG,
1408 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 1409
17d7904d 1410 /* Set the VIF opmode */
5640b08e
S
1411 avp->av_opmode = ic_opmode;
1412 avp->av_bslot = -1;
1413
2c3db3d5 1414 sc->nvifs++;
8ca21f01
JM
1415
1416 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1417 ath9k_set_bssid_mask(hw);
1418
2c3db3d5
JM
1419 if (sc->nvifs > 1)
1420 goto out; /* skip global settings for secondary vif */
1421
b238e90e 1422 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 1423 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S
1424 sc->sc_flags |= SC_OP_TSF_RESET;
1425 }
5640b08e 1426
5640b08e 1427 /* Set the device opmode */
2660b81a 1428 sc->sc_ah->opmode = ic_opmode;
5640b08e 1429
4e30ffa2
VN
1430 /*
1431 * Enable MIB interrupts when there are hardware phy counters.
1432 * Note we only do this (at the moment) for station mode.
1433 */
1ed32e4f
JB
1434 if ((vif->type == NL80211_IFTYPE_STATION) ||
1435 (vif->type == NL80211_IFTYPE_ADHOC) ||
1436 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 1437 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S
1438 sc->imask |= ATH9K_INT_TSFOOR;
1439 }
1440
17d7904d 1441 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 1442
1ed32e4f
JB
1443 if (vif->type == NL80211_IFTYPE_AP ||
1444 vif->type == NL80211_IFTYPE_ADHOC ||
1445 vif->type == NL80211_IFTYPE_MONITOR)
3d536acf 1446 ath_start_ani(common);
6f255425 1447
2c3db3d5 1448out:
141b38b6 1449 mutex_unlock(&sc->mutex);
2c3db3d5 1450 return ret;
f078f209
LR
1451}
1452
8feceb67 1453static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1454 struct ieee80211_vif *vif)
f078f209 1455{
bce048d7
JM
1456 struct ath_wiphy *aphy = hw->priv;
1457 struct ath_softc *sc = aphy->sc;
c46917bb 1458 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1ed32e4f 1459 struct ath_vif *avp = (void *)vif->drv_priv;
2c3db3d5 1460 int i;
f078f209 1461
c46917bb 1462 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1463
141b38b6
S
1464 mutex_lock(&sc->mutex);
1465
6f255425 1466 /* Stop ANI */
3d536acf 1467 del_timer_sync(&common->ani.timer);
580f0b8a 1468
8feceb67 1469 /* Reclaim beacon resources */
9cb5412b
PE
1470 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
1471 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
1472 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
5f70a88f 1473 ath9k_ps_wakeup(sc);
b77f483f 1474 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 1475 ath_beacon_return(sc, avp);
5f70a88f 1476 ath9k_ps_restore(sc);
580f0b8a 1477 }
f078f209 1478
8feceb67 1479 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 1480
2c3db3d5 1481 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1ed32e4f 1482 if (sc->beacon.bslot[i] == vif) {
2c3db3d5
JM
1483 printk(KERN_DEBUG "%s: vif had allocated beacon "
1484 "slot\n", __func__);
1485 sc->beacon.bslot[i] = NULL;
c52f33d0 1486 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM
1487 }
1488 }
1489
17d7904d 1490 sc->nvifs--;
141b38b6
S
1491
1492 mutex_unlock(&sc->mutex);
f078f209
LR
1493}
1494
e8975581 1495static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1496{
bce048d7
JM
1497 struct ath_wiphy *aphy = hw->priv;
1498 struct ath_softc *sc = aphy->sc;
c46917bb 1499 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8975581 1500 struct ieee80211_conf *conf = &hw->conf;
8782b41d 1501 struct ath_hw *ah = sc->sc_ah;
194b7c13 1502 bool disable_radio;
f078f209 1503
aa33de09 1504 mutex_lock(&sc->mutex);
141b38b6 1505
194b7c13
LR
1506 /*
1507 * Leave this as the first check because we need to turn on the
1508 * radio if it was disabled before prior to processing the rest
1509 * of the changes. Likewise we must only disable the radio towards
1510 * the end.
1511 */
64839170 1512 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR
1513 bool enable_radio;
1514 bool all_wiphys_idle;
1515 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR
1516
1517 spin_lock_bh(&sc->wiphy_lock);
1518 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR
1519 ath9k_set_wiphy_idle(aphy, idle);
1520
1521 if (!idle && all_wiphys_idle)
1522 enable_radio = true;
1523
1524 /*
1525 * After we unlock here its possible another wiphy
1526 * can be re-renabled so to account for that we will
1527 * only disable the radio toward the end of this routine
1528 * if by then all wiphys are still idle.
1529 */
64839170
LR
1530 spin_unlock_bh(&sc->wiphy_lock);
1531
194b7c13 1532 if (enable_radio) {
1dbfd9d4 1533 sc->ps_idle = false;
68a89116 1534 ath_radio_enable(sc, hw);
c46917bb
LR
1535 ath_print(common, ATH_DBG_CONFIG,
1536 "not-idle: enabling radio\n");
64839170
LR
1537 }
1538 }
1539
e7824a50
LR
1540 /*
1541 * We just prepare to enable PS. We have to wait until our AP has
1542 * ACK'd our null data frame to disable RX otherwise we'll ignore
1543 * those ACKs and end up retransmitting the same null data frames.
1544 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1545 */
3cbb5dd7
VN
1546 if (changed & IEEE80211_CONF_CHANGE_PS) {
1547 if (conf->flags & IEEE80211_CONF_PS) {
1b04b930 1548 sc->ps_flags |= PS_ENABLED;
8782b41d
VN
1549 if (!(ah->caps.hw_caps &
1550 ATH9K_HW_CAP_AUTOSLEEP)) {
1551 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
1552 sc->imask |= ATH9K_INT_TIM_TIMER;
1553 ath9k_hw_set_interrupts(sc->sc_ah,
1554 sc->imask);
1555 }
3cbb5dd7 1556 }
e7824a50
LR
1557 /*
1558 * At this point we know hardware has received an ACK
1559 * of a previously sent null data frame.
1560 */
1b04b930
S
1561 if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
1562 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
e7824a50
LR
1563 sc->ps_enabled = true;
1564 ath9k_hw_setrxabort(sc->sc_ah, 1);
1565 }
3cbb5dd7 1566 } else {
96148326 1567 sc->ps_enabled = false;
1b04b930
S
1568 sc->ps_flags &= ~(PS_ENABLED |
1569 PS_NULLFUNC_COMPLETED);
9ecdef4b 1570 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8782b41d
VN
1571 if (!(ah->caps.hw_caps &
1572 ATH9K_HW_CAP_AUTOSLEEP)) {
1573 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930
S
1574 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1575 PS_WAIT_FOR_CAB |
1576 PS_WAIT_FOR_PSPOLL_DATA |
1577 PS_WAIT_FOR_TX_ACK);
8782b41d
VN
1578 if (sc->imask & ATH9K_INT_TIM_TIMER) {
1579 sc->imask &= ~ATH9K_INT_TIM_TIMER;
1580 ath9k_hw_set_interrupts(sc->sc_ah,
1581 sc->imask);
1582 }
3cbb5dd7
VN
1583 }
1584 }
1585 }
1586
199afd9d
S
1587 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1588 if (conf->flags & IEEE80211_CONF_MONITOR) {
1589 ath_print(common, ATH_DBG_CONFIG,
1590 "HW opmode set to Monitor mode\n");
1591 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1592 }
1593 }
1594
4797938c 1595 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1596 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1597 int pos = curchan->hw_value;
ae5eb026 1598
0e2dedf9
JM
1599 aphy->chan_idx = pos;
1600 aphy->chan_is_ht = conf_is_ht(conf);
1601
8089cc47
JM
1602 if (aphy->state == ATH_WIPHY_SCAN ||
1603 aphy->state == ATH_WIPHY_ACTIVE)
1604 ath9k_wiphy_pause_all_forced(sc, aphy);
1605 else {
1606 /*
1607 * Do not change operational channel based on a paused
1608 * wiphy changes.
1609 */
1610 goto skip_chan_change;
1611 }
0e2dedf9 1612
c46917bb
LR
1613 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1614 curchan->center_freq);
f078f209 1615
5f8e077c 1616 /* XXX: remove me eventualy */
0e2dedf9 1617 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 1618
ecf70441 1619 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 1620
0e2dedf9 1621 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
c46917bb
LR
1622 ath_print(common, ATH_DBG_FATAL,
1623 "Unable to set channel\n");
aa33de09 1624 mutex_unlock(&sc->mutex);
e11602b7
S
1625 return -EINVAL;
1626 }
094d05dc 1627 }
f078f209 1628
8089cc47 1629skip_chan_change:
c9f6a656 1630 if (changed & IEEE80211_CONF_CHANGE_POWER) {
17d7904d 1631 sc->config.txpowlimit = 2 * conf->power_level;
c9f6a656
LR
1632 ath_update_txpow(sc);
1633 }
f078f209 1634
194b7c13
LR
1635 spin_lock_bh(&sc->wiphy_lock);
1636 disable_radio = ath9k_all_wiphys_idle(sc);
1637 spin_unlock_bh(&sc->wiphy_lock);
1638
64839170 1639 if (disable_radio) {
c46917bb 1640 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1dbfd9d4 1641 sc->ps_idle = true;
68a89116 1642 ath_radio_disable(sc, hw);
64839170
LR
1643 }
1644
aa33de09 1645 mutex_unlock(&sc->mutex);
141b38b6 1646
f078f209
LR
1647 return 0;
1648}
1649
8feceb67
VT
1650#define SUPPORTED_FILTERS \
1651 (FIF_PROMISC_IN_BSS | \
1652 FIF_ALLMULTI | \
1653 FIF_CONTROL | \
af6a3fc7 1654 FIF_PSPOLL | \
8feceb67
VT
1655 FIF_OTHER_BSS | \
1656 FIF_BCN_PRBRESP_PROMISC | \
1657 FIF_FCSFAIL)
c83be688 1658
8feceb67
VT
1659/* FIXME: sc->sc_full_reset ? */
1660static void ath9k_configure_filter(struct ieee80211_hw *hw,
1661 unsigned int changed_flags,
1662 unsigned int *total_flags,
3ac64bee 1663 u64 multicast)
8feceb67 1664{
bce048d7
JM
1665 struct ath_wiphy *aphy = hw->priv;
1666 struct ath_softc *sc = aphy->sc;
8feceb67 1667 u32 rfilt;
f078f209 1668
8feceb67
VT
1669 changed_flags &= SUPPORTED_FILTERS;
1670 *total_flags &= SUPPORTED_FILTERS;
f078f209 1671
b77f483f 1672 sc->rx.rxfilter = *total_flags;
aa68aeaa 1673 ath9k_ps_wakeup(sc);
8feceb67
VT
1674 rfilt = ath_calcrxfilter(sc);
1675 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1676 ath9k_ps_restore(sc);
f078f209 1677
c46917bb
LR
1678 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1679 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1680}
f078f209 1681
8feceb67
VT
1682static void ath9k_sta_notify(struct ieee80211_hw *hw,
1683 struct ieee80211_vif *vif,
1684 enum sta_notify_cmd cmd,
17741cdc 1685 struct ieee80211_sta *sta)
8feceb67 1686{
bce048d7
JM
1687 struct ath_wiphy *aphy = hw->priv;
1688 struct ath_softc *sc = aphy->sc;
f078f209 1689
8feceb67
VT
1690 switch (cmd) {
1691 case STA_NOTIFY_ADD:
5640b08e 1692 ath_node_attach(sc, sta);
8feceb67
VT
1693 break;
1694 case STA_NOTIFY_REMOVE:
b5aa9bf9 1695 ath_node_detach(sc, sta);
8feceb67
VT
1696 break;
1697 default:
1698 break;
1699 }
f078f209
LR
1700}
1701
141b38b6 1702static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1703 const struct ieee80211_tx_queue_params *params)
f078f209 1704{
bce048d7
JM
1705 struct ath_wiphy *aphy = hw->priv;
1706 struct ath_softc *sc = aphy->sc;
c46917bb 1707 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67
VT
1708 struct ath9k_tx_queue_info qi;
1709 int ret = 0, qnum;
f078f209 1710
8feceb67
VT
1711 if (queue >= WME_NUM_AC)
1712 return 0;
f078f209 1713
141b38b6
S
1714 mutex_lock(&sc->mutex);
1715
1ffb0610
S
1716 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1717
8feceb67
VT
1718 qi.tqi_aifs = params->aifs;
1719 qi.tqi_cwmin = params->cw_min;
1720 qi.tqi_cwmax = params->cw_max;
1721 qi.tqi_burstTime = params->txop;
1722 qnum = ath_get_hal_qnum(queue, sc);
f078f209 1723
c46917bb
LR
1724 ath_print(common, ATH_DBG_CONFIG,
1725 "Configure tx [queue/halq] [%d/%d], "
1726 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1727 queue, qnum, params->aifs, params->cw_min,
1728 params->cw_max, params->txop);
f078f209 1729
8feceb67
VT
1730 ret = ath_txq_update(sc, qnum, &qi);
1731 if (ret)
c46917bb 1732 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 1733
94db2936
VN
1734 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1735 if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
1736 ath_beaconq_config(sc);
1737
141b38b6
S
1738 mutex_unlock(&sc->mutex);
1739
8feceb67
VT
1740 return ret;
1741}
f078f209 1742
8feceb67
VT
1743static int ath9k_set_key(struct ieee80211_hw *hw,
1744 enum set_key_cmd cmd,
dc822b5d
JB
1745 struct ieee80211_vif *vif,
1746 struct ieee80211_sta *sta,
8feceb67
VT
1747 struct ieee80211_key_conf *key)
1748{
bce048d7
JM
1749 struct ath_wiphy *aphy = hw->priv;
1750 struct ath_softc *sc = aphy->sc;
c46917bb 1751 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1752 int ret = 0;
f078f209 1753
b3bd89ce
JM
1754 if (modparam_nohwcrypt)
1755 return -ENOSPC;
1756
141b38b6 1757 mutex_lock(&sc->mutex);
3cbb5dd7 1758 ath9k_ps_wakeup(sc);
c46917bb 1759 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1760
8feceb67
VT
1761 switch (cmd) {
1762 case SET_KEY:
7e86c104 1763 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1764 if (ret >= 0) {
1765 key->hw_key_idx = ret;
8feceb67
VT
1766 /* push IV and Michael MIC generation to stack */
1767 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1768 if (key->alg == ALG_TKIP)
1769 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM
1770 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
1771 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1772 ret = 0;
8feceb67
VT
1773 }
1774 break;
1775 case DISABLE_KEY:
7e86c104 1776 ath_key_delete(common, key);
8feceb67
VT
1777 break;
1778 default:
1779 ret = -EINVAL;
1780 }
f078f209 1781
3cbb5dd7 1782 ath9k_ps_restore(sc);
141b38b6
S
1783 mutex_unlock(&sc->mutex);
1784
8feceb67
VT
1785 return ret;
1786}
f078f209 1787
8feceb67
VT
1788static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1789 struct ieee80211_vif *vif,
1790 struct ieee80211_bss_conf *bss_conf,
1791 u32 changed)
1792{
bce048d7
JM
1793 struct ath_wiphy *aphy = hw->priv;
1794 struct ath_softc *sc = aphy->sc;
2d0ddec5 1795 struct ath_hw *ah = sc->sc_ah;
1510718d 1796 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1797 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1798 int slottime;
c6089ccc 1799 int error;
f078f209 1800
141b38b6
S
1801 mutex_lock(&sc->mutex);
1802
c6089ccc
S
1803 if (changed & BSS_CHANGED_BSSID) {
1804 /* Set BSSID */
1805 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1806 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 1807 common->curaid = 0;
f2b2143e 1808 ath9k_hw_write_associd(ah);
2d0ddec5 1809
c6089ccc
S
1810 /* Set aggregation protection mode parameters */
1811 sc->config.ath_aggr_prot = 0;
2d0ddec5 1812
c6089ccc
S
1813 /* Only legacy IBSS for now */
1814 if (vif->type == NL80211_IFTYPE_ADHOC)
1815 ath_update_chainmask(sc, 0);
2d0ddec5 1816
c6089ccc
S
1817 ath_print(common, ATH_DBG_CONFIG,
1818 "BSSID: %pM aid: 0x%x\n",
1819 common->curbssid, common->curaid);
2d0ddec5 1820
c6089ccc
S
1821 /* need to reconfigure the beacon */
1822 sc->sc_flags &= ~SC_OP_BEACONS ;
1823 }
2d0ddec5 1824
c6089ccc
S
1825 /* Enable transmission of beacons (AP, IBSS, MESH) */
1826 if ((changed & BSS_CHANGED_BEACON) ||
1827 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
1828 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1829 error = ath_beacon_alloc(aphy, vif);
1830 if (!error)
1831 ath_beacon_config(sc, vif);
0005baf4
FF
1832 }
1833
1834 if (changed & BSS_CHANGED_ERP_SLOT) {
1835 if (bss_conf->use_short_slot)
1836 slottime = 9;
1837 else
1838 slottime = 20;
1839 if (vif->type == NL80211_IFTYPE_AP) {
1840 /*
1841 * Defer update, so that connected stations can adjust
1842 * their settings at the same time.
1843 * See beacon.c for more details
1844 */
1845 sc->beacon.slottime = slottime;
1846 sc->beacon.updateslot = UPDATE;
1847 } else {
1848 ah->slottime = slottime;
1849 ath9k_hw_init_global_settings(ah);
1850 }
2d0ddec5
JB
1851 }
1852
c6089ccc
S
1853 /* Disable transmission of beacons */
1854 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
1855 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5 1856
c6089ccc
S
1857 if (changed & BSS_CHANGED_BEACON_INT) {
1858 sc->beacon_interval = bss_conf->beacon_int;
1859 /*
1860 * In case of AP mode, the HW TSF has to be reset
1861 * when the beacon interval changes.
1862 */
1863 if (vif->type == NL80211_IFTYPE_AP) {
1864 sc->sc_flags |= SC_OP_TSF_RESET;
1865 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5
JB
1866 error = ath_beacon_alloc(aphy, vif);
1867 if (!error)
1868 ath_beacon_config(sc, vif);
c6089ccc
S
1869 } else {
1870 ath_beacon_config(sc, vif);
2d0ddec5
JB
1871 }
1872 }
1873
8feceb67 1874 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
c46917bb
LR
1875 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1876 bss_conf->use_short_preamble);
8feceb67
VT
1877 if (bss_conf->use_short_preamble)
1878 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1879 else
1880 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1881 }
f078f209 1882
8feceb67 1883 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
c46917bb
LR
1884 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1885 bss_conf->use_cts_prot);
8feceb67
VT
1886 if (bss_conf->use_cts_prot &&
1887 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1888 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1889 else
1890 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1891 }
f078f209 1892
8feceb67 1893 if (changed & BSS_CHANGED_ASSOC) {
c46917bb 1894 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 1895 bss_conf->assoc);
5640b08e 1896 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 1897 }
141b38b6
S
1898
1899 mutex_unlock(&sc->mutex);
8feceb67 1900}
f078f209 1901
8feceb67
VT
1902static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1903{
1904 u64 tsf;
bce048d7
JM
1905 struct ath_wiphy *aphy = hw->priv;
1906 struct ath_softc *sc = aphy->sc;
f078f209 1907
141b38b6
S
1908 mutex_lock(&sc->mutex);
1909 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1910 mutex_unlock(&sc->mutex);
f078f209 1911
8feceb67
VT
1912 return tsf;
1913}
f078f209 1914
3b5d665b
AF
1915static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
1916{
bce048d7
JM
1917 struct ath_wiphy *aphy = hw->priv;
1918 struct ath_softc *sc = aphy->sc;
3b5d665b 1919
141b38b6
S
1920 mutex_lock(&sc->mutex);
1921 ath9k_hw_settsf64(sc->sc_ah, tsf);
1922 mutex_unlock(&sc->mutex);
3b5d665b
AF
1923}
1924
8feceb67
VT
1925static void ath9k_reset_tsf(struct ieee80211_hw *hw)
1926{
bce048d7
JM
1927 struct ath_wiphy *aphy = hw->priv;
1928 struct ath_softc *sc = aphy->sc;
c83be688 1929
141b38b6 1930 mutex_lock(&sc->mutex);
21526d57
LR
1931
1932 ath9k_ps_wakeup(sc);
141b38b6 1933 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
1934 ath9k_ps_restore(sc);
1935
141b38b6 1936 mutex_unlock(&sc->mutex);
8feceb67 1937}
f078f209 1938
8feceb67 1939static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1940 struct ieee80211_vif *vif,
141b38b6
S
1941 enum ieee80211_ampdu_mlme_action action,
1942 struct ieee80211_sta *sta,
1943 u16 tid, u16 *ssn)
8feceb67 1944{
bce048d7
JM
1945 struct ath_wiphy *aphy = hw->priv;
1946 struct ath_softc *sc = aphy->sc;
8feceb67 1947 int ret = 0;
f078f209 1948
8feceb67
VT
1949 switch (action) {
1950 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
1951 if (!(sc->sc_flags & SC_OP_RXAGGR))
1952 ret = -ENOTSUPP;
8feceb67
VT
1953 break;
1954 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
1955 break;
1956 case IEEE80211_AMPDU_TX_START:
8b685ba9 1957 ath9k_ps_wakeup(sc);
f83da965 1958 ath_tx_aggr_start(sc, sta, tid, ssn);
c951ad35 1959 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1960 ath9k_ps_restore(sc);
8feceb67
VT
1961 break;
1962 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 1963 ath9k_ps_wakeup(sc);
f83da965 1964 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 1965 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1966 ath9k_ps_restore(sc);
8feceb67 1967 break;
b1720231 1968 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1969 ath9k_ps_wakeup(sc);
8469cdef 1970 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1971 ath9k_ps_restore(sc);
8469cdef 1972 break;
8feceb67 1973 default:
c46917bb
LR
1974 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1975 "Unknown AMPDU action\n");
8feceb67
VT
1976 }
1977
1978 return ret;
f078f209
LR
1979}
1980
0c98de65
S
1981static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
1982{
bce048d7
JM
1983 struct ath_wiphy *aphy = hw->priv;
1984 struct ath_softc *sc = aphy->sc;
05c78d6d 1985 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0c98de65 1986
3d832611 1987 mutex_lock(&sc->mutex);
8089cc47
JM
1988 if (ath9k_wiphy_scanning(sc)) {
1989 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
1990 "same time\n");
1991 /*
1992 * Do not allow the concurrent scanning state for now. This
1993 * could be improved with scanning control moved into ath9k.
1994 */
3d832611 1995 mutex_unlock(&sc->mutex);
8089cc47
JM
1996 return;
1997 }
1998
1999 aphy->state = ATH_WIPHY_SCAN;
2000 ath9k_wiphy_pause_all_forced(sc, aphy);
0c98de65 2001 sc->sc_flags |= SC_OP_SCANNING;
05c78d6d 2002 del_timer_sync(&common->ani.timer);
b6ce5c33 2003 cancel_delayed_work_sync(&sc->tx_complete_work);
3d832611 2004 mutex_unlock(&sc->mutex);
0c98de65
S
2005}
2006
2007static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2008{
bce048d7
JM
2009 struct ath_wiphy *aphy = hw->priv;
2010 struct ath_softc *sc = aphy->sc;
05c78d6d 2011 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0c98de65 2012
3d832611 2013 mutex_lock(&sc->mutex);
8089cc47 2014 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2015 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2016 sc->sc_flags |= SC_OP_FULL_RESET;
05c78d6d 2017 ath_start_ani(common);
b6ce5c33 2018 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
d0bec342 2019 ath_beacon_config(sc, NULL);
3d832611 2020 mutex_unlock(&sc->mutex);
0c98de65
S
2021}
2022
e239d859
FF
2023static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2024{
2025 struct ath_wiphy *aphy = hw->priv;
2026 struct ath_softc *sc = aphy->sc;
2027 struct ath_hw *ah = sc->sc_ah;
2028
2029 mutex_lock(&sc->mutex);
2030 ah->coverage_class = coverage_class;
2031 ath9k_hw_init_global_settings(ah);
2032 mutex_unlock(&sc->mutex);
2033}
2034
6baff7f9 2035struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2036 .tx = ath9k_tx,
2037 .start = ath9k_start,
2038 .stop = ath9k_stop,
2039 .add_interface = ath9k_add_interface,
2040 .remove_interface = ath9k_remove_interface,
2041 .config = ath9k_config,
8feceb67 2042 .configure_filter = ath9k_configure_filter,
8feceb67
VT
2043 .sta_notify = ath9k_sta_notify,
2044 .conf_tx = ath9k_conf_tx,
8feceb67 2045 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2046 .set_key = ath9k_set_key,
8feceb67 2047 .get_tsf = ath9k_get_tsf,
3b5d665b 2048 .set_tsf = ath9k_set_tsf,
8feceb67 2049 .reset_tsf = ath9k_reset_tsf,
4233df6b 2050 .ampdu_action = ath9k_ampdu_action,
0c98de65
S
2051 .sw_scan_start = ath9k_sw_scan_start,
2052 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2053 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2054 .set_coverage_class = ath9k_set_coverage_class,
8feceb67 2055};