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Commit | Line | Data |
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6baff7f9 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
6baff7f9 GJ |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/nl80211.h> | |
18 | #include <linux/pci.h> | |
a05b5d45 | 19 | #include <linux/ath9k_platform.h> |
394cf0a1 | 20 | #include "ath9k.h" |
6baff7f9 | 21 | |
a3aa1884 | 22 | static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = { |
6baff7f9 GJ |
23 | { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ |
24 | { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ | |
25 | { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ | |
26 | { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ | |
27 | { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ | |
28 | { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ | |
5ffaf8a3 | 29 | { PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */ |
ac88b6ec VN |
30 | { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */ |
31 | { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */ | |
0efabd51 | 32 | { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */ |
1435894d | 33 | { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */ |
6baff7f9 GJ |
34 | { 0 } |
35 | }; | |
36 | ||
37 | /* return bus cachesize in 4B word units */ | |
5bb12791 | 38 | static void ath_pci_read_cachesize(struct ath_common *common, int *csz) |
6baff7f9 | 39 | { |
bc974f4a | 40 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
6baff7f9 GJ |
41 | u8 u8tmp; |
42 | ||
f020979d | 43 | pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp); |
6baff7f9 GJ |
44 | *csz = (int)u8tmp; |
45 | ||
46 | /* | |
25985edc | 47 | * This check was put in to avoid "unpleasant" consequences if |
6baff7f9 GJ |
48 | * the bootrom has not fully initialized all PCI devices. |
49 | * Sometimes the cache line size register is not set | |
50 | */ | |
51 | ||
52 | if (*csz == 0) | |
53 | *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ | |
54 | } | |
55 | ||
5bb12791 | 56 | static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data) |
9dbeb91a | 57 | { |
a05b5d45 FF |
58 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
59 | struct ath9k_platform_data *pdata = sc->dev->platform_data; | |
60 | ||
61 | if (pdata) { | |
62 | if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { | |
3800276a JP |
63 | ath_err(common, |
64 | "%s: eeprom read failed, offset %08x is out of range\n", | |
65 | __func__, off); | |
a05b5d45 FF |
66 | } |
67 | ||
68 | *data = pdata->eeprom_data[off]; | |
69 | } else { | |
70 | struct ath_hw *ah = (struct ath_hw *) common->ah; | |
71 | ||
72 | common->ops->read(ah, AR5416_EEPROM_OFFSET + | |
73 | (off << AR5416_EEPROM_S)); | |
74 | ||
75 | if (!ath9k_hw_wait(ah, | |
76 | AR_EEPROM_STATUS_DATA, | |
77 | AR_EEPROM_STATUS_DATA_BUSY | | |
78 | AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, | |
79 | AH_WAIT_TIMEOUT)) { | |
80 | return false; | |
81 | } | |
82 | ||
83 | *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA), | |
84 | AR_EEPROM_STATUS_DATA_VAL); | |
9dbeb91a GJ |
85 | } |
86 | ||
9dbeb91a GJ |
87 | return true; |
88 | } | |
89 | ||
867633f0 LR |
90 | /* |
91 | * Bluetooth coexistance requires disabling ASPM. | |
92 | */ | |
5bb12791 | 93 | static void ath_pci_bt_coex_prep(struct ath_common *common) |
867633f0 | 94 | { |
bc974f4a | 95 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
867633f0 LR |
96 | struct pci_dev *pdev = to_pci_dev(sc->dev); |
97 | u8 aspm; | |
98 | ||
e40b5faa | 99 | if (!pci_is_pcie(pdev)) |
867633f0 LR |
100 | return; |
101 | ||
102 | pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm); | |
103 | aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1); | |
104 | pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm); | |
105 | } | |
106 | ||
8060e169 VT |
107 | static void ath_pci_extn_synch_enable(struct ath_common *common) |
108 | { | |
109 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
110 | struct pci_dev *pdev = to_pci_dev(sc->dev); | |
111 | u8 lnkctl; | |
112 | ||
113 | pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl); | |
114 | lnkctl |= PCI_EXP_LNKCTL_ES; | |
115 | pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl); | |
116 | } | |
117 | ||
83bd11a0 | 118 | static const struct ath_bus_ops ath_pci_bus_ops = { |
497ad9ad | 119 | .ath_bus_type = ATH_PCI, |
6baff7f9 | 120 | .read_cachesize = ath_pci_read_cachesize, |
9dbeb91a | 121 | .eeprom_read = ath_pci_eeprom_read, |
867633f0 | 122 | .bt_coex_prep = ath_pci_bt_coex_prep, |
8060e169 | 123 | .extn_synch_en = ath_pci_extn_synch_enable, |
6baff7f9 GJ |
124 | }; |
125 | ||
126 | static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
127 | { | |
128 | void __iomem *mem; | |
129 | struct ath_softc *sc; | |
130 | struct ieee80211_hw *hw; | |
131 | u8 csz; | |
aeac355d | 132 | u16 subsysid; |
f0214843 | 133 | u32 val; |
6baff7f9 | 134 | int ret = 0; |
f934c4d9 | 135 | char hw_name[64]; |
6baff7f9 GJ |
136 | |
137 | if (pci_enable_device(pdev)) | |
138 | return -EIO; | |
139 | ||
e930438c | 140 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
6baff7f9 GJ |
141 | if (ret) { |
142 | printk(KERN_ERR "ath9k: 32-bit DMA not available\n"); | |
285f2dda | 143 | goto err_dma; |
6baff7f9 GJ |
144 | } |
145 | ||
e930438c | 146 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
6baff7f9 GJ |
147 | if (ret) { |
148 | printk(KERN_ERR "ath9k: 32-bit DMA consistent " | |
149 | "DMA enable failed\n"); | |
285f2dda | 150 | goto err_dma; |
6baff7f9 GJ |
151 | } |
152 | ||
153 | /* | |
154 | * Cache line size is used to size and align various | |
155 | * structures used to communicate with the hardware. | |
156 | */ | |
157 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); | |
158 | if (csz == 0) { | |
159 | /* | |
160 | * Linux 2.4.18 (at least) writes the cache line size | |
161 | * register as a 16-bit wide register which is wrong. | |
162 | * We must have this setup properly for rx buffer | |
163 | * DMA to work so force a reasonable value here if it | |
164 | * comes up zero. | |
165 | */ | |
166 | csz = L1_CACHE_BYTES / sizeof(u32); | |
167 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); | |
168 | } | |
169 | /* | |
170 | * The default setting of latency timer yields poor results, | |
171 | * set it to the value used by other systems. It may be worth | |
172 | * tweaking this setting more. | |
173 | */ | |
174 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); | |
175 | ||
176 | pci_set_master(pdev); | |
177 | ||
f0214843 JM |
178 | /* |
179 | * Disable the RETRY_TIMEOUT register (0x41) to keep | |
180 | * PCI Tx retries from interfering with C3 CPU state. | |
181 | */ | |
182 | pci_read_config_dword(pdev, 0x40, &val); | |
183 | if ((val & 0x0000ff00) != 0) | |
184 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
185 | ||
6baff7f9 GJ |
186 | ret = pci_request_region(pdev, 0, "ath9k"); |
187 | if (ret) { | |
188 | dev_err(&pdev->dev, "PCI memory region reserve error\n"); | |
189 | ret = -ENODEV; | |
285f2dda | 190 | goto err_region; |
6baff7f9 GJ |
191 | } |
192 | ||
193 | mem = pci_iomap(pdev, 0, 0); | |
194 | if (!mem) { | |
195 | printk(KERN_ERR "PCI memory map error\n") ; | |
196 | ret = -EIO; | |
285f2dda | 197 | goto err_iomap; |
6baff7f9 GJ |
198 | } |
199 | ||
9ac58615 | 200 | hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); |
db6be53c | 201 | if (!hw) { |
285f2dda | 202 | dev_err(&pdev->dev, "No memory for ieee80211_hw\n"); |
db6be53c | 203 | ret = -ENOMEM; |
285f2dda | 204 | goto err_alloc_hw; |
6baff7f9 GJ |
205 | } |
206 | ||
207 | SET_IEEE80211_DEV(hw, &pdev->dev); | |
208 | pci_set_drvdata(pdev, hw); | |
209 | ||
9ac58615 | 210 | sc = hw->priv; |
6baff7f9 GJ |
211 | sc->hw = hw; |
212 | sc->dev = &pdev->dev; | |
213 | sc->mem = mem; | |
6baff7f9 | 214 | |
5e4ea1f0 S |
215 | /* Will be cleared in ath9k_start() */ |
216 | sc->sc_flags |= SC_OP_INVALID; | |
6baff7f9 | 217 | |
fc548af8 | 218 | ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc); |
580171f7 LR |
219 | if (ret) { |
220 | dev_err(&pdev->dev, "request_irq failed\n"); | |
285f2dda | 221 | goto err_irq; |
6baff7f9 GJ |
222 | } |
223 | ||
224 | sc->irq = pdev->irq; | |
225 | ||
285f2dda S |
226 | pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid); |
227 | ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops); | |
228 | if (ret) { | |
229 | dev_err(&pdev->dev, "Failed to initialize device\n"); | |
230 | goto err_init; | |
231 | } | |
232 | ||
233 | ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); | |
c96c31e4 JP |
234 | wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", |
235 | hw_name, (unsigned long)mem, pdev->irq); | |
6baff7f9 GJ |
236 | |
237 | return 0; | |
285f2dda S |
238 | |
239 | err_init: | |
240 | free_irq(sc->irq, sc); | |
241 | err_irq: | |
6baff7f9 | 242 | ieee80211_free_hw(hw); |
285f2dda | 243 | err_alloc_hw: |
6baff7f9 | 244 | pci_iounmap(pdev, mem); |
285f2dda | 245 | err_iomap: |
6baff7f9 | 246 | pci_release_region(pdev, 0); |
285f2dda S |
247 | err_region: |
248 | /* Nothing */ | |
249 | err_dma: | |
6baff7f9 GJ |
250 | pci_disable_device(pdev); |
251 | return ret; | |
252 | } | |
253 | ||
254 | static void ath_pci_remove(struct pci_dev *pdev) | |
255 | { | |
256 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
9ac58615 | 257 | struct ath_softc *sc = hw->priv; |
ab5132a2 | 258 | void __iomem *mem = sc->mem; |
6baff7f9 | 259 | |
d584747b RM |
260 | if (!is_ath9k_unloaded) |
261 | sc->sc_ah->ah_flags |= AH_UNPLUGGED; | |
285f2dda S |
262 | ath9k_deinit_device(sc); |
263 | free_irq(sc->irq, sc); | |
264 | ieee80211_free_hw(sc->hw); | |
ab5132a2 PR |
265 | |
266 | pci_iounmap(pdev, mem); | |
267 | pci_disable_device(pdev); | |
268 | pci_release_region(pdev, 0); | |
6baff7f9 GJ |
269 | } |
270 | ||
271 | #ifdef CONFIG_PM | |
272 | ||
f0e94b47 | 273 | static int ath_pci_suspend(struct device *device) |
6baff7f9 | 274 | { |
f0e94b47 | 275 | struct pci_dev *pdev = to_pci_dev(device); |
6baff7f9 | 276 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
9ac58615 | 277 | struct ath_softc *sc = hw->priv; |
6baff7f9 | 278 | |
08fc5c1b | 279 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); |
6baff7f9 | 280 | |
6baff7f9 GJ |
281 | return 0; |
282 | } | |
283 | ||
f0e94b47 | 284 | static int ath_pci_resume(struct device *device) |
6baff7f9 | 285 | { |
f0e94b47 | 286 | struct pci_dev *pdev = to_pci_dev(device); |
6baff7f9 | 287 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
9ac58615 | 288 | struct ath_softc *sc = hw->priv; |
f0214843 | 289 | u32 val; |
523c36fc | 290 | |
f0214843 JM |
291 | /* |
292 | * Suspend/Resume resets the PCI configuration space, so we have to | |
293 | * re-disable the RETRY_TIMEOUT register (0x41) to keep | |
294 | * PCI Tx retries from interfering with C3 CPU state | |
295 | */ | |
296 | pci_read_config_dword(pdev, 0x40, &val); | |
297 | if ((val & 0x0000ff00) != 0) | |
298 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
6baff7f9 GJ |
299 | |
300 | /* Enable LED */ | |
08fc5c1b | 301 | ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin, |
6baff7f9 | 302 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 303 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); |
6baff7f9 | 304 | |
db7ec38d MSS |
305 | /* |
306 | * Reset key cache to sane defaults (all entries cleared) instead of | |
307 | * semi-random values after suspend/resume. | |
308 | */ | |
309 | ath9k_ps_wakeup(sc); | |
310 | ath9k_init_crypto(sc); | |
311 | ath9k_ps_restore(sc); | |
312 | ||
a08e7ade LR |
313 | sc->ps_idle = true; |
314 | ath_radio_disable(sc, hw); | |
315 | ||
6baff7f9 GJ |
316 | return 0; |
317 | } | |
318 | ||
f0e94b47 RW |
319 | static const struct dev_pm_ops ath9k_pm_ops = { |
320 | .suspend = ath_pci_suspend, | |
321 | .resume = ath_pci_resume, | |
322 | .freeze = ath_pci_suspend, | |
323 | .thaw = ath_pci_resume, | |
324 | .poweroff = ath_pci_suspend, | |
325 | .restore = ath_pci_resume, | |
326 | }; | |
327 | ||
328 | #define ATH9K_PM_OPS (&ath9k_pm_ops) | |
329 | ||
330 | #else /* !CONFIG_PM */ | |
331 | ||
332 | #define ATH9K_PM_OPS NULL | |
333 | ||
334 | #endif /* !CONFIG_PM */ | |
335 | ||
6baff7f9 GJ |
336 | |
337 | MODULE_DEVICE_TABLE(pci, ath_pci_id_table); | |
338 | ||
339 | static struct pci_driver ath_pci_driver = { | |
340 | .name = "ath9k", | |
341 | .id_table = ath_pci_id_table, | |
342 | .probe = ath_pci_probe, | |
343 | .remove = ath_pci_remove, | |
f0e94b47 | 344 | .driver.pm = ATH9K_PM_OPS, |
6baff7f9 GJ |
345 | }; |
346 | ||
db0f41f5 | 347 | int ath_pci_init(void) |
6baff7f9 GJ |
348 | { |
349 | return pci_register_driver(&ath_pci_driver); | |
350 | } | |
351 | ||
352 | void ath_pci_exit(void) | |
353 | { | |
354 | pci_unregister_driver(&ath_pci_driver); | |
355 | } |